µGFX library fork

board_SSD1289.h 6.4KB

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  1. /*
  2. * This file is subject to the terms of the GFX License. If a copy of
  3. * the license was not distributed with this file, you can obtain one at:
  4. *
  5. * http://ugfx.org/license.html
  6. */
  7. /**
  8. * @file boards/addons/gdisp/board_SSD1289_stm32f4discovery.h
  9. * @brief GDISP Graphic Driver subsystem board interface for the SSD1289 display.
  10. *
  11. * @note This file contains a mix of hardware specific and operating system specific
  12. * code. You will need to change it for your CPU and/or operating system.
  13. */
  14. #ifndef _GDISP_LLD_BOARD_H
  15. #define _GDISP_LLD_BOARD_H
  16. // For a multiple display configuration we would put all this in a structure and then
  17. // set g->board to that structure.
  18. #define GDISP_REG ((volatile uint16_t *) 0x60000000)[0] /* RS = 0 */
  19. #define GDISP_RAM ((volatile uint16_t *) 0x60020000)[0] /* RS = 1 */
  20. #define GDISP_DMA_STREAM STM32_DMA2_STREAM6
  21. #define FSMC_BANK 0
  22. /* PWM configuration structure. We use timer 3 channel 3 */
  23. static const PWMConfig pwmcfg = {
  24. 100000, /* 100 kHz PWM clock frequency. */
  25. 100, /* PWM period is 100 cycles. */
  26. 0,
  27. {
  28. {PWM_OUTPUT_DISABLED, 0},
  29. {PWM_OUTPUT_DISABLED, 0},
  30. {PWM_OUTPUT_ACTIVE_HIGH, 0},
  31. {PWM_OUTPUT_DISABLED, 0}
  32. },
  33. 0,
  34. 0
  35. };
  36. static GFXINLINE void init_board(GDisplay *g) {
  37. // As we are not using multiple displays we set g->board to NULL as we don't use it.
  38. g->board = 0;
  39. switch(g->controllerdisplay) {
  40. case 0: // Set up for Display 0
  41. /**
  42. * Performs the following functions:
  43. * 1. initialise the io port used by the display
  44. * 2. initialise the reset pin (initial state not-in-reset)
  45. * 3. initialise the chip select pin (initial state not-active)
  46. * 4. initialise the backlight pin (initial state back-light off)
  47. */
  48. #if defined(STM32F1XX) || defined(STM32F3XX)
  49. /* FSMC setup for F1/F3 */
  50. rccEnableAHB(RCC_AHBENR_FSMCEN, 0);
  51. #if defined(GDISP_USE_DMA)
  52. #error "GDISP: SSD1289 - DMA not implemented for F1/F3 Devices"
  53. #endif
  54. #elif defined(STM32F4XX) || defined(STM32F2XX)
  55. /* STM32F2-F4 FSMC init */
  56. rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0);
  57. #if defined(GDISP_USE_DMA)
  58. if (dmaStreamAllocate(GDISP_DMA_STREAM, 0, 0, 0)) gfxExit();
  59. dmaStreamSetMemory0(GDISP_DMA_STREAM, &GDISP_RAM);
  60. dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
  61. #else
  62. #if GFX_COMPILER_WARNING_TYPE == GFX_COMPILER_WARNING_DIRECT
  63. #warning "GDISP: SSD1289 - DMA is supported for F2/F4 Devices. Define GDISP_USE_DMA in your gfxconf.h to turn this on for better performance."
  64. #elif GFX_COMPILER_WARNING_TYPE == GFX_COMPILER_WARNING_MACRO
  65. COMPILER_WARNING("GDISP: SSD1289 - DMA is supported for F2/F4 Devices. Define GDISP_USE_DMA in your gfxconf.h to turn this on for better performance.")
  66. #endif
  67. #endif
  68. #else
  69. #error "GDISP: SSD1289 - FSMC not implemented for this device"
  70. #endif
  71. /* set pins to FSMC mode */
  72. IOBus busD = {GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) | (1 << 7) | (1 << 8) |
  73. (1 << 9) | (1 << 10) | (1 << 11) | (1 << 14) | (1 << 15), 0};
  74. IOBus busE = {GPIOE, (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) |
  75. (1 << 13) | (1 << 14) | (1 << 15), 0};
  76. palSetBusMode(&busD, PAL_MODE_ALTERNATE(12));
  77. palSetBusMode(&busE, PAL_MODE_ALTERNATE(12));
  78. /* FSMC timing */
  79. // FSMC_Bank1->BTCR[FSMC_BANK+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0 ;
  80. //FSMC_Bank1->BTCR[FSMC_BANK+1] = FSMC_BTR1_ADDSET_2 | FSMC_BTR1_ADDSET_1 | FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_DATAST_1 | FSMC_BTR1_DATAST_0 | FSMC_BTR1_BUSTURN_2 | FSMC_BTR1_BUSTURN_1 | FSMC_BTR1_BUSTURN_0;
  81. //this works// FSMC_Bank1->BTCR[FSMC_BANK+1] = FSMC_BTR1_ADDSET_2 | FSMC_BTR1_ADDSET_1 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_DATAST_1 | FSMC_BTR1_BUSTURN_2;
  82. FSMC_Bank1->BTCR[FSMC_BANK+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_DATAST_0 | FSMC_BTR1_BUSTURN_0;
  83. /* Bank1 NOR/SRAM control register configuration
  84. * This is actually not needed as already set by default after reset */
  85. FSMC_Bank1->BTCR[FSMC_BANK] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
  86. /* Display backlight control */
  87. /* TIM3 is an alternate function 2 (AF2) */
  88. pwmStart(&PWMD3, &pwmcfg);
  89. palSetPadMode(GPIOB, 0, PAL_MODE_ALTERNATE(2));
  90. pwmEnableChannel(&PWMD3, 2, 100);
  91. break;
  92. }
  93. }
  94. static GFXINLINE void post_init_board(GDisplay *g) {
  95. (void) g;
  96. }
  97. static GFXINLINE void setpin_reset(GDisplay *g, bool_t state) {
  98. (void) g;
  99. (void) state;
  100. }
  101. static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
  102. (void) g;
  103. pwmEnableChannel(&PWMD3, 2, percent);
  104. }
  105. static GFXINLINE void acquire_bus(GDisplay *g) {
  106. (void) g;
  107. }
  108. static GFXINLINE void release_bus(GDisplay *g) {
  109. (void) g;
  110. }
  111. static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
  112. (void) g;
  113. GDISP_REG = index;
  114. }
  115. static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
  116. (void) g;
  117. GDISP_RAM = data;
  118. }
  119. static GFXINLINE void setreadmode(GDisplay *g) {
  120. (void) g;
  121. FSMC_Bank1->BTCR[FSMC_BANK+1] = FSMC_BTR1_ADDSET_3 | FSMC_BTR1_DATAST_3 | FSMC_BTR1_BUSTURN_0; /* FSMC timing */
  122. }
  123. static GFXINLINE void setwritemode(GDisplay *g) {
  124. (void) g;
  125. FSMC_Bank1->BTCR[FSMC_BANK+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0; /* FSMC timing */
  126. }
  127. static GFXINLINE uint16_t read_data(GDisplay *g) {
  128. (void) g;
  129. return GDISP_RAM;
  130. }
  131. #if defined(GDISP_USE_DMA) || defined(__DOXYGEN__)
  132. static GFXINLINE void dma_with_noinc(GDisplay *g, color_t *buffer, int area) {
  133. (void) g;
  134. dmaStreamSetPeripheral(GDISP_DMA_STREAM, buffer);
  135. dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
  136. for (; area > 0; area -= 65535) {
  137. dmaStreamSetTransactionSize(GDISP_DMA_STREAM, area > 65535 ? 65535 : area);
  138. dmaStreamEnable(GDISP_DMA_STREAM);
  139. dmaWaitCompletion(GDISP_DMA_STREAM);
  140. }
  141. }
  142. static GFXINLINE void dma_with_inc(GDisplay *g, color_t *buffer, int area) {
  143. (void) g;
  144. dmaStreamSetPeripheral(GDISP_DMA_STREAM, buffer);
  145. dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PINC | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
  146. for (; area > 0; area -= 65535) {
  147. dmaStreamSetTransactionSize(GDISP_DMA_STREAM, area > 65535 ? 65535 : area);
  148. dmaStreamEnable(GDISP_DMA_STREAM);
  149. dmaWaitCompletion(GDISP_DMA_STREAM);
  150. }
  151. }
  152. #endif
  153. #endif /* _GDISP_LLD_BOARD_H */