103 lines
2.9 KiB
ArmAsm
103 lines
2.9 KiB
ArmAsm
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.extern system_init
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.extern __bss_start
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.extern __bss_end
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.extern vFreeRTOS_ISR
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.extern vPortYieldProcessor
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.extern DisableInterrupts
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.extern main
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.section .init
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.globl _start
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;;
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_start:
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;@ All the following instruction should be read as:
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;@ Load the address at symbol into the program counter.
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ldr pc,reset_handler ;@ Processor Reset handler -- we will have to force this on the raspi!
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;@ Because this is the first instruction executed, of cause it causes an immediate branch into reset!
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ldr pc,undefined_handler ;@ Undefined instruction handler -- processors that don't have thumb can emulate thumb!
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ldr pc,swi_handler ;@ Software interrupt / TRAP (SVC) -- system SVC handler for switching to kernel mode.
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ldr pc,prefetch_handler ;@ Prefetch/abort handler.
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ldr pc,data_handler ;@ Data abort handler/
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ldr pc,unused_handler ;@ -- Historical from 26-bit addressing ARMs -- was invalid address handler.
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ldr pc,irq_handler ;@ IRQ handler
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ldr pc,fiq_handler ;@ Fast interrupt handler.
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;@ Here we create an exception address table! This means that reset/hang/irq can be absolute addresses
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reset_handler: .word reset
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undefined_handler: .word undefined_instruction
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swi_handler: .word vPortYieldProcessor
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prefetch_handler: .word prefetch_abort
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data_handler: .word data_abort
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unused_handler: .word unused
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irq_handler: .word vFreeRTOS_ISR
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fiq_handler: .word fiq
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reset:
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;@ In the reset handler, we need to copy our interrupt vector table to 0x0000, its currently at 0x8000
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mov r0,#0x8000 ;@ Store the source pointer
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mov r1,#0x0000 ;@ Store the destination pointer.
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;@ Here we copy the branching instructions
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ldmia r0!,{r2,r3,r4,r5,r6,r7,r8,r9} ;@ Load multiple values from indexed address. ; Auto-increment R0
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stmia r1!,{r2,r3,r4,r5,r6,r7,r8,r9} ;@ Store multiple values from the indexed address. ; Auto-increment R1
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;@ So the branches get the correct address we also need to copy our vector table!
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ldmia r0!,{r2,r3,r4,r5,r6,r7,r8,r9} ;@ Load from 4*n of regs (8) as R0 is now incremented.
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stmia r1!,{r2,r3,r4,r5,r6,r7,r8,r9} ;@ Store this extra set of data.
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;@ Set up the various STACK pointers for different CPU modes
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;@ (PSR_IRQ_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS)
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mov r0,#0xD2
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msr cpsr_c,r0
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mov sp,#0x8000
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;@ (PSR_FIQ_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS)
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mov r0,#0xD1
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msr cpsr_c,r0
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mov sp,#0x4000
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;@ (PSR_SVC_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS)
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mov r0,#0xD3
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msr cpsr_c,r0
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mov sp,#0x8000000
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ldr r0, =__bss_start
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ldr r1, =__bss_end
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mov r2, #0
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zero_loop:
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cmp r0,r1
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it lt
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strlt r2,[r0], #4
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blt zero_loop
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bl DisableInterrupts
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;@ mov sp,#0x1000000
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b main ;@ We're ready?? Lets start main execution!
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.section .text
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undefined_instruction:
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b undefined_instruction
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prefetch_abort:
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b prefetch_abort
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data_abort:
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b data_abort
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unused:
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b unused
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fiq:
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b fiq
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hang:
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b hang
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