2013-10-19 07:58:57 +00:00
|
|
|
/*
|
|
|
|
* This file is subject to the terms of the GFX License. If a copy of
|
|
|
|
* the license was not distributed with this file, you can obtain one at:
|
|
|
|
*
|
|
|
|
* http://ugfx.org/license.html
|
|
|
|
*/
|
|
|
|
|
|
|
|
/**
|
2014-03-27 22:52:30 +00:00
|
|
|
* @file boards/addons/gdisp/board_S6D1121_olimex_e407.h
|
|
|
|
* @brief GDISP Graphic Driver subsystem board interface for the S6D1121 display.
|
|
|
|
*
|
|
|
|
* @note This file contains a mix of hardware specific and operating system specific
|
|
|
|
* code. You will need to change it for your CPU and/or operating system.
|
2013-10-19 07:58:57 +00:00
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef _GDISP_LLD_BOARD_H
|
|
|
|
#define _GDISP_LLD_BOARD_H
|
|
|
|
|
|
|
|
// For a multiple display configuration we would put all this in a structure and then
|
2013-10-21 07:11:07 +00:00
|
|
|
// set g->board to that structure.
|
2013-10-19 07:58:57 +00:00
|
|
|
#define GDISP_REG (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
|
|
|
|
#define GDISP_RAM (*((volatile uint16_t *) 0x60020000)) /* RS = 1 */
|
|
|
|
|
|
|
|
static inline void init_board(GDisplay *g) {
|
|
|
|
|
2013-10-21 05:13:10 +00:00
|
|
|
// As we are not using multiple displays we set g->board to NULL as we don't use it.
|
|
|
|
g->board = 0;
|
2013-10-19 07:58:57 +00:00
|
|
|
|
|
|
|
switch(g->controllerdisplay) {
|
|
|
|
case 0: // Set up for Display 0
|
|
|
|
/* STM32F4 FSMC init */
|
|
|
|
rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0);
|
|
|
|
|
|
|
|
/* set pins to FSMC mode */
|
|
|
|
IOBus busD = {GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) | (1 << 7) | (1 << 8) |
|
|
|
|
(1 << 9) | (1 << 10) | (1 << 11) | (1 << 14) | (1 << 15), 0};
|
|
|
|
|
|
|
|
IOBus busE = {GPIOE, (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) |
|
|
|
|
(1 << 13) | (1 << 14) | (1 << 15), 0};
|
|
|
|
|
|
|
|
palSetBusMode(&busD, PAL_MODE_ALTERNATE(12));
|
|
|
|
palSetBusMode(&busE, PAL_MODE_ALTERNATE(12));
|
|
|
|
|
|
|
|
/* FSMC timing */
|
|
|
|
FSMC_Bank1->BTCR[0+1] = (6) | (10 << 8) | (10 << 16);
|
|
|
|
|
|
|
|
/* Bank1 NOR/SRAM control register configuration */
|
|
|
|
FSMC_Bank1->BTCR[0] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void setpin_reset(GDisplay *g, bool_t state) {
|
|
|
|
(void) g;
|
|
|
|
(void) state;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void set_backlight(GDisplay *g, uint8_t percent) {
|
|
|
|
(void) g;
|
|
|
|
(void) percent;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void acquire_bus(GDisplay *g) {
|
|
|
|
(void) g;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void release_bus(GDisplay *g) {
|
|
|
|
(void) g;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void write_index(GDisplay *g, uint16_t index) {
|
|
|
|
(void) g;
|
|
|
|
GDISP_REG = index;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void write_data(GDisplay *g, uint16_t data) {
|
|
|
|
(void) g;
|
|
|
|
GDISP_RAM = data;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void setreadmode(GDisplay *g) {
|
|
|
|
(void) g;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void setwritemode(GDisplay *g) {
|
|
|
|
(void) g;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint16_t read_data(GDisplay *g) {
|
|
|
|
(void) g;
|
|
|
|
return GDISP_RAM;
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* _GDISP_LLD_BOARD_H */
|