From 49f32f5ce7e88877abc66b091e5d00e32681a150 Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Wed, 8 Jul 2015 02:41:20 +0200 Subject: [PATCH 01/26] Starting STM32F7 Discovery driver development --- .../board_STM32F746Discovery_template.h | 73 +++ drivers/gdisp/STM32F746Discovery/driver.mk | 2 + .../gdisp_lld_STM32F746Discovery.c | 425 ++++++++++++++++++ .../STM32F746Discovery/gdisp_lld_config.h | 24 + drivers/gdisp/STM32F746Discovery/readme.txt | 11 + drivers/gdisp/STM32F746Discovery/stm32_ltdc.h | 138 ++++++ 6 files changed, 673 insertions(+) create mode 100644 drivers/gdisp/STM32F746Discovery/board_STM32F746Discovery_template.h create mode 100644 drivers/gdisp/STM32F746Discovery/driver.mk create mode 100644 drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c create mode 100644 drivers/gdisp/STM32F746Discovery/gdisp_lld_config.h create mode 100644 drivers/gdisp/STM32F746Discovery/readme.txt create mode 100644 drivers/gdisp/STM32F746Discovery/stm32_ltdc.h diff --git a/drivers/gdisp/STM32F746Discovery/board_STM32F746Discovery_template.h b/drivers/gdisp/STM32F746Discovery/board_STM32F746Discovery_template.h new file mode 100644 index 00000000..2f7be489 --- /dev/null +++ b/drivers/gdisp/STM32F746Discovery/board_STM32F746Discovery_template.h @@ -0,0 +1,73 @@ +/* + * This file is subject to the terms of the GFX License. If a copy of + * the license was not distributed with this file, you can obtain one at: + * + * http://ugfx.org/license.html + */ + +#ifndef _GDISP_LLD_BOARD_H +#define _GDISP_LLD_BOARD_H + +static const ltdcConfig driverCfg = { + 480, 270, // Width, Height (pixels) + 10, 2, // Horizontal, Vertical sync (pixels) + 20, 2, // Horizontal, Vertical back porch (pixels) + 10, 4, // Horizontal, Vertical front porch (pixels) + 0, // Sync flags + 0x000000, // Clear color (RGB888) + + { // Background layer config + (LLDCOLOR_TYPE *)SDRAM_BANK_ADDR, // Frame buffer address + 480, 270, // Width, Height (pixels) + 480 * LTDC_PIXELBYTES, // Line pitch (bytes) + LTDC_PIXELFORMAT, // Pixel format + 0, 0, // Start pixel position (x, y) + 480, 270, // Size of virtual layer (cx, cy) + LTDC_COLOR_FUCHSIA, // Default color (ARGB8888) + 0x980088, // Color key (RGB888) + LTDC_BLEND_FIX1_FIX2, // Blending factors + 0, // Palette (RGB888, can be NULL) + 0, // Palette length + 0xFF, // Constant alpha factor + LTDC_LEF_ENABLE // Layer configuration flags + }, + LTDC_UNUSED_LAYER_CONFIG // Foreground layer config +}; + +static inline void init_board(GDisplay *g) { + + // As we are not using multiple displays we set g->board to NULL as we don't use it. + g->board = 0; + + switch(g->controllerdisplay) { + case 0: // Set up for Display 0 + // Your init here + break; + } +} + +static inline void post_init_board(GDisplay* g) +{ +} + +static inline void set_backlight(GDisplay* g, uint8_t percent) +{ +} + +static inline void acquire_bus(GDisplay* g) +{ +} + +static inline void release_bus(GDisplay* g) +{ +} + +static inline void write_index(GDisplay* g, uint8_t index) +{ +} + +static inline void write_data(GDisplay* g, uint8_t data) +{ +} + +#endif /* _GDISP_LLD_BOARD_H */ diff --git a/drivers/gdisp/STM32F746Discovery/driver.mk b/drivers/gdisp/STM32F746Discovery/driver.mk new file mode 100644 index 00000000..720d5d1c --- /dev/null +++ b/drivers/gdisp/STM32F746Discovery/driver.mk @@ -0,0 +1,2 @@ +GFXINC += $(GFXLIB)/drivers/gdisp/STM32F746Discovery +GFXSRC += $(GFXLIB)/drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c diff --git a/drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c b/drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c new file mode 100644 index 00000000..7077f024 --- /dev/null +++ b/drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c @@ -0,0 +1,425 @@ +/* + * This file is subject to the terms of the GFX License. If a copy of + * the license was not distributed with this file, you can obtain one at: + * + * http://ugfx.org/license.html + */ + +#include "gfx.h" + +#if GFX_USE_GDISP + +#if defined(GDISP_SCREEN_HEIGHT) + #warning "GDISP: This low level driver does not support setting a screen size. It is being ignored." + #undef GISP_SCREEN_HEIGHT +#endif +#if defined(GDISP_SCREEN_WIDTH) + #warning "GDISP: This low level driver does not support setting a screen size. It is being ignored." + #undef GDISP_SCREEN_WIDTH +#endif + +#define GDISP_DRIVER_VMT GDISPVMT_STM32F746Discovery +#include "drivers/gdisp/STM32F746Discovery/gdisp_lld_config.h" +#include "src/gdisp/gdisp_driver.h" + +#include "stm32_ltdc.h" + +typedef struct ltdcLayerConfig { + // frame + LLDCOLOR_TYPE *frame; // Frame buffer address + coord_t width, height; // Frame size in pixels + coord_t pitch; // Line pitch, in bytes + uint16_t fmt; // Pixel format in LTDC format + + // window + coord_t x, y; // Start pixel position of the virtual layer + coord_t cx, cy; // Size of the virtual layer + + uint32_t defcolor; // Default color, ARGB8888 + uint32_t keycolor; // Color key, RGB888 + uint32_t blending; // Blending factors + const uint32_t *palette; // The palette, RGB888 (can be NULL) + uint16_t palettelen; // Palette length + uint8_t alpha; // Constant alpha factor + uint8_t layerflags; // Layer configuration +} ltdcLayerConfig; + +#define LTDC_UNUSED_LAYER_CONFIG { 0, 1, 1, 1, LTDC_FMT_L8, 0, 0, 1, 1, 0x000000, 0x000000, LTDC_BLEND_FIX1_FIX2, 0, 0, 0, 0 } + +typedef struct ltdcConfig { + coord_t width, height; // Screen size + coord_t hsync, vsync; // Horizontal and Vertical sync pixels + coord_t hbackporch, vbackporch; // Horizontal and Vertical back porch pixels + coord_t hfrontporch, vfrontporch; // Horizontal and Vertical front porch pixels + uint8_t syncflags; // Sync flags + uint32_t bgcolor; // Clear screen color RGB888 + + ltdcLayerConfig bglayer; // Background layer config + ltdcLayerConfig fglayer; // Foreground layer config +} ltdcConfig; + +#if GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB565 + #define LTDC_PIXELFORMAT LTDC_FMT_RGB565 + #define LTDC_PIXELBYTES 2 + #define LTDC_PIXELBITS 16 +#elif GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB888 + #define LTDC_PIXELFORMAT LTDC_FMT_RGB888 + #define LTDC_PIXELBYTES 3 + #define LTDC_PIXELBITS 24 +#else + #error "GDISP: STM32F4iDiscovery - unsupported pixel format" +#endif + +#include "board_STM32F429iDiscovery.h" + +#include "ili9341.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#ifndef GDISP_INITIAL_CONTRAST + #define GDISP_INITIAL_CONTRAST 50 +#endif +#ifndef GDISP_INITIAL_BACKLIGHT + #define GDISP_INITIAL_BACKLIGHT 100 +#endif + +/*===========================================================================*/ +/* Driver local routines . */ +/*===========================================================================*/ + +#define PIXIL_POS(g, x, y) ((y) * driverCfg.bglayer.pitch + (x) * LTDC_PIXELBYTES) +#define PIXEL_ADDR(g, pos) ((LLDCOLOR_TYPE *)((uint8_t *)driverCfg.bglayer.frame+pos)) + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +static void InitController(GDisplay *g) { + #define REG_TYPEMASK 0xFF00 + #define REG_DATAMASK 0x00FF + + #define REG_DATA 0x0000 + #define REG_COMMAND 0x0100 + #define REG_DELAY 0x0200 + + static const uint16_t initdata[] = { + REG_COMMAND | ILI9341_CMD_RESET, + REG_DELAY | 5, + REG_COMMAND | ILI9341_CMD_DISPLAY_OFF, + REG_COMMAND | ILI9341_SET_FRAME_CTL_NORMAL, 0x00, 0x1B, + REG_COMMAND | ILI9341_SET_FUNCTION_CTL, 0x0A, 0xA2, + REG_COMMAND | ILI9341_SET_POWER_CTL_1, 0x10, + REG_COMMAND | ILI9341_SET_POWER_CTL_2, 0x10, + #if 1 + REG_COMMAND | ILI9341_SET_VCOM_CTL_1, 0x45, 0x15, + REG_COMMAND | ILI9341_SET_VCOM_CTL_2, 0x90, + #else + REG_COMMAND | ILI9341_SET_VCOM_CTL_1, 0x35, 0x3E, + REG_COMMAND | ILI9341_SET_VCOM_CTL_2, 0xBE, + #endif + REG_COMMAND | ILI9341_SET_MEM_ACS_CTL, 0xC8, + REG_COMMAND | ILI9341_SET_RGB_IF_SIG_CTL, 0xC2, + REG_COMMAND | ILI9341_SET_FUNCTION_CTL, 0x0A, 0xA7, 0x27, 0x04, + REG_COMMAND | ILI9341_SET_COL_ADDR, 0x00, 0x00, 0x00, 0xEF, + REG_COMMAND | ILI9341_SET_PAGE_ADDR, 0x00, 0x00, 0x01, 0x3F, + REG_COMMAND | ILI9341_SET_IF_CTL, 0x01, 0x00, 0x06, + REG_COMMAND | ILI9341_SET_GAMMA, 0x01, + REG_COMMAND | ILI9341_SET_PGAMMA, + #if 1 + 0x0F, 0x29, 0x24, 0x0C, 0x0E, 0x09, 0x4E, 0x78, + 0x3C, 0x09, 0x13, 0x05, 0x17, 0x11, 0x00, + #else + 0x1F, 0x1a, 0x18, 0x0a, 0x0f, 0x06, 0x45, 0x87, + 0x32, 0x0a, 0x07, 0x02, 0x07, 0x05, 0x00, + #endif + REG_COMMAND | ILI9341_SET_NGAMMA, + #if 1 + 0x00, 0x16, 0x1B, 0x04, 0x11, 0x07, 0x31, 0x33, + 0x42, 0x05, 0x0C, 0x0A, 0x28, 0x2F, 0x0F, + #else + 0x00, 0x25, 0x27, 0x05, 0x10, 0x09, 0x3a, 0x78, + 0x4d, 0x05, 0x18, 0x0d, 0x38, 0x3a, 0x1f, + #endif + REG_COMMAND | ILI9341_CMD_SLEEP_OFF, + REG_DELAY | 10, + REG_COMMAND | ILI9341_CMD_DISPLAY_ON, + REG_COMMAND | ILI9341_SET_MEM + }; + + const uint16_t *p; + + acquire_bus(g); + for(p = initdata; p < &initdata[sizeof(initdata)/sizeof(initdata[0])]; p++) { + switch(*p & REG_TYPEMASK) { + case REG_DATA: write_data(g, *p); break; + case REG_COMMAND: write_index(g, *p); break; + case REG_DELAY: gfxSleepMilliseconds(*p & 0xFF); break; + } + } + release_bus(g); +} + +static void LTDC_Reload(void) { + LTDC->SRCR |= LTDC_SRCR_IMR; + while (LTDC->SRCR & (LTDC_SRCR_IMR | LTDC_SRCR_VBR)) + gfxYield(); +} + +static void LTDC_LayerInit(LTDC_Layer_TypeDef *pLayReg, const ltdcLayerConfig * pCfg) { + static const uint8_t fmt2Bpp[] = { + 4, /* LTDC_FMT_ARGB8888 */ + 3, /* LTDC_FMT_RGB888 */ + 2, /* LTDC_FMT_RGB565 */ + 2, /* LTDC_FMT_ARGB1555 */ + 2, /* LTDC_FMT_ARGB4444 */ + 1, /* LTDC_FMT_L8 */ + 1, /* LTDC_FMT_AL44 */ + 2 /* LTDC_FMT_AL88 */ + }; + uint32_t start, stop; + + // Set the framebuffer dimensions and format + pLayReg->PFCR = (pLayReg->PFCR & ~LTDC_LxPFCR_PF) | ((uint32_t)pCfg->fmt & LTDC_LxPFCR_PF); + pLayReg->CFBAR = (uint32_t)pCfg->frame & LTDC_LxCFBAR_CFBADD; + pLayReg->CFBLR = ((((uint32_t)pCfg->pitch << 16) & LTDC_LxCFBLR_CFBP) | (((uint32_t)fmt2Bpp[pCfg->fmt] * pCfg->width + 3) & LTDC_LxCFBLR_CFBLL)); + pLayReg->CFBLNR = (uint32_t)pCfg->height & LTDC_LxCFBLNR_CFBLNBR; + + // Set the display window boundaries + start = (uint32_t)pCfg->x + driverCfg.hsync + driverCfg.hbackporch; + stop = start + pCfg->cx - 1; + pLayReg->WHPCR = ((start << 0) & LTDC_LxWHPCR_WHSTPOS) | ((stop << 16) & LTDC_LxWHPCR_WHSPPOS); + start = (uint32_t)pCfg->y + driverCfg.vsync + driverCfg.vbackporch; + stop = start + pCfg->cy - 1; + pLayReg->WVPCR = ((start << 0) & LTDC_LxWVPCR_WVSTPOS) | ((stop << 16) & LTDC_LxWVPCR_WVSPPOS); + + // Set colors + pLayReg->DCCR = pCfg->defcolor; + pLayReg->CKCR = (pLayReg->CKCR & ~0x00FFFFFF) | (pCfg->keycolor & 0x00FFFFFF); + pLayReg->CACR = (pLayReg->CACR & ~LTDC_LxCACR_CONSTA) | ((uint32_t)pCfg->alpha & LTDC_LxCACR_CONSTA); + pLayReg->BFCR = (pLayReg->BFCR & ~(LTDC_LxBFCR_BF1 | LTDC_LxBFCR_BF2)) | ((uint32_t)pCfg->blending & (LTDC_LxBFCR_BF1 | LTDC_LxBFCR_BF2)); + for (start = 0; start < pCfg->palettelen; start++) + pLayReg->CLUTWR = ((uint32_t)start << 24) | (pCfg->palette[start] & 0x00FFFFFF); + + // Final flags + pLayReg->CR = (pLayReg->CR & ~LTDC_LEF_MASK) | ((uint32_t)pCfg->layerflags & LTDC_LEF_MASK); +} + +static void LTDC_Init(void) { + // Set up the display scanning + uint32_t hacc, vacc; + + /* Reset the LTDC hardware module.*/ + RCC->APB2RSTR |= RCC_APB2RSTR_LTDCRST; + RCC->APB2RSTR = 0; + + /* Enable the LTDC clock.*/ + RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | (1 << 16); /* /4 */ + + // Enable the module + RCC->APB2ENR |= RCC_APB2ENR_LTDCEN; + + // Turn off the controller and its interrupts. + LTDC->GCR = 0; + LTDC->IER = 0; + LTDC_Reload(); + + // Set synchronization params + hacc = driverCfg.hsync - 1; + vacc = driverCfg.vsync - 1; + LTDC->SSCR = ((hacc << 16) & LTDC_SSCR_HSW) | ((vacc << 0) & LTDC_SSCR_VSH); + + // Set accumulated back porch params + hacc += driverCfg.hbackporch; + vacc += driverCfg.vbackporch; + LTDC->BPCR = ((hacc << 16) & LTDC_BPCR_AHBP) | ((vacc << 0) & LTDC_BPCR_AVBP); + + // Set accumulated active params + hacc += driverCfg.width; + vacc += driverCfg.height; + LTDC->AWCR = ((hacc << 16) & LTDC_AWCR_AAW) | ((vacc << 0) & LTDC_AWCR_AAH); + + // Set accumulated total params + hacc += driverCfg.hfrontporch; + vacc += driverCfg.vfrontporch; + LTDC->TWCR = ((hacc << 16) & LTDC_TWCR_TOTALW) | ((vacc << 0) & LTDC_TWCR_TOTALH); + + // Set signal polarities and other flags + LTDC->GCR = driverCfg.syncflags & (LTDC_EF_MASK & ~LTDC_EF_ENABLE); + + // Set background color + LTDC->BCCR = (LTDC->BCCR & ~0x00FFFFFF) | (driverCfg.bgcolor & 0x00FFFFFF); + + // Load the background layer + LTDC_LayerInit(LTDC_Layer1, &driverCfg.bglayer); + + // Load the foreground layer + LTDC_LayerInit(LTDC_Layer2, &driverCfg.fglayer); + + // Interrupt handling + //nvicEnableVector(STM32_LTDC_EV_NUMBER, CORTEX_PRIORITY_MASK(STM32_LTDC_EV_IRQ_PRIORITY)); + //nvicEnableVector(STM32_LTDC_ER_NUMBER, CORTEX_PRIORITY_MASK(STM32_LTDC_ER_IRQ_PRIORITY)); + // Possible flags - LTDC_IER_RRIE, LTDC_IER_LIE, LTDC_IER_FUIE, LTDC_IER_TERRIE etc + LTDC->IER = 0; + + // Set everything going + LTDC_Reload(); + LTDC->GCR |= LTDC_GCR_LTDCEN; + LTDC_Reload(); +} + +LLDSPEC bool_t gdisp_lld_init(GDisplay *g) { + + // Initialize the private structure + g->priv = 0; + g->board = 0; + //if (!(g->priv = gfxAlloc(sizeof(fbPriv)))) + // gfxHalt("GDISP Framebuffer: Failed to allocate private memory"); + + // Init the board + init_board(g); + //((fbPriv *)g->priv)->fbi.cfg = init_board(g); + + // Initialise the ILI9341 controller + InitController(g); + + // Initialise the LTDC controller + LTDC_Init(); + + // Initialise DMA2D + //dma2dStart(&DMA2DD1, &dma2d_cfg); + //dma2d_test(); + + // Finish Init the board + post_init_board(g); + + /* Turn on the back-light */ + set_backlight(g, GDISP_INITIAL_BACKLIGHT); + + /* Initialise the GDISP structure */ + g->g.Width = driverCfg.bglayer.width; + g->g.Height = driverCfg.bglayer.height; + g->g.Orientation = GDISP_ROTATE_0; + g->g.Powermode = powerOn; + g->g.Backlight = GDISP_INITIAL_BACKLIGHT; + g->g.Contrast = GDISP_INITIAL_CONTRAST; + return TRUE; +} + +LLDSPEC void gdisp_lld_draw_pixel(GDisplay *g) { + unsigned pos; + + #if GDISP_NEED_CONTROL + switch(g->g.Orientation) { + case GDISP_ROTATE_0: + default: + pos = PIXIL_POS(g, g->p.x, g->p.y); + break; + case GDISP_ROTATE_90: + pos = PIXIL_POS(g, g->p.y, g->g.Width-g->p.x-1); + break; + case GDISP_ROTATE_180: + pos = PIXIL_POS(g, g->g.Width-g->p.x-1, g->g.Height-g->p.y-1); + break; + case GDISP_ROTATE_270: + pos = PIXIL_POS(g, g->g.Height-g->p.y-1, g->p.x); + break; + } + #else + pos = PIXIL_POS(g, g->p.x, g->p.y); + #endif + + PIXEL_ADDR(g, pos)[0] = gdispColor2Native(g->p.color); +} + +LLDSPEC color_t gdisp_lld_get_pixel_color(GDisplay *g) { + unsigned pos; + LLDCOLOR_TYPE color; + + #if GDISP_NEED_CONTROL + switch(g->g.Orientation) { + case GDISP_ROTATE_0: + default: + pos = PIXIL_POS(g, g->p.x, g->p.y); + break; + case GDISP_ROTATE_90: + pos = PIXIL_POS(g, g->p.y, g->g.Width-g->p.x-1); + break; + case GDISP_ROTATE_180: + pos = PIXIL_POS(g, g->g.Width-g->p.x-1, g->g.Height-g->p.y-1); + break; + case GDISP_ROTATE_270: + pos = PIXIL_POS(g, g->g.Height-g->p.y-1, g->p.x); + break; + } + #else + pos = PIXIL_POS(g, g->p.x, g->p.y); + #endif + + color = PIXEL_ADDR(g, pos)[0]; + return gdispNative2Color(color); +} + +#if GDISP_NEED_CONTROL + LLDSPEC void gdisp_lld_control(GDisplay *g) { + switch(g->p.x) { + case GDISP_CONTROL_POWER: + if (g->g.Powermode == (powermode_t)g->p.ptr) + return; + switch((powermode_t)g->p.ptr) { + case powerOff: case powerOn: case powerSleep: case powerDeepSleep: + // TODO + break; + default: + return; + } + g->g.Powermode = (powermode_t)g->p.ptr; + return; + + case GDISP_CONTROL_ORIENTATION: + if (g->g.Orientation == (orientation_t)g->p.ptr) + return; + switch((orientation_t)g->p.ptr) { + case GDISP_ROTATE_0: + case GDISP_ROTATE_180: + if (g->g.Orientation == GDISP_ROTATE_90 || g->g.Orientation == GDISP_ROTATE_270) { + coord_t tmp; + + tmp = g->g.Width; + g->g.Width = g->g.Height; + g->g.Height = tmp; + } + break; + case GDISP_ROTATE_90: + case GDISP_ROTATE_270: + if (g->g.Orientation == GDISP_ROTATE_0 || g->g.Orientation == GDISP_ROTATE_180) { + coord_t tmp; + + tmp = g->g.Width; + g->g.Width = g->g.Height; + g->g.Height = tmp; + } + break; + default: + return; + } + g->g.Orientation = (orientation_t)g->p.ptr; + return; + + case GDISP_CONTROL_BACKLIGHT: + if ((unsigned)g->p.ptr > 100) g->p.ptr = (void *)100; + set_backlight(g, (unsigned)g->p.ptr); + g->g.Backlight = (unsigned)g->p.ptr; + return; + + case GDISP_CONTROL_CONTRAST: + if ((unsigned)g->p.ptr > 100) g->p.ptr = (void *)100; + // TODO + g->g.Contrast = (unsigned)g->p.ptr; + return; + } + } +#endif + +#endif /* GFX_USE_GDISP */ diff --git a/drivers/gdisp/STM32F746Discovery/gdisp_lld_config.h b/drivers/gdisp/STM32F746Discovery/gdisp_lld_config.h new file mode 100644 index 00000000..29e016ce --- /dev/null +++ b/drivers/gdisp/STM32F746Discovery/gdisp_lld_config.h @@ -0,0 +1,24 @@ +/* + * This file is subject to the terms of the GFX License. If a copy of + * the license was not distributed with this file, you can obtain one at: + * + * http://ugfx.org/license.html + */ + +#ifndef _GDISP_LLD_CONFIG_H +#define _GDISP_LLD_CONFIG_H + +#if GFX_USE_GDISP + +/*===========================================================================*/ +/* Driver hardware support. */ +/*===========================================================================*/ + +#define GDISP_HARDWARE_DRAWPIXEL TRUE +#define GDISP_HARDWARE_PIXELREAD TRUE +#define GDISP_HARDWARE_CONTROL TRUE +#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_RGB565 + +#endif /* GFX_USE_GDISP */ + +#endif /* _GDISP_LLD_CONFIG_H */ diff --git a/drivers/gdisp/STM32F746Discovery/readme.txt b/drivers/gdisp/STM32F746Discovery/readme.txt new file mode 100644 index 00000000..ab87e1d8 --- /dev/null +++ b/drivers/gdisp/STM32F746Discovery/readme.txt @@ -0,0 +1,11 @@ +To use this driver: + +1. Add in your gfxconf.h: + a) #define GFX_USE_GDISP TRUE + +2. To your makefile add the following lines: + include $(GFXLIB)/gfx.mk + include $(GFXLIB)/drivers/gdisp/STM32F746Discovery/driver.mk + +3. Add a board_STM32F746Discovery.h to you project directory (or board directory) + base on one of the templates. diff --git a/drivers/gdisp/STM32F746Discovery/stm32_ltdc.h b/drivers/gdisp/STM32F746Discovery/stm32_ltdc.h new file mode 100644 index 00000000..429d8627 --- /dev/null +++ b/drivers/gdisp/STM32F746Discovery/stm32_ltdc.h @@ -0,0 +1,138 @@ +/* + * This file is subject to the terms of the GFX License. If a copy of + * the license was not distributed with this file, you can obtain one at: + * + * http://ugfx.org/license.html + */ + +#ifndef STM32_LTDC_H +#define STM32_LTDC_H + +// LTDC enable flags +#define LTDC_EF_ENABLE (1 << 0) /**< LTDC enabled.*/ +#define LTDC_EF_DITHER (1 << 16) /**< Dithering enabled.*/ +#define LTDC_EF_PIXCLK_INVERT (1 << 28) /**< Inverted pixel clock.*/ +#define LTDC_EF_DATAEN_HIGH (1 << 29) /**< Active-high data enable.*/ +#define LTDC_EF_VSYNC_HIGH (1 << 30) /**< Active-high vsync.*/ +#define LTDC_EF_HSYNC_HIGH (1 << 31) /**< Active-high hsync.*/ + +#define LTDC_EF_MASK (LTDC_EF_ENABLE | LTDC_EF_DITHER | LTDC_EF_PIXCLK_INVERT | LTDC_EF_DATAEN_HIGH | LTDC_EF_VSYNC_HIGH | LTDC_EF_HSYNC_HIGH) + +// LTDC layer enable flags +#define LTDC_LEF_ENABLE (1 << 0) /**< Layer enabled*/ +#define LTDC_LEF_KEYING (1 << 1) /**< Color keying enabled.*/ +#define LTDC_LEF_PALETTE (1 << 4) /**< Palette enabled.*/ + +#define LTDC_LEF_MASK (LTDC_LEF_ENABLE | LTDC_LEF_KEYING | LTDC_LEF_PALETTE) + +// LTDC pixel formats +#define LTDC_FMT_ARGB8888 0 /**< ARGB-8888 format.*/ +#define LTDC_FMT_RGB888 1 /**< RGB-888 format.*/ +#define LTDC_FMT_RGB565 2 /**< RGB-565 format.*/ +#define LTDC_FMT_ARGB1555 3 /**< ARGB-1555 format.*/ +#define LTDC_FMT_ARGB4444 4 /**< ARGB-4444 format.*/ +#define LTDC_FMT_L8 5 /**< L-8 format.*/ +#define LTDC_FMT_AL44 6 /**< AL-44 format.*/ +#define LTDC_FMT_AL88 7 /**< AL-88 format.*/ + +// LTDC pixel format aliased raw masks +#define LTDC_XMASK_ARGB8888 0xFFFFFFFF /**< ARGB-8888 aliased mask.*/ +#define LTDC_XMASK_RGB888 0x00FFFFFF /**< RGB-888 aliased mask.*/ +#define LTDC_XMASK_RGB565 0x00F8FCF8 /**< RGB-565 aliased mask.*/ +#define LTDC_XMASK_ARGB1555 0x80F8F8F8 /**< ARGB-1555 aliased mask.*/ +#define LTDC_XMASK_ARGB4444 0xF0F0F0F0 /**< ARGB-4444 aliased mask.*/ +#define LTDC_XMASK_L8 0x000000FF /**< L-8 aliased mask.*/ +#define LTDC_XMASK_AL44 0xF00000F0 /**< AL-44 aliased mask.*/ +#define LTDC_XMASK_AL88 0xFF0000FF /**< AL-88 aliased mask.*/ + +// LTDC blending factors +#define LTDC_BLEND_FIX1_FIX2 0x0405 /**< cnst1; 1 - cnst2 */ +#define LTDC_BLEND_FIX1_MOD2 0x0407 /**< cnst1; 1 - a2 * cnst2 */ +#define LTDC_BLEND_MOD1_FIX2 0x0605 /**< a1 * cnst1; 1 - cnst2 */ +#define LTDC_BLEND_MOD1_MOD2 0x0607 /**< a1 * cnst1; 1 - a2 * cnst2 */ + +// LTDC parameter bounds +#define LTDC_MIN_SCREEN_WIDTH 1 +#define LTDC_MIN_SCREEN_HEIGHT 1 +#define LTDC_MAX_SCREEN_WIDTH 800 +#define LTDC_MAX_SCREEN_HEIGHT 600 + +#define LTDC_MIN_HSYNC_WIDTH 1 +#define LTDC_MIN_VSYNC_HEIGHT 1 +#define LTDC_MAX_HSYNC_WIDTH (1 << 12) +#define LTDC_MAX_VSYNC_HEIGHT (1 << 11) + +#define LTDC_MIN_HBP_WIDTH 0 +#define LTDC_MIN_VBP_HEIGHT 0 +#define LTDC_MAX_HBP_WIDTH (1 << 12) +#define LTDC_MAX_VBP_HEIGHT (1 << 11) + +#define LTDC_MIN_ACC_HBP_WIDTH 1 +#define LTDC_MIN_ACC_VBP_HEIGHT 1 +#define LTDC_MAX_ACC_HBP_WIDTH (1 << 12) +#define LTDC_MAX_ACC_VBP_HEIGHT (1 << 11) + +#define LTDC_MIN_HFP_WIDTH 0 +#define LTDC_MIN_VFP_HEIGHT 0 +#define LTDC_MAX_HFP_WIDTH (1 << 12) +#define LTDC_MAX_VFP_HEIGHT (1 << 11) + +#define LTDC_MIN_ACTIVE_WIDTH 0 +#define LTDC_MIN_ACTIVE_HEIGHT 0 +#define LTDC_MAX_ACTIVE_WIDTH (1 << 12) +#define LTDC_MAX_ACTIVE_HEIGHT (1 << 11) + +#define LTDC_MIN_ACC_ACTIVE_WIDTH 1 +#define LTDC_MIN_ACC_ACTIVE_HEIGHT 1 +#define LTDC_MAX_ACC_ACTIVE_WIDTH (1 << 12) +#define LTDC_MAX_ACC_ACTIVE_HEIGHT (1 << 11) + +#define LTDC_MIN_ACC_TOTAL_WIDTH 1 +#define LTDC_MIN_ACC_TOTAL_HEIGHT 1 +#define LTDC_MAX_ACC_TOTAL_WIDTH (1 << 12) +#define LTDC_MAX_ACC_TOTAL_HEIGHT (1 << 11) + +#define LTDC_MIN_LINE_INTERRUPT_POS 0 +#define LTDC_MAX_LINE_INTERRUPT_POS ((1 << 11) - 1) + +#define LTDC_MIN_WINDOW_HSTART 0 +#define LTDC_MIN_WINDOW_HSTART 0 +#define LTDC_MAX_WINDOW_HSTOP ((1 << 12) - 1) +#define LTDC_MAX_WINDOW_HSTOP ((1 << 12) - 1) + +#define LTDC_MIN_WINDOW_VSTART 0 +#define LTDC_MIN_WINDOW_VSTART 0 +#define LTDC_MAX_WINDOW_VSTOP ((1 << 11) - 1) +#define LTDC_MAX_WINDOW_VSTOP ((1 << 11) - 1) + +#define LTDC_MIN_FRAME_WIDTH_BYTES 0 +#define LTDC_MIN_FRAME_HEIGHT_LINES 0 +#define LTDC_MIN_FRAME_PITCH_BYTES 0 +#define LTDC_MAX_FRAME_WIDTH_BYTES ((1 << 13) - 1 - 3) +#define LTDC_MAX_FRAME_HEIGHT_LINES ((1 << 11) - 1) +#define LTDC_MAX_FRAME_PITCH_BYTES ((1 << 13) - 1) + +#define LTDC_MIN_PIXFMT_ID 0 +#define LTDC_MAX_PIXFMT_ID 7 + +#define LTDC_MAX_PALETTE_LENGTH 256 + +// LTDC basic ARGB-8888 colors. +#define LTDC_COLOR_BLACK 0xFF000000 +#define LTDC_COLOR_MAROON 0xFF800000 +#define LTDC_COLOR_GREEN 0xFF008000 +#define LTDC_COLOR_OLIVE 0xFF808000 +#define LTDC_COLOR_NAVY 0xFF000080 +#define LTDC_COLOR_PURPLE 0xFF800080 +#define LTDC_COLOR_TEAL 0xFF008080 +#define LTDC_COLOR_SILVER 0xFFC0C0C0 +#define LTDC_COLOR_GRAY 0xFF808080 +#define LTDC_COLOR_RED 0xFFFF0000 +#define LTDC_COLOR_LIME 0xFF00FF00 +#define LTDC_COLOR_YELLOW 0xFFFFFF00 +#define LTDC_COLOR_BLUE 0xFF0000FF +#define LTDC_COLOR_FUCHSIA 0xFFFF00FF +#define LTDC_COLOR_AQUA 0xFF00FFFF +#define LTDC_COLOR_WHITE 0xFFFFFFFF + +#endif /* STM32_LTDC_H */ From 43758829b8452499ea3d736028354b10f93721e8 Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Wed, 8 Jul 2015 02:48:18 +0200 Subject: [PATCH 02/26] Fixing include paths --- .../gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c b/drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c index 7077f024..e9b4e54b 100644 --- a/drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c +++ b/drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c @@ -67,12 +67,10 @@ typedef struct ltdcConfig { #define LTDC_PIXELBYTES 3 #define LTDC_PIXELBITS 24 #else - #error "GDISP: STM32F4iDiscovery - unsupported pixel format" + #error "GDISP: STM32F746Discovery - unsupported pixel format" #endif -#include "board_STM32F429iDiscovery.h" - -#include "ili9341.h" +#include "board_STM32F746Discovery.h" /*===========================================================================*/ /* Driver local definitions. */ From c610eeb65c3c1fe6656959e2b42f7dd45540635c Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Wed, 8 Jul 2015 02:52:22 +0200 Subject: [PATCH 03/26] Remove obsolete ILI9341 stuff. --- .../gdisp_lld_STM32F746Discovery.c | 73 +------------------ 1 file changed, 3 insertions(+), 70 deletions(-) diff --git a/drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c b/drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c index e9b4e54b..e27264e2 100644 --- a/drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c +++ b/drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c @@ -94,71 +94,6 @@ typedef struct ltdcConfig { /* Driver exported functions. */ /*===========================================================================*/ -static void InitController(GDisplay *g) { - #define REG_TYPEMASK 0xFF00 - #define REG_DATAMASK 0x00FF - - #define REG_DATA 0x0000 - #define REG_COMMAND 0x0100 - #define REG_DELAY 0x0200 - - static const uint16_t initdata[] = { - REG_COMMAND | ILI9341_CMD_RESET, - REG_DELAY | 5, - REG_COMMAND | ILI9341_CMD_DISPLAY_OFF, - REG_COMMAND | ILI9341_SET_FRAME_CTL_NORMAL, 0x00, 0x1B, - REG_COMMAND | ILI9341_SET_FUNCTION_CTL, 0x0A, 0xA2, - REG_COMMAND | ILI9341_SET_POWER_CTL_1, 0x10, - REG_COMMAND | ILI9341_SET_POWER_CTL_2, 0x10, - #if 1 - REG_COMMAND | ILI9341_SET_VCOM_CTL_1, 0x45, 0x15, - REG_COMMAND | ILI9341_SET_VCOM_CTL_2, 0x90, - #else - REG_COMMAND | ILI9341_SET_VCOM_CTL_1, 0x35, 0x3E, - REG_COMMAND | ILI9341_SET_VCOM_CTL_2, 0xBE, - #endif - REG_COMMAND | ILI9341_SET_MEM_ACS_CTL, 0xC8, - REG_COMMAND | ILI9341_SET_RGB_IF_SIG_CTL, 0xC2, - REG_COMMAND | ILI9341_SET_FUNCTION_CTL, 0x0A, 0xA7, 0x27, 0x04, - REG_COMMAND | ILI9341_SET_COL_ADDR, 0x00, 0x00, 0x00, 0xEF, - REG_COMMAND | ILI9341_SET_PAGE_ADDR, 0x00, 0x00, 0x01, 0x3F, - REG_COMMAND | ILI9341_SET_IF_CTL, 0x01, 0x00, 0x06, - REG_COMMAND | ILI9341_SET_GAMMA, 0x01, - REG_COMMAND | ILI9341_SET_PGAMMA, - #if 1 - 0x0F, 0x29, 0x24, 0x0C, 0x0E, 0x09, 0x4E, 0x78, - 0x3C, 0x09, 0x13, 0x05, 0x17, 0x11, 0x00, - #else - 0x1F, 0x1a, 0x18, 0x0a, 0x0f, 0x06, 0x45, 0x87, - 0x32, 0x0a, 0x07, 0x02, 0x07, 0x05, 0x00, - #endif - REG_COMMAND | ILI9341_SET_NGAMMA, - #if 1 - 0x00, 0x16, 0x1B, 0x04, 0x11, 0x07, 0x31, 0x33, - 0x42, 0x05, 0x0C, 0x0A, 0x28, 0x2F, 0x0F, - #else - 0x00, 0x25, 0x27, 0x05, 0x10, 0x09, 0x3a, 0x78, - 0x4d, 0x05, 0x18, 0x0d, 0x38, 0x3a, 0x1f, - #endif - REG_COMMAND | ILI9341_CMD_SLEEP_OFF, - REG_DELAY | 10, - REG_COMMAND | ILI9341_CMD_DISPLAY_ON, - REG_COMMAND | ILI9341_SET_MEM - }; - - const uint16_t *p; - - acquire_bus(g); - for(p = initdata; p < &initdata[sizeof(initdata)/sizeof(initdata[0])]; p++) { - switch(*p & REG_TYPEMASK) { - case REG_DATA: write_data(g, *p); break; - case REG_COMMAND: write_index(g, *p); break; - case REG_DELAY: gfxSleepMilliseconds(*p & 0xFF); break; - } - } - release_bus(g); -} - static void LTDC_Reload(void) { LTDC->SRCR |= LTDC_SRCR_IMR; while (LTDC->SRCR & (LTDC_SRCR_IMR | LTDC_SRCR_VBR)) @@ -279,9 +214,6 @@ LLDSPEC bool_t gdisp_lld_init(GDisplay *g) { init_board(g); //((fbPriv *)g->priv)->fbi.cfg = init_board(g); - // Initialise the ILI9341 controller - InitController(g); - // Initialise the LTDC controller LTDC_Init(); @@ -292,16 +224,17 @@ LLDSPEC bool_t gdisp_lld_init(GDisplay *g) { // Finish Init the board post_init_board(g); - /* Turn on the back-light */ + // Turn on the back-light set_backlight(g, GDISP_INITIAL_BACKLIGHT); - /* Initialise the GDISP structure */ + // Initialise the GDISP structure g->g.Width = driverCfg.bglayer.width; g->g.Height = driverCfg.bglayer.height; g->g.Orientation = GDISP_ROTATE_0; g->g.Powermode = powerOn; g->g.Backlight = GDISP_INITIAL_BACKLIGHT; g->g.Contrast = GDISP_INITIAL_CONTRAST; + return TRUE; } From f5f18fc2d3fd9191dda10ac7d654ce5e87e85b6a Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Wed, 8 Jul 2015 02:55:33 +0200 Subject: [PATCH 04/26] Whitespaces --- .../gdisp_lld_STM32F746Discovery.c | 26 ++++++++++++------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c b/drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c index e27264e2..c46bf27e 100644 --- a/drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c +++ b/drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c @@ -94,13 +94,17 @@ typedef struct ltdcConfig { /* Driver exported functions. */ /*===========================================================================*/ -static void LTDC_Reload(void) { +static void LTDC_Reload(void) +{ LTDC->SRCR |= LTDC_SRCR_IMR; - while (LTDC->SRCR & (LTDC_SRCR_IMR | LTDC_SRCR_VBR)) + + while (LTDC->SRCR & (LTDC_SRCR_IMR | LTDC_SRCR_VBR)) { gfxYield(); + } } -static void LTDC_LayerInit(LTDC_Layer_TypeDef *pLayReg, const ltdcLayerConfig * pCfg) { +static void LTDC_LayerInit(LTDC_Layer_TypeDef* pLayReg, const ltdcLayerConfig* pCfg) +{ static const uint8_t fmt2Bpp[] = { 4, /* LTDC_FMT_ARGB8888 */ 3, /* LTDC_FMT_RGB888 */ @@ -139,7 +143,8 @@ static void LTDC_LayerInit(LTDC_Layer_TypeDef *pLayReg, const ltdcLayerConfig * pLayReg->CR = (pLayReg->CR & ~LTDC_LEF_MASK) | ((uint32_t)pCfg->layerflags & LTDC_LEF_MASK); } -static void LTDC_Init(void) { +static void LTDC_Init(void) +{ // Set up the display scanning uint32_t hacc, vacc; @@ -202,8 +207,8 @@ static void LTDC_Init(void) { LTDC_Reload(); } -LLDSPEC bool_t gdisp_lld_init(GDisplay *g) { - +LLDSPEC bool_t gdisp_lld_init(GDisplay* g) +{ // Initialize the private structure g->priv = 0; g->board = 0; @@ -238,7 +243,8 @@ LLDSPEC bool_t gdisp_lld_init(GDisplay *g) { return TRUE; } -LLDSPEC void gdisp_lld_draw_pixel(GDisplay *g) { +LLDSPEC void gdisp_lld_draw_pixel(GDisplay* g) +{ unsigned pos; #if GDISP_NEED_CONTROL @@ -264,7 +270,8 @@ LLDSPEC void gdisp_lld_draw_pixel(GDisplay *g) { PIXEL_ADDR(g, pos)[0] = gdispColor2Native(g->p.color); } -LLDSPEC color_t gdisp_lld_get_pixel_color(GDisplay *g) { +LLDSPEC color_t gdisp_lld_get_pixel_color(GDisplay* g) +{ unsigned pos; LLDCOLOR_TYPE color; @@ -293,7 +300,8 @@ LLDSPEC color_t gdisp_lld_get_pixel_color(GDisplay *g) { } #if GDISP_NEED_CONTROL - LLDSPEC void gdisp_lld_control(GDisplay *g) { + LLDSPEC void gdisp_lld_control(GDisplay* g) + { switch(g->p.x) { case GDISP_CONTROL_POWER: if (g->g.Powermode == (powermode_t)g->p.ptr) From ac231c558c7c9758c487f5407017d406299c49cb Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Wed, 8 Jul 2015 03:26:23 +0200 Subject: [PATCH 05/26] Adding some board file stuff for the F7 discovery (nothing done yet, just adding the required files) --- boards/base/STM32F746-Discovery/board.mk | 5 + .../board_STM32F746Discovery.h | 85 ++ .../stm32746g_discovery_sdram.c | 499 ++++++ .../stm32746g_discovery_sdram.h | 165 ++ .../stm32f429i_discovery_sdram.c | 333 ++++ .../stm32f429i_discovery_sdram.h | 96 ++ .../STM32F746-Discovery/stm32f7xx_ll_fmc.c | 1123 ++++++++++++++ .../STM32F746-Discovery/stm32f7xx_ll_fmc.h | 1337 +++++++++++++++++ .../board_STM32F746Discovery_template.h | 22 +- .../gdisp_lld_STM32F746Discovery.c | 1 + drivers/gdisp/STM32F746Discovery/readme.txt | 2 +- 11 files changed, 3650 insertions(+), 18 deletions(-) create mode 100644 boards/base/STM32F746-Discovery/board.mk create mode 100644 boards/base/STM32F746-Discovery/board_STM32F746Discovery.h create mode 100644 boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.c create mode 100644 boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.h create mode 100644 boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.c create mode 100644 boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.h create mode 100644 boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c create mode 100644 boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.h diff --git a/boards/base/STM32F746-Discovery/board.mk b/boards/base/STM32F746-Discovery/board.mk new file mode 100644 index 00000000..92854414 --- /dev/null +++ b/boards/base/STM32F746-Discovery/board.mk @@ -0,0 +1,5 @@ +GFXINC += $(GFXLIB)/boards/base/STM32F746-Discovery +GFXSRC += $(GFXLIB)/boards/base/STM32F746-Discovery/STM32F746_discovery_sdram.c \ + $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f4xx_fmc.c + +include $(GFXLIB)/drivers/gdisp/STM32F746Discovery/driver.mk \ No newline at end of file diff --git a/boards/base/STM32F746-Discovery/board_STM32F746Discovery.h b/boards/base/STM32F746-Discovery/board_STM32F746Discovery.h new file mode 100644 index 00000000..c06d06c6 --- /dev/null +++ b/boards/base/STM32F746-Discovery/board_STM32F746Discovery.h @@ -0,0 +1,85 @@ +/* + * This file is subject to the terms of the GFX License. If a copy of + * the license was not distributed with this file, you can obtain one at: + * + * http://ugfx.org/license.html + */ + +#ifndef _GDISP_LLD_BOARD_H +#define _GDISP_LLD_BOARD_H + +#include "stm32f4xx_fmc.h" +#include "stm32f429i_discovery_sdram.h" +#include + +static const ltdcConfig driverCfg = { + 480, 270, // Width, Height (pixels) + 10, 2, // Horizontal, Vertical sync (pixels) + 20, 2, // Horizontal, Vertical back porch (pixels) + 10, 4, // Horizontal, Vertical front porch (pixels) + 0, // Sync flags + 0x000000, // Clear color (RGB888) + + { // Background layer config + (LLDCOLOR_TYPE *)SDRAM_BANK_ADDR, // Frame buffer address + 480, 270, // Width, Height (pixels) + 480 * LTDC_PIXELBYTES, // Line pitch (bytes) + LTDC_PIXELFORMAT, // Pixel format + 0, 0, // Start pixel position (x, y) + 480, 270, // Size of virtual layer (cx, cy) + LTDC_COLOR_FUCHSIA, // Default color (ARGB8888) + 0x980088, // Color key (RGB888) + LTDC_BLEND_FIX1_FIX2, // Blending factors + 0, // Palette (RGB888, can be NULL) + 0, // Palette length + 0xFF, // Constant alpha factor + LTDC_LEF_ENABLE // Layer configuration flags + }, + + LTDC_UNUSED_LAYER_CONFIG // Foreground layer config +}; + +static inline void init_board(GDisplay *g) { + + // As we are not using multiple displays we set g->board to NULL as we don't use it. + g->board = 0; + + switch(g->controllerdisplay) { + case 0: + #define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */ + #define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */ + #define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */ + #define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */ + #define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */ + #define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */ + + #define STM32_PLLSAIN_VALUE 192 + #define STM32_PLLSAIQ_VALUE 7 + #define STM32_PLLSAIR_VALUE 4 + #define STM32_PLLSAIR_POST STM32_SAIR_DIV4 + + /* PLLSAI activation.*/ + RCC->PLLSAICFGR = (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24); + RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST; + RCC->CR |= RCC_CR_PLLSAION; + + // Initialise the SDRAM + SDRAM_Init(); + + // Clear the SDRAM + memset((void *)SDRAM_BANK_ADDR, 0, 0x400000); + + break; + } +} + +static inline void post_init_board(GDisplay *g) { + (void) g; +} + +static inline void set_backlight(GDisplay *g, uint8_t percent) { + (void) g; + (void) percent; +} + +#endif /* _GDISP_LLD_BOARD_H */ diff --git a/boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.c b/boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.c new file mode 100644 index 00000000..d214b3f1 --- /dev/null +++ b/boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.c @@ -0,0 +1,499 @@ +/** + ****************************************************************************** + * @file stm32746g_discovery_sdram.c + * @author MCD Application Team + * @version V1.0.0 + * @date 25-June-2015 + * @brief This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory + * device mounted on STM32746G-Discovery board. + @verbatim + 1. How To use this driver: + -------------------------- + - This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted + on STM32746G-Discovery board. + - This driver does not need a specific component driver for the SDRAM device + to be included with. + + 2. Driver description: + --------------------- + + Initialization steps: + o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This + function includes the MSP layer hardware resources initialization and the + FMC controller configuration to interface with the external SDRAM memory. + o It contains the SDRAM initialization sequence to program the SDRAM external + device using the function BSP_SDRAM_Initialization_sequence(). Note that this + sequence is standard for all SDRAM devices, but can include some differences + from a device to another. If it is the case, the right sequence should be + implemented separately. + + + SDRAM read/write operations + o SDRAM external memory can be accessed with read/write operations once it is + initialized. + Read/write operation can be performed with AHB access using the functions + BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions + BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA(). + o The AHB access is performed with 32-bit width transaction, the DMA transfer + configuration is fixed at single (no burst) word transfer (see the + SDRAM_MspInit() static function). + o User can implement his own functions for read/write access with his desired + configurations. + o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler() + is called in IRQ handler file, to serve the generated interrupt once the DMA + transfer is complete. + o You can send a command to the SDRAM device in runtime using the function + BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between + the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32746g_discovery_sdram.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup STM32746G_DISCOVERY + * @{ + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM STM32746G_DISCOVERY_SDRAM + * @{ + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Types_Definitions STM32746G_DISCOVERY_SDRAM Private Types Definitions + * @{ + */ +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Defines STM32746G_DISCOVERY_SDRAM Private Defines + * @{ + */ +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Macros STM32746G_DISCOVERY_SDRAM Private Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Variables STM32746G_DISCOVERY_SDRAM Private Variables + * @{ + */ +static SDRAM_HandleTypeDef sdramHandle; +static FMC_SDRAM_TimingTypeDef Timing; +static FMC_SDRAM_CommandTypeDef Command; +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Function_Prototypes STM32746G_DISCOVERY_SDRAM Private Function Prototypes + * @{ + */ +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Functions STM32746G_DISCOVERY_SDRAM Exported Functions + * @{ + */ + +/** + * @brief Initializes the SDRAM device. + * @retval SDRAM status + */ +uint8_t BSP_SDRAM_Init(void) +{ + static uint8_t sdramstatus = SDRAM_ERROR; + /* SDRAM device configuration */ + sdramHandle.Instance = FMC_SDRAM_DEVICE; + + /* Timing configuration for 100Mhz as SD clock frequency (System clock is up to 200Mhz) */ + Timing.LoadToActiveDelay = 2; + Timing.ExitSelfRefreshDelay = 7; + Timing.SelfRefreshTime = 4; + Timing.RowCycleDelay = 7; + Timing.WriteRecoveryTime = 2; + Timing.RPDelay = 2; + Timing.RCDDelay = 2; + + sdramHandle.Init.SDBank = FMC_SDRAM_BANK1; + sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8; + sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; + sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH; + sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; + sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2; + sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; + sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD; + sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE; + sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0; + + /* SDRAM controller initialization */ + + BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */ + + if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK) + { + sdramstatus = SDRAM_ERROR; + } + else + { + sdramstatus = SDRAM_OK; + } + + /* SDRAM initialization sequence */ + BSP_SDRAM_Initialization_sequence(REFRESH_COUNT); + + return sdramstatus; +} + +/** + * @brief DeInitializes the SDRAM device. + * @retval SDRAM status + */ +uint8_t BSP_SDRAM_DeInit(void) +{ + static uint8_t sdramstatus = SDRAM_ERROR; + /* SDRAM device de-initialization */ + sdramHandle.Instance = FMC_SDRAM_DEVICE; + + if(HAL_SDRAM_DeInit(&sdramHandle) != HAL_OK) + { + sdramstatus = SDRAM_ERROR; + } + else + { + sdramstatus = SDRAM_OK; + } + + /* SDRAM controller de-initialization */ + BSP_SDRAM_MspDeInit(&sdramHandle, NULL); + + return sdramstatus; +} + +/** + * @brief Programs the SDRAM device. + * @param RefreshCount: SDRAM refresh counter value + * @retval None + */ +void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) +{ + __IO uint32_t tmpmrd = 0; + + /* Step 1: Configure a clock configuration enable command */ + Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE; + Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + Command.AutoRefreshNumber = 1; + Command.ModeRegisterDefinition = 0; + + /* Send the command */ + HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + + /* Step 2: Insert 100 us minimum delay */ + /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */ + HAL_Delay(1); + + /* Step 3: Configure a PALL (precharge all) command */ + Command.CommandMode = FMC_SDRAM_CMD_PALL; + Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + Command.AutoRefreshNumber = 1; + Command.ModeRegisterDefinition = 0; + + /* Send the command */ + HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + + /* Step 4: Configure an Auto Refresh command */ + Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE; + Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + Command.AutoRefreshNumber = 8; + Command.ModeRegisterDefinition = 0; + + /* Send the command */ + HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + + /* Step 5: Program the external memory mode register */ + tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\ + SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\ + SDRAM_MODEREG_CAS_LATENCY_2 |\ + SDRAM_MODEREG_OPERATING_MODE_STANDARD |\ + SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; + + Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE; + Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + Command.AutoRefreshNumber = 1; + Command.ModeRegisterDefinition = tmpmrd; + + /* Send the command */ + HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); + + /* Step 6: Set the refresh rate counter */ + /* Set the device refresh rate */ + HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount); +} + +/** + * @brief Reads an amount of data from the SDRAM memory in polling mode. + * @param uwStartAddress: Read start address + * @param pData: Pointer to data to be read + * @param uwDataSize: Size of read data from the memory + * @retval SDRAM status + */ +uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) +{ + if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) + { + return SDRAM_ERROR; + } + else + { + return SDRAM_OK; + } +} + +/** + * @brief Reads an amount of data from the SDRAM memory in DMA mode. + * @param uwStartAddress: Read start address + * @param pData: Pointer to data to be read + * @param uwDataSize: Size of read data from the memory + * @retval SDRAM status + */ +uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) +{ + if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) + { + return SDRAM_ERROR; + } + else + { + return SDRAM_OK; + } +} + +/** + * @brief Writes an amount of data to the SDRAM memory in polling mode. + * @param uwStartAddress: Write start address + * @param pData: Pointer to data to be written + * @param uwDataSize: Size of written data from the memory + * @retval SDRAM status + */ +uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) +{ + if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) + { + return SDRAM_ERROR; + } + else + { + return SDRAM_OK; + } +} + +/** + * @brief Writes an amount of data to the SDRAM memory in DMA mode. + * @param uwStartAddress: Write start address + * @param pData: Pointer to data to be written + * @param uwDataSize: Size of written data from the memory + * @retval SDRAM status + */ +uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) +{ + if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) + { + return SDRAM_ERROR; + } + else + { + return SDRAM_OK; + } +} + +/** + * @brief Sends command to the SDRAM bank. + * @param SdramCmd: Pointer to SDRAM command structure + * @retval SDRAM status + */ +uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd) +{ + if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK) + { + return SDRAM_ERROR; + } + else + { + return SDRAM_OK; + } +} + +/** + * @brief Handles SDRAM DMA transfer interrupt request. + * @retval None + */ +void BSP_SDRAM_DMA_IRQHandler(void) +{ + HAL_DMA_IRQHandler(sdramHandle.hdma); +} + +/** + * @brief Initializes SDRAM MSP. + * @param hsdram: SDRAM handle + * @param Params + * @retval None + */ +__weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params) +{ + static DMA_HandleTypeDef dma_handle; + GPIO_InitTypeDef gpio_init_structure; + + /* Enable FMC clock */ + __HAL_RCC_FMC_CLK_ENABLE(); + + /* Enable chosen DMAx clock */ + __DMAx_CLK_ENABLE(); + + /* Enable GPIOs clock */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + + /* Common GPIO configuration */ + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + gpio_init_structure.Pull = GPIO_PULLUP; + gpio_init_structure.Speed = GPIO_SPEED_FAST; + gpio_init_structure.Alternate = GPIO_AF12_FMC; + + /* GPIOC configuration */ + gpio_init_structure.Pin = GPIO_PIN_3; + HAL_GPIO_Init(GPIOC, &gpio_init_structure); + + /* GPIOD configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_8 | GPIO_PIN_9 | + GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15; + HAL_GPIO_Init(GPIOD, &gpio_init_structure); + + /* GPIOE configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\ + GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ + GPIO_PIN_15; + HAL_GPIO_Init(GPIOE, &gpio_init_structure); + + /* GPIOF configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\ + GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ + GPIO_PIN_15; + HAL_GPIO_Init(GPIOF, &gpio_init_structure); + + /* GPIOG configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\ + GPIO_PIN_15; + HAL_GPIO_Init(GPIOG, &gpio_init_structure); + + /* GPIOH configuration */ + gpio_init_structure.Pin = GPIO_PIN_3 | GPIO_PIN_5; + HAL_GPIO_Init(GPIOH, &gpio_init_structure); + + /* Configure common DMA parameters */ + dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL; + dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY; + dma_handle.Init.PeriphInc = DMA_PINC_ENABLE; + dma_handle.Init.MemInc = DMA_MINC_ENABLE; + dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + dma_handle.Init.Mode = DMA_NORMAL; + dma_handle.Init.Priority = DMA_PRIORITY_HIGH; + dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + dma_handle.Init.MemBurst = DMA_MBURST_SINGLE; + dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE; + + dma_handle.Instance = SDRAM_DMAx_STREAM; + + /* Associate the DMA handle */ + __HAL_LINKDMA(hsdram, hdma, dma_handle); + + /* Deinitialize the stream for new transfer */ + HAL_DMA_DeInit(&dma_handle); + + /* Configure the DMA stream */ + HAL_DMA_Init(&dma_handle); + + /* NVIC configuration for DMA transfer complete interrupt */ + HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn); +} + +/** + * @brief DeInitializes SDRAM MSP. + * @param hsdram: SDRAM handle + * @param Params + * @retval None + */ +__weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params) +{ + static DMA_HandleTypeDef dma_handle; + + /* Disable NVIC configuration for DMA interrupt */ + HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn); + + /* Deinitialize the stream for new transfer */ + dma_handle.Instance = SDRAM_DMAx_STREAM; + HAL_DMA_DeInit(&dma_handle); + + /* GPIO pins clock, FMC clock and DMA clock can be shut down in the applications + by surcharging this __weak function */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.h b/boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.h new file mode 100644 index 00000000..cafdce5c --- /dev/null +++ b/boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.h @@ -0,0 +1,165 @@ +/** + ****************************************************************************** + * @file stm32746g_discovery_sdram.h + * @author MCD Application Team + * @version V1.0.0 + * @date 25-June-2015 + * @brief This file contains the common defines and functions prototypes for + * the stm32746g_discovery_sdram.c driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32746G_DISCOVERY_SDRAM_H +#define __STM32746G_DISCOVERY_SDRAM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup STM32746G_DISCOVERY + * @{ + */ + +/** @addtogroup STM32746G_DISCOVERY_SDRAM + * @{ + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Types STM32746G_DISCOVERY_SDRAM Exported Types + * @{ + */ + +/** + * @brief SDRAM status structure definition + */ +#define SDRAM_OK ((uint8_t)0x00) +#define SDRAM_ERROR ((uint8_t)0x01) + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Constants STM32746G_DISCOVERY_SDRAM Exported Constants + * @{ + */ +#define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000) +#define SDRAM_DEVICE_SIZE ((uint32_t)0x800000) /* SDRAM device size in MBytes */ + +/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */ +#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16 + +#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2 +/* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */ + +#define REFRESH_COUNT ((uint32_t)0x0603) /* SDRAM refresh counter (100Mhz SD clock) */ + +#define SDRAM_TIMEOUT ((uint32_t)0xFFFF) + +/* DMA definitions for SDRAM DMA transfer */ +#define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMAx_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0 +#define SDRAM_DMAx_STREAM DMA2_Stream0 +#define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn +#define SDRAM_DMAx_IRQHandler DMA2_Stream0_IRQHandler +/** + * @} + */ + +/** + * @brief FMC SDRAM Mode definition register defines + */ +#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) +#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) +#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) +#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) +#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) +#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) +/** + * @} + */ + +/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Macro STM32746G_DISCOVERY_SDRAM Exported Macro + * @{ + */ +/** + * @} + */ + +/** @addtogroup STM32746G_DISCOVERY_SDRAM_Exported_Functions + * @{ + */ +uint8_t BSP_SDRAM_Init(void); +uint8_t BSP_SDRAM_DeInit(void); +void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount); +uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); +uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); +uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); +uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); +uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd); +void BSP_SDRAM_DMA_IRQHandler(void); + +/* These functions can be modified in case the current settings (e.g. DMA stream) + need to be changed for specific application needs */ +void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params); +void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params); + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32746G_DISCOVERY_SDRAM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.c b/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.c new file mode 100644 index 00000000..3b467b4b --- /dev/null +++ b/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.c @@ -0,0 +1,333 @@ +#include "ch.h" +#include "hal.h" + +#include "stm32f429i_discovery_sdram.h" +#include "stm32f4xx_fmc.h" + +/** + * @brief Configures the FMC and GPIOs to interface with the SDRAM memory. + * This function must be called before any read/write operation + * on the SDRAM. + * @param None + * @retval None + */ +void SDRAM_Init(void) +{ + FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure; + FMC_SDRAMTimingInitTypeDef FMC_SDRAMTimingInitStructure; + + /* Enable FMC clock */ + rccEnableAHB3(RCC_AHB3ENR_FMCEN, FALSE); + +/* FMC Configuration ---------------------------------------------------------*/ +/* FMC SDRAM Bank configuration */ + /* Timing configuration for 84 Mhz of SD clock frequency (168Mhz/2) */ + /* TMRD: 2 Clock cycles */ + FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2; + /* TXSR: min=70ns (6x11.90ns) */ + FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 7; + /* TRAS: min=42ns (4x11.90ns) max=120k (ns) */ + FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4; + /* TRC: min=63 (6x11.90ns) */ + FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 7; + /* TWR: 2 Clock cycles */ + FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2; + /* TRP: 15ns => 2x11.90ns */ + FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2; + /* TRCD: 15ns => 2x11.90ns */ + FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2; + +/* FMC SDRAM control configuration */ + FMC_SDRAMInitStructure.FMC_Bank = FMC_Bank2_SDRAM; + /* Row addressing: [7:0] */ + FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b; + /* Column addressing: [11:0] */ + FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_12b; + FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = SDRAM_MEMORY_WIDTH; + FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4; + FMC_SDRAMInitStructure.FMC_CASLatency = SDRAM_CAS_LATENCY; + FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable; + FMC_SDRAMInitStructure.FMC_SDClockPeriod = SDCLOCK_PERIOD; + FMC_SDRAMInitStructure.FMC_ReadBurst = SDRAM_READBURST; + FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1; + FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure; + + /* FMC SDRAM bank initialization */ + FMC_SDRAMInit(&FMC_SDRAMInitStructure); + + /* FMC SDRAM device initialization sequence */ + SDRAM_InitSequence(); + +} + +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+--------------------+--------------------+ + + SDRAM pins assignment + + +-------------------+--------------------+--------------------+--------------------+ + | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 | + | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 | + | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF2 <-> FMC_A2 | PG8 <-> FMC_SDCLK | + | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF3 <-> FMC_A3 | PG15 <-> FMC_NCAS | + | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF4 <-> FMC_A4 |--------------------+ + | PD14 <-> FMC_D0 | PE10 <-> FMC_D7 | PF5 <-> FMC_A5 | + | PD15 <-> FMC_D1 | PE11 <-> FMC_D8 | PF11 <-> FMC_NRAS | + +-------------------| PE12 <-> FMC_D9 | PF12 <-> FMC_A6 | + | PE13 <-> FMC_D10 | PF13 <-> FMC_A7 | + | PE14 <-> FMC_D11 | PF14 <-> FMC_A8 | + | PE15 <-> FMC_D12 | PF15 <-> FMC_A9 | + +-------------------+--------------------+--------------------+ + | PB5 <-> FMC_SDCKE1| + | PB6 <-> FMC_SDNE1 | + | PC0 <-> FMC_SDNWE | + +-------------------+ + +*/ + +// /* Common GPIO configuration */ +// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; +// GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +// GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; +// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; +// +// /* GPIOB configuration */ +// GPIO_PinAFConfig(GPIOB, GPIO_PinSource5 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOB, GPIO_PinSource6 , GPIO_AF_FMC); +// +// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6; +// +// GPIO_Init(GPIOB, &GPIO_InitStructure); +// +// /* GPIOC configuration */ +// GPIO_PinAFConfig(GPIOC, GPIO_PinSource0 , GPIO_AF_FMC); +// +// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; +// +// GPIO_Init(GPIOC, &GPIO_InitStructure); +// +// /* GPIOD configuration */ +// GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FMC); +// +// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | +// GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | +// GPIO_Pin_15; +// +// GPIO_Init(GPIOD, &GPIO_InitStructure); +// +// /* GPIOE configuration */ +// GPIO_PinAFConfig(GPIOE, GPIO_PinSource0 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOE, GPIO_PinSource1 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FMC); +// +// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_7 | +// GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | +// GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | +// GPIO_Pin_14 | GPIO_Pin_15; +// +// GPIO_Init(GPIOE, &GPIO_InitStructure); +// +// /* GPIOF configuration */ +// GPIO_PinAFConfig(GPIOF, GPIO_PinSource0 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOF, GPIO_PinSource1 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOF, GPIO_PinSource2 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOF, GPIO_PinSource3 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOF, GPIO_PinSource4 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOF, GPIO_PinSource5 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOF, GPIO_PinSource11 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOF, GPIO_PinSource12 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOF, GPIO_PinSource13 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOF, GPIO_PinSource14 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOF, GPIO_PinSource15 , GPIO_AF_FMC); +// +// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | +// GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | +// GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | +// GPIO_Pin_14 | GPIO_Pin_15; +// +// GPIO_Init(GPIOF, &GPIO_InitStructure); +// +// /* GPIOG configuration */ +// GPIO_PinAFConfig(GPIOG, GPIO_PinSource0 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOG, GPIO_PinSource1 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOG, GPIO_PinSource4 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOG, GPIO_PinSource5 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOG, GPIO_PinSource8 , GPIO_AF_FMC); +// GPIO_PinAFConfig(GPIOG, GPIO_PinSource15 , GPIO_AF_FMC); +// +// +// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | +// GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_15; +// +// GPIO_Init(GPIOG, &GPIO_InitStructure); + +/** + * @brief Executes the SDRAM memory initialization sequence. + * @param None. + * @retval None. + */ +void SDRAM_InitSequence(void) +{ + FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure; + uint32_t tmpr = 0; + +/* Step 3 --------------------------------------------------------------------*/ + /* Configure a clock configuration enable command */ + FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled; + FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; + FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; + FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; + /* Wait until the SDRAM controller is ready */ + while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) + { + } + /* Send the command */ + FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); + + //In the ST example, this is 100ms, but the 429 RM says 100us is typical, and + //the ISSI datasheet confirms this. 1ms seems plenty, and is much shorter than + //refresh interval, meaning we won't risk losing contents if the SDRAM is in self-refresh + //mode +/* Step 4 --------------------------------------------------------------------*/ + /* Insert 1 ms delay */ + chThdSleepMilliseconds(1); + +/* Step 5 --------------------------------------------------------------------*/ + /* Configure a PALL (precharge all) command */ + FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL; + FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; + FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; + FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; + /* Wait until the SDRAM controller is ready */ + while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) + { + } + /* Send the command */ + FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); + +/* Step 6 --------------------------------------------------------------------*/ + /* Configure a Auto-Refresh command */ + FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh; + FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; + FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 4; + FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; + /* Wait until the SDRAM controller is ready */ + while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) + { + } + /* Send the first command */ + FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); + + /* Wait until the SDRAM controller is ready */ + while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) + { + } + /* Send the second command */ + FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); + +/* Step 7 --------------------------------------------------------------------*/ + /* Program the external memory mode register */ + tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 | + SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | + SDRAM_MODEREG_CAS_LATENCY_3 | + SDRAM_MODEREG_OPERATING_MODE_STANDARD | + SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; + + /* Configure a load Mode register command*/ + FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode; + FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; + FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; + FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr; + /* Wait until the SDRAM controller is ready */ + while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) + { + } + /* Send the command */ + FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); + +/* Step 8 --------------------------------------------------------------------*/ + + /* Set the refresh rate counter */ + /* (7.81 us x Freq) - 20 */ + /* Set the device refresh counter */ + FMC_SetRefreshCount(683); + /* Wait until the SDRAM controller is ready */ + while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) + { + } +} + + +/** + * @brief Writes a Entire-word buffer to the SDRAM memory. + * @param pBuffer: pointer to buffer. + * @param uwWriteAddress: SDRAM memory internal address from which the data will be + * written. + * @param uwBufferSize: number of words to write. + * @retval None. + */ +void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize) +{ + __IO uint32_t write_pointer = (uint32_t)uwWriteAddress; + + /* Disable write protection */ + FMC_SDRAMWriteProtectionConfig(FMC_Bank2_SDRAM, DISABLE); + + /* Wait until the SDRAM controller is ready */ + while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) + { + } + + /* While there is data to write */ + for (; uwBufferSize != 0; uwBufferSize--) + { + /* Transfer data to the memory */ + *(uint32_t *) (SDRAM_BANK_ADDR + write_pointer) = *pBuffer++; + + /* Increment the address*/ + write_pointer += 4; + } + +} + +/** + * @brief Reads data buffer from the SDRAM memory. + * @param pBuffer: pointer to buffer. + * @param ReadAddress: SDRAM memory internal address from which the data will be + * read. + * @param uwBufferSize: number of words to write. + * @retval None. + */ +void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize) +{ + __IO uint32_t write_pointer = (uint32_t)uwReadAddress; + + + /* Wait until the SDRAM controller is ready */ + while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) + { + } + + /* Read data */ + for(; uwBufferSize != 0x00; uwBufferSize--) + { + *pBuffer++ = *(__IO uint32_t *)(SDRAM_BANK_ADDR + write_pointer ); + + /* Increment the address*/ + write_pointer += 4; + } +} + diff --git a/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.h b/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.h new file mode 100644 index 00000000..fba5115d --- /dev/null +++ b/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.h @@ -0,0 +1,96 @@ +/** + ****************************************************************************** + * @file stm32f429i_discovery_sdram.h + * @author MCD Application Team + * @version V1.0.0 + * @date 20-September-2013 + * @brief This file contains all the functions prototypes for the + * stm324x9i_disco_sdram.c driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2013 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32429I_DISCO_SDRAM_H +#define __STM32429I_DISCO_SDRAM_H + +#ifdef __cplusplus + extern "C" { +#endif + +//FIXME this should not be needed +#define STM32F429_439xx + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** + * @brief FMC SDRAM Bank address + */ +#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000) + +/** + * @brief FMC SDRAM Memory Width + */ +/* #define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_8b */ +#define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_16b + +/** + * @brief FMC SDRAM CAS Latency + */ +/* #define SDRAM_CAS_LATENCY FMC_CAS_Latency_2 */ +#define SDRAM_CAS_LATENCY FMC_CAS_Latency_3 + +/** + * @brief FMC SDRAM Memory clock period + */ +#define SDCLOCK_PERIOD FMC_SDClock_Period_2 /* Default configuration used with LCD */ +/* #define SDCLOCK_PERIOD FMC_SDClock_Period_3 */ + +/** + * @brief FMC SDRAM Memory Read Burst feature + */ +#define SDRAM_READBURST FMC_Read_Burst_Disable /* Default configuration used with LCD */ +/* #define SDRAM_READBURST FMC_Read_Burst_Enable */ + +/** + * @brief FMC SDRAM Mode definition register defines + */ +#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) +#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) +#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) +#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) +#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) +#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) + +void SDRAM_Init(void); +void SDRAM_InitSequence(void); +void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize); +void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c b/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c new file mode 100644 index 00000000..38adbcae --- /dev/null +++ b/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c @@ -0,0 +1,1123 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_fmc.c + * @author MCD Application Team + * @version V1.0.1 + * @date 25-June-2015 + * @brief FMC Low Layer HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Flexible Memory Controller (FMC) peripheral memories: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### FMC peripheral features ##### + ============================================================================== + [..] The Flexible memory controller (FMC) includes three memory controllers: + (+) The NOR/PSRAM memory controller + (+) The NAND memory controller + (+) The Synchronous DRAM (SDRAM) controller + + [..] The FMC functional block makes the interface with synchronous and asynchronous static + memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are: + (+) to translate AHB transactions into the appropriate external device protocol + (+) to meet the access time requirements of the external memory devices + + [..] All external memories share the addresses, data and control signals with the controller. + Each external device is accessed by means of a unique Chip Select. The FMC performs + only one access at a time to an external device. + The main features of the FMC controller are the following: + (+) Interface with static-memory mapped devices including: + (++) Static random access memory (SRAM) + (++) Read-only memory (ROM) + (++) NOR Flash memory/OneNAND Flash memory + (++) PSRAM (4 memory banks) + (++) 16-bit PC Card compatible devices + (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of + data + (+) Interface with synchronous DRAM (SDRAM) memories + (+) Independent Chip Select control for each memory bank + (+) Independent configuration for each memory bank + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup FMC_LL FMC Low Layer + * @brief FMC driver modules + * @{ + */ + +#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions + * @{ + */ + +/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions + * @brief NORSRAM Controller functions + * + @verbatim + ============================================================================== + ##### How to use NORSRAM device driver ##### + ============================================================================== + + [..] + This driver contains a set of APIs to interface with the FMC NORSRAM banks in order + to run the NORSRAM external devices. + + (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() + (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init() + (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init() + (+) FMC NORSRAM bank extended timing configuration using the function + FMC_NORSRAM_Extended_Timing_Init() + (+) FMC NORSRAM bank enable/disable write operation using the functions + FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() + + +@endverbatim + * @{ + */ + +/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FMC NORSRAM interface + (+) De-initialize the FMC NORSRAM interface + (+) Configure the FMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the FMC_NORSRAM device according to the specified + * control parameters in the FMC_NORSRAM_InitTypeDef + * @param Device: Pointer to NORSRAM device instance + * @param Init: Pointer to NORSRAM Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init) +{ + uint32_t tmpr = 0; + + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); + assert_param(IS_FMC_MUX(Init->DataAddressMux)); + assert_param(IS_FMC_MEMORY(Init->MemoryType)); + assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); + assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); + assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); + assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); + assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); + assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); + assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); + assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); + assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); + assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); + assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); + assert_param(IS_FMC_PAGESIZE(Init->PageSize)); + + /* Get the BTCR register value */ + tmpr = Device->BTCR[Init->NSBank]; + + /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN, + WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */ + tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \ + FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \ + FMC_BCR1_WAITPOL | FMC_BCR1_CPSIZE | FMC_BCR1_WAITCFG | \ + FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \ + FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS)); + + /* Set NORSRAM device control parameters */ + tmpr |= (uint32_t)(Init->DataAddressMux |\ + Init->MemoryType |\ + Init->MemoryDataWidth |\ + Init->BurstAccessMode |\ + Init->WaitSignalPolarity |\ + Init->WaitSignalActive |\ + Init->WriteOperation |\ + Init->WaitSignal |\ + Init->ExtendedMode |\ + Init->AsynchronousWait |\ + Init->WriteBurst |\ + Init->ContinuousClock |\ + Init->PageSize |\ + Init->WriteFifo); + + if(Init->MemoryType == FMC_MEMORY_TYPE_NOR) + { + tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE; + } + + Device->BTCR[Init->NSBank] = tmpr; + + /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ + if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) + { + Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE; + Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode |\ + Init->ContinuousClock); + } + if(Init->NSBank != FMC_NORSRAM_BANK1) + { + Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo); + } + + return HAL_OK; +} + + +/** + * @brief DeInitialize the FMC_NORSRAM peripheral + * @param Device: Pointer to NORSRAM device instance + * @param ExDevice: Pointer to NORSRAM extended mode device instance + * @param Bank: NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Disable the FMC_NORSRAM device */ + __FMC_NORSRAM_DISABLE(Device, Bank); + + /* De-initialize the FMC_NORSRAM device */ + /* FMC_NORSRAM_BANK1 */ + if(Bank == FMC_NORSRAM_BANK1) + { + Device->BTCR[Bank] = 0x000030DB; + } + /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */ + else + { + Device->BTCR[Bank] = 0x000030D2; + } + + Device->BTCR[Bank + 1] = 0x0FFFFFFF; + ExDevice->BWTR[Bank] = 0x0FFFFFFF; + + return HAL_OK; +} + + +/** + * @brief Initialize the FMC_NORSRAM Timing according to the specified + * parameters in the FMC_NORSRAM_TimingTypeDef + * @param Device: Pointer to NORSRAM device instance + * @param Timing: Pointer to NORSRAM Timing structure + * @param Bank: NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) +{ + uint32_t tmpr = 0; + + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); + assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); + assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); + assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); + assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); + assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); + assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Get the BTCR register value */ + tmpr = Device->BTCR[Bank + 1]; + + /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ + tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \ + FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \ + FMC_BTR1_ACCMOD)); + + /* Set FMC_NORSRAM device timing parameters */ + tmpr |= (uint32_t)(Timing->AddressSetupTime |\ + ((Timing->AddressHoldTime) << 4) |\ + ((Timing->DataSetupTime) << 8) |\ + ((Timing->BusTurnAroundDuration) << 16) |\ + (((Timing->CLKDivision)-1) << 20) |\ + (((Timing->DataLatency)-2) << 24) |\ + (Timing->AccessMode) + ); + + Device->BTCR[Bank + 1] = tmpr; + + /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ + if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) + { + tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20)); + tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20); + Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr; + } + + return HAL_OK; +} + +/** + * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified + * parameters in the FMC_NORSRAM_TimingTypeDef + * @param Device: Pointer to NORSRAM device instance + * @param Timing: Pointer to NORSRAM Timing structure + * @param Bank: NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) +{ + uint32_t tmpr = 0; + + /* Check the parameters */ + assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); + + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ + if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE) + { + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); + assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); + assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); + assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); + assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); + assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); + assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); + assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Get the BWTR register value */ + tmpr = Device->BWTR[Bank]; + + /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ + tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \ + FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD)); + + tmpr |= (uint32_t)(Timing->AddressSetupTime |\ + ((Timing->AddressHoldTime) << 4) |\ + ((Timing->DataSetupTime) << 8) |\ + ((Timing->BusTurnAroundDuration) << 16) |\ + (Timing->AccessMode)); + + Device->BWTR[Bank] = tmpr; + } + else + { + Device->BWTR[Bank] = 0x0FFFFFFF; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2 + * @brief management functions + * +@verbatim + ============================================================================== + ##### FMC_NORSRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the FMC NORSRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically FMC_NORSRAM write operation. + * @param Device: Pointer to NORSRAM device instance + * @param Bank: NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Enable write operation */ + Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE; + + return HAL_OK; +} + +/** + * @brief Disables dynamically FMC_NORSRAM write operation. + * @param Device: Pointer to NORSRAM device instance + * @param Bank: NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Disable write operation */ + Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE; + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions + * @brief NAND Controller functions + * + @verbatim + ============================================================================== + ##### How to use NAND device driver ##### + ============================================================================== + [..] + This driver contains a set of APIs to interface with the FMC NAND banks in order + to run the NAND external devices. + + (+) FMC NAND bank reset using the function FMC_NAND_DeInit() + (+) FMC NAND bank control configuration using the function FMC_NAND_Init() + (+) FMC NAND bank common space timing configuration using the function + FMC_NAND_CommonSpace_Timing_Init() + (+) FMC NAND bank attribute space timing configuration using the function + FMC_NAND_AttributeSpace_Timing_Init() + (+) FMC NAND bank enable/disable ECC correction feature using the functions + FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable() + (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() + +@endverbatim + * @{ + */ + +/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FMC NAND interface + (+) De-initialize the FMC NAND interface + (+) Configure the FMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the FMC_NAND device according to the specified + * control parameters in the FMC_NAND_HandleTypeDef + * @param Device: Pointer to NAND device instance + * @param Init: Pointer to NAND Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) +{ + uint32_t tmpr = 0; + + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Init->NandBank)); + assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); + assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); + assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); + assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); + assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); + assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); + + /* Get the NAND bank 3 register value */ + tmpr = Device->PCR; + + /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ + tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \ + FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \ + FMC_PCR_TAR | FMC_PCR_ECCPS)); + /* Set NAND device control parameters */ + tmpr |= (uint32_t)(Init->Waitfeature |\ + FMC_PCR_MEMORY_TYPE_NAND |\ + Init->MemoryDataWidth |\ + Init->EccComputation |\ + Init->ECCPageSize |\ + ((Init->TCLRSetupTime) << 9) |\ + ((Init->TARSetupTime) << 13)); + + /* NAND bank 3 registers configuration */ + Device->PCR = tmpr; + + return HAL_OK; + +} + +/** + * @brief Initializes the FMC_NAND Common space Timing according to the specified + * parameters in the FMC_NAND_PCC_TimingTypeDef + * @param Device: Pointer to NAND device instance + * @param Timing: Pointer to NAND timing structure + * @param Bank: NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +{ + uint32_t tmpr = 0; + + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); + assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Get the NAND bank 3 register value */ + tmpr = Device->PMEM; + + /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ + tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET3 | FMC_PMEM_MEMWAIT3 | FMC_PMEM_MEMHOLD3 | \ + FMC_PMEM_MEMHIZ3)); + /* Set FMC_NAND device timing parameters */ + tmpr |= (uint32_t)(Timing->SetupTime |\ + ((Timing->WaitSetupTime) << 8) |\ + ((Timing->HoldSetupTime) << 16) |\ + ((Timing->HiZSetupTime) << 24) + ); + + /* NAND bank 3 registers configuration */ + Device->PMEM = tmpr; + + return HAL_OK; +} + +/** + * @brief Initializes the FMC_NAND Attribute space Timing according to the specified + * parameters in the FMC_NAND_PCC_TimingTypeDef + * @param Device: Pointer to NAND device instance + * @param Timing: Pointer to NAND timing structure + * @param Bank: NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +{ + uint32_t tmpr = 0; + + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); + assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Get the NAND bank 3 register value */ + tmpr = Device->PATT; + + /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ + tmpr &= ((uint32_t)~(FMC_PATT_ATTSET3 | FMC_PATT_ATTWAIT3 | FMC_PATT_ATTHOLD3 | \ + FMC_PATT_ATTHIZ3)); + /* Set FMC_NAND device timing parameters */ + tmpr |= (uint32_t)(Timing->SetupTime |\ + ((Timing->WaitSetupTime) << 8) |\ + ((Timing->HoldSetupTime) << 16) |\ + ((Timing->HiZSetupTime) << 24)); + + /* NAND bank 3 registers configuration */ + Device->PATT = tmpr; + + return HAL_OK; +} + +/** + * @brief DeInitializes the FMC_NAND device + * @param Device: Pointer to NAND device instance + * @param Bank: NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Disable the NAND Bank */ + __FMC_NAND_DISABLE(Device); + + /* Set the FMC_NAND_BANK3 registers to their reset values */ + Device->PCR = 0x00000018; + Device->SR = 0x00000040; + Device->PMEM = 0xFCFCFCFC; + Device->PATT = 0xFCFCFCFC; + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_FMC_NAND_Group3 Control functions + * @brief management functions + * +@verbatim + ============================================================================== + ##### FMC_NAND Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the FMC NAND interface. + +@endverbatim + * @{ + */ + + +/** + * @brief Enables dynamically FMC_NAND ECC feature. + * @param Device: Pointer to NAND device instance + * @param Bank: NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Enable ECC feature */ + Device->PCR |= FMC_PCR_ECCEN; + + return HAL_OK; +} + + +/** + * @brief Disables dynamically FMC_NAND ECC feature. + * @param Device: Pointer to NAND device instance + * @param Bank: NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Disable ECC feature */ + Device->PCR &= ~FMC_PCR_ECCEN; + + return HAL_OK; +} + +/** + * @brief Disables dynamically FMC_NAND ECC feature. + * @param Device: Pointer to NAND device instance + * @param ECCval: Pointer to ECC value + * @param Bank: NAND bank number + * @param Timeout: Timeout wait value + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until FIFO is empty */ + while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + return HAL_TIMEOUT; + } + } + } + + /* Get the ECCR register value */ + *ECCval = (uint32_t)Device->ECCR; + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FMC_LL_SDRAM + * @brief SDRAM Controller functions + * + @verbatim + ============================================================================== + ##### How to use SDRAM device driver ##### + ============================================================================== + [..] + This driver contains a set of APIs to interface with the FMC SDRAM banks in order + to run the SDRAM external devices. + + (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit() + (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init() + (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init() + (+) FMC SDRAM bank enable/disable write operation using the functions + FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable() + (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand() + +@endverbatim + * @{ + */ + +/** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FMC SDRAM interface + (+) De-initialize the FMC SDRAM interface + (+) Configure the FMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the FMC_SDRAM device according to the specified + * control parameters in the FMC_SDRAM_InitTypeDef + * @param Device: Pointer to SDRAM device instance + * @param Init: Pointer to SDRAM Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) +{ + uint32_t tmpr1 = 0; + uint32_t tmpr2 = 0; + + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Init->SDBank)); + assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber)); + assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber)); + assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth)); + assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber)); + assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency)); + assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection)); + assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); + assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); + assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); + + /* Set SDRAM bank configuration parameters */ + if (Init->SDBank != FMC_SDRAM_BANK2) + { + tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; + + /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ + tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ + FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ + FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); + + tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\ + Init->RowBitsNumber |\ + Init->MemoryDataWidth |\ + Init->InternalBankNumber |\ + Init->CASLatency |\ + Init->WriteProtection |\ + Init->SDClockPeriod |\ + Init->ReadBurst |\ + Init->ReadPipeDelay + ); + Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; + } + else /* FMC_Bank2_SDRAM */ + { + tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; + + /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ + tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ + FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ + FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); + + tmpr1 |= (uint32_t)(Init->SDClockPeriod |\ + Init->ReadBurst |\ + Init->ReadPipeDelay); + + tmpr2 = Device->SDCR[FMC_SDRAM_BANK2]; + + /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ + tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ + FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ + FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); + + tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\ + Init->RowBitsNumber |\ + Init->MemoryDataWidth |\ + Init->InternalBankNumber |\ + Init->CASLatency |\ + Init->WriteProtection); + + Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; + Device->SDCR[FMC_SDRAM_BANK2] = tmpr2; + } + + return HAL_OK; +} + +/** + * @brief Initializes the FMC_SDRAM device timing according to the specified + * parameters in the FMC_SDRAM_TimingTypeDef + * @param Device: Pointer to SDRAM device instance + * @param Timing: Pointer to SDRAM Timing structure + * @param Bank: SDRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) +{ + uint32_t tmpr1 = 0; + uint32_t tmpr2 = 0; + + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay)); + assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay)); + assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime)); + assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay)); + assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime)); + assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); + assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Set SDRAM device timing parameters */ + if (Bank != FMC_SDRAM_BANK2) + { + tmpr1 = Device->SDTR[FMC_SDRAM_BANK1]; + + /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ + tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ + FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ + FMC_SDTR1_TRCD)); + + tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ + (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ + (((Timing->SelfRefreshTime)-1) << 8) |\ + (((Timing->RowCycleDelay)-1) << 12) |\ + (((Timing->WriteRecoveryTime)-1) <<16) |\ + (((Timing->RPDelay)-1) << 20) |\ + (((Timing->RCDDelay)-1) << 24)); + Device->SDTR[FMC_SDRAM_BANK1] = tmpr1; + } + else /* FMC_Bank2_SDRAM */ + { + tmpr1 = Device->SDTR[FMC_SDRAM_BANK2]; + + /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ + tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ + FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ + FMC_SDTR1_TRCD)); + + tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ + (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ + (((Timing->SelfRefreshTime)-1) << 8) |\ + (((Timing->WriteRecoveryTime)-1) <<16) |\ + (((Timing->RCDDelay)-1) << 24)); + + tmpr2 = Device->SDTR[FMC_SDRAM_BANK1]; + + /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ + tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ + FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ + FMC_SDTR1_TRCD)); + tmpr2 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\ + (((Timing->RPDelay)-1) << 20)); + + Device->SDTR[FMC_SDRAM_BANK2] = tmpr1; + Device->SDTR[FMC_SDRAM_BANK1] = tmpr2; + } + + return HAL_OK; +} + +/** + * @brief DeInitializes the FMC_SDRAM peripheral + * @param Device: Pointer to SDRAM device instance + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* De-initialize the SDRAM device */ + Device->SDCR[Bank] = 0x000002D0; + Device->SDTR[Bank] = 0x0FFFFFFF; + Device->SDCMR = 0x00000000; + Device->SDRTR = 0x00000000; + Device->SDSR = 0x00000000; + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2 + * @brief management functions + * +@verbatim + ============================================================================== + ##### FMC_SDRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the FMC SDRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically FMC_SDRAM write protection. + * @param Device: Pointer to SDRAM device instance + * @param Bank: SDRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Enable write protection */ + Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE; + + return HAL_OK; +} + +/** + * @brief Disables dynamically FMC_SDRAM write protection. + * @param hsdram: FMC_SDRAM handle + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Disable write protection */ + Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE; + + return HAL_OK; +} + +/** + * @brief Send Command to the FMC SDRAM bank + * @param Device: Pointer to SDRAM device instance + * @param Command: Pointer to SDRAM command structure + * @param Timing: Pointer to SDRAM Timing structure + * @param Timeout: Timeout wait value + * @retval HAL state + */ +HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) +{ + __IO uint32_t tmpr = 0; + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode)); + assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget)); + assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber)); + assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); + + /* Set command register */ + tmpr = (uint32_t)((Command->CommandMode) |\ + (Command->CommandTarget) |\ + (((Command->AutoRefreshNumber)-1) << 5) |\ + ((Command->ModeRegisterDefinition) << 9) + ); + + Device->SDCMR = tmpr; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* wait until command is send */ + while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY)) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + return HAL_TIMEOUT; + } + } + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Program the SDRAM Memory Refresh rate. + * @param Device: Pointer to SDRAM device instance + * @param RefreshRate: The SDRAM refresh rate value. + * @retval HAL state + */ +HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_REFRESH_RATE(RefreshRate)); + + /* Set the refresh rate in command register */ + Device->SDRTR |= (RefreshRate<<1); + + return HAL_OK; +} + +/** + * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands. + * @param Device: Pointer to SDRAM device instance + * @param AutoRefreshNumber: Specifies the auto Refresh number. + * @retval None + */ +HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber)); + + /* Set the Auto-refresh number in command register */ + Device->SDCMR |= (AutoRefreshNumber << 5); + + return HAL_OK; +} + +/** + * @brief Returns the indicated FMC SDRAM bank mode status. + * @param Device: Pointer to SDRAM device instance + * @param Bank: Defines the FMC SDRAM bank. This parameter can be + * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. + * @retval The FMC SDRAM bank mode status, could be on of the following values: + * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or + * FMC_SDRAM_POWER_DOWN_MODE. + */ +uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Get the corresponding bank mode */ + if(Bank == FMC_SDRAM_BANK1) + { + tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); + } + else + { + tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2); + } + + /* Return the mode status */ + return tmpreg; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.h b/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.h new file mode 100644 index 00000000..019ec064 --- /dev/null +++ b/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.h @@ -0,0 +1,1337 @@ +/** + ****************************************************************************** + * @file stm32f7xx_ll_fmc.h + * @author MCD Application Team + * @version V1.0.1 + * @date 25-June-2015 + * @brief Header file of FMC HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_FMC_H +#define __STM32F7xx_LL_FMC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup FMC_LL + * @{ + */ + +/** @addtogroup FMC_LL_Private_Macros + * @{ + */ +#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \ + ((BANK) == FMC_NORSRAM_BANK2) || \ + ((BANK) == FMC_NORSRAM_BANK3) || \ + ((BANK) == FMC_NORSRAM_BANK4)) + +#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ + ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) + +#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ + ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ + ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) + +#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ + ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) + +#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ + ((__MODE__) == FMC_ACCESS_MODE_B) || \ + ((__MODE__) == FMC_ACCESS_MODE_C) || \ + ((__MODE__) == FMC_ACCESS_MODE_D)) + +#define IS_FMC_NAND_BANK(BANK) ((BANK) == FMC_NAND_BANK3) + +#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ + ((FEATURE) == FMC_NAND_WAIT_FEATURE_ENABLE)) + +#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_8) || \ + ((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_16)) + +#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \ + ((STATE) == FMC_NAND_ECC_ENABLE)) + +#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ + ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ + ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ + ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ + ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ + ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) + +#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \ + ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \ + ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32)) + +#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \ + ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE)) + +#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \ + ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \ + ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3)) + +#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \ + ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE)) + +#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \ + ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \ + ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2)) + +#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE)) + +#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \ + ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \ + ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2)) + +/** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time + * @{ + */ +#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255) +/** + * @} + */ + +/** @defgroup FMC_TAR_Setup_Time FMC TAR Setup Time + * @{ + */ +#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255) +/** + * @} + */ + +/** @defgroup FMC_Setup_Time FMC Setup Time + * @{ + */ +#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 254) +/** + * @} + */ + +/** @defgroup FMC_Wait_Setup_Time FMC Wait Setup Time + * @{ + */ +#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 254) +/** + * @} + */ + +/** @defgroup FMC_Hold_Setup_Time FMC Hold Setup Time + * @{ + */ +#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 254) +/** + * @} + */ + +/** @defgroup FMC_HiZ_Setup_Time FMC HiZ Setup Time + * @{ + */ +#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 254) +/** + * @} + */ + +#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ + ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) + +#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ + ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) + +#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ + ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) + +#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ + ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) + +#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ + ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) + +#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ + ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) + +#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ + ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) + +/** @defgroup FMC_Data_Latency FMC Data Latency + * @{ + */ +#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) +/** + * @} + */ + +#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ + ((__BURST__) == FMC_WRITE_BURST_ENABLE)) + +#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ + ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) + + +/** @defgroup FMC_Address_Setup_Time FMC Address Setup Time + * @{ + */ +#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) +/** + * @} + */ + +/** @defgroup FMC_Address_Hold_Time FMC Address Hold Time + * @{ + */ +#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) +/** + * @} + */ + +/** @defgroup FMC_Data_Setup_Time FMC Data Setup Time + * @{ + */ +#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) +/** + * @} + */ + +/** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration + * @{ + */ +#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) +/** + * @} + */ + +/** @defgroup FMC_CLK_Division FMC CLK Division + * @{ + */ +#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_LoadToActive_Delay FMC SDRAM LoadToActive Delay + * @{ + */ +#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay FMC SDRAM ExitSelfRefresh Delay + * @{ + */ +#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_SelfRefresh_Time FMC SDRAM SelfRefresh Time + * @{ + */ +#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_RowCycle_Delay FMC SDRAM RowCycle Delay + * @{ + */ +#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Write_Recovery_Time FMC SDRAM Write Recovery Time + * @{ + */ +#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_RP_Delay FMC SDRAM RP Delay + * @{ + */ +#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_RCD_Delay FMC SDRAM RCD Delay + * @{ + */ +#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_AutoRefresh_Number FMC SDRAM AutoRefresh Number + * @{ + */ +#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0) && ((__NUMBER__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_ModeRegister_Definition FMC SDRAM ModeRegister Definition + * @{ + */ +#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Refresh_rate FMC SDRAM Refresh rate + * @{ + */ +#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191) +/** + * @} + */ + +/** @defgroup FMC_NORSRAM_Device_Instance FMC NORSRAM Device Instance + * @{ + */ +#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) +/** + * @} + */ + +/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NORSRAM EXTENDED Device Instance + * @{ + */ +#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) +/** + * @} + */ + +/** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance + * @{ + */ +#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Device_Instance FMC SDRAM Device Instance + * @{ + */ +#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE) +/** + * @} + */ + +#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \ + ((BANK) == FMC_SDRAM_BANK2)) + +#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \ + ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \ + ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \ + ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11)) + +#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \ + ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \ + ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13)) + +#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \ + ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4)) + + +#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \ + ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \ + ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3)) + +#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ + ((__SIZE__) == FMC_PAGE_SIZE_128) || \ + ((__SIZE__) == FMC_PAGE_SIZE_256) || \ + ((__SIZE__) == FMC_PAGE_SIZE_1024)) + +#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ + ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) +/** + * @} + */ + +/* Exported typedef ----------------------------------------------------------*/ +/** @defgroup FMC_Exported_typedef FMC Low Layer Exported Types + * @{ + */ +#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef +#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef +#define FMC_NAND_TypeDef FMC_Bank3_TypeDef +#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef + +#define FMC_NORSRAM_DEVICE FMC_Bank1 +#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E +#define FMC_NAND_DEVICE FMC_Bank3 +#define FMC_SDRAM_DEVICE FMC_Bank5_6 + +/** + * @brief FMC NORSRAM Configuration Structure definition + */ +typedef struct +{ + uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. + This parameter can be a value of @ref FMC_NORSRAM_Bank */ + + uint32_t DataAddressMux; /*!< Specifies whether the address and data values are + multiplexed on the data bus or not. + This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ + + uint32_t MemoryType; /*!< Specifies the type of external memory attached to + the corresponding memory device. + This parameter can be a value of @ref FMC_Memory_Type */ + + uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ + + uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FMC_Burst_Access_Mode */ + + uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ + + uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FMC_Wait_Timing */ + + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. + This parameter can be a value of @ref FMC_Write_Operation */ + + uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FMC_Wait_Signal */ + + uint32_t ExtendedMode; /*!< Enables or disables the extended mode. + This parameter can be a value of @ref FMC_Extended_Mode */ + + uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, + valid only with asynchronous Flash memories. + This parameter can be a value of @ref FMC_AsynchronousWait */ + + uint32_t WriteBurst; /*!< Enables or disables the write burst operation. + This parameter can be a value of @ref FMC_Write_Burst */ + + uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. + This parameter is only enabled through the FMC_BCR1 register, and don't care + through FMC_BCR2..4 registers. + This parameter can be a value of @ref FMC_Continous_Clock */ + + uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. + This parameter is only enabled through the FMC_BCR1 register, and don't care + through FMC_BCR2..4 registers. + This parameter can be a value of @ref FMC_Write_FIFO */ + + uint32_t PageSize; /*!< Specifies the memory page size. + This parameter can be a value of @ref FMC_Page_Size */ + +}FMC_NORSRAM_InitTypeDef; + +/** + * @brief FMC NORSRAM Timing parameters structure definition + */ +typedef struct +{ + uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between Min_Data = 0 and Max_Data = 15. + @note This parameter is not used with synchronous NOR Flash memories. */ + + uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between Min_Data = 1 and Max_Data = 15. + @note This parameter is not used with synchronous NOR Flash memories. */ + + uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between Min_Data = 1 and Max_Data = 255. + @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed + NOR Flash memories. */ + + uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between Min_Data = 0 and Max_Data = 15. + @note This parameter is only used for multiplexed NOR Flash memories. */ + + uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of + HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. + @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM + accesses. */ + + uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The parameter value depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is don't care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories + with synchronous burst mode enable */ + + uint32_t AccessMode; /*!< Specifies the asynchronous access mode. + This parameter can be a value of @ref FMC_Access_Mode */ +}FMC_NORSRAM_TimingTypeDef; + +/** + * @brief FMC NAND Configuration Structure definition + */ +typedef struct +{ + uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. + This parameter can be a value of @ref FMC_NAND_Bank */ + + uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. + This parameter can be any value of @ref FMC_Wait_feature */ + + uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be any value of @ref FMC_NAND_Data_Width */ + + uint32_t EccComputation; /*!< Enables or disables the ECC computation. + This parameter can be any value of @ref FMC_ECC */ + + uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. + This parameter can be any value of @ref FMC_ECC_Page_Size */ + + uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ + + uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ +}FMC_NAND_InitTypeDef; + +/** + * @brief FMC NAND Timing parameters structure definition + */ +typedef struct +{ + uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before + the command assertion for NAND-Flash read or write access + to common/Attribute or I/O memory space (depending on + the memory space timing to be configured). + This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ + + uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the + command for NAND-Flash read or write access to + common/Attribute or I/O memory space (depending on the + memory space timing to be configured). + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ + + uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address + (and data for write access) after the command de-assertion + for NAND-Flash read or write access to common/Attribute + or I/O memory space (depending on the memory space timing + to be configured). + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ + + uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the + data bus is kept in HiZ after the start of a NAND-Flash + write access to common/Attribute or I/O memory space (depending + on the memory space timing to be configured). + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ +}FMC_NAND_PCC_TimingTypeDef; + +/** + * @brief FMC SDRAM Configuration Structure definition + */ +typedef struct +{ + uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used. + This parameter can be a value of @ref FMC_SDRAM_Bank */ + + uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address. + This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */ + + uint32_t RowBitsNumber; /*!< Defines the number of bits of column address. + This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */ + + uint32_t MemoryDataWidth; /*!< Defines the memory device width. + This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */ + + uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks. + This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */ + + uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles. + This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */ + + uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode. + This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */ + + uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow + to disable the clock before changing frequency. + This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */ + + uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read + commands during the CAS latency and stores data in the Read FIFO. + This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */ + + uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. + This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */ +}FMC_SDRAM_InitTypeDef; + +/** + * @brief FMC SDRAM Timing parameters structure definition + */ +typedef struct +{ + uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and + an active or Refresh command in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to + issuing the Activate command in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock + cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command + and the delay between two consecutive Refresh commands in number of + memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command + in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write + command in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ +}FMC_SDRAM_TimingTypeDef; + +/** + * @brief SDRAM command parameters structure definition + */ +typedef struct +{ + uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device. + This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */ + + uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to. + This parameter can be a value of @ref FMC_SDRAM_Command_Target. */ + + uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued + in auto refresh mode. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ +}FMC_SDRAM_CommandTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants + * @{ + */ + +/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller + * @{ + */ + +/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank + * @{ + */ +#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000) +#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002) +#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004) +#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006) +/** + * @} + */ + +/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing + * @{ + */ +#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) +#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002) +/** + * @} + */ + +/** @defgroup FMC_Memory_Type FMC Memory Type + * @{ + */ +#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) +#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004) +#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008) +/** + * @} + */ + +/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width + * @{ + */ +#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) +#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) +#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020) +/** + * @} + */ + +/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access + * @{ + */ +#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040) +#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) +/** + * @} + */ + +/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode + * @{ + */ +#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) +#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100) +/** + * @} + */ + +/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity + * @{ + */ +#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) +#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200) +/** + * @} + */ + +/** @defgroup FMC_Wait_Timing FMC Wait Timing + * @{ + */ +#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) +#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800) +/** + * @} + */ + +/** @defgroup FMC_Write_Operation FMC Write Operation + * @{ + */ +#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) +#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000) +/** + * @} + */ + +/** @defgroup FMC_Wait_Signal FMC Wait Signal + * @{ + */ +#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) +#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000) +/** + * @} + */ + +/** @defgroup FMC_Extended_Mode FMC Extended Mode + * @{ + */ +#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) +#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000) +/** + * @} + */ + +/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait + * @{ + */ +#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) +#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000) +/** + * @} + */ + +/** @defgroup FMC_Page_Size FMC Page Size + * @{ + */ +#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000) +#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0) +#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1) +#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2) +/** + * @} + */ + +/** @defgroup FMC_Write_Burst FMC Write Burst + * @{ + */ +#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) +#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000) +/** + * @} + */ + +/** @defgroup FMC_Continous_Clock FMC Continuous Clock + * @{ + */ +#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000) +#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000) +/** + * @} + */ + +/** @defgroup FMC_Write_FIFO FMC Write FIFO + * @{ + */ +#define FMC_WRITE_FIFO_DISABLE ((uint32_t)0x00000000) +#define FMC_WRITE_FIFO_ENABLE ((uint32_t)FMC_BCR1_WFDIS) +/** + * @} + */ + +/** @defgroup FMC_Access_Mode FMC Access Mode + * @{ + */ +#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000) +#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000) +#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000) +#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller + * @{ + */ +/** @defgroup FMC_NAND_Bank FMC NAND Bank + * @{ + */ +#define FMC_NAND_BANK3 ((uint32_t)0x00000100) +/** + * @} + */ + +/** @defgroup FMC_Wait_feature FMC Wait feature + * @{ + */ +#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000) +#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002) +/** + * @} + */ + +/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type + * @{ + */ +#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008) +/** + * @} + */ + +/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width + * @{ + */ +#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) +#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) +/** + * @} + */ + +/** @defgroup FMC_ECC FMC ECC + * @{ + */ +#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) +#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040) +/** + * @} + */ + +/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size + * @{ + */ +#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000) +#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000) +#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000) +#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000) +#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000) +#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller + * @{ + */ +/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank + * @{ + */ +#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000) +#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number + * @{ + */ +#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000) +#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001) +#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002) +#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number + * @{ + */ +#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000) +#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004) +#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width + * @{ + */ +#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) +#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) +#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number + * @{ + */ +#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000) +#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency + * @{ + */ +#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080) +#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100) +#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection + * @{ + */ +#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000) +#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period + * @{ + */ +#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000) +#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800) +#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst + * @{ + */ +#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000) +#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay + * @{ + */ +#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000) +#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000) +#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode + * @{ + */ +#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000) +#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001) +#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002) +#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003) +#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004) +#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005) +#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target + * @{ + */ +#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2 +#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1 +#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status + * @{ + */ +#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000) +#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0 +#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1 +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition + * @{ + */ +#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008) +#define FMC_IT_LEVEL ((uint32_t)0x00000010) +#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020) +#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000) +/** + * @} + */ + +/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition + * @{ + */ +#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001) +#define FMC_FLAG_LEVEL ((uint32_t)0x00000002) +#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004) +#define FMC_FLAG_FEMPT ((uint32_t)0x00000040) +#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE +#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY +#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros + * @{ + */ + +/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros + * @brief macros to handle NOR device enable/disable and read/write operations + * @{ + */ + +/** + * @brief Enable the NORSRAM device access. + * @param __INSTANCE__: FMC_NORSRAM Instance + * @param __BANK__: FMC_NORSRAM Bank + * @retval None + */ +#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN) + +/** + * @brief Disable the NORSRAM device access. + * @param __INSTANCE__: FMC_NORSRAM Instance + * @param __BANK__: FMC_NORSRAM Bank + * @retval None + */ +#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN) + +/** + * @} + */ + +/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros + * @brief macros to handle NAND device enable/disable + * @{ + */ + +/** + * @brief Enable the NAND device access. + * @param __INSTANCE__: FMC_NAND Instance + * @retval None + */ +#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) + +/** + * @brief Disable the NAND device access. + * @param __INSTANCE__: FMC_NAND Instance + * @retval None + */ +#define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN) + +/** + * @} + */ + +/** @defgroup FMC_Interrupt FMC Interrupt + * @brief macros to handle FMC interrupts + * @{ + */ + +/** + * @brief Enable the NAND device interrupt. + * @param __INSTANCE__: FMC_NAND instance + * @param __INTERRUPT__: FMC_NAND interrupt + * This parameter can be any combination of the following values: + * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. + * @arg FMC_IT_LEVEL: Interrupt level. + * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. + * @retval None + */ +#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) + +/** + * @brief Disable the NAND device interrupt. + * @param __INSTANCE__: FMC_NAND Instance + * @param __INTERRUPT__: FMC_NAND interrupt + * This parameter can be any combination of the following values: + * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. + * @arg FMC_IT_LEVEL: Interrupt level. + * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. + * @retval None + */ +#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) + +/** + * @brief Get flag status of the NAND device. + * @param __INSTANCE__: FMC_NAND Instance + * @param __BANK__: FMC_NAND Bank + * @param __FLAG__: FMC_NAND flag + * This parameter can be any combination of the following values: + * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. + * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg FMC_FLAG_FEMPT: FIFO empty flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear flag status of the NAND device. + * @param __INSTANCE__: FMC_NAND Instance + * @param __FLAG__: FMC_NAND flag + * This parameter can be any combination of the following values: + * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. + * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg FMC_FLAG_FEMPT: FIFO empty flag. + * @retval None + */ +#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) + +/** + * @brief Enable the SDRAM device interrupt. + * @param __INSTANCE__: FMC_SDRAM instance + * @param __INTERRUPT__: FMC_SDRAM interrupt + * This parameter can be any combination of the following values: + * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error + * @retval None + */ +#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__)) + +/** + * @brief Disable the SDRAM device interrupt. + * @param __INSTANCE__: FMC_SDRAM instance + * @param __INTERRUPT__: FMC_SDRAM interrupt + * This parameter can be any combination of the following values: + * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error + * @retval None + */ +#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__)) + +/** + * @brief Get flag status of the SDRAM device. + * @param __INSTANCE__: FMC_SDRAM instance + * @param __FLAG__: FMC_SDRAM flag + * This parameter can be any combination of the following values: + * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error. + * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag. + * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear flag status of the SDRAM device. + * @param __INSTANCE__: FMC_SDRAM instance + * @param __FLAG__: FMC_SDRAM flag + * This parameter can be any combination of the following values: + * @arg FMC_SDRAM_FLAG_REFRESH_ERROR + * @retval None + */ +#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__)) +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions + * @{ + */ + +/** @defgroup FMC_LL_NORSRAM NOR SRAM + * @{ + */ +/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions + * @{ + */ +HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); +HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); +/** + * @} + */ + +/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions + * @{ + */ +HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); +/** + * @} + */ +/** + * @} + */ + +/** @defgroup FMC_LL_NAND NAND + * @{ + */ +/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions + * @{ + */ +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); +/** + * @} + */ + +/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions + * @{ + */ +HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); +/** + * @} + */ + +/** @defgroup FMC_LL_SDRAM SDRAM + * @{ + */ +/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions + * @{ + */ +HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); +HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); + +/** + * @} + */ + +/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions + * @{ + */ +HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); +HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); +HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber); +uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_FMC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/drivers/gdisp/STM32F746Discovery/board_STM32F746Discovery_template.h b/drivers/gdisp/STM32F746Discovery/board_STM32F746Discovery_template.h index 2f7be489..df605838 100644 --- a/drivers/gdisp/STM32F746Discovery/board_STM32F746Discovery_template.h +++ b/drivers/gdisp/STM32F746Discovery/board_STM32F746Discovery_template.h @@ -31,10 +31,11 @@ static const ltdcConfig driverCfg = { 0xFF, // Constant alpha factor LTDC_LEF_ENABLE // Layer configuration flags }, + LTDC_UNUSED_LAYER_CONFIG // Foreground layer config }; -static inline void init_board(GDisplay *g) { +static inline void init_board(GDisplay* g) { // As we are not using multiple displays we set g->board to NULL as we don't use it. g->board = 0; @@ -48,26 +49,13 @@ static inline void init_board(GDisplay *g) { static inline void post_init_board(GDisplay* g) { + (void)g; } static inline void set_backlight(GDisplay* g, uint8_t percent) { -} - -static inline void acquire_bus(GDisplay* g) -{ -} - -static inline void release_bus(GDisplay* g) -{ -} - -static inline void write_index(GDisplay* g, uint8_t index) -{ -} - -static inline void write_data(GDisplay* g, uint8_t data) -{ + (void)g; + (void)percent; } #endif /* _GDISP_LLD_BOARD_H */ diff --git a/drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c b/drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c index c46bf27e..ed4e8e20 100644 --- a/drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c +++ b/drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c @@ -296,6 +296,7 @@ LLDSPEC color_t gdisp_lld_get_pixel_color(GDisplay* g) #endif color = PIXEL_ADDR(g, pos)[0]; + return gdispNative2Color(color); } diff --git a/drivers/gdisp/STM32F746Discovery/readme.txt b/drivers/gdisp/STM32F746Discovery/readme.txt index ab87e1d8..e21429df 100644 --- a/drivers/gdisp/STM32F746Discovery/readme.txt +++ b/drivers/gdisp/STM32F746Discovery/readme.txt @@ -8,4 +8,4 @@ To use this driver: include $(GFXLIB)/drivers/gdisp/STM32F746Discovery/driver.mk 3. Add a board_STM32F746Discovery.h to you project directory (or board directory) - base on one of the templates. + based on one of the templates. From ed75f5e8c34051942531bfe96c9827978796320e Mon Sep 17 00:00:00 2001 From: inmarket Date: Wed, 8 Jul 2015 15:21:53 +1000 Subject: [PATCH 06/26] Updated gos/threads and gos/threads_advanced demos. --- demos/modules/gos/threads/gfxconf.h | 64 ++++++------ demos/modules/gos/threads/main.c | 102 +++++++------------ demos/modules/gos/threads_advanced/gfxconf.h | 21 +++- demos/modules/gos/threads_advanced/main.c | 25 ++++- 4 files changed, 108 insertions(+), 104 deletions(-) diff --git a/demos/modules/gos/threads/gfxconf.h b/demos/modules/gos/threads/gfxconf.h index 71a23ac0..dd36bf3d 100644 --- a/demos/modules/gos/threads/gfxconf.h +++ b/demos/modules/gos/threads/gfxconf.h @@ -1,39 +1,43 @@ -/* - * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu - * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket +/** + * This file has a different license to the rest of the uGFX system. + * You can copy, modify and distribute this file as you see fit. + * You do not need to publish your source modifications to this file. + * The only thing you are not permitted to do is to relicense it + * under a different license. + */ + +/** + * Copy this file into your project directory and rename it as gfxconf.h + * Edit your copy to turn on the uGFX features you want to use. + * The values below are the defaults. * - * All rights reserved. + * Only remove the comments from lines where you want to change the + * default value. This allows definitions to be included from + * driver makefiles when required and provides the best future + * compatibility for your project. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * Please use spaces instead of tabs in this file. */ #ifndef _GFXCONF_H #define _GFXCONF_H -/* The operating system to use. One of these must be defined - preferably in your Makefile */ -//#define GFX_USE_OS_CHIBIOS FALSE -//#define GFX_USE_OS_WIN32 FALSE -//#define GFX_USE_OS_LINUX FALSE -//#define GFX_USE_OS_OSX FALSE + +/////////////////////////////////////////////////////////////////////////// +// GOS - One of these must be defined, preferably in your Makefile // +/////////////////////////////////////////////////////////////////////////// +//#define GFX_USE_OS_CHIBIOS FALSE +//#define GFX_USE_OS_FREERTOS FALSE +// #define GFX_FREERTOS_USE_TRACE FALSE +//#define GFX_USE_OS_WIN32 FALSE +//#define GFX_USE_OS_LINUX FALSE +//#define GFX_USE_OS_OSX FALSE +//#define GFX_USE_OS_ECOS FALSE +//#define GFX_USE_OS_RAWRTOS FALSE +//#define GFX_USE_OS_RAW32 FALSE + +// We define this here in case you are using raw32 or arduino with this demo +// and have a non-thread-safe C library. +#define GOS_RAW_HEAP_SIZE 10240 #endif /* _GFXCONF_H */ diff --git a/demos/modules/gos/threads/main.c b/demos/modules/gos/threads/main.c index c68fcd18..b15c656d 100644 --- a/demos/modules/gos/threads/main.c +++ b/demos/modules/gos/threads/main.c @@ -1,83 +1,55 @@ -/* - * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu - * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - #include "gfx.h" -gfxThreadHandle thd1; -gfxThreadHandle thd2; +#if defined(WIN32) + #include -/* - * Function 1: Prints a message - */ -threadreturn_t Thread1_function(void* param) + static DWORD nres; + + // On Win32 don't use the C library fprintf or write as they crash. + // Maybe we just need to add the multi-thread C library options to the compile. + // Instead we use the Win32 API directly as that always works. + #define DEBUGWRITE(str) WriteFile(GetStdHandle(STD_ERROR_HANDLE), str, strlen(str), &nres, 0) +#else + #warning "You must alter this demo to define a DEBUGWRITE macro for your platform." + #warning "Be careful of using C library functions as they sometimes crash if they are not expecting stack changes (if possible use a multi-thread aware C library)" + #warning "You might flash LED's instead if that is better for your platform." + #error "--" +#endif + +threadreturn_t heartbeat1(void* param) { - // We don't use the parameter - (void)param; + (void)param; - // We never return - while (1) { - printf("Message from Thread 1\r\n"); - gfxSleepMilliseconds(500); - } + while (TRUE) { + DEBUGWRITE("thread 1\n"); + gfxSleepMilliseconds(500); + } - return (threadreturn_t)0; + return (threadreturn_t)0; } -/* - * Function 2: Prints a message and appends the parameter - */ -threadreturn_t Thread2_function(void* param) +threadreturn_t heartbeat2(void* param) { - int i; + (void)param; - // we never return - while (1) { - printf("Message from Thread 2: %s\r\n", (char*)param); - gfxSleepMilliseconds(500); - } + while (TRUE) { + DEBUGWRITE("thread 2\n"); + gfxSleepMilliseconds(900); + } - return (threadreturn_t)0; + return (threadreturn_t)0; } int main(void) { - char* msg = "uGFX"; + gfxInit(); - gfxInit(); + // Give this plenty of stack. Stack size optimisation should be a production change only + gfxThreadCreate(0, 2048, NORMAL_PRIORITY, heartbeat1, 0); + gfxThreadCreate(0, 2048, NORMAL_PRIORITY, heartbeat2, 0); - /* Create a static thread from the default heap with normal priority. No parameter passed */ - thd1 = gfxThreadCreate(NULL, 128, NORMAL_PRIORITY, Thread1_function, 0); - - /* Create a static thread from the default heap with normal priority. String parameter passed */ - thd2 = gfxThreadCreate(NULL, 128, NORMAL_PRIORITY, Thread2_function, (void*)msg); - - while(TRUE) { - gfxSleepMilliseconds(500); - } + while (TRUE) { + DEBUGWRITE("thread main\n"); + gfxSleepMilliseconds(1400); + } } diff --git a/demos/modules/gos/threads_advanced/gfxconf.h b/demos/modules/gos/threads_advanced/gfxconf.h index f954e973..9a35130a 100644 --- a/demos/modules/gos/threads_advanced/gfxconf.h +++ b/demos/modules/gos/threads_advanced/gfxconf.h @@ -30,11 +30,22 @@ #ifndef _GFXCONF_H #define _GFXCONF_H -/* The operating system to use. One of these must be defined - preferably in your Makefile */ -//#define GFX_USE_OS_CHIBIOS FALSE -//#define GFX_USE_OS_WIN32 FALSE -//#define GFX_USE_OS_LINUX FALSE -//#define GFX_USE_OS_OSX FALSE +/////////////////////////////////////////////////////////////////////////// +// GOS - One of these must be defined, preferably in your Makefile // +/////////////////////////////////////////////////////////////////////////// +//#define GFX_USE_OS_CHIBIOS FALSE +//#define GFX_USE_OS_FREERTOS FALSE +// #define GFX_FREERTOS_USE_TRACE FALSE +//#define GFX_USE_OS_WIN32 FALSE +//#define GFX_USE_OS_LINUX FALSE +//#define GFX_USE_OS_OSX FALSE +//#define GFX_USE_OS_ECOS FALSE +//#define GFX_USE_OS_RAWRTOS FALSE +//#define GFX_USE_OS_RAW32 FALSE + +// We define this here in case you are using raw32 or arduino with this demo +// and have a non-thread-safe C library. +#define GOS_RAW_HEAP_SIZE 10240 #define GFX_USE_GTIMER TRUE diff --git a/demos/modules/gos/threads_advanced/main.c b/demos/modules/gos/threads_advanced/main.c index ecb552ab..89cada9f 100644 --- a/demos/modules/gos/threads_advanced/main.c +++ b/demos/modules/gos/threads_advanced/main.c @@ -43,6 +43,22 @@ GTimer gt; gfxThreadHandle thd; +#if defined(WIN32) + #include + + static DWORD nres; + + // On Win32 don't use the C library fprintf or write as they crash. + // Maybe we just need to add the multi-thread C library options to the compile. + // Instead we use the Win32 API directly as that always works. + #define DEBUGWRITE(str) WriteFile(GetStdHandle(STD_ERROR_HANDLE), str, strlen(str), &nres, 0) +#else + #warning "You must alter this demo to define a DEBUGWRITE macro for your platform." + #warning "Be careful of using C library functions as they sometimes crash if they are not expecting stack changes (if possible use a multi-thread aware C library)" + #warning "You might flash LED's instead if that is better for your platform." + #error "--" +#endif + /* * Thread function * Prints a message @@ -54,7 +70,7 @@ threadreturn_t Thread_function(void* param) /* Execute this until we shall be terminated */ while (*doExit == FALSE) { - printf("Message from Thread\r\n"); + DEBUGWRITE("Message from Thread\n"); gfxSleepMilliseconds(500); } @@ -72,7 +88,7 @@ void timerCallback(void* param) bool_t* threadExit = (bool_t*)param; /* Ask the Thread to fall over the end */ - printf("Closing thread!\r\n"); + DEBUGWRITE("Closing thread!\n"); *threadExit = TRUE; } @@ -91,14 +107,15 @@ int main(void) /* Create a static thread from the default heap with normal priority. * We pass a the parameter to the thread which tells the thread whether to return or not */ - thd = gfxThreadCreate(NULL, 128, NORMAL_PRIORITY, Thread_function, (void*)&exitThread); + thd = gfxThreadCreate(NULL, 2048, NORMAL_PRIORITY, Thread_function, (void*)&exitThread); /* Start the timer. The callback function will be called once after 2000ms - * We will pass the thread handle as a parameter so the timer can ask the thread to termite + * We will pass the thread handle as a parameter so the timer can ask the thread to terminate */ gtimerStart(>, timerCallback, (void*)&exitThread, FALSE, 2000); while(TRUE) { + DEBUGWRITE("Message from main!\n"); gfxSleepMilliseconds(500); } } From b9dcbc850676ab05e9706b9f1e5918bcf87587d4 Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Wed, 8 Jul 2015 22:06:18 +0200 Subject: [PATCH 07/26] Fixing typo in Raw32 code --- src/gos/gos_raw32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gos/gos_raw32.c b/src/gos/gos_raw32.c index f1ff6c45..caacab20 100644 --- a/src/gos/gos_raw32.c +++ b/src/gos/gos_raw32.c @@ -694,7 +694,7 @@ gfxThreadHandle gfxThreadCreate(void *stackarea, size_t stacksz, threadpriority_ memcpy(t+1, (char *)&t - stackbase, stackbase+sizeof(char *)); #else // Stack grows down - nf = (char *)(t) + size - (stackbase + sizeof(char *)); + nf = (char *)(t) + t->size - (stackbase + sizeof(char *)); memcpy(nf, &t, stackbase+sizeof(char *)); #endif From ba6c037e4ce475410d92d400b2ff0b0601103cb3 Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Wed, 8 Jul 2015 22:13:32 +0200 Subject: [PATCH 08/26] Renaming JSON files used by the uGFX-Studio --- tools/studio/options_v0.json | 471 +++++++++++++++++++++++++++++++++++ tools/studio/options_v1.json | 471 +++++++++++++++++++++++++++++++++++ 2 files changed, 942 insertions(+) create mode 100644 tools/studio/options_v0.json create mode 100644 tools/studio/options_v1.json diff --git a/tools/studio/options_v0.json b/tools/studio/options_v0.json new file mode 100644 index 00000000..edaf5efa --- /dev/null +++ b/tools/studio/options_v0.json @@ -0,0 +1,471 @@ +[ + { + "GOS" : [ + { + "Priorities" : [ + { + "User": "Low", + "Library": "LOW_PRIORITY" + }, + { + "User": "Normal", + "Library": "NORMAL_PRIORITY" + }, + { + "User": "High", + "Library": "HIGH_PRIORITY" + } + ] + } + ] + }, + { + "GDISP" : [ + { + "Orientations" : [ + { + "User": "Native", + "Library": "GDISP_ROTATE_0" + }, + { + "User": "Portrait", + "Library": "GDISP_ROTATE_PORTRAIT" + }, + { + "User": "Landscape", + "Library": "GDISP_ROTATE_LANDSCAPE" + }, + { + "User": "Rotate 90 degree", + "Library": "GDISP_ROTATE_90" + }, + { + "User": "Rotate 180 degree", + "Library": "GDISP_ROTATE_180" + }, + { + "User": "Rotate 270 degree", + "Library": "GDISP_ROTATE_270" + } + ] + }, + { + "Colors" : [ + { + "User": "White", + "Library" : "White", + "RGB": "0xFFFFFF" + }, + { + "User": "Black", + "Library": "Black", + "RGB": "0x000000" + }, + { + "User": "Gray", + "Library": "Gray", + "RGB": "0x808080" + }, + { + "User": "Blue", + "Library": "Blue", + "RGB": "0x0000FF" + }, + { + "User": "Red", + "Library": "Red", + "RGB": "0xFF0000" + }, + { + "User": "Magenta", + "Library": "Magenta", + "RGB": "0xFF00FF" + }, + { + "User": "Green", + "Library": "Green", + "RGB": "0x008000" + }, + { + "User": "Yellow", + "Library": "Yellow", + "RGB": "0xFFFF00" + }, + { + "User": "Cyan", + "Library": "Cyan", + "RGB": "0x00FFFF" + }, + { + "User": "Lime", + "Library": "Lime", + "RGB": "0x00FF00" + }, + { + "User": "Maroon", + "Library": "Maroon", + "RGB": "0x800000" + }, + { + "User": "Navy", + "Library": "Navy", + "RGB": "0x000080" + }, + { + "User": "Olive", + "Library": "Olive", + "RGB": "0x808000" + }, + { + "User": "Purple", + "Library": "Purple", + "RGB": "0x800080" + }, + { + "User": "Silver", + "Library": "Silver", + "RGB": "0xC0C0C0" + }, + { + "User": "Teal", + "Library": "Teal", + "RGB": "0x008080" + }, + { + "User": "Orange", + "Library": "Orange", + "RGB": "0xFFA500" + }, + { + "User": "Pink", + "Library": "Pink", + "RGB": "0xFFC0CB" + }, + { + "User": "SkyBlue", + "Library": "SkyBlue", + "RGB": "0x87CEEB" + } + ] + }, + { + "Justifications" : [ + { + "User": "Left", + "Library": "justifyLeft" + }, + { + "User": "Right", + "Library": "justifyRight" + }, + { + "User": "Center", + "Library": "justifyCenter" + } + ] + } + ] + }, + { + "GWIN" : [ + { + "Fonts" : [ + { + "User": "uGFX Font 1", + "Library": "UI1", + "Config": "GDISP_INCLUDE_FONT_UI1", + "Size": 10 + }, + { + "User": "uGFX Font 2", + "Library": "UI2", + "Config": "GDISP_INCLUDE_FONT_UI2", + "Size": 10 + }, + { + "User": "Fixed 5x8", + "Library": "fixed_5x8", + "Config": "GDISP_INCLUDE_FONT_FIXED_5X8", + "Size": 8 + }, + { + "User": "Fixed 7x14", + "Library": "fixed_7x14", + "Config": "GDISP_INCLUDE_FONT_FIXED_7X14", + "Size": 14 + }, + { + "User": "Fixed 10x20", + "Library": "fixed_10x20", + "Config": "GDISP_INCLUDE_FONT_FIXED_10X20", + "Size": 20 + }, + { + "User": "DejaVu Sans 10", + "Library": "DejaVuSans10", + "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS10", + "Size": 10 + }, + { + "User": "DejaVu Sans 12", + "Library": "DejaVuSans12", + "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS12", + "Size": 12 + }, + { + "User": "DejaVu Sans 16", + "Library": "DejaVuSans16", + "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS16", + "Size": 16 + }, + { + "User": "DejaVu Sans 20", + "Library": "DejaVuSans20", + "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS20", + "Size": 20 + }, + { + "User": "DejaVu Sans 24", + "Library": "DejaVuSans24", + "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS24", + "Size": 24 + }, + { + "User": "DejaVu Sans 32", + "Library": "DejaVuSans32", + "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS32", + "Size": 32 + }, + { + "User": "DejaVu Sans 12 Anti-Aliased", + "Library": "DejaVuSans12_aa", + "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS12_AA", + "Size": 12 + }, + { + "User": "DejaVu Sans 16 Anti-Aliased", + "Library": "DejaVuSans16_aa", + "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS16_AA", + "Size": 16 + }, + { + "User": "DejaVu Sans 20 Anti-Aliased", + "Library": "DejaVuSans20_aa", + "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS20_AA", + "Size": 20 + }, + { + "User": "DejaVu Sans 24 Anti-Aliased", + "Library": "DejaVuSans24_aa", + "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS24_AA", + "Size": 24 + }, + { + "User": "DejaVu Sans 32 Anti-Aliased", + "Library": "DejaVuSans32_aa", + "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS32_AA", + "Size": 32 + }, + { + "User": "Large Numbers", + "Library": "LargeNumbers", + "Config": "GDISP_INCLUDE_FONT_LARGENUMBERS", + "Size": 23 + } + ] + }, + { + "Styles" : [ + { + "User": "White", + "Handle": "WhiteWidgetStyle", + "Colors": + { + "Background": + { + "User": "", + "Library": "", + "RGB": "0xFFFFFF" + }, + "Enabled": + { + "Text": + { + "User": "", + "Library": "", + "RGB": "0x000000" + }, + "Edge": + { + "User": "", + "Library": "", + "RGB": "0x404040" + }, + "Fill": + { + "User": "", + "Library": "", + "RGB": "0xE0E0E0" + }, + "Progress": + { + "User": "", + "Library": "", + "RGB": "0xE0E0E0" + } + }, + "Disabled": + { + "Text": + { + "User": "", + "Library": "", + "RGB": "0xC0C0C0" + }, + "Edge": + { + "User": "", + "Library": "", + "RGB": "0x808080" + }, + "Fill": + { + "User": "", + "Library": "", + "RGB": "0xE0E0E0" + }, + "Progress": + { + "User": "", + "Library": "", + "RGB": "0xC0E0C0" + } + }, + "Pressed": + { + "Text": + { + "User": "", + "Library": "", + "RGB": "0x404040" + }, + "Edge": + { + "User": "", + "Library": "", + "RGB": "0x404040" + }, + "Fill": + { + "User": "", + "Library": "", + "RGB": "0x808080" + }, + "Progress": + { + "User": "", + "Library": "", + "RGB": "0x00E000" + } + } + } + }, + { + "User": "Black", + "Handle": "BlackWidgetStyle", + "Colors": + { + "Background": + { + "User": "", + "Library": "", + "RGB": "0x000000" + }, + "Enabled": + { + "Text": + { + "User": "", + "Library": "", + "RGB": "0xC0C0C0" + }, + "Edge": + { + "User": "", + "Library": "", + "RGB": "0xC0C0C0" + }, + "Fill": + { + "User": "", + "Library": "", + "RGB": "0x606060" + }, + "Progress": + { + "User": "", + "Library": "", + "RGB": "0x404040" + } + }, + "Disabled": + { + "Text": + { + "User": "", + "Library": "", + "RGB": "0x808080" + }, + "Edge": + { + "User": "", + "Library": "", + "RGB": "0x404040" + }, + "Fill": + { + "User": "", + "Library": "", + "RGB": "0x404040" + }, + "Progress": + { + "User": "", + "Library": "", + "RGB": "0x004000" + } + }, + "Pressed": + { + "Text": + { + "User": "", + "Library": "", + "RGB": "0xFFFFFF" + }, + "Edge": + { + "User": "", + "Library": "", + "RGB": "0xC0C0C0" + }, + "Fill": + { + "User": "", + "Library": "", + "RGB": "0xE0E0E0" + }, + "Progress": + { + "User": "", + "Library": "", + "RGB": "0x008000" + } + } + } + } + ] + } + ] + } +] diff --git a/tools/studio/options_v1.json b/tools/studio/options_v1.json new file mode 100644 index 00000000..edaf5efa --- /dev/null +++ b/tools/studio/options_v1.json @@ -0,0 +1,471 @@ +[ + { + "GOS" : [ + { + "Priorities" : [ + { + "User": "Low", + "Library": "LOW_PRIORITY" + }, + { + "User": "Normal", + "Library": "NORMAL_PRIORITY" + }, + { + "User": "High", + "Library": "HIGH_PRIORITY" + } + ] + } + ] + }, + { + "GDISP" : [ + { + "Orientations" : [ + { + "User": "Native", + "Library": "GDISP_ROTATE_0" + }, + { + "User": "Portrait", + "Library": "GDISP_ROTATE_PORTRAIT" + }, + { + "User": "Landscape", + "Library": "GDISP_ROTATE_LANDSCAPE" + }, + { + "User": "Rotate 90 degree", + "Library": "GDISP_ROTATE_90" + }, + { + "User": "Rotate 180 degree", + "Library": "GDISP_ROTATE_180" + }, + { + "User": "Rotate 270 degree", + "Library": "GDISP_ROTATE_270" + } + ] + }, + { + "Colors" : [ + { + "User": "White", + "Library" : "White", + "RGB": "0xFFFFFF" + }, + { + "User": "Black", + "Library": "Black", + "RGB": "0x000000" + }, + { + "User": "Gray", + "Library": "Gray", + "RGB": "0x808080" + }, + { + "User": "Blue", + "Library": "Blue", + "RGB": "0x0000FF" + }, + { + "User": "Red", + "Library": "Red", + "RGB": "0xFF0000" + }, + { + "User": "Magenta", + "Library": "Magenta", + "RGB": "0xFF00FF" + }, + { + "User": "Green", + "Library": "Green", + "RGB": "0x008000" + }, + { + "User": "Yellow", + "Library": "Yellow", + "RGB": "0xFFFF00" + }, + { + "User": "Cyan", + "Library": "Cyan", + "RGB": "0x00FFFF" + }, + { + "User": "Lime", + "Library": "Lime", + "RGB": "0x00FF00" + }, + { + "User": "Maroon", + "Library": "Maroon", + "RGB": "0x800000" + }, + { + "User": "Navy", + "Library": "Navy", + "RGB": "0x000080" + }, + { + "User": "Olive", + "Library": "Olive", + "RGB": "0x808000" + }, + { + "User": "Purple", + "Library": "Purple", + "RGB": "0x800080" + }, + { + "User": "Silver", + "Library": "Silver", + "RGB": "0xC0C0C0" + }, + { + "User": "Teal", + "Library": "Teal", + "RGB": "0x008080" + }, + { + "User": "Orange", + "Library": "Orange", + "RGB": "0xFFA500" + }, + { + "User": "Pink", + "Library": "Pink", + "RGB": "0xFFC0CB" + }, + { + "User": "SkyBlue", + "Library": "SkyBlue", + "RGB": "0x87CEEB" + } + ] + }, + { + "Justifications" : [ + { + "User": "Left", + "Library": "justifyLeft" + }, + { + "User": "Right", + "Library": "justifyRight" + }, + { + "User": "Center", + "Library": "justifyCenter" + } + ] + } + ] + }, + { + "GWIN" : [ + { + "Fonts" : [ + { + "User": "uGFX Font 1", + "Library": "UI1", + "Config": "GDISP_INCLUDE_FONT_UI1", + "Size": 10 + }, + { + "User": "uGFX Font 2", + "Library": "UI2", + "Config": "GDISP_INCLUDE_FONT_UI2", + "Size": 10 + }, + { + "User": "Fixed 5x8", + "Library": "fixed_5x8", + "Config": "GDISP_INCLUDE_FONT_FIXED_5X8", + "Size": 8 + }, + { + "User": "Fixed 7x14", + "Library": "fixed_7x14", + "Config": "GDISP_INCLUDE_FONT_FIXED_7X14", + "Size": 14 + }, + { + "User": "Fixed 10x20", + "Library": "fixed_10x20", + "Config": "GDISP_INCLUDE_FONT_FIXED_10X20", + "Size": 20 + }, + { + "User": "DejaVu Sans 10", + "Library": "DejaVuSans10", + "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS10", + "Size": 10 + }, + { + "User": "DejaVu Sans 12", + "Library": "DejaVuSans12", + "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS12", + "Size": 12 + }, + { + "User": "DejaVu Sans 16", + "Library": "DejaVuSans16", + "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS16", + "Size": 16 + }, + { + "User": "DejaVu Sans 20", + "Library": "DejaVuSans20", + "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS20", + "Size": 20 + }, + { + "User": "DejaVu Sans 24", + "Library": "DejaVuSans24", + "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS24", + "Size": 24 + }, + { + "User": "DejaVu Sans 32", + "Library": "DejaVuSans32", + "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS32", + "Size": 32 + }, + { + "User": "DejaVu Sans 12 Anti-Aliased", + "Library": "DejaVuSans12_aa", + "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS12_AA", + "Size": 12 + }, + { + "User": "DejaVu Sans 16 Anti-Aliased", + "Library": "DejaVuSans16_aa", + "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS16_AA", + "Size": 16 + }, + { + "User": "DejaVu Sans 20 Anti-Aliased", + "Library": "DejaVuSans20_aa", + "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS20_AA", + "Size": 20 + }, + { + "User": "DejaVu Sans 24 Anti-Aliased", + "Library": "DejaVuSans24_aa", + "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS24_AA", + "Size": 24 + }, + { + "User": "DejaVu Sans 32 Anti-Aliased", + "Library": "DejaVuSans32_aa", + "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS32_AA", + "Size": 32 + }, + { + "User": "Large Numbers", + "Library": "LargeNumbers", + "Config": "GDISP_INCLUDE_FONT_LARGENUMBERS", + "Size": 23 + } + ] + }, + { + "Styles" : [ + { + "User": "White", + "Handle": "WhiteWidgetStyle", + "Colors": + { + "Background": + { + "User": "", + "Library": "", + "RGB": "0xFFFFFF" + }, + "Enabled": + { + "Text": + { + "User": "", + "Library": "", + "RGB": "0x000000" + }, + "Edge": + { + "User": "", + "Library": "", + "RGB": "0x404040" + }, + "Fill": + { + "User": "", + "Library": "", + "RGB": "0xE0E0E0" + }, + "Progress": + { + "User": "", + "Library": "", + "RGB": "0xE0E0E0" + } + }, + "Disabled": + { + "Text": + { + "User": "", + "Library": "", + "RGB": "0xC0C0C0" + }, + "Edge": + { + "User": "", + "Library": "", + "RGB": "0x808080" + }, + "Fill": + { + "User": "", + "Library": "", + "RGB": "0xE0E0E0" + }, + "Progress": + { + "User": "", + "Library": "", + "RGB": "0xC0E0C0" + } + }, + "Pressed": + { + "Text": + { + "User": "", + "Library": "", + "RGB": "0x404040" + }, + "Edge": + { + "User": "", + "Library": "", + "RGB": "0x404040" + }, + "Fill": + { + "User": "", + "Library": "", + "RGB": "0x808080" + }, + "Progress": + { + "User": "", + "Library": "", + "RGB": "0x00E000" + } + } + } + }, + { + "User": "Black", + "Handle": "BlackWidgetStyle", + "Colors": + { + "Background": + { + "User": "", + "Library": "", + "RGB": "0x000000" + }, + "Enabled": + { + "Text": + { + "User": "", + "Library": "", + "RGB": "0xC0C0C0" + }, + "Edge": + { + "User": "", + "Library": "", + "RGB": "0xC0C0C0" + }, + "Fill": + { + "User": "", + "Library": "", + "RGB": "0x606060" + }, + "Progress": + { + "User": "", + "Library": "", + "RGB": "0x404040" + } + }, + "Disabled": + { + "Text": + { + "User": "", + "Library": "", + "RGB": "0x808080" + }, + "Edge": + { + "User": "", + "Library": "", + "RGB": "0x404040" + }, + "Fill": + { + "User": "", + "Library": "", + "RGB": "0x404040" + }, + "Progress": + { + "User": "", + "Library": "", + "RGB": "0x004000" + } + }, + "Pressed": + { + "Text": + { + "User": "", + "Library": "", + "RGB": "0xFFFFFF" + }, + "Edge": + { + "User": "", + "Library": "", + "RGB": "0xC0C0C0" + }, + "Fill": + { + "User": "", + "Library": "", + "RGB": "0xE0E0E0" + }, + "Progress": + { + "User": "", + "Library": "", + "RGB": "0x008000" + } + } + } + } + ] + } + ] + } +] From 9198aa8facea5262dcf96069cfafaafd1e28f6db Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Wed, 8 Jul 2015 22:45:51 +0200 Subject: [PATCH 09/26] Renaming JSON files used by the uGFX-Studio --- tools/studio/options_v0.json | 471 ----------------------------------- 1 file changed, 471 deletions(-) delete mode 100644 tools/studio/options_v0.json diff --git a/tools/studio/options_v0.json b/tools/studio/options_v0.json deleted file mode 100644 index edaf5efa..00000000 --- a/tools/studio/options_v0.json +++ /dev/null @@ -1,471 +0,0 @@ -[ - { - "GOS" : [ - { - "Priorities" : [ - { - "User": "Low", - "Library": "LOW_PRIORITY" - }, - { - "User": "Normal", - "Library": "NORMAL_PRIORITY" - }, - { - "User": "High", - "Library": "HIGH_PRIORITY" - } - ] - } - ] - }, - { - "GDISP" : [ - { - "Orientations" : [ - { - "User": "Native", - "Library": "GDISP_ROTATE_0" - }, - { - "User": "Portrait", - "Library": "GDISP_ROTATE_PORTRAIT" - }, - { - "User": "Landscape", - "Library": "GDISP_ROTATE_LANDSCAPE" - }, - { - "User": "Rotate 90 degree", - "Library": "GDISP_ROTATE_90" - }, - { - "User": "Rotate 180 degree", - "Library": "GDISP_ROTATE_180" - }, - { - "User": "Rotate 270 degree", - "Library": "GDISP_ROTATE_270" - } - ] - }, - { - "Colors" : [ - { - "User": "White", - "Library" : "White", - "RGB": "0xFFFFFF" - }, - { - "User": "Black", - "Library": "Black", - "RGB": "0x000000" - }, - { - "User": "Gray", - "Library": "Gray", - "RGB": "0x808080" - }, - { - "User": "Blue", - "Library": "Blue", - "RGB": "0x0000FF" - }, - { - "User": "Red", - "Library": "Red", - "RGB": "0xFF0000" - }, - { - "User": "Magenta", - "Library": "Magenta", - "RGB": "0xFF00FF" - }, - { - "User": "Green", - "Library": "Green", - "RGB": "0x008000" - }, - { - "User": "Yellow", - "Library": "Yellow", - "RGB": "0xFFFF00" - }, - { - "User": "Cyan", - "Library": "Cyan", - "RGB": "0x00FFFF" - }, - { - "User": "Lime", - "Library": "Lime", - "RGB": "0x00FF00" - }, - { - "User": "Maroon", - "Library": "Maroon", - "RGB": "0x800000" - }, - { - "User": "Navy", - "Library": "Navy", - "RGB": "0x000080" - }, - { - "User": "Olive", - "Library": "Olive", - "RGB": "0x808000" - }, - { - "User": "Purple", - "Library": "Purple", - "RGB": "0x800080" - }, - { - "User": "Silver", - "Library": "Silver", - "RGB": "0xC0C0C0" - }, - { - "User": "Teal", - "Library": "Teal", - "RGB": "0x008080" - }, - { - "User": "Orange", - "Library": "Orange", - "RGB": "0xFFA500" - }, - { - "User": "Pink", - "Library": "Pink", - "RGB": "0xFFC0CB" - }, - { - "User": "SkyBlue", - "Library": "SkyBlue", - "RGB": "0x87CEEB" - } - ] - }, - { - "Justifications" : [ - { - "User": "Left", - "Library": "justifyLeft" - }, - { - "User": "Right", - "Library": "justifyRight" - }, - { - "User": "Center", - "Library": "justifyCenter" - } - ] - } - ] - }, - { - "GWIN" : [ - { - "Fonts" : [ - { - "User": "uGFX Font 1", - "Library": "UI1", - "Config": "GDISP_INCLUDE_FONT_UI1", - "Size": 10 - }, - { - "User": "uGFX Font 2", - "Library": "UI2", - "Config": "GDISP_INCLUDE_FONT_UI2", - "Size": 10 - }, - { - "User": "Fixed 5x8", - "Library": "fixed_5x8", - "Config": "GDISP_INCLUDE_FONT_FIXED_5X8", - "Size": 8 - }, - { - "User": "Fixed 7x14", - "Library": "fixed_7x14", - "Config": "GDISP_INCLUDE_FONT_FIXED_7X14", - "Size": 14 - }, - { - "User": "Fixed 10x20", - "Library": "fixed_10x20", - "Config": "GDISP_INCLUDE_FONT_FIXED_10X20", - "Size": 20 - }, - { - "User": "DejaVu Sans 10", - "Library": "DejaVuSans10", - "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS10", - "Size": 10 - }, - { - "User": "DejaVu Sans 12", - "Library": "DejaVuSans12", - "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS12", - "Size": 12 - }, - { - "User": "DejaVu Sans 16", - "Library": "DejaVuSans16", - "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS16", - "Size": 16 - }, - { - "User": "DejaVu Sans 20", - "Library": "DejaVuSans20", - "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS20", - "Size": 20 - }, - { - "User": "DejaVu Sans 24", - "Library": "DejaVuSans24", - "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS24", - "Size": 24 - }, - { - "User": "DejaVu Sans 32", - "Library": "DejaVuSans32", - "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS32", - "Size": 32 - }, - { - "User": "DejaVu Sans 12 Anti-Aliased", - "Library": "DejaVuSans12_aa", - "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS12_AA", - "Size": 12 - }, - { - "User": "DejaVu Sans 16 Anti-Aliased", - "Library": "DejaVuSans16_aa", - "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS16_AA", - "Size": 16 - }, - { - "User": "DejaVu Sans 20 Anti-Aliased", - "Library": "DejaVuSans20_aa", - "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS20_AA", - "Size": 20 - }, - { - "User": "DejaVu Sans 24 Anti-Aliased", - "Library": "DejaVuSans24_aa", - "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS24_AA", - "Size": 24 - }, - { - "User": "DejaVu Sans 32 Anti-Aliased", - "Library": "DejaVuSans32_aa", - "Config": "GDISP_INCLUDE_FONT_DEJAVUSANS32_AA", - "Size": 32 - }, - { - "User": "Large Numbers", - "Library": "LargeNumbers", - "Config": "GDISP_INCLUDE_FONT_LARGENUMBERS", - "Size": 23 - } - ] - }, - { - "Styles" : [ - { - "User": "White", - "Handle": "WhiteWidgetStyle", - "Colors": - { - "Background": - { - "User": "", - "Library": "", - "RGB": "0xFFFFFF" - }, - "Enabled": - { - "Text": - { - "User": "", - "Library": "", - "RGB": "0x000000" - }, - "Edge": - { - "User": "", - "Library": "", - "RGB": "0x404040" - }, - "Fill": - { - "User": "", - "Library": "", - "RGB": "0xE0E0E0" - }, - "Progress": - { - "User": "", - "Library": "", - "RGB": "0xE0E0E0" - } - }, - "Disabled": - { - "Text": - { - "User": "", - "Library": "", - "RGB": "0xC0C0C0" - }, - "Edge": - { - "User": "", - "Library": "", - "RGB": "0x808080" - }, - "Fill": - { - "User": "", - "Library": "", - "RGB": "0xE0E0E0" - }, - "Progress": - { - "User": "", - "Library": "", - "RGB": "0xC0E0C0" - } - }, - "Pressed": - { - "Text": - { - "User": "", - "Library": "", - "RGB": "0x404040" - }, - "Edge": - { - "User": "", - "Library": "", - "RGB": "0x404040" - }, - "Fill": - { - "User": "", - "Library": "", - "RGB": "0x808080" - }, - "Progress": - { - "User": "", - "Library": "", - "RGB": "0x00E000" - } - } - } - }, - { - "User": "Black", - "Handle": "BlackWidgetStyle", - "Colors": - { - "Background": - { - "User": "", - "Library": "", - "RGB": "0x000000" - }, - "Enabled": - { - "Text": - { - "User": "", - "Library": "", - "RGB": "0xC0C0C0" - }, - "Edge": - { - "User": "", - "Library": "", - "RGB": "0xC0C0C0" - }, - "Fill": - { - "User": "", - "Library": "", - "RGB": "0x606060" - }, - "Progress": - { - "User": "", - "Library": "", - "RGB": "0x404040" - } - }, - "Disabled": - { - "Text": - { - "User": "", - "Library": "", - "RGB": "0x808080" - }, - "Edge": - { - "User": "", - "Library": "", - "RGB": "0x404040" - }, - "Fill": - { - "User": "", - "Library": "", - "RGB": "0x404040" - }, - "Progress": - { - "User": "", - "Library": "", - "RGB": "0x004000" - } - }, - "Pressed": - { - "Text": - { - "User": "", - "Library": "", - "RGB": "0xFFFFFF" - }, - "Edge": - { - "User": "", - "Library": "", - "RGB": "0xC0C0C0" - }, - "Fill": - { - "User": "", - "Library": "", - "RGB": "0xE0E0E0" - }, - "Progress": - { - "User": "", - "Library": "", - "RGB": "0x008000" - } - } - } - } - ] - } - ] - } -] From 926c8e507b7611e5bf182942872f770b22a5c7bd Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Wed, 8 Jul 2015 23:55:02 +0200 Subject: [PATCH 10/26] Adding correct display parameters --- .../base/STM32F746-Discovery/board_STM32F746Discovery.h | 8 ++++---- .../board_STM32F746Discovery_template.h | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/boards/base/STM32F746-Discovery/board_STM32F746Discovery.h b/boards/base/STM32F746-Discovery/board_STM32F746Discovery.h index c06d06c6..735cdbdb 100644 --- a/boards/base/STM32F746-Discovery/board_STM32F746Discovery.h +++ b/boards/base/STM32F746-Discovery/board_STM32F746Discovery.h @@ -14,9 +14,9 @@ static const ltdcConfig driverCfg = { 480, 270, // Width, Height (pixels) - 10, 2, // Horizontal, Vertical sync (pixels) - 20, 2, // Horizontal, Vertical back porch (pixels) - 10, 4, // Horizontal, Vertical front porch (pixels) + 41, 10, // Horizontal, Vertical sync (pixels) + 13, 2, // Horizontal, Vertical back porch (pixels) + 32, 2, // Horizontal, Vertical front porch (pixels) 0, // Sync flags 0x000000, // Clear color (RGB888) @@ -35,7 +35,7 @@ static const ltdcConfig driverCfg = { 0xFF, // Constant alpha factor LTDC_LEF_ENABLE // Layer configuration flags }, - + LTDC_UNUSED_LAYER_CONFIG // Foreground layer config }; diff --git a/drivers/gdisp/STM32F746Discovery/board_STM32F746Discovery_template.h b/drivers/gdisp/STM32F746Discovery/board_STM32F746Discovery_template.h index df605838..7f785e18 100644 --- a/drivers/gdisp/STM32F746Discovery/board_STM32F746Discovery_template.h +++ b/drivers/gdisp/STM32F746Discovery/board_STM32F746Discovery_template.h @@ -10,9 +10,9 @@ static const ltdcConfig driverCfg = { 480, 270, // Width, Height (pixels) - 10, 2, // Horizontal, Vertical sync (pixels) - 20, 2, // Horizontal, Vertical back porch (pixels) - 10, 4, // Horizontal, Vertical front porch (pixels) + 41, 10, // Horizontal, Vertical sync (pixels) + 13, 2, // Horizontal, Vertical back porch (pixels) + 32, 2, // Horizontal, Vertical front porch (pixels) 0, // Sync flags 0x000000, // Clear color (RGB888) From c58dabc9c9aaa26e1d273e62c8e7508a0a3f7690 Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Thu, 9 Jul 2015 00:43:04 +0200 Subject: [PATCH 11/26] Renaming driver to STM32LTDC as this will be a generic one --- boards/base/STM32F746-Discovery/board.mk | 2 +- drivers/gdisp/STM32F746Discovery/driver.mk | 2 -- .../board_STM32LTDC_template.h} | 0 drivers/gdisp/STM32LTDC/driver.mk | 2 ++ .../gdisp_lld_STM32LTDC.c} | 8 ++++---- .../{STM32F746Discovery => STM32LTDC}/gdisp_lld_config.h | 0 .../gdisp/{STM32F746Discovery => STM32LTDC}/readme.txt | 4 ++-- .../gdisp/{STM32F746Discovery => STM32LTDC}/stm32_ltdc.h | 0 8 files changed, 9 insertions(+), 9 deletions(-) delete mode 100644 drivers/gdisp/STM32F746Discovery/driver.mk rename drivers/gdisp/{STM32F746Discovery/board_STM32F746Discovery_template.h => STM32LTDC/board_STM32LTDC_template.h} (100%) create mode 100644 drivers/gdisp/STM32LTDC/driver.mk rename drivers/gdisp/{STM32F746Discovery/gdisp_lld_STM32F746Discovery.c => STM32LTDC/gdisp_lld_STM32LTDC.c} (98%) rename drivers/gdisp/{STM32F746Discovery => STM32LTDC}/gdisp_lld_config.h (100%) rename drivers/gdisp/{STM32F746Discovery => STM32LTDC}/readme.txt (56%) rename drivers/gdisp/{STM32F746Discovery => STM32LTDC}/stm32_ltdc.h (100%) diff --git a/boards/base/STM32F746-Discovery/board.mk b/boards/base/STM32F746-Discovery/board.mk index 92854414..d43e1709 100644 --- a/boards/base/STM32F746-Discovery/board.mk +++ b/boards/base/STM32F746-Discovery/board.mk @@ -2,4 +2,4 @@ GFXINC += $(GFXLIB)/boards/base/STM32F746-Discovery GFXSRC += $(GFXLIB)/boards/base/STM32F746-Discovery/STM32F746_discovery_sdram.c \ $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f4xx_fmc.c -include $(GFXLIB)/drivers/gdisp/STM32F746Discovery/driver.mk \ No newline at end of file +include $(GFXLIB)/drivers/gdisp/STM32LTDC/driver.mk \ No newline at end of file diff --git a/drivers/gdisp/STM32F746Discovery/driver.mk b/drivers/gdisp/STM32F746Discovery/driver.mk deleted file mode 100644 index 720d5d1c..00000000 --- a/drivers/gdisp/STM32F746Discovery/driver.mk +++ /dev/null @@ -1,2 +0,0 @@ -GFXINC += $(GFXLIB)/drivers/gdisp/STM32F746Discovery -GFXSRC += $(GFXLIB)/drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c diff --git a/drivers/gdisp/STM32F746Discovery/board_STM32F746Discovery_template.h b/drivers/gdisp/STM32LTDC/board_STM32LTDC_template.h similarity index 100% rename from drivers/gdisp/STM32F746Discovery/board_STM32F746Discovery_template.h rename to drivers/gdisp/STM32LTDC/board_STM32LTDC_template.h diff --git a/drivers/gdisp/STM32LTDC/driver.mk b/drivers/gdisp/STM32LTDC/driver.mk new file mode 100644 index 00000000..efed78f5 --- /dev/null +++ b/drivers/gdisp/STM32LTDC/driver.mk @@ -0,0 +1,2 @@ +GFXINC += $(GFXLIB)/drivers/gdisp/STM32LTDC +GFXSRC += $(GFXLIB)/drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c diff --git a/drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c b/drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c similarity index 98% rename from drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c rename to drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c index ed4e8e20..118b6874 100644 --- a/drivers/gdisp/STM32F746Discovery/gdisp_lld_STM32F746Discovery.c +++ b/drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c @@ -18,8 +18,8 @@ #undef GDISP_SCREEN_WIDTH #endif -#define GDISP_DRIVER_VMT GDISPVMT_STM32F746Discovery -#include "drivers/gdisp/STM32F746Discovery/gdisp_lld_config.h" +#define GDISP_DRIVER_VMT GDISPVMT_STM32LTDC +#include "drivers/gdisp/STM32LTDC/gdisp_lld_config.h" #include "src/gdisp/gdisp_driver.h" #include "stm32_ltdc.h" @@ -67,10 +67,10 @@ typedef struct ltdcConfig { #define LTDC_PIXELBYTES 3 #define LTDC_PIXELBITS 24 #else - #error "GDISP: STM32F746Discovery - unsupported pixel format" + #error "GDISP: STM32LTDC - unsupported pixel format" #endif -#include "board_STM32F746Discovery.h" +#include "board_STM32LTDC.h" /*===========================================================================*/ /* Driver local definitions. */ diff --git a/drivers/gdisp/STM32F746Discovery/gdisp_lld_config.h b/drivers/gdisp/STM32LTDC/gdisp_lld_config.h similarity index 100% rename from drivers/gdisp/STM32F746Discovery/gdisp_lld_config.h rename to drivers/gdisp/STM32LTDC/gdisp_lld_config.h diff --git a/drivers/gdisp/STM32F746Discovery/readme.txt b/drivers/gdisp/STM32LTDC/readme.txt similarity index 56% rename from drivers/gdisp/STM32F746Discovery/readme.txt rename to drivers/gdisp/STM32LTDC/readme.txt index e21429df..269d3cfb 100644 --- a/drivers/gdisp/STM32F746Discovery/readme.txt +++ b/drivers/gdisp/STM32LTDC/readme.txt @@ -5,7 +5,7 @@ To use this driver: 2. To your makefile add the following lines: include $(GFXLIB)/gfx.mk - include $(GFXLIB)/drivers/gdisp/STM32F746Discovery/driver.mk + include $(GFXLIB)/drivers/gdisp/STM32LTDC/driver.mk -3. Add a board_STM32F746Discovery.h to you project directory (or board directory) +3. Add a board_STM32LTDC.h to you project directory (or board directory) based on one of the templates. diff --git a/drivers/gdisp/STM32F746Discovery/stm32_ltdc.h b/drivers/gdisp/STM32LTDC/stm32_ltdc.h similarity index 100% rename from drivers/gdisp/STM32F746Discovery/stm32_ltdc.h rename to drivers/gdisp/STM32LTDC/stm32_ltdc.h From d4f2cb0d72c3fd6d0c57113bf71e3225b82c5306 Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Thu, 9 Jul 2015 03:12:16 +0200 Subject: [PATCH 12/26] Some more work on the F7 discovery --- boards/base/STM32F746-Discovery/board.mk | 4 +- .../board_STM32F746Discovery.h | 4 +- .../stm32f429i_discovery_sdram.c | 333 ------------------ .../stm32f429i_discovery_sdram.h | 96 ----- ...y_sdram.c => stm32f746g_discovery_sdram.c} | 2 +- ...y_sdram.h => stm32f746g_discovery_sdram.h} | 66 ++-- 6 files changed, 39 insertions(+), 466 deletions(-) delete mode 100644 boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.c delete mode 100644 boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.h rename boards/base/STM32F746-Discovery/{stm32746g_discovery_sdram.c => stm32f746g_discovery_sdram.c} (99%) rename boards/base/STM32F746-Discovery/{stm32746g_discovery_sdram.h => stm32f746g_discovery_sdram.h} (93%) diff --git a/boards/base/STM32F746-Discovery/board.mk b/boards/base/STM32F746-Discovery/board.mk index d43e1709..ce70ef15 100644 --- a/boards/base/STM32F746-Discovery/board.mk +++ b/boards/base/STM32F746-Discovery/board.mk @@ -1,5 +1,5 @@ GFXINC += $(GFXLIB)/boards/base/STM32F746-Discovery -GFXSRC += $(GFXLIB)/boards/base/STM32F746-Discovery/STM32F746_discovery_sdram.c \ - $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f4xx_fmc.c +GFXSRC += $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c \ + $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c include $(GFXLIB)/drivers/gdisp/STM32LTDC/driver.mk \ No newline at end of file diff --git a/boards/base/STM32F746-Discovery/board_STM32F746Discovery.h b/boards/base/STM32F746-Discovery/board_STM32F746Discovery.h index 735cdbdb..33f6e2cb 100644 --- a/boards/base/STM32F746-Discovery/board_STM32F746Discovery.h +++ b/boards/base/STM32F746-Discovery/board_STM32F746Discovery.h @@ -8,8 +8,8 @@ #ifndef _GDISP_LLD_BOARD_H #define _GDISP_LLD_BOARD_H -#include "stm32f4xx_fmc.h" -#include "stm32f429i_discovery_sdram.h" +#include "stm32f7xx_ll_fmc.h" +#include "stm32f746g_discovery_sdram.h" #include static const ltdcConfig driverCfg = { diff --git a/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.c b/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.c deleted file mode 100644 index 3b467b4b..00000000 --- a/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.c +++ /dev/null @@ -1,333 +0,0 @@ -#include "ch.h" -#include "hal.h" - -#include "stm32f429i_discovery_sdram.h" -#include "stm32f4xx_fmc.h" - -/** - * @brief Configures the FMC and GPIOs to interface with the SDRAM memory. - * This function must be called before any read/write operation - * on the SDRAM. - * @param None - * @retval None - */ -void SDRAM_Init(void) -{ - FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure; - FMC_SDRAMTimingInitTypeDef FMC_SDRAMTimingInitStructure; - - /* Enable FMC clock */ - rccEnableAHB3(RCC_AHB3ENR_FMCEN, FALSE); - -/* FMC Configuration ---------------------------------------------------------*/ -/* FMC SDRAM Bank configuration */ - /* Timing configuration for 84 Mhz of SD clock frequency (168Mhz/2) */ - /* TMRD: 2 Clock cycles */ - FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2; - /* TXSR: min=70ns (6x11.90ns) */ - FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 7; - /* TRAS: min=42ns (4x11.90ns) max=120k (ns) */ - FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4; - /* TRC: min=63 (6x11.90ns) */ - FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 7; - /* TWR: 2 Clock cycles */ - FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2; - /* TRP: 15ns => 2x11.90ns */ - FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2; - /* TRCD: 15ns => 2x11.90ns */ - FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2; - -/* FMC SDRAM control configuration */ - FMC_SDRAMInitStructure.FMC_Bank = FMC_Bank2_SDRAM; - /* Row addressing: [7:0] */ - FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b; - /* Column addressing: [11:0] */ - FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_12b; - FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = SDRAM_MEMORY_WIDTH; - FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4; - FMC_SDRAMInitStructure.FMC_CASLatency = SDRAM_CAS_LATENCY; - FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable; - FMC_SDRAMInitStructure.FMC_SDClockPeriod = SDCLOCK_PERIOD; - FMC_SDRAMInitStructure.FMC_ReadBurst = SDRAM_READBURST; - FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1; - FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure; - - /* FMC SDRAM bank initialization */ - FMC_SDRAMInit(&FMC_SDRAMInitStructure); - - /* FMC SDRAM device initialization sequence */ - SDRAM_InitSequence(); - -} - -/*-- GPIOs Configuration -----------------------------------------------------*/ -/* - +-------------------+--------------------+--------------------+--------------------+ - + SDRAM pins assignment + - +-------------------+--------------------+--------------------+--------------------+ - | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 | - | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 | - | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF2 <-> FMC_A2 | PG8 <-> FMC_SDCLK | - | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF3 <-> FMC_A3 | PG15 <-> FMC_NCAS | - | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF4 <-> FMC_A4 |--------------------+ - | PD14 <-> FMC_D0 | PE10 <-> FMC_D7 | PF5 <-> FMC_A5 | - | PD15 <-> FMC_D1 | PE11 <-> FMC_D8 | PF11 <-> FMC_NRAS | - +-------------------| PE12 <-> FMC_D9 | PF12 <-> FMC_A6 | - | PE13 <-> FMC_D10 | PF13 <-> FMC_A7 | - | PE14 <-> FMC_D11 | PF14 <-> FMC_A8 | - | PE15 <-> FMC_D12 | PF15 <-> FMC_A9 | - +-------------------+--------------------+--------------------+ - | PB5 <-> FMC_SDCKE1| - | PB6 <-> FMC_SDNE1 | - | PC0 <-> FMC_SDNWE | - +-------------------+ - -*/ - -// /* Common GPIO configuration */ -// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; -// GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; -// GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; -// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; -// -// /* GPIOB configuration */ -// GPIO_PinAFConfig(GPIOB, GPIO_PinSource5 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOB, GPIO_PinSource6 , GPIO_AF_FMC); -// -// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6; -// -// GPIO_Init(GPIOB, &GPIO_InitStructure); -// -// /* GPIOC configuration */ -// GPIO_PinAFConfig(GPIOC, GPIO_PinSource0 , GPIO_AF_FMC); -// -// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; -// -// GPIO_Init(GPIOC, &GPIO_InitStructure); -// -// /* GPIOD configuration */ -// GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FMC); -// -// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | -// GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | -// GPIO_Pin_15; -// -// GPIO_Init(GPIOD, &GPIO_InitStructure); -// -// /* GPIOE configuration */ -// GPIO_PinAFConfig(GPIOE, GPIO_PinSource0 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOE, GPIO_PinSource1 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FMC); -// -// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_7 | -// GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | -// GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | -// GPIO_Pin_14 | GPIO_Pin_15; -// -// GPIO_Init(GPIOE, &GPIO_InitStructure); -// -// /* GPIOF configuration */ -// GPIO_PinAFConfig(GPIOF, GPIO_PinSource0 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOF, GPIO_PinSource1 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOF, GPIO_PinSource2 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOF, GPIO_PinSource3 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOF, GPIO_PinSource4 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOF, GPIO_PinSource5 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOF, GPIO_PinSource11 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOF, GPIO_PinSource12 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOF, GPIO_PinSource13 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOF, GPIO_PinSource14 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOF, GPIO_PinSource15 , GPIO_AF_FMC); -// -// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | -// GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | -// GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | -// GPIO_Pin_14 | GPIO_Pin_15; -// -// GPIO_Init(GPIOF, &GPIO_InitStructure); -// -// /* GPIOG configuration */ -// GPIO_PinAFConfig(GPIOG, GPIO_PinSource0 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOG, GPIO_PinSource1 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOG, GPIO_PinSource4 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOG, GPIO_PinSource5 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOG, GPIO_PinSource8 , GPIO_AF_FMC); -// GPIO_PinAFConfig(GPIOG, GPIO_PinSource15 , GPIO_AF_FMC); -// -// -// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | -// GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_15; -// -// GPIO_Init(GPIOG, &GPIO_InitStructure); - -/** - * @brief Executes the SDRAM memory initialization sequence. - * @param None. - * @retval None. - */ -void SDRAM_InitSequence(void) -{ - FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure; - uint32_t tmpr = 0; - -/* Step 3 --------------------------------------------------------------------*/ - /* Configure a clock configuration enable command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - - //In the ST example, this is 100ms, but the 429 RM says 100us is typical, and - //the ISSI datasheet confirms this. 1ms seems plenty, and is much shorter than - //refresh interval, meaning we won't risk losing contents if the SDRAM is in self-refresh - //mode -/* Step 4 --------------------------------------------------------------------*/ - /* Insert 1 ms delay */ - chThdSleepMilliseconds(1); - -/* Step 5 --------------------------------------------------------------------*/ - /* Configure a PALL (precharge all) command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - -/* Step 6 --------------------------------------------------------------------*/ - /* Configure a Auto-Refresh command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 4; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - /* Send the first command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - /* Send the second command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - -/* Step 7 --------------------------------------------------------------------*/ - /* Program the external memory mode register */ - tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 | - SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | - SDRAM_MODEREG_CAS_LATENCY_3 | - SDRAM_MODEREG_OPERATING_MODE_STANDARD | - SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; - - /* Configure a load Mode register command*/ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - -/* Step 8 --------------------------------------------------------------------*/ - - /* Set the refresh rate counter */ - /* (7.81 us x Freq) - 20 */ - /* Set the device refresh counter */ - FMC_SetRefreshCount(683); - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } -} - - -/** - * @brief Writes a Entire-word buffer to the SDRAM memory. - * @param pBuffer: pointer to buffer. - * @param uwWriteAddress: SDRAM memory internal address from which the data will be - * written. - * @param uwBufferSize: number of words to write. - * @retval None. - */ -void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize) -{ - __IO uint32_t write_pointer = (uint32_t)uwWriteAddress; - - /* Disable write protection */ - FMC_SDRAMWriteProtectionConfig(FMC_Bank2_SDRAM, DISABLE); - - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - - /* While there is data to write */ - for (; uwBufferSize != 0; uwBufferSize--) - { - /* Transfer data to the memory */ - *(uint32_t *) (SDRAM_BANK_ADDR + write_pointer) = *pBuffer++; - - /* Increment the address*/ - write_pointer += 4; - } - -} - -/** - * @brief Reads data buffer from the SDRAM memory. - * @param pBuffer: pointer to buffer. - * @param ReadAddress: SDRAM memory internal address from which the data will be - * read. - * @param uwBufferSize: number of words to write. - * @retval None. - */ -void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize) -{ - __IO uint32_t write_pointer = (uint32_t)uwReadAddress; - - - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - - /* Read data */ - for(; uwBufferSize != 0x00; uwBufferSize--) - { - *pBuffer++ = *(__IO uint32_t *)(SDRAM_BANK_ADDR + write_pointer ); - - /* Increment the address*/ - write_pointer += 4; - } -} - diff --git a/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.h b/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.h deleted file mode 100644 index fba5115d..00000000 --- a/boards/base/STM32F746-Discovery/stm32f429i_discovery_sdram.h +++ /dev/null @@ -1,96 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f429i_discovery_sdram.h - * @author MCD Application Team - * @version V1.0.0 - * @date 20-September-2013 - * @brief This file contains all the functions prototypes for the - * stm324x9i_disco_sdram.c driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32429I_DISCO_SDRAM_H -#define __STM32429I_DISCO_SDRAM_H - -#ifdef __cplusplus - extern "C" { -#endif - -//FIXME this should not be needed -#define STM32F429_439xx - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** - * @brief FMC SDRAM Bank address - */ -#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000) - -/** - * @brief FMC SDRAM Memory Width - */ -/* #define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_8b */ -#define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_16b - -/** - * @brief FMC SDRAM CAS Latency - */ -/* #define SDRAM_CAS_LATENCY FMC_CAS_Latency_2 */ -#define SDRAM_CAS_LATENCY FMC_CAS_Latency_3 - -/** - * @brief FMC SDRAM Memory clock period - */ -#define SDCLOCK_PERIOD FMC_SDClock_Period_2 /* Default configuration used with LCD */ -/* #define SDCLOCK_PERIOD FMC_SDClock_Period_3 */ - -/** - * @brief FMC SDRAM Memory Read Burst feature - */ -#define SDRAM_READBURST FMC_Read_Burst_Disable /* Default configuration used with LCD */ -/* #define SDRAM_READBURST FMC_Read_Burst_Enable */ - -/** - * @brief FMC SDRAM Mode definition register defines - */ -#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) -#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) -#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) -#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) -#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) -#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) -#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) - -void SDRAM_Init(void); -void SDRAM_InitSequence(void); -void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize); -void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.c b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c similarity index 99% rename from boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.c rename to boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c index d214b3f1..0ef2d634 100644 --- a/boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.c +++ b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c @@ -76,7 +76,7 @@ */ /* Includes ------------------------------------------------------------------*/ -#include "stm32746g_discovery_sdram.h" +#include "stm32f746g_discovery_sdram.h" /** @addtogroup BSP * @{ diff --git a/boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.h b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h similarity index 93% rename from boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.h rename to boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h index cafdce5c..56d7fd4b 100644 --- a/boards/base/STM32F746-Discovery/stm32746g_discovery_sdram.h +++ b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h @@ -34,44 +34,46 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32746G_DISCOVERY_SDRAM_H -#define __STM32746G_DISCOVERY_SDRAM_H +#ifndef __STM32F746G_DISCOVERY_SDRAM_H +#define __STM32F746G_DISCOVERY_SDRAM_H #ifdef __cplusplus extern "C" { -#endif +#endif /* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" +#include "stm32f7xx_hal_sdram.h" +#include "stm32f7xx_hal_dma.h" +#include "stm32f7xx_ll_fmc.h" /** @addtogroup BSP * @{ - */ + */ /** @addtogroup STM32746G_DISCOVERY * @{ */ - + /** @addtogroup STM32746G_DISCOVERY_SDRAM * @{ - */ + */ /** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Types STM32746G_DISCOVERY_SDRAM Exported Types * @{ */ -/** - * @brief SDRAM status structure definition - */ +/** + * @brief SDRAM status structure definition + */ #define SDRAM_OK ((uint8_t)0x00) #define SDRAM_ERROR ((uint8_t)0x01) /** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Constants STM32746G_DISCOVERY_SDRAM Exported Constants * @{ - */ + */ #define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000) #define SDRAM_DEVICE_SIZE ((uint32_t)0x800000) /* SDRAM device size in MBytes */ @@ -79,23 +81,23 @@ #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16 #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2 -/* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */ +/* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */ #define REFRESH_COUNT ((uint32_t)0x0603) /* SDRAM refresh counter (100Mhz SD clock) */ - + #define SDRAM_TIMEOUT ((uint32_t)0xFFFF) /* DMA definitions for SDRAM DMA transfer */ #define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE #define __DMAx_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE #define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0 -#define SDRAM_DMAx_STREAM DMA2_Stream0 +#define SDRAM_DMAx_STREAM DMA2_Stream0 #define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn -#define SDRAM_DMAx_IRQHandler DMA2_Stream0_IRQHandler +#define SDRAM_DMAx_IRQHandler DMA2_Stream0_IRQHandler /** * @} - */ - + */ + /** * @brief FMC SDRAM Mode definition register defines */ @@ -108,22 +110,22 @@ #define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) #define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) #define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) /** * @} - */ - + */ + /** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Macro STM32746G_DISCOVERY_SDRAM Exported Macro * @{ - */ + */ /** * @} - */ - + */ + /** @addtogroup STM32746G_DISCOVERY_SDRAM_Exported_Functions * @{ - */ + */ uint8_t BSP_SDRAM_Init(void); uint8_t BSP_SDRAM_DeInit(void); void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount); @@ -132,8 +134,8 @@ uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_ uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize); uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd); -void BSP_SDRAM_DMA_IRQHandler(void); - +void BSP_SDRAM_DMA_IRQHandler(void); + /* These functions can be modified in case the current settings (e.g. DMA stream) need to be changed for specific application needs */ void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params); @@ -142,19 +144,19 @@ void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params); /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ #ifdef __cplusplus } From 1137ed6ee76251180dc12b8db59768382fdd3023 Mon Sep 17 00:00:00 2001 From: inmarket Date: Fri, 10 Jul 2015 18:11:36 +1000 Subject: [PATCH 13/26] Makefile additions for stm32m7 and raw32 --- tools/gmake_scripts/cpu_stm32m7.mk | 24 ++++++++++++++++++++++++ tools/gmake_scripts/os_raw32.mk | 13 +++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 tools/gmake_scripts/cpu_stm32m7.mk create mode 100644 tools/gmake_scripts/os_raw32.mk diff --git a/tools/gmake_scripts/cpu_stm32m7.mk b/tools/gmake_scripts/cpu_stm32m7.mk new file mode 100644 index 00000000..0a59e24f --- /dev/null +++ b/tools/gmake_scripts/cpu_stm32m7.mk @@ -0,0 +1,24 @@ +# +# This file is subject to the terms of the GFX License. If a copy of +# the license was not distributed with this file, you can obtain one at: +# +# http://ugfx.org/license.html +# + +# +# See readme.txt for the make API +# + +# Requirements: +# +# NONE +# + +#SRCFLAGS += -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -fsingle-precision-constant -falign-functions=16 +#LDFLAGS += -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -fsingle-precision-constant -falign-functions=16 +#DEFS += CORTEX_USE_FPU=TRUE +#LIBS += m +SRCFLAGS += -mcpu=cortex-m7 -falign-functions=16 +LDFLAGS += -mcpu=cortex-m7 +DEFS += CORTEX_USE_FPU=FALSE + diff --git a/tools/gmake_scripts/os_raw32.mk b/tools/gmake_scripts/os_raw32.mk new file mode 100644 index 00000000..1c96c8ec --- /dev/null +++ b/tools/gmake_scripts/os_raw32.mk @@ -0,0 +1,13 @@ +# +# This file is subject to the terms of the GFX License. If a copy of +# the license was not distributed with this file, you can obtain one at: +# +# http://ugfx.org/license.html +# + +# See readme.txt for the make API + +# Requirements: +# +# NONE +# From dbeb320fd3bf884a6c88f5183e66a91790bc98a6 Mon Sep 17 00:00:00 2001 From: inmarket Date: Fri, 10 Jul 2015 18:12:52 +1000 Subject: [PATCH 14/26] Example make for stm32m7 using ugfx make system (not complete) Changes to some stm32f746 files --- .../Example RAW32/Makefile | 95 +++++++++++++++++++ ...STM32F746Discovery.h => board_STM32LTDC.h} | 0 .../stm32f746g_discovery_sdram.c | 1 + .../STM32F746-Discovery/stm32f7xx_ll_fmc.h | 1 + 4 files changed, 97 insertions(+) create mode 100644 boards/base/STM32F746-Discovery/Example RAW32/Makefile rename boards/base/STM32F746-Discovery/{board_STM32F746Discovery.h => board_STM32LTDC.h} (100%) diff --git a/boards/base/STM32F746-Discovery/Example RAW32/Makefile b/boards/base/STM32F746-Discovery/Example RAW32/Makefile new file mode 100644 index 00000000..48283ebb --- /dev/null +++ b/boards/base/STM32F746-Discovery/Example RAW32/Makefile @@ -0,0 +1,95 @@ +# Possible Targets: all clean Debug cleanDebug Release cleanRelease + +############################################################################################## +# Settings +# + +# General settings + # See $(GFXLIB)/tools/gmake_scripts/readme.txt for the list of variables + OPT_OS = raw32 + OPT_THUMB = yes + OPT_LINK_OPTIMIZE = yes + OPT_CPU = stm32m7 + +# uGFX settings + # See $(GFXLIB)/tools/gmake_scripts/library_ugfx.mk for the list of variables + GFXLIB = ../uGFX + GFXBOARD = STM32F746-Discovery + GFXDEMO = modules/gwin/widgets + #GFXDRIVERS = + +# ChibiOS settings +ifeq ($(OPT_OS),chibios) + # See $(GFXLIB)/tools/gmake_scripts/os_chibios.mk for the list of variables + CHIBIOS = ../ChibiOS + CHIBIOS_BOARD = ST_STM32F429I_DISCOVERY + CHIBIOS_PLATFORM = STM32F4xx + CHIBIOS_PORT = GCC/ARMCMx/STM32F4xx + CHIBIOS_LDSCRIPT = STM32F407xG.ld + + #CHIBIOS = ../ChibiOS3 + #CHIBIOS_VERSION = 3 + #CHIBIOS_BOARD = ST_STM32F429I_DISCOVERY + #CHIBIOS_CPUCLASS = ARMCMx + #CHIBIOS_PLATFORM = STM32/STM32F4xx + #CHIBIOS_PORT = stm32f4xx + #CHIBIOS_LDSCRIPT = STM32F407xG.ld +endif + +CMSIS = CMSIS +HAL = STM32F7xx_HAL_Driver +CONTROLLER = STM32F746xx + +############################################################################################## +# Set these for your project +# + +ARCH = arm-none-eabi- +SRCFLAGS = -ggdb -O0 +CFLAGS = +CXXFLAGS = -fno-rtti +ASFLAGS = +LDFLAGS = + +#SRC = $(HAL)/Src/stm32f7xx_hal.c \ + $(HAL)/Src/stm32f7xx_hal_cortex.c \ + $(HAL)/Src/stm32f7xx_hal_flash.c \ + $(HAL)/Src/stm32f7xx_hal_flash_ex.c \ + $(HAL)/Src/stm32f7xx_hal_rcc.c \ + $(HAL)/Src/stm32f7xx_hal_rcc_ex.h \ + $(HAL)/Src/stm32f7xx_hal_gpio.c \ + $(HAL)/Src/stm32f7xx_hal_pwr.c \ + $(HAL)/Src/stm32f7xx_hal_pwr_ex.c \ + $(HAL)/Src/stm32f7xx_hal_ltdc.c \ + STM32746G-Discovery/stm32746g_discovery.c \ + stm32f7xx_hal_msp.c \ + stm32f7xx_it.c \ + system_stm32f7xx.c \ + ugfx_raw32_implementations.c \ + main.c \ + startup_stm32f746xx.s + +OBJS = +DEFS = +LIBS = +INCPATH = $(CMSIS)/Device/ST/STM32F7xx/Include \ + $(CMSIS)/Include \ + $(HAL)/Inc \ + STM32746G-Discovery + +LIBPATH = +LDSCRIPT = stm32f746nghx_flash.ld + +############################################################################################## +# These should be at the end +# + +include $(GFXLIB)/tools/gmake_scripts/library_ugfx.mk +include $(GFXLIB)/tools/gmake_scripts/os_$(OPT_OS).mk +include $(GFXLIB)/tools/gmake_scripts/compiler_gcc.mk +# *** EOF *** + +#ASFLAGS = -ggdb -Wall +#CFLAGS = -ggdb -g3 -Wall -std=c99 -O0 +#CPPFLAGS = -ggdb -Wall +#LDFLAGS = -fdata-sections diff --git a/boards/base/STM32F746-Discovery/board_STM32F746Discovery.h b/boards/base/STM32F746-Discovery/board_STM32LTDC.h similarity index 100% rename from boards/base/STM32F746-Discovery/board_STM32F746Discovery.h rename to boards/base/STM32F746-Discovery/board_STM32LTDC.h diff --git a/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c index 0ef2d634..5fc5e559 100644 --- a/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c +++ b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c @@ -76,6 +76,7 @@ */ /* Includes ------------------------------------------------------------------*/ +#include "gfx.h" #include "stm32f746g_discovery_sdram.h" /** @addtogroup BSP diff --git a/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.h b/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.h index 019ec064..85e8bedf 100644 --- a/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.h +++ b/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.h @@ -44,6 +44,7 @@ #endif /* Includes ------------------------------------------------------------------*/ +#include "gfx.h" #include "stm32f7xx_hal_def.h" /** @addtogroup STM32F7xx_HAL_Driver From 1dad1ed21f737bea5ba2e6b1491cf48074aa5649 Mon Sep 17 00:00:00 2001 From: inmarket Date: Fri, 10 Jul 2015 18:11:36 +1000 Subject: [PATCH 15/26] Makefile additions for stm32m7 and raw32 --- tools/gmake_scripts/cpu_stm32m7.mk | 24 ++++++++++++++++++++++++ tools/gmake_scripts/os_raw32.mk | 13 +++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 tools/gmake_scripts/cpu_stm32m7.mk create mode 100644 tools/gmake_scripts/os_raw32.mk diff --git a/tools/gmake_scripts/cpu_stm32m7.mk b/tools/gmake_scripts/cpu_stm32m7.mk new file mode 100644 index 00000000..0a59e24f --- /dev/null +++ b/tools/gmake_scripts/cpu_stm32m7.mk @@ -0,0 +1,24 @@ +# +# This file is subject to the terms of the GFX License. If a copy of +# the license was not distributed with this file, you can obtain one at: +# +# http://ugfx.org/license.html +# + +# +# See readme.txt for the make API +# + +# Requirements: +# +# NONE +# + +#SRCFLAGS += -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -fsingle-precision-constant -falign-functions=16 +#LDFLAGS += -mcpu=cortex-m4 -mfloat-abi=hard -mfpu=fpv4-sp-d16 -fsingle-precision-constant -falign-functions=16 +#DEFS += CORTEX_USE_FPU=TRUE +#LIBS += m +SRCFLAGS += -mcpu=cortex-m7 -falign-functions=16 +LDFLAGS += -mcpu=cortex-m7 +DEFS += CORTEX_USE_FPU=FALSE + diff --git a/tools/gmake_scripts/os_raw32.mk b/tools/gmake_scripts/os_raw32.mk new file mode 100644 index 00000000..1c96c8ec --- /dev/null +++ b/tools/gmake_scripts/os_raw32.mk @@ -0,0 +1,13 @@ +# +# This file is subject to the terms of the GFX License. If a copy of +# the license was not distributed with this file, you can obtain one at: +# +# http://ugfx.org/license.html +# + +# See readme.txt for the make API + +# Requirements: +# +# NONE +# From 36906d8877e33ae85a0e9422fa19c486a6e8625e Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Fri, 10 Jul 2015 11:56:25 +0200 Subject: [PATCH 16/26] More work on the F7 discovery --- boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c | 2 ++ boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h | 5 ++++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c index 0ef2d634..9f4511c8 100644 --- a/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c +++ b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c @@ -77,6 +77,8 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f746g_discovery_sdram.h" +#include "stm32f7xx_hal_rcc.h" +#include "stm32f7xx_hal_rcc_ex.h" /** @addtogroup BSP * @{ diff --git a/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h index 56d7fd4b..5512f9d8 100644 --- a/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h +++ b/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h @@ -45,8 +45,11 @@ #endif /* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_sdram.h" +#include "stm32f7xx_hal_rcc.h" +#include "stm32f7xx_hal_rcc_ex.h" #include "stm32f7xx_hal_dma.h" +#include "stm32f7xx_hal_gpio.h" +#include "stm32f7xx_hal_sdram.h" #include "stm32f7xx_ll_fmc.h" /** @addtogroup BSP From a3d67e76e5f65a1fd52642db0fefd81fd6e7cfe6 Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Fri, 10 Jul 2015 12:00:04 +0200 Subject: [PATCH 17/26] Fix in FT5x06 touch driver --- drivers/ginput/touch/FT5x06/gmouse_lld_FT5x06.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ginput/touch/FT5x06/gmouse_lld_FT5x06.c b/drivers/ginput/touch/FT5x06/gmouse_lld_FT5x06.c index ab331f8f..b354dba3 100644 --- a/drivers/ginput/touch/FT5x06/gmouse_lld_FT5x06.c +++ b/drivers/ginput/touch/FT5x06/gmouse_lld_FT5x06.c @@ -128,7 +128,7 @@ const GMouseVMT const GMOUSE_DRIVER_VMT[1] = {{ }, MouseInit, // init 0, // deinit - read_xyz, // get + MouseXYZ, // get 0, // calsave 0 // calload }}; From e69fff510001cab99a716de45a43554311162906 Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Fri, 10 Jul 2015 12:18:49 +0200 Subject: [PATCH 18/26] Revert "Fix in FT5x06 touch driver" This reverts commit a3d67e76e5f65a1fd52642db0fefd81fd6e7cfe6. --- drivers/ginput/touch/FT5x06/gmouse_lld_FT5x06.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ginput/touch/FT5x06/gmouse_lld_FT5x06.c b/drivers/ginput/touch/FT5x06/gmouse_lld_FT5x06.c index b354dba3..ab331f8f 100644 --- a/drivers/ginput/touch/FT5x06/gmouse_lld_FT5x06.c +++ b/drivers/ginput/touch/FT5x06/gmouse_lld_FT5x06.c @@ -128,7 +128,7 @@ const GMouseVMT const GMOUSE_DRIVER_VMT[1] = {{ }, MouseInit, // init 0, // deinit - MouseXYZ, // get + read_xyz, // get 0, // calsave 0 // calload }}; From 6f181c17e6dec2457a1d9612c7109f93c21e5bd6 Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Fri, 10 Jul 2015 12:19:17 +0200 Subject: [PATCH 19/26] Fix in FT5x06 touch driver --- drivers/ginput/touch/FT5x06/gmouse_lld_FT5x06.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ginput/touch/FT5x06/gmouse_lld_FT5x06.c b/drivers/ginput/touch/FT5x06/gmouse_lld_FT5x06.c index ab331f8f..da7c46ed 100644 --- a/drivers/ginput/touch/FT5x06/gmouse_lld_FT5x06.c +++ b/drivers/ginput/touch/FT5x06/gmouse_lld_FT5x06.c @@ -56,7 +56,7 @@ static bool_t MouseInit(GMouse* m, unsigned driverinstance) { return TRUE; } -static bool_t MouseXYZ(GMouse* m, GMouseReading* pdr) +static bool_t read_xyz(GMouse* m, GMouseReading* pdr) { // Assume not touched. pdr->buttons = 0; From 6af2d41ea39474900b74e9fad5d2fbad5a6c302f Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Fri, 10 Jul 2015 12:55:16 +0200 Subject: [PATCH 20/26] Renaming example dir to keep naming consistent --- .../STM32F746-Discovery/{Example RAW32 => example_raw32}/Makefile | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename boards/base/STM32F746-Discovery/{Example RAW32 => example_raw32}/Makefile (100%) diff --git a/boards/base/STM32F746-Discovery/Example RAW32/Makefile b/boards/base/STM32F746-Discovery/example_raw32/Makefile similarity index 100% rename from boards/base/STM32F746-Discovery/Example RAW32/Makefile rename to boards/base/STM32F746-Discovery/example_raw32/Makefile From 5a1f527fcfa9e6bd69517be78481dc7688cb6522 Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Fri, 10 Jul 2015 14:50:12 +0200 Subject: [PATCH 21/26] working on the LTDC driver (not done yet and also hacky code) --- boards/base/STM32F746-Discovery/board_STM32LTDC.h | 8 +++++--- drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c | 2 +- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/boards/base/STM32F746-Discovery/board_STM32LTDC.h b/boards/base/STM32F746-Discovery/board_STM32LTDC.h index 33f6e2cb..53940ad2 100644 --- a/boards/base/STM32F746-Discovery/board_STM32LTDC.h +++ b/boards/base/STM32F746-Discovery/board_STM32LTDC.h @@ -12,6 +12,8 @@ #include "stm32f746g_discovery_sdram.h" #include +#include "RGB565_480x272.h" + static const ltdcConfig driverCfg = { 480, 270, // Width, Height (pixels) 41, 10, // Horizontal, Vertical sync (pixels) @@ -21,7 +23,7 @@ static const ltdcConfig driverCfg = { 0x000000, // Clear color (RGB888) { // Background layer config - (LLDCOLOR_TYPE *)SDRAM_BANK_ADDR, // Frame buffer address + (LLDCOLOR_TYPE *)RGB565_480x272, // Frame buffer address 480, 270, // Width, Height (pixels) 480 * LTDC_PIXELBYTES, // Line pitch (bytes) LTDC_PIXELFORMAT, // Pixel format @@ -60,14 +62,14 @@ static inline void init_board(GDisplay *g) { /* PLLSAI activation.*/ RCC->PLLSAICFGR = (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24); - RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST; + RCC->DCKCFGR1 = (RCC->DCKCFGR1 & ~RCC_DCKCFGR1_PLLSAIDIVR) | STM32_PLLSAIR_POST; RCC->CR |= RCC_CR_PLLSAION; // Initialise the SDRAM SDRAM_Init(); // Clear the SDRAM - memset((void *)SDRAM_BANK_ADDR, 0, 0x400000); + //memset((void *)SDRAM_BANK_ADDR, 0, 0x400000); break; } diff --git a/drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c b/drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c index 118b6874..a6a185ee 100644 --- a/drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c +++ b/drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c @@ -153,7 +153,7 @@ static void LTDC_Init(void) RCC->APB2RSTR = 0; /* Enable the LTDC clock.*/ - RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | (1 << 16); /* /4 */ + RCC->DCKCFGR1 = (RCC->DCKCFGR1 & ~RCC_DCKCFGR1_PLLSAIDIVR) | (1 << 16); /* /4 */ // Enable the module RCC->APB2ENR |= RCC_APB2ENR_LTDCEN; From daab60de98bcb5b97d7ae75e0da5d2646cadbba0 Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Fri, 10 Jul 2015 16:42:06 +0200 Subject: [PATCH 22/26] Improving formatting of makefile verbose output --- tools/gmake_scripts/compiler_gcc.mk | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/tools/gmake_scripts/compiler_gcc.mk b/tools/gmake_scripts/compiler_gcc.mk index c6225d4d..ca029b30 100644 --- a/tools/gmake_scripts/compiler_gcc.mk +++ b/tools/gmake_scripts/compiler_gcc.mk @@ -196,24 +196,34 @@ builddirs: $(FAKEFILE): ifneq ($(OPT_VERBOSE_COMPILE),yes) - @echo . + @echo ifneq ($(filter %.cpp,$(SRC) $(SRC_NOTHUMB) $(SRC_THUMB)),) - @echo C++ Compiler Options.. $(XCXX) -c $(CPPFLAGS) $(CXXFLAGS) $(SRCFLAGS) $(@:.o=.cpp) -o $(OBJDIR)/$@ + @echo + @echo C++ Compiler Options.. + @echo $(XCXX) -c $(CPPFLAGS) $(CXXFLAGS) $(SRCFLAGS) $(@:.o=.cpp) -o $(OBJDIR)/$@ else ifneq ($(filter %.c++,$(SRC) $(SRC_NOTHUMB) $(SRC_THUMB)),) - @echo C++ Compiler Options.. $(XCXX) -c $(CPPFLAGS) $(CXXFLAGS) $(SRCFLAGS) $(@:.o=.c++) -o $(OBJDIR)/$@ + @echo + @echo C++ Compiler Options.. + @echo $(XCXX) -c $(CPPFLAGS) $(CXXFLAGS) $(SRCFLAGS) $(@:.o=.c++) -o $(OBJDIR)/$@ endif endif ifneq ($(filter %.c,$(SRC) $(SRC_NOTHUMB) $(SRC_THUMB)),) - @echo C Compiler Options.... $(XCC) -c $(CPPFLAGS) $(CFLAGS) $(SRCFLAGS) $(@:.o=.c) -o $(OBJDIR)/$@ + @echo + @echo C Compiler Options.... + @echo $(XCC) -c $(CPPFLAGS) $(CFLAGS) $(SRCFLAGS) $(@:.o=.c) -o $(OBJDIR)/$@ endif ifneq ($(filter %.s,$(SRC) $(SRC_NOTHUMB) $(SRC_THUMB)),) - @echo Assembler Options..... $(XCC) -c $(CPPFLAGS) $(CFLAGS) $(SRCFLAGS) $(@:.o=.s) -o $(OBJDIR)/$@ + @echo + @echo Assembler Options..... + @echo $(XCC) -c $(CPPFLAGS) $(CFLAGS) $(SRCFLAGS) $(@:.o=.s) -o $(OBJDIR)/$@ endif ifneq ($(OPT_MAKE_LIB),yes) - @echo Linker Options........ $(XLD) $(LDFLAGS) $(OBJDIR)/$@ -o $(EXEFILE) + @echo + @echo Linker Options........ + @echo $(XLD) $(LDFLAGS) $(OBJDIR)/$@ -o $(EXEFILE) endif - @echo . + @echo endif fakethumbfile.o $(OBJS_THUMB): SRCFLAGS += -mthumb -DTHUMB From 38b0cdd5e8d0783489fae0f23e2b748d787c7b4c Mon Sep 17 00:00:00 2001 From: inmarket Date: Sat, 11 Jul 2015 16:13:05 +1000 Subject: [PATCH 23/26] Working STM32F746G-Discovery board + example for raw32 Working STM32LTDC video driver --- boards/base/STM32F746-Discovery/board.mk | 25 + .../STM32F746-Discovery/board_STM32LTDC.h | 105 ++- .../example_raw32/Makefile | 71 +- .../example_raw32/openocd.cfg | 94 +++ .../example_raw32/stm32f7xx_hal_conf.h | 418 ++++++++++++ .../stm32f746g_raw32_interrupts.c | 185 ++++++ .../stm32f746g_raw32_startup.s | 606 ++++++++++++++++++ .../stm32f746g_raw32_system.c | 504 +++++++++++++++ .../stm32f746g_raw32_ugfx.c | 122 ++++ .../stm32f746nghx_flash.ld | 169 +++++ .../STM32LTDC/board_STM32LTDC_template.h | 8 +- tools/gmake_scripts/compiler_gcc.mk | 13 +- 12 files changed, 2251 insertions(+), 69 deletions(-) create mode 100644 boards/base/STM32F746-Discovery/example_raw32/openocd.cfg create mode 100644 boards/base/STM32F746-Discovery/example_raw32/stm32f7xx_hal_conf.h create mode 100644 boards/base/STM32F746-Discovery/stm32f746g_raw32_interrupts.c create mode 100644 boards/base/STM32F746-Discovery/stm32f746g_raw32_startup.s create mode 100644 boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c create mode 100644 boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c create mode 100644 boards/base/STM32F746-Discovery/stm32f746nghx_flash.ld diff --git a/boards/base/STM32F746-Discovery/board.mk b/boards/base/STM32F746-Discovery/board.mk index ce70ef15..dd1f8441 100644 --- a/boards/base/STM32F746-Discovery/board.mk +++ b/boards/base/STM32F746-Discovery/board.mk @@ -1,5 +1,30 @@ GFXINC += $(GFXLIB)/boards/base/STM32F746-Discovery GFXSRC += $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c \ $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c +GFXDEFS += STM32F746xx + +ifeq ($(OPT_OS),raw32) + GFXSRC += $(HAL)/Src/stm32f7xx_hal.c \ + $(HAL)/Src/stm32f7xx_hal_cortex.c \ + $(HAL)/Src/stm32f7xx_hal_flash.c \ + $(HAL)/Src/stm32f7xx_hal_flash_ex.c \ + $(HAL)/Src/stm32f7xx_hal_rcc.c \ + $(HAL)/Src/stm32f7xx_hal_rcc_ex.h \ + $(HAL)/Src/stm32f7xx_hal_gpio.c \ + $(HAL)/Src/stm32f7xx_hal_pwr.c \ + $(HAL)/Src/stm32f7xx_hal_pwr_ex.c \ + $(HAL)/Src/stm32f7xx_hal_sdram.c \ + $(HAL)/Src/stm32f7xx_hal_dma.c + GFXSRC += $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_startup.s \ + $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c \ + $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c \ + $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_interrupts.c + GFXDEFS += GFX_OS_EXTRA_INIT_FUNCTION=Raw32OSInit + SRCFLAGS+= -std=c99 + GFXINC += $(CMSIS)/Device/ST/STM32F7xx/Include \ + $(CMSIS)/Include \ + $(HAL)/Inc + LDSCRIPT = $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746nghx_flash.ld +endif include $(GFXLIB)/drivers/gdisp/STM32LTDC/driver.mk \ No newline at end of file diff --git a/boards/base/STM32F746-Discovery/board_STM32LTDC.h b/boards/base/STM32F746-Discovery/board_STM32LTDC.h index 53940ad2..151a19ca 100644 --- a/boards/base/STM32F746-Discovery/board_STM32LTDC.h +++ b/boards/base/STM32F746-Discovery/board_STM32LTDC.h @@ -12,10 +12,8 @@ #include "stm32f746g_discovery_sdram.h" #include -#include "RGB565_480x272.h" - static const ltdcConfig driverCfg = { - 480, 270, // Width, Height (pixels) + 480, 272, // Width, Height (pixels) 41, 10, // Horizontal, Vertical sync (pixels) 13, 2, // Horizontal, Vertical back porch (pixels) 32, 2, // Horizontal, Vertical front porch (pixels) @@ -23,12 +21,12 @@ static const ltdcConfig driverCfg = { 0x000000, // Clear color (RGB888) { // Background layer config - (LLDCOLOR_TYPE *)RGB565_480x272, // Frame buffer address - 480, 270, // Width, Height (pixels) + (LLDCOLOR_TYPE *)SDRAM_DEVICE_ADDR, // Frame buffer address + 480, 272, // Width, Height (pixels) 480 * LTDC_PIXELBYTES, // Line pitch (bytes) LTDC_PIXELFORMAT, // Pixel format 0, 0, // Start pixel position (x, y) - 480, 270, // Size of virtual layer (cx, cy) + 480, 272, // Size of virtual layer (cx, cy) LTDC_COLOR_FUCHSIA, // Default color (ARGB8888) 0x980088, // Color key (RGB888) LTDC_BLEND_FIX1_FIX2, // Blending factors @@ -41,13 +39,95 @@ static const ltdcConfig driverCfg = { LTDC_UNUSED_LAYER_CONFIG // Foreground layer config }; +/** + * @brief LCD special pins + */ +/* Display enable pin */ +#define LCD_DISP_PIN GPIO_PIN_12 +#define LCD_DISP_GPIO_PORT GPIOI + +/* Backlight control pin */ +#define LCD_BL_CTRL_PIN GPIO_PIN_3 +#define LCD_BL_CTRL_GPIO_PORT GPIOK + +/* Display timing */ +#define RK043FN48H_FREQUENCY_DIVIDER 5 + +static void SetBoardPinDirectionsForLCD(void) +{ + GPIO_InitTypeDef gpio_init_structure; + + // Enable GPIOs clock */ + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOI_CLK_ENABLE(); // Display pin + __HAL_RCC_GPIOJ_CLK_ENABLE(); + __HAL_RCC_GPIOK_CLK_ENABLE(); // BL pin + + //*** LTDC Pins configuration + // GPIOE configuration + gpio_init_structure.Pin = GPIO_PIN_4; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + gpio_init_structure.Pull = GPIO_NOPULL; + gpio_init_structure.Speed = GPIO_SPEED_FAST; + gpio_init_structure.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOE, &gpio_init_structure); + + // GPIOG configuration + gpio_init_structure.Pin = GPIO_PIN_12; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + gpio_init_structure.Alternate = GPIO_AF9_LTDC; + HAL_GPIO_Init(GPIOG, &gpio_init_structure); + + // GPIOI LTDC alternate configuration + gpio_init_structure.Pin = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | \ + GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + gpio_init_structure.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOI, &gpio_init_structure); + + // GPIOJ configuration + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | \ + GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | \ + GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | \ + GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + gpio_init_structure.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOJ, &gpio_init_structure); + + // GPIOK configuration + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | \ + GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7; + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + gpio_init_structure.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOK, &gpio_init_structure); + + // LCD_DISP GPIO configuration + gpio_init_structure.Pin = LCD_DISP_PIN; /* LCD_DISP pin has to be manually controlled */ + gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + HAL_GPIO_Init(LCD_DISP_GPIO_PORT, &gpio_init_structure); + + // LCD_BL_CTRL GPIO configuration + gpio_init_structure.Pin = LCD_BL_CTRL_PIN; /* LCD_BL_CTRL pin has to be manually controlled */ + gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + HAL_GPIO_Init(LCD_BL_CTRL_GPIO_PORT, &gpio_init_structure); +} + static inline void init_board(GDisplay *g) { // As we are not using multiple displays we set g->board to NULL as we don't use it. g->board = 0; switch(g->controllerdisplay) { - case 0: + case 0: + + // Set pin directions + SetBoardPinDirectionsForLCD(); + + // Enable the display and turn on the backlight + HAL_GPIO_WritePin(LCD_DISP_GPIO_PORT, LCD_DISP_PIN, GPIO_PIN_SET); + HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_PORT, LCD_BL_CTRL_PIN, GPIO_PIN_SET); + #define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */ #define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */ #define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */ @@ -55,18 +135,21 @@ static inline void init_board(GDisplay *g) { #define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */ #define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */ + // RK043FN48H LCD clock configuration + // PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 Mhz + // PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 192 Mhz + // PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 192/5 = 38.4 Mhz + // LTDC clock frequency = PLLLCDCLK / LTDC_PLLSAI_DIVR_4 = 38.4/4 = 9.6Mhz #define STM32_PLLSAIN_VALUE 192 #define STM32_PLLSAIQ_VALUE 7 - #define STM32_PLLSAIR_VALUE 4 + #define STM32_PLLSAIR_VALUE RK043FN48H_FREQUENCY_DIVIDER #define STM32_PLLSAIR_POST STM32_SAIR_DIV4 - - /* PLLSAI activation.*/ RCC->PLLSAICFGR = (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24); RCC->DCKCFGR1 = (RCC->DCKCFGR1 & ~RCC_DCKCFGR1_PLLSAIDIVR) | STM32_PLLSAIR_POST; RCC->CR |= RCC_CR_PLLSAION; // Initialise the SDRAM - SDRAM_Init(); + BSP_SDRAM_Init(); // Clear the SDRAM //memset((void *)SDRAM_BANK_ADDR, 0, 0x400000); diff --git a/boards/base/STM32F746-Discovery/example_raw32/Makefile b/boards/base/STM32F746-Discovery/example_raw32/Makefile index 48283ebb..298d74bf 100644 --- a/boards/base/STM32F746-Discovery/example_raw32/Makefile +++ b/boards/base/STM32F746-Discovery/example_raw32/Makefile @@ -8,37 +8,38 @@ # See $(GFXLIB)/tools/gmake_scripts/readme.txt for the list of variables OPT_OS = raw32 OPT_THUMB = yes - OPT_LINK_OPTIMIZE = yes + OPT_LINK_OPTIMIZE = no OPT_CPU = stm32m7 # uGFX settings # See $(GFXLIB)/tools/gmake_scripts/library_ugfx.mk for the list of variables - GFXLIB = ../uGFX + GFXLIB = ../ugfx GFXBOARD = STM32F746-Discovery - GFXDEMO = modules/gwin/widgets - #GFXDRIVERS = + GFXDEMO = modules/gdisp/basics + #GFXDRIVERS = # ChibiOS settings +# Note: not supported by ChibiOS yet! ifeq ($(OPT_OS),chibios) # See $(GFXLIB)/tools/gmake_scripts/os_chibios.mk for the list of variables CHIBIOS = ../ChibiOS - CHIBIOS_BOARD = ST_STM32F429I_DISCOVERY - CHIBIOS_PLATFORM = STM32F4xx - CHIBIOS_PORT = GCC/ARMCMx/STM32F4xx - CHIBIOS_LDSCRIPT = STM32F407xG.ld + CHIBIOS_BOARD = ST_STM32F746_DISCOVERY + CHIBIOS_PLATFORM = STM32F7xx + CHIBIOS_PORT = GCC/ARMCMx/STM32F7xx + CHIBIOS_LDSCRIPT = STM32F746.ld - #CHIBIOS = ../ChibiOS3 - #CHIBIOS_VERSION = 3 - #CHIBIOS_BOARD = ST_STM32F429I_DISCOVERY - #CHIBIOS_CPUCLASS = ARMCMx - #CHIBIOS_PLATFORM = STM32/STM32F4xx - #CHIBIOS_PORT = stm32f4xx - #CHIBIOS_LDSCRIPT = STM32F407xG.ld + #CHIBIOS = ../ChibiOS3 + #CHIBIOS_VERSION = 3 + #CHIBIOS_BOARD = ST_STM32F746_DISCOVERY + #CHIBIOS_CPUCLASS = ARMCMx + #CHIBIOS_PLATFORM = STM32/STM32F7xx + #CHIBIOS_PORT = stm32f7xx + #CHIBIOS_LDSCRIPT = STM32F746.ld endif -CMSIS = CMSIS -HAL = STM32F7xx_HAL_Driver -CONTROLLER = STM32F746xx +# Raw32 settings +CMSIS = ../STM32/CMSIS +HAL = ../STM32/STM32F7xx_HAL_Driver ############################################################################################## # Set these for your project @@ -46,39 +47,20 @@ CONTROLLER = STM32F746xx ARCH = arm-none-eabi- SRCFLAGS = -ggdb -O0 -CFLAGS = +CFLAGS = CXXFLAGS = -fno-rtti ASFLAGS = LDFLAGS = -#SRC = $(HAL)/Src/stm32f7xx_hal.c \ - $(HAL)/Src/stm32f7xx_hal_cortex.c \ - $(HAL)/Src/stm32f7xx_hal_flash.c \ - $(HAL)/Src/stm32f7xx_hal_flash_ex.c \ - $(HAL)/Src/stm32f7xx_hal_rcc.c \ - $(HAL)/Src/stm32f7xx_hal_rcc_ex.h \ - $(HAL)/Src/stm32f7xx_hal_gpio.c \ - $(HAL)/Src/stm32f7xx_hal_pwr.c \ - $(HAL)/Src/stm32f7xx_hal_pwr_ex.c \ - $(HAL)/Src/stm32f7xx_hal_ltdc.c \ - STM32746G-Discovery/stm32746g_discovery.c \ - stm32f7xx_hal_msp.c \ - stm32f7xx_it.c \ - system_stm32f7xx.c \ - ugfx_raw32_implementations.c \ - main.c \ - startup_stm32f746xx.s +SRC = OBJS = -DEFS = +DEFS = GOS_RAW_HEAP_SIZE=40960 LIBS = -INCPATH = $(CMSIS)/Device/ST/STM32F7xx/Include \ - $(CMSIS)/Include \ - $(HAL)/Inc \ - STM32746G-Discovery +INCPATH = LIBPATH = -LDSCRIPT = stm32f746nghx_flash.ld +LDSCRIPT = ############################################################################################## # These should be at the end @@ -88,8 +70,3 @@ include $(GFXLIB)/tools/gmake_scripts/library_ugfx.mk include $(GFXLIB)/tools/gmake_scripts/os_$(OPT_OS).mk include $(GFXLIB)/tools/gmake_scripts/compiler_gcc.mk # *** EOF *** - -#ASFLAGS = -ggdb -Wall -#CFLAGS = -ggdb -g3 -Wall -std=c99 -O0 -#CPPFLAGS = -ggdb -Wall -#LDFLAGS = -fdata-sections diff --git a/boards/base/STM32F746-Discovery/example_raw32/openocd.cfg b/boards/base/STM32F746-Discovery/example_raw32/openocd.cfg new file mode 100644 index 00000000..e2d732a4 --- /dev/null +++ b/boards/base/STM32F746-Discovery/example_raw32/openocd.cfg @@ -0,0 +1,94 @@ +# This is a script file for OpenOCD ?.?.? +# +# It is set up for the STM32F749-Discovery board using the ST-Link JTAG adaptor. +# +# Assuming the current directory is your project directory containing this openocd.cfg file... +# +# To program your device: +# +# openocd -f openocd.cfg -c "Burn yourfile.bin" -c shutdown +# +# To debug your device: +# +# openocd +# (This will run openocd in gdb server debug mode. Leave it running in the background) +# +# gdb yourfile.elf +# (To start gdb. Then run the following commands in gdb...) +# +# target remote 127.0.0.1:3333 +# monitor Debug +# stepi +# (This last stepi resynchronizes gdb). +# +# If you want to reprogram from within gdb: +# +# monitor Burn yourfile.bin +# + +echo "" +echo "##### Loading debugger..." +source [find interface/stlink-v2-1.cfg] + +echo "" +echo "##### Loading CPU..." +source [find target/stm32f7x.cfg] + +echo "" +echo "##### Configuring..." +#reset_config srst_only srst_nogate +#cortex_m maskisr (auto|on|off) +#cortex_m vector_catch [all|none|list] +#cortex_m reset_config (srst|sysresetreq|vectreset) +#gdb_breakpoint_override hard + +proc Debug { } { + echo "" + echo "##### Debug Session Connected..." + reset init + echo "Ready..." +} + +proc Burn {file} { + echo "" + echo "##### Burning $file to device..." + halt + # Due to an issue with the combination of the ST-Link adapters and OpenOCD + # applying the stm32f2x unlock 0 command actaully applies read protection - VERY BAD! + # If this happens to you - use the ST-Link utility to set the option byte back to normal. + # If you are using a different debugger eg a FT2232 based adapter you can uncomment the line below. + #stm32f2x unlock 0 + #flash protect 0 0 last off + reset halt + flash write_image erase $file 0 elf + verify_image $file 0x0 elf + #flash protect 0 0 last on + reset + echo "Burning Complete!" +} + +echo "" +echo "##### Leaving Configuration Mode..." +init +reset init +flash probe 0 +flash banks +#flash info 0 + +echo "" +echo "##### Waiting for debug connections..." + +##### OLD ###### +#source [find interface/stlink-v2-1.cfg] +#source [find target/stm32f7x.cfg] +# +#proc flash_chip {} { +# halt +# reset halt +# flash write_image erase main.elf 0 elf +# verify_image main.elf 0 elf +# reset +# shutdown +#} +# +#init diff --git a/boards/base/STM32F746-Discovery/example_raw32/stm32f7xx_hal_conf.h b/boards/base/STM32F746-Discovery/example_raw32/stm32f7xx_hal_conf.h new file mode 100644 index 00000000..765e1377 --- /dev/null +++ b/boards/base/STM32F746-Discovery/example_raw32/stm32f7xx_hal_conf.h @@ -0,0 +1,418 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_conf.h + * @author MCD Application Team + * @version V1.0.0 + * @date 25-June-2015 + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_CONF_H +#define __STM32F7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +#define HAL_DMA_MODULE_ENABLED +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +#define HAL_FLASH_MODULE_ENABLED +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +#define HAL_SDRAM_MODULE_ENABLED +/* #define HAL_HASH_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +/* #define HAL_I2C_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +#define HAL_PWR_MODULE_ENABLED +/* #define HAL_QSPI_MODULE_ENABLED */ +#define HAL_RCC_MODULE_ENABLED +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ +/* #define HAL_UART_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_CORTEX_MODULE_ENABLED +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ + + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)40000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */ +#define USE_RTOS 0 +#define ART_ACCLERATOR_ENABLE 1 /* To enable instruction cache and prefetch */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1 */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2 +#define MAC_ADDR1 0 +#define MAC_ADDR2 0 +#define MAC_ADDR3 0 +#define MAC_ADDR4 0 +#define MAC_ADDR5 0 + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848 PHY Address*/ +#define DP83848_PHY_ADDRESS 0x01 +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FF) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF) + +#define PHY_READ_TO ((uint32_t)0x0000FFFF) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFF) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ + +#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */ +#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */ +#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */ + +#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ + +#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ +#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ + +#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ +#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f7xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/boards/base/STM32F746-Discovery/stm32f746g_raw32_interrupts.c b/boards/base/STM32F746-Discovery/stm32f746g_raw32_interrupts.c new file mode 100644 index 00000000..d5dcec0b --- /dev/null +++ b/boards/base/STM32F746-Discovery/stm32f746g_raw32_interrupts.c @@ -0,0 +1,185 @@ +/** + ****************************************************************************** + * @file LTDC/LTDC_Display_1Layer/Src/stm32f7xx_it.c + * @author MCD Application Team + * @version V1.0.0 + * @date 25-June-2015 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Examples + * @{ + */ + +/** @addtogroup LTDC_Display_1Layer + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M4 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + HAL_IncTick(); +} + +/******************************************************************************/ +/* STM32F7xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f7xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/boards/base/STM32F746-Discovery/stm32f746g_raw32_startup.s b/boards/base/STM32F746-Discovery/stm32f746g_raw32_startup.s new file mode 100644 index 00000000..55b89c72 --- /dev/null +++ b/boards/base/STM32F746-Discovery/stm32f746g_raw32_startup.s @@ -0,0 +1,606 @@ +/** + ****************************************************************************** + * @file startup_stm32f746xx.s + * @author MCD Application Team + * Version V1.0.0 + * Date 25-June-2015 + * @brief STM32F746xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M7 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system initialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr + +.global WeakCInit +WeakCInit: + mov pc, lr + + .weak _init + .thumb_set _init,WeakCInit + +.global WeakCExit +WeakCExit: + b WeakCExit + + .weak exit + .thumb_set exit,WeakCExit + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M7. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word SAI2_IRQHandler /* SAI2 */ + .word QUADSPI_IRQHandler /* QUADSPI */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word I2C4_EV_IRQHandler /* I2C4 Event */ + .word I2C4_ER_IRQHandler /* I2C4 Error */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c b/boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c new file mode 100644 index 00000000..9ffe25ee --- /dev/null +++ b/boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c @@ -0,0 +1,504 @@ +/** + ****************************************************************************** + * @file system_stm32f7xx.c + * @author MCD Application Team + * @version V1.0.0 + * @date 25-June-2015 + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f7xx_system + * @{ + */ + +/** @addtogroup STM32F7xx_System_Private_Includes + * @{ + */ + +#include "stm32f7xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted + on EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ +/* #define DATA_IN_ExtSDRAM */ + +#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM) + #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Variables + * @{ + */ + + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000; + __IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes + * @{ + */ +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f7xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration ------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + + /* Configure and enable SDRAM bank1 */ + FMC_Bank5_6->SDCR[0] = 0x000019E0; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +#endif /* DATA_IN_ExtSDRAM */ + +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; + +#endif /* DATA_IN_ExtSRAM */ +} +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c b/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c new file mode 100644 index 00000000..3d493e5c --- /dev/null +++ b/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c @@ -0,0 +1,122 @@ +#include "gfx.h" +#include "stm32f7xx_hal.h" + +systemticks_t gfxSystemTicks(void) +{ + return HAL_GetTick(); +} + +systemticks_t gfxMillisecondsToTicks(delaytime_t ms) +{ + return ms; +} + +static void SystemClock_Config(void); +static void CPU_CACHE_Enable(void); +static void LCD_Config(void); + +void Raw32OSInit(void) { + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + + /* Enable the CPU Cache */ + CPU_CACHE_Enable(); + + /* STM32F7xx HAL library initialization: + - Configure the Flash ART accelerator on ITCM interface + - Configure the Systick to generate an interrupt each 1 msec + - Set NVIC Group Priority to 4 + - Global MSP (MCU Support Package) initialization + */ + HAL_Init(); + + /* Configure the system clock to 216 MHz */ + SystemClock_Config(); + + // LED - for testing + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Pin = GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FAST; + __GPIOI_CLK_ENABLE(); + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + +} + +/** + * @brief System Clock Configuration + * The system Clock is configured as follow : + * System Clock source = PLL (HSE) + * SYSCLK(Hz) = 200000000 / 216000000 + * HCLK(Hz) = 200000000 / 216000000 + * AHB Prescaler = 1 + * APB1 Prescaler = 4 + * APB2 Prescaler = 2 + * HSE Frequency(Hz) = 25000000 + * PLL_M = 25 + * PLL_N = 400 / 432 + * PLL_P = 2 + * PLL_Q = 8 / 9 + * VDD(V) = 3.3 + * Main regulator output voltage = Scale1 mode + * Flash Latency(WS) = 6 / 7 + * @param None + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + HAL_StatusTypeDef ret = HAL_OK; + + /* Enable HSE Oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 25; + RCC_OscInitStruct.PLL.PLLN = 400; // 432 + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 8; // 9 + + ret = HAL_RCC_OscConfig(&RCC_OscInitStruct); + if(ret != HAL_OK) + { + while(1) { ; } + } + + /* Activate the OverDrive to reach the 200/216 MHz Frequency */ + ret = HAL_PWREx_EnableOverDrive(); + if(ret != HAL_OK) + { + while(1) { ; } + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6); // FLASH_LATENCY_7 + if(ret != HAL_OK) + { + while(1) { ; } + } +} + +/** + * @brief CPU L1-Cache enable. + * @param None + * @retval None + */ +static void CPU_CACHE_Enable(void) +{ + /* Enable I-Cache */ + SCB_EnableICache(); + + /* Enable D-Cache */ + SCB_EnableDCache(); +} + diff --git a/boards/base/STM32F746-Discovery/stm32f746nghx_flash.ld b/boards/base/STM32F746-Discovery/stm32f746nghx_flash.ld new file mode 100644 index 00000000..c481002d --- /dev/null +++ b/boards/base/STM32F746-Discovery/stm32f746nghx_flash.ld @@ -0,0 +1,169 @@ +/* +***************************************************************************** +** + +** File : LinkerScript.ld +** +** Abstract : Linker script for STM32F746NGHx Device with +** 1024KByte FLASH, 320KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +** (c)Copyright Ac6. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Ac6 permit registered System Workbench for MCU users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the System Workbench for MCU toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x2004FFFF; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200;; /* required amount of heap */ +_Min_Stack_Size = 0x400;; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 320K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/drivers/gdisp/STM32LTDC/board_STM32LTDC_template.h b/drivers/gdisp/STM32LTDC/board_STM32LTDC_template.h index 7f785e18..4ea3e03d 100644 --- a/drivers/gdisp/STM32LTDC/board_STM32LTDC_template.h +++ b/drivers/gdisp/STM32LTDC/board_STM32LTDC_template.h @@ -9,7 +9,7 @@ #define _GDISP_LLD_BOARD_H static const ltdcConfig driverCfg = { - 480, 270, // Width, Height (pixels) + 480, 272, // Width, Height (pixels) 41, 10, // Horizontal, Vertical sync (pixels) 13, 2, // Horizontal, Vertical back porch (pixels) 32, 2, // Horizontal, Vertical front porch (pixels) @@ -17,12 +17,12 @@ static const ltdcConfig driverCfg = { 0x000000, // Clear color (RGB888) { // Background layer config - (LLDCOLOR_TYPE *)SDRAM_BANK_ADDR, // Frame buffer address - 480, 270, // Width, Height (pixels) + (LLDCOLOR_TYPE *)SDRAM_DEVICE_ADDR, // Frame buffer address + 480, 272, // Width, Height (pixels) 480 * LTDC_PIXELBYTES, // Line pitch (bytes) LTDC_PIXELFORMAT, // Pixel format 0, 0, // Start pixel position (x, y) - 480, 270, // Size of virtual layer (cx, cy) + 480, 272, // Size of virtual layer (cx, cy) LTDC_COLOR_FUCHSIA, // Default color (ARGB8888) 0x980088, // Color key (RGB888) LTDC_BLEND_FIX1_FIX2, // Blending factors diff --git a/tools/gmake_scripts/compiler_gcc.mk b/tools/gmake_scripts/compiler_gcc.mk index ca029b30..23912992 100644 --- a/tools/gmake_scripts/compiler_gcc.mk +++ b/tools/gmake_scripts/compiler_gcc.mk @@ -196,34 +196,33 @@ builddirs: $(FAKEFILE): ifneq ($(OPT_VERBOSE_COMPILE),yes) - @echo ifneq ($(filter %.cpp,$(SRC) $(SRC_NOTHUMB) $(SRC_THUMB)),) - @echo + @echo . @echo C++ Compiler Options.. @echo $(XCXX) -c $(CPPFLAGS) $(CXXFLAGS) $(SRCFLAGS) $(@:.o=.cpp) -o $(OBJDIR)/$@ else ifneq ($(filter %.c++,$(SRC) $(SRC_NOTHUMB) $(SRC_THUMB)),) - @echo + @echo . @echo C++ Compiler Options.. @echo $(XCXX) -c $(CPPFLAGS) $(CXXFLAGS) $(SRCFLAGS) $(@:.o=.c++) -o $(OBJDIR)/$@ endif endif ifneq ($(filter %.c,$(SRC) $(SRC_NOTHUMB) $(SRC_THUMB)),) - @echo + @echo . @echo C Compiler Options.... @echo $(XCC) -c $(CPPFLAGS) $(CFLAGS) $(SRCFLAGS) $(@:.o=.c) -o $(OBJDIR)/$@ endif ifneq ($(filter %.s,$(SRC) $(SRC_NOTHUMB) $(SRC_THUMB)),) - @echo + @echo . @echo Assembler Options..... @echo $(XCC) -c $(CPPFLAGS) $(CFLAGS) $(SRCFLAGS) $(@:.o=.s) -o $(OBJDIR)/$@ endif ifneq ($(OPT_MAKE_LIB),yes) - @echo + @echo . @echo Linker Options........ @echo $(XLD) $(LDFLAGS) $(OBJDIR)/$@ -o $(EXEFILE) endif - @echo + @echo . endif fakethumbfile.o $(OBJS_THUMB): SRCFLAGS += -mthumb -DTHUMB From 64752ab52c61f053c0690cf36c712f4662bccfb1 Mon Sep 17 00:00:00 2001 From: inmarket Date: Sat, 11 Jul 2015 16:22:47 +1000 Subject: [PATCH 24/26] Small bug fix + doco --- docs/releases.txt | 3 +++ src/gos/gos_raw32.c | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/docs/releases.txt b/docs/releases.txt index 004a4748..03045d13 100644 --- a/docs/releases.txt +++ b/docs/releases.txt @@ -6,6 +6,9 @@ FIX: Add missing stm32m3 cpu makefile option. Update doc to match. FEATURE: Added ability to compile ugfx as a single file. Simply compile src/gfx_mk.c FEATURE: Added GFXSINGLEMAKE=yes|no to the ugfx makefile to compile ugfx as a single file. +FEATURE: New board STM32F746G-Discovery +FEATURE: New gdisp driver STM32LTDC +FEATURE: Better support for Raw32 platforms *** Release 2.3 *** FEATURE: Added more events to the slider widget diff --git a/src/gos/gos_raw32.c b/src/gos/gos_raw32.c index caacab20..c454a68b 100644 --- a/src/gos/gos_raw32.c +++ b/src/gos/gos_raw32.c @@ -685,7 +685,7 @@ gfxThreadHandle gfxThreadCreate(void *stackarea, size_t stacksz, threadpriority_ nf = (char *)(t) + sizeof(thread) + stackbase; memcpy(t+1, (char *)&t - stackbase, stackbase+sizeof(char *)); } else { // Stack grows down - nf = (char *)(t) + stacksz - (stackbase + sizeof(char *)); + nf = (char *)(t) + t->size - (stackbase + sizeof(char *)); memcpy(nf, &t, stackbase+sizeof(char *)); } #elif STACK_DIR_UP From 83bd8c21a35a14eef0c059dd8b730aa13e8eb99d Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Sun, 12 Jul 2015 01:43:23 +0200 Subject: [PATCH 25/26] Adding DMA2D support to STM32LTDC driver --- drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c | 96 ++++++++++++++++++- drivers/gdisp/STM32LTDC/gdisp_lld_config.h | 14 +++ drivers/gdisp/STM32LTDC/stm32_dma2d.h | 18 ++++ 3 files changed, 126 insertions(+), 2 deletions(-) create mode 100644 drivers/gdisp/STM32LTDC/stm32_dma2d.h diff --git a/drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c b/drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c index a6a185ee..ebde3345 100644 --- a/drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c +++ b/drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c @@ -18,12 +18,20 @@ #undef GDISP_SCREEN_WIDTH #endif +#ifndef LTDC_USE_DMA2D + #define LTDC_USE_DMA2D FALSE +#endif + #define GDISP_DRIVER_VMT GDISPVMT_STM32LTDC #include "drivers/gdisp/STM32LTDC/gdisp_lld_config.h" #include "src/gdisp/gdisp_driver.h" #include "stm32_ltdc.h" +#if LTDC_USE_DMA2D + #include "stm32_dma2d.h" +#endif + typedef struct ltdcLayerConfig { // frame LLDCOLOR_TYPE *frame; // Frame buffer address @@ -223,8 +231,9 @@ LLDSPEC bool_t gdisp_lld_init(GDisplay* g) LTDC_Init(); // Initialise DMA2D - //dma2dStart(&DMA2DD1, &dma2d_cfg); - //dma2d_test(); + #if LTDC_USE_DMA2D + dma2d_init(); + #endif // Finish Init the board post_init_board(g); @@ -362,4 +371,87 @@ LLDSPEC color_t gdisp_lld_get_pixel_color(GDisplay* g) } #endif +#if LTDC_USE_DMA2D + static void dma2d_init(void) + { + // Enable DMA2D clock (DMA2DEN = 1) + RCC->AHB1ENR |= RCC_AHB1ENR_DMA2DEN; + + // Output color format + #if GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB565 + DMA2D->OPFCCR = OPFCCR_RGB565; + #elif GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB888 + DMA2D->OPFCCR = OPFCCR_OPFCCR_RGB888; + #endif + + // Foreground color format + #if GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB565 + DMA2D->FGPFCCR = FGPFCCR_CM_RGB565; + #elif GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB888 + DMA2D->FGPFCCR = FGPFCCR_CM_RGB888; + #endif + } + + // Uses p.x,p.y p.cx,p.cy p.color + LLDSPEC void gdisp_lld_fill_area(GDisplay* g) + { + LLDCOLOR_TYPE c; + + // Wait until DMA2D is ready + while (1) { + if (!(DMA2D->CR & DMA2D_CR_START)) { + break; + } + } + + c = gdispColor2Native(g->p.color); + + // Output color register + DMA2D->OCOLR = (uint32_t)c; + + // Output memory address register + DMA2D->OMAR = g->p.y * g->g.Width * LTDC_PIXELBYTES + g->p.x * LTDC_PIXELBYTES + (uint32_t)driverCfg.bglayer.frame; + + // Output offset register (in pixels) + DMA2D->OOR = g->g.Width - g->p.cx; + + // PL (pixel per lines to be transferred); NL (number of lines) + DMA2D->NLR = (g->p.cx << 16) | (g->p.cy); + + // Set MODE to R2M and Start the process + DMA2D->CR = DMA2D_CR_MODE_R2M | DMA2D_CR_START; + } + + // Uses p.x,p.y p.cx,p.cy p.x1,p.y1 (=srcx,srcy) p.x2 (=srccx), p.ptr (=buffer) + LLDSPEC void gdisp_lld_blit_area(GDisplay* g) + { + // Wait until DMA2D is ready + while (1) { + if (!(DMA2D->CR & DMA2D_CR_START)) { + break; + } + } + + // Foreground memory address register + DMA2D->FGMAR = g->p.y1 * g->p.x2 * LTDC_PIXELBYTES + g->p.x1 * LTDC_PIXELBYTES + (uint32_t)g->p.ptr; + + // Foreground offset register (expressed in pixels) + DMA2D->FGOR = g->p.x2 - g->p.cx; + + // Output memory address register + DMA2D->OMAR = g->p.y * g->g.Width * LTDC_PIXELBYTES + g->p.x * LTDC_PIXELBYTES + (uint32_t)driverCfg.bglayer.frame; + + // Output offset register (expressed in pixels) + DMA2D->OOR = g->g.Width - g->p.cx; + + // PL (pixel per lines to be transferred); NL (number of lines) + DMA2D->NLR = (g->p.cx << 16) | (g->p.cy); + + // Set MODE to M2M and Start the process + DMA2D->CR = DMA2D_CR_MODE_M2M | DMA2D_CR_START; + } + +#endif /* LTDC_USE_DMA2D */ + + #endif /* GFX_USE_GDISP */ diff --git a/drivers/gdisp/STM32LTDC/gdisp_lld_config.h b/drivers/gdisp/STM32LTDC/gdisp_lld_config.h index 29e016ce..c661f67c 100644 --- a/drivers/gdisp/STM32LTDC/gdisp_lld_config.h +++ b/drivers/gdisp/STM32LTDC/gdisp_lld_config.h @@ -14,11 +14,25 @@ /* Driver hardware support. */ /*===========================================================================*/ +#define LTDC_USE_DMA2D TRUE #define GDISP_HARDWARE_DRAWPIXEL TRUE #define GDISP_HARDWARE_PIXELREAD TRUE #define GDISP_HARDWARE_CONTROL TRUE #define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_RGB565 + +/*===========================================================================*/ +/* Don't change stuff below this line. Please. */ +/*===========================================================================*/ + +#if LTDC_USE_DMA2D + #define GDISP_HARDWARE_FILLS TRUE + #define GDISP_HARDWARE_BITFILLS TRUE +#else + #define GDISP_HARDWARE_FILLS FALSE + #define GDISP_HARDWARE_BITFILLS FALSE +#endif /* GDISP_USE_DMA2D */ + #endif /* GFX_USE_GDISP */ #endif /* _GDISP_LLD_CONFIG_H */ diff --git a/drivers/gdisp/STM32LTDC/stm32_dma2d.h b/drivers/gdisp/STM32LTDC/stm32_dma2d.h new file mode 100644 index 00000000..d3374d05 --- /dev/null +++ b/drivers/gdisp/STM32LTDC/stm32_dma2d.h @@ -0,0 +1,18 @@ +#ifndef _STM32_DMA2D_H +#define _STM32_DMA2D_H + +#define OPFCCR_ARGB8888 0x00 +#define OPFCCR_RGB888 0x01 +#define OPFCCR_RGB565 0x02 +#define OPFCCR_ARGB1555 0x03 +#define OPFCCR_ARGB4444 0x04 + +#define FGPFCCR_CM_RGB888 0x01 +#define FGPFCCR_CM_RGB565 0x02 + +#define DMA2D_CR_MODE_R2M ((uint32_t)0x00030000) /* Register-to-memory mode */ +#define DMA2D_CR_MODE_M2M ((uint32_t)0x00000000) /* Register-to-memory mode */ + +static void dma2d_init(void); + +#endif /* _STM32_DMA2D_H */ From 3e6c7accdc2f89908389df126f3fb7294eb9be45 Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Sun, 12 Jul 2015 02:54:17 +0200 Subject: [PATCH 26/26] Adding DMA2D to STM32F429i-Discovery --- .../gdisp_lld_STM32F429iDiscovery.c | 95 +++++++++++++++++++ .../STM32F429iDiscovery/gdisp_lld_config.h | 14 +++ .../gdisp/STM32F429iDiscovery/stm32_dma2d.h | 18 ++++ 3 files changed, 127 insertions(+) create mode 100644 drivers/gdisp/STM32F429iDiscovery/stm32_dma2d.h diff --git a/drivers/gdisp/STM32F429iDiscovery/gdisp_lld_STM32F429iDiscovery.c b/drivers/gdisp/STM32F429iDiscovery/gdisp_lld_STM32F429iDiscovery.c index a42fe990..204097d3 100644 --- a/drivers/gdisp/STM32F429iDiscovery/gdisp_lld_STM32F429iDiscovery.c +++ b/drivers/gdisp/STM32F429iDiscovery/gdisp_lld_STM32F429iDiscovery.c @@ -18,12 +18,20 @@ #undef GDISP_SCREEN_WIDTH #endif +#ifndef LTDC_USE_DMA2D + #define LTDC_USE_DMA2D FALSE +#endif + #define GDISP_DRIVER_VMT GDISPVMT_STM32F429iDiscovery #include "drivers/gdisp/STM32F429iDiscovery/gdisp_lld_config.h" #include "src/gdisp/gdisp_driver.h" #include "stm32_ltdc.h" +#if LTDC_USE_DMA2D + #include "stm32_dma2d.h" +#endif + typedef struct ltdcLayerConfig { // frame LLDCOLOR_TYPE *frame; // Frame buffer address @@ -287,6 +295,11 @@ LLDSPEC bool_t gdisp_lld_init(GDisplay *g) { // Initialise the LTDC controller LTDC_Init(); + // Initialise DMA2D + #if LTDC_USE_DMA2D + dma2d_init(); + #endif + // Initialise DMA2D //dma2dStart(&DMA2DD1, &dma2d_cfg); //dma2d_test(); @@ -422,4 +435,86 @@ LLDSPEC color_t gdisp_lld_get_pixel_color(GDisplay *g) { } #endif +#if LTDC_USE_DMA2D + static void dma2d_init(void) + { + // Enable DMA2D clock (DMA2DEN = 1) + RCC->AHB1ENR |= RCC_AHB1ENR_DMA2DEN; + + // Output color format + #if GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB565 + DMA2D->OPFCCR = OPFCCR_RGB565; + #elif GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB888 + DMA2D->OPFCCR = OPFCCR_OPFCCR_RGB888; + #endif + + // Foreground color format + #if GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB565 + DMA2D->FGPFCCR = FGPFCCR_CM_RGB565; + #elif GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB888 + DMA2D->FGPFCCR = FGPFCCR_CM_RGB888; + #endif + } + + // Uses p.x,p.y p.cx,p.cy p.color + LLDSPEC void gdisp_lld_fill_area(GDisplay* g) + { + LLDCOLOR_TYPE c; + + // Wait until DMA2D is ready + while (1) { + if (!(DMA2D->CR & DMA2D_CR_START)) { + break; + } + } + + c = gdispColor2Native(g->p.color); + + // Output color register + DMA2D->OCOLR = (uint32_t)c; + + // Output memory address register + DMA2D->OMAR = g->p.y * g->g.Width * LTDC_PIXELBYTES + g->p.x * LTDC_PIXELBYTES + (uint32_t)driverCfg.bglayer.frame; + + // Output offset register (in pixels) + DMA2D->OOR = g->g.Width - g->p.cx; + + // PL (pixel per lines to be transferred); NL (number of lines) + DMA2D->NLR = (g->p.cx << 16) | (g->p.cy); + + // Set MODE to R2M and Start the process + DMA2D->CR = DMA2D_CR_MODE_R2M | DMA2D_CR_START; + } + + // Uses p.x,p.y p.cx,p.cy p.x1,p.y1 (=srcx,srcy) p.x2 (=srccx), p.ptr (=buffer) + LLDSPEC void gdisp_lld_blit_area(GDisplay* g) + { + // Wait until DMA2D is ready + while (1) { + if (!(DMA2D->CR & DMA2D_CR_START)) { + break; + } + } + + // Foreground memory address register + DMA2D->FGMAR = g->p.y1 * g->p.x2 * LTDC_PIXELBYTES + g->p.x1 * LTDC_PIXELBYTES + (uint32_t)g->p.ptr; + + // Foreground offset register (expressed in pixels) + DMA2D->FGOR = g->p.x2 - g->p.cx; + + // Output memory address register + DMA2D->OMAR = g->p.y * g->g.Width * LTDC_PIXELBYTES + g->p.x * LTDC_PIXELBYTES + (uint32_t)driverCfg.bglayer.frame; + + // Output offset register (expressed in pixels) + DMA2D->OOR = g->g.Width - g->p.cx; + + // PL (pixel per lines to be transferred); NL (number of lines) + DMA2D->NLR = (g->p.cx << 16) | (g->p.cy); + + // Set MODE to M2M and Start the process + DMA2D->CR = DMA2D_CR_MODE_M2M | DMA2D_CR_START; + } + +#endif /* LTDC_USE_DMA2D */ + #endif /* GFX_USE_GDISP */ diff --git a/drivers/gdisp/STM32F429iDiscovery/gdisp_lld_config.h b/drivers/gdisp/STM32F429iDiscovery/gdisp_lld_config.h index 29e016ce..c661f67c 100644 --- a/drivers/gdisp/STM32F429iDiscovery/gdisp_lld_config.h +++ b/drivers/gdisp/STM32F429iDiscovery/gdisp_lld_config.h @@ -14,11 +14,25 @@ /* Driver hardware support. */ /*===========================================================================*/ +#define LTDC_USE_DMA2D TRUE #define GDISP_HARDWARE_DRAWPIXEL TRUE #define GDISP_HARDWARE_PIXELREAD TRUE #define GDISP_HARDWARE_CONTROL TRUE #define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_RGB565 + +/*===========================================================================*/ +/* Don't change stuff below this line. Please. */ +/*===========================================================================*/ + +#if LTDC_USE_DMA2D + #define GDISP_HARDWARE_FILLS TRUE + #define GDISP_HARDWARE_BITFILLS TRUE +#else + #define GDISP_HARDWARE_FILLS FALSE + #define GDISP_HARDWARE_BITFILLS FALSE +#endif /* GDISP_USE_DMA2D */ + #endif /* GFX_USE_GDISP */ #endif /* _GDISP_LLD_CONFIG_H */ diff --git a/drivers/gdisp/STM32F429iDiscovery/stm32_dma2d.h b/drivers/gdisp/STM32F429iDiscovery/stm32_dma2d.h new file mode 100644 index 00000000..d3374d05 --- /dev/null +++ b/drivers/gdisp/STM32F429iDiscovery/stm32_dma2d.h @@ -0,0 +1,18 @@ +#ifndef _STM32_DMA2D_H +#define _STM32_DMA2D_H + +#define OPFCCR_ARGB8888 0x00 +#define OPFCCR_RGB888 0x01 +#define OPFCCR_RGB565 0x02 +#define OPFCCR_ARGB1555 0x03 +#define OPFCCR_ARGB4444 0x04 + +#define FGPFCCR_CM_RGB888 0x01 +#define FGPFCCR_CM_RGB565 0x02 + +#define DMA2D_CR_MODE_R2M ((uint32_t)0x00030000) /* Register-to-memory mode */ +#define DMA2D_CR_MODE_M2M ((uint32_t)0x00000000) /* Register-to-memory mode */ + +static void dma2d_init(void); + +#endif /* _STM32_DMA2D_H */