From 04cb37f834bf2ba60c25d1f8d315a9462ad77f50 Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Sat, 17 Nov 2012 13:52:33 +0100 Subject: [PATCH] SSD1289 fix --- .../SSD1289/gdisp_lld_board_firebullstm32f103.h | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gdisp/SSD1289/gdisp_lld_board_firebullstm32f103.h b/drivers/gdisp/SSD1289/gdisp_lld_board_firebullstm32f103.h index 9c5d18c0..94e8090d 100644 --- a/drivers/gdisp/SSD1289/gdisp_lld_board_firebullstm32f103.h +++ b/drivers/gdisp/SSD1289/gdisp_lld_board_firebullstm32f103.h @@ -45,10 +45,18 @@ * @notapi */ static __inline void init_board(void) { - // This should set the GPIO port up for the correct hardware config here + /* set pin modes in case of defaults by board files have been overwritten */ + palSetBusMode(GDISP_DATA_PORT, PAL_MODE_OUTPUT_PUSHPULL); + palSetPadMode(GDISP_CMD_PORT, GDISP_CS, PAL_MODE_OUTPUT_PUSHPULL); + palSetPadMode(GDISP_CMD_PORT, GDISP_RS, PAL_MODE_OUTPUT_PUSHPULL); + palSetPadMode(GDISP_CMD_PORT, GDISP_WR, PAL_MODE_OUTPUT_PUSHPULL); + palSetPadMode(GDISP_CMD_PORT, GDISP_RD, PAL_MODE_OUTPUT_PUSHPULL); // Configure the pins to a well know state - SET_RS; SET_RD; SET_WR; CLR_CS; + SET_RS; + SET_RD; + SET_WR; + CLR_CS; }