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RA8875 changes from v1.7

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This commit is contained in:
inmarket 2013-07-19 13:22:42 +10:00
parent 386539072c
commit 0f3f885e4d
8 changed files with 135 additions and 570 deletions
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16
drivers/gdisp/RA8875/gdisp_lld.c
View file

@ -387,23 +387,13 @@ void gdisp_lld_draw_pixel(coord_t x, coord_t y, color_t color) {
return;
switch((gdisp_powermode_t)value) {
case powerOff:
write_index(SSD1963_EXIT_SLEEP_MODE); // leave sleep mode
chThdSleepMilliseconds(5);
write_index(SSD1963_SET_DISPLAY_OFF);
write_index(SSD1963_SET_DEEP_SLEEP); // enter deep sleep mode
/* ToDo */
break;
case powerOn:
read_reg(0x0000); chThdSleepMilliseconds(5); // 2x Dummy reads to wake up from deep sleep
read_reg(0x0000); chThdSleepMilliseconds(5);
if (GDISP.Powermode != powerSleep)
gdisp_lld_init();
write_index(SSD1963_SET_DISPLAY_ON);
/* ToDo */
break;
case powerSleep:
write_index(SSD1963_SET_DISPLAY_OFF);
write_index(SSD1963_ENTER_SLEEP_MODE); // enter sleep mode
chThdSleepMilliseconds(5);
/* ToDo */
break;
default:
return;

32
drivers/gdisp/RA8875/gdisp_lld_board.h
View file

@ -16,22 +16,9 @@
#ifndef _GDISP_LLD_BOARD_H
#define _GDISP_LLD_BOARD_H
#if defined(GDISP_USE_GPIO)
#define Set_CS palSetPad(GDISP_CMD_PORT, GDISP_CS);
#define Clr_CS palClearPad(GDISP_CMD_PORT, GDISP_CS);
#define Set_RS palSetPad(GDISP_CMD_PORT, GDISP_RS);
#define Clr_RS palClearPad(GDISP_CMD_PORT, GDISP_RS);
#define Set_WR palSetPad(GDISP_CMD_PORT, GDISP_WR);
#define Clr_WR palClearPad(GDISP_CMD_PORT, GDISP_WR);
#define Set_RD palSetPad(GDISP_CMD_PORT, GDISP_RD);
#define Clr_RD palClearPad(GDISP_CMD_PORT, GDISP_RD);
#endif
#if defined(GDISP_USE_FSMC)
/* Using FSMC A16 as RS */
#define GDISP_RAM (*((volatile uint16_t *) 0x68000000)) /* RS = 0 */
#define GDISP_REG (*((volatile uint16_t *) 0x68020000)) /* RS = 1 */
#endif
/* Using FSMC A16 as RS */
#define GDISP_RAM (*((volatile uint16_t *) 0x68000000)) /* RS = 0 */
#define GDISP_REG (*((volatile uint16_t *) 0x68020000)) /* RS = 1 */
/**
* @brief Send data to the index register.
@ -40,7 +27,9 @@
*
* @notapi
*/
static inline void write_index(uint16_t index) { GDISP_REG = index; }
static inline void write_index(uint16_t index) {
GDISP_REG = index;
}
/**
* @brief Send data to the lcd.
@ -49,7 +38,9 @@ static inline void write_index(uint16_t index) { GDISP_REG = index; }
*
* @notapi
*/
static inline void write_data(uint16_t data) { GDISP_RAM = data; }
static inline void write_data(uint16_t data) {
GDISP_RAM = data;
}
/**
* @brief Read data from the lcd.
@ -60,7 +51,9 @@ static inline void write_data(uint16_t data) { GDISP_RAM = data; }
*
* @notapi
*/
static inline uint16_t read_data(void) { return GDISP_RAM; }
static inline uint16_t read_data(void) {
return GDISP_RAM;
}
/**
* @brief Initialise the board for the display.
@ -197,3 +190,4 @@ static inline void release_bus(void) {
#endif /* _GDISP_LLD_BOARD_H */
/** @} */

119
drivers/gdisp/RA8875/gdisp_lld_board_example.h Normal file
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@ -0,0 +1,119 @@
/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://chibios-gfx.com/license.html
*/
/**
* @file drivers/gdisp/SSD1963/gdisp_lld_board_example.h
* @brief GDISP Graphic Driver subsystem board interface for the SSD1963 display.
*
* @addtogroup GDISP
* @{
*/
#ifndef _GDISP_LLD_BOARD_H
#define _GDISP_LLD_BOARD_H
/**
* @brief Send data to the index register.
*
* @param[in] index The index register to set
*
* @notapi
*/
static inline void write_index(uint16_t index) {
}
/**
* @brief Send data to the lcd.
*
* @param[in] data The data to send
*
* @notapi
*/
static inline void write_data(uint16_t data) {
}
/**
* @brief Initialise the board for the display.
*
* @notapi
*/
static inline void init_board(void) {
}
static inline void post_init_board(void) {
}
/**
* @brief Set or clear the lcd reset pin.
*
* @param[in] state TRUE = lcd in reset, FALSE = normal operation
*
* @notapi
*/
static inline void setpin_reset(bool_t state) {
}
/**
* @brief Set the lcd back-light level.
*
* @param[in] percent 0 to 100%
*
* @notapi
*/
static inline void set_backlight(uint8_t percent) {
}
/**
* @brief Take exclusive control of the bus
*
* @notapi
*/
static inline void acquire_bus(void) {
}
/**
* @brief Release exclusive control of the bus
*
* @notapi
*/
static inline void release_bus(void) {
}
__inline void write_stream(uint16_t *buffer, uint16_t size) {
}
__inline void read_stream(uint16_t *buffer, size_t size) {
}
#if GDISP_HARDWARE_READPIXEL || GDISP_HARDWARE_SCROLL || defined(__DOXYGEN__)
/**
* @brief Read data from the lcd.
*
* @return The data from the lcd
* @note The chip select may need to be asserted/de-asserted
* around the actual spi read
*
* @notapi
*/
static inline uint16_t read_data(void) {
}
#endif
#endif /* _GDISP_LLD_BOARD_H */
/** @} */

181
drivers/gdisp/RA8875/gdisp_lld_board_example_fsmc.h
View file

@ -1,181 +0,0 @@
/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://chibios-gfx.com/license.html
*/
/**
* @file drivers/gdisp/SSD1289/gdisp_lld_board_example_fsmc.h
* @brief GDISP Graphic Driver subsystem board interface for the SSD1289 display.
*
* @addtogroup GDISP
* @{
*/
#ifndef _GDISP_LLD_BOARD_H
#define _GDISP_LLD_BOARD_H
#if defined(GDISP_USE_GPIO)
#define Set_CS palSetPad(GDISP_CMD_PORT, GDISP_CS);
#define Clr_CS palClearPad(GDISP_CMD_PORT, GDISP_CS);
#define Set_RS palSetPad(GDISP_CMD_PORT, GDISP_RS);
#define Clr_RS palClearPad(GDISP_CMD_PORT, GDISP_RS);
#define Set_WR palSetPad(GDISP_CMD_PORT, GDISP_WR);
#define Clr_WR palClearPad(GDISP_CMD_PORT, GDISP_WR);
#define Set_RD palSetPad(GDISP_CMD_PORT, GDISP_RD);
#define Clr_RD palClearPad(GDISP_CMD_PORT, GDISP_RD);
#endif
#if defined(GDISP_USE_FSMC)
/* Using FSMC A16 as RS */
#define GDISP_REG (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
#define GDISP_RAM (*((volatile uint16_t *) 0x60020000)) /* RS = 1 */
#endif
/**
* @brief Send data to the index register.
*
* @param[in] index The index register to set
*
* @notapi
*/
static inline void write_index(uint16_t index) { GDISP_REG = index; }
/**
* @brief Send data to the lcd.
*
* @param[in] data The data to send
*
* @notapi
*/
static inline void write_data(uint16_t data) { GDISP_RAM = data; }
/**
* @brief Initialise the board for the display.
* @notes Performs the following functions:
* 1. initialise the io port used by your display
* 2. initialise the reset pin (initial state not-in-reset)
* 3. initialise the chip select pin (initial state not-active)
* 4. initialise the backlight pin (initial state back-light off)
*
* @notapi
*/
static inline void init_board(void) {
const unsigned char FSMC_Bank = 0;
#if defined(STM32F1XX) || defined(STM32F3XX)
/* FSMC setup for F1/F3 */
rccEnableAHB(RCC_AHBENR_FSMCEN, 0);
#if defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM)
#error "DMA not implemented for F1/F3 Devices"
#endif
#elif defined(STM32F4XX) || defined(STM32F2XX)
/* STM32F2-F4 FSMC init */
rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0);
#if defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM)
if (dmaStreamAllocate(GDISP_DMA_STREAM, 0, NULL, NULL)) chSysHalt();
dmaStreamSetMemory0(GDISP_DMA_STREAM, &GDISP_RAM);
dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
#endif
#else
#error "FSMC not implemented for this device"
#endif
/* set pins to FSMC mode */
IOBus busD = {GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) | (1 << 7) | (1 << 8) |
(1 << 9) | (1 << 10) | (1 << 11) | (1 << 14) | (1 << 15), 0};
IOBus busE = {GPIOE, (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) |
(1 << 13) | (1 << 14) | (1 << 15), 0};
palSetBusMode(&busD, PAL_MODE_ALTERNATE(12));
palSetBusMode(&busE, PAL_MODE_ALTERNATE(12));
/* FSMC timing */
FSMC_Bank1->BTCR[FSMC_Bank+1] = (FSMC_BTR1_ADDSET_1 | FSMC_BTR1_ADDSET_3) \
| (FSMC_BTR1_DATAST_1 | FSMC_BTR1_DATAST_3) \
| (FSMC_BTR1_BUSTURN_1 | FSMC_BTR1_BUSTURN_3) ;
/* Bank1 NOR/SRAM control register configuration
* This is actually not needed as already set by default after reset */
FSMC_Bank1->BTCR[FSMC_Bank] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
}
static inline void post_init_board(void) {
const unsigned char FSMC_Bank = 0;
/* FSMC delay reduced as the controller now runs at full speed */
FSMC_Bank1->BTCR[FSMC_Bank+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0 ;
FSMC_Bank1->BTCR[FSMC_Bank] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
}
/**
* @brief Set or clear the lcd reset pin.
*
* @param[in] state TRUE = lcd in reset, FALSE = normal operation
*
* @notapi
*/
static inline void setpin_reset(bool_t state) {
(void) state;
/* Nothing to do here */
}
/**
* @brief Set the lcd back-light level.
*
* @param[in] percent 0 to 100%
*
* @notapi
*/
static inline void set_backlight(uint8_t percent) {
//duty_cycle is 00..FF
//Work in progress: the SSD1963 has a built-in PWM, its output can
//be used by a Dynamic Background Control or by a host (user)
//Check your LCD's hardware, the PWM connection is default left open and instead
//connected to a LED connection on the breakout board
write_index(SSD1963_SET_PWM_CONF);//set PWM for BackLight
write_data(0x0001);
write_data(percent & 0x00FF);
write_data(0x0001);//controlled by host (not DBC), enabled
write_data(0x00FF);
write_data(0x0060);//don't let it go too dark, avoid a useless LCD
write_data(0x000F);//prescaler ???
}
/**
* @brief Take exclusive control of the bus
*
* @notapi
*/
static inline void acquire_bus(void) {
/* Nothing to do here */
}
/**
* @brief Release exclusive control of the bus
*
* @notapi
*/
static inline void release_bus(void) {
/* Nothing to do here */
}
#if GDISP_HARDWARE_READPIXEL || GDISP_HARDWARE_SCROLL || defined(__DOXYGEN__)
/**
* @brief Read data from the lcd.
*
* @return The data from the lcd
* @note The chip select may need to be asserted/de-asserted
* around the actual spi read
*
* @notapi
*/
static inline uint16_t read_data(void) { return GDISP_RAM; }
#endif
#endif /* _GDISP_LLD_BOARD_H */
/** @} */

171
drivers/gdisp/RA8875/gdisp_lld_board_example_gpio.h
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@ -1,171 +0,0 @@
/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://chibios-gfx.com/license.html
*/
/**
* @file drivers/gdisp/SSD1963/gdisp_lld_board_example_gpio.h
* @brief GDISP Graphic Driver subsystem board interface for the SSD1963 display.
*
* @addtogroup GDISP
* @{
*/
#ifndef _GDISP_LLD_BOARD_H
#define _GDISP_LLD_BOARD_H
#if defined(GDISP_USE_GPIO)
#define Set_CS palSetPad(GDISP_CMD_PORT, GDISP_CS);
#define Clr_CS palClearPad(GDISP_CMD_PORT, GDISP_CS);
#define Set_RS palSetPad(GDISP_CMD_PORT, GDISP_RS);
#define Clr_RS palClearPad(GDISP_CMD_PORT, GDISP_RS);
#define Set_WR palSetPad(GDISP_CMD_PORT, GDISP_WR);
#define Clr_WR palClearPad(GDISP_CMD_PORT, GDISP_WR);
#define Set_RD palSetPad(GDISP_CMD_PORT, GDISP_RD);
#define Clr_RD palClearPad(GDISP_CMD_PORT, GDISP_RD);
#endif
#if defined(GDISP_USE_FSMC)
/* Using FSMC A16 as RS */
#define GDISP_REG (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
#define GDISP_RAM (*((volatile uint16_t *) 0x60020000)) /* RS = 1 */
#endif
/**
* @brief Send data to the index register.
*
* @param[in] index The index register to set
*
* @notapi
*/
static inline void write_index(uint16_t index) {
Set_CS; Set_RS; Set_WR; Clr_RD;
palWritePort(GDISP_DATA_PORT, index);
Clr_CS;
}
/**
* @brief Send data to the lcd.
*
* @param[in] data The data to send
*
* @notapi
*/
static inline void write_data(uint16_t data) {
Set_CS; Clr_RS; Set_WR; Clr_RD;
palWritePort(GDISP_DATA_PORT, data);
Clr_CS;
}
/**
* @brief Initialise the board for the display.
*
* @notapi
*/
static inline void init_board(void) {
IOBus busCMD = {GDISP_CMD_PORT, (1 << GDISP_CS) | (1 << GDISP_RS) | (1 << GDISP_WR) | (1 << GDISP_RD), 0};
IOBus busDATA = {GDISP_CMD_PORT, 0xFFFFF, 0};
palSetBusMode(&busCMD, PAL_MODE_OUTPUT_PUSHPULL);
palSetBusMode(&busDATA, PAL_MODE_OUTPUT_PUSHPULL);
}
static inline void post_init_board(void) {
/* Nothing to do here */
}
/**
* @brief Set or clear the lcd reset pin.
*
* @param[in] state TRUE = lcd in reset, FALSE = normal operation
*
* @notapi
*/
static inline void setpin_reset(bool_t state) {
}
/**
* @brief Set the lcd back-light level.
*
* @param[in] percent 0 to 100%
*
* @notapi
*/
static inline void set_backlight(uint8_t percent) {
//duty_cycle is 00..FF
//Work in progress: the SSD1963 has a built-in PWM, its output can
//be used by a Dynamic Background Control or by a host (user)
//Check your LCD's hardware, the PWM connection is default left open and instead
//connected to a LED connection on the breakout board
write_index(SSD1963_SET_PWM_CONF);//set PWM for BackLight
write_data(0x0001);
write_data(percent & 0x00FF);
write_data(0x0001);//controlled by host (not DBC), enabled
write_data(0x00FF);
write_data(0x0060);//don't let it go too dark, avoid a useless LCD
write_data(0x000F);//prescaler ???
}
/**
* @brief Take exclusive control of the bus
*
* @notapi
*/
static inline void acquire_bus(void) {
/* Nothing to do here */
}
/**
* @brief Release exclusive control of the bus
*
* @notapi
*/
static inline void release_bus(void) {
/* Nothing to do here */
}
__inline void write_stream(uint16_t *buffer, uint16_t size) {
uint16_t i;
Set_CS; Clr_RS; Set_WR; Clr_RD;
for(i = 0; i < size; i++) {
Set_WR;
palWritePort(GDISP_DATA_PORT, buffer[i]);
Clr_WR;
}
Clr_CS;
}
__inline void read_stream(uint16_t *buffer, size_t size) {
uint16_t i;
Set_CS; Clr_RS; Clr_WR; Set_RD;
for(i = 0; i < size; i++) {
Set_RD;
buffer[i] = palReadPort(GDISP_DATA_PORT);
Clr_RD;
}
}
#if GDISP_HARDWARE_READPIXEL || GDISP_HARDWARE_SCROLL || defined(__DOXYGEN__)
/**
* @brief Read data from the lcd.
*
* @return The data from the lcd
* @note The chip select may need to be asserted/de-asserted
* around the actual spi read
*
* @notapi
*/
static inline uint16_t read_data(void) {
Set_CS; Clr_RS; Clr_WR; Set_RD;
uint16_t data = palReadPort(GDISP_DATA_PORT);
Clr_CS;
return data;
}
#endif
#endif /* _GDISP_LLD_BOARD_H */
/** @} */

74
drivers/gdisp/RA8875/gdisp_lld_panel.h
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@ -1,74 +0,0 @@
/*
* This file is subject to the terms of the GFX License, v1.0. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://chibios-gfx.com/license.html
*/
/**
* @file drivers/gdisp/SSD1963/gdisp_lld_panel_example.h
* @brief TFT LCD panel properties.
*
* @addtogroup GDISP
* @{
*/
#ifndef _GDISP_LLD_PANEL_H
#define _GDISP_LLD_PANEL_H
/* LCD panel specs */
/* The timings need to follow the datasheet for your particular TFT/LCD screen (the actual screen, not the controller)
*** Datasheets normally use a specific set of timings and acronyms, their value refers to the number of pixel clocks
** Non-display periods refer to pulses/timings that occur before or after the timings that actually put pixels on the screen
** Display periods refer to pulses/timings that directly put pixels on the screen
HDP: Horizontal Display Period, normally the width - 1
HT: Horizontal Total period (display + non-display)
HPS: non-display period between the start of the horizontal sync (LLINE) signal and the first display data
LPS: horizontal sync pulse (LLINE) start location in pixel clocks
HPW: Horizontal sync Pulse Width
VDP: Vertical Display period, normally height - 1
VT: Vertical Total period (display + non-display)
VPS: non-display period in lines between the start of the frame and the first display data in number of lines
FPS: vertical sync pulse (LFRAME) start location in lines.
VPW: Vertical sync Pulse Width
*** Here's how to convert them:
HPS = SCREEN_HSYNC_PULSE + SCREEN_HSYNC_BACK_PORCH
HT - HPS = GDISP_SCREEN_WIDTH + SCREEN_HSYNC_FRONT_PORCH
=> SCREEN_HSYNC_FRONT_PORCH = ( HT - HPS ) - GDISP_SCREEN_WIDTH
SCREEN_HSYNC_PULSE = HPW
SCREEN_HSYNC_BACK_PORCH = HPS - HPW
SCREEN_HSYNC_PERIOD = HT
VPS = SCREEN_VSYNC_PULSE + SCREEN_VSYNC_BACK_PORCH
VT - VPS = GDISP_SCREEN_HEIGHT + SCREEN_VSYNC_FRONT_PORCH
=> SCREEN_VSYNC_FRONT_PORCH = ( VT - VPS ) - GDISP_SCREEN_HEIGHT
SCREEN_VSYNC_PULSE = VPW
SCREEN_VSYNC_BACK_PORCH = VPS - LPS
SCREEN_VSYNC_PERIOD = VT
*/
#define SCREEN_FPS 60ULL
//The following values are for a 4.3" TFT LCD
#define GDISP_SCREEN_WIDTH 480
#define GDISP_SCREEN_HEIGHT 272
#define SCREEN_HSYNC_BACK_PORCH 2
#define SCREEN_HSYNC_FRONT_PORCH 2
#define SCREEN_HSYNC_PULSE 41
#define SCREEN_VSYNC_BACK_PORCH 2
#define SCREEN_VSYNC_FRONT_PORCH 2
#define SCREEN_VSYNC_PULSE 10
#define SCREEN_HSYNC_PERIOD (SCREEN_HSYNC_PULSE + SCREEN_HSYNC_BACK_PORCH + GDISP_SCREEN_WIDTH + SCREEN_HSYNC_FRONT_PORCH)
#define SCREEN_VSYNC_PERIOD (SCREEN_VSYNC_PULSE + SCREEN_VSYNC_BACK_PORCH + GDISP_SCREEN_HEIGHT + SCREEN_VSYNC_FRONT_PORCH)
#define SCREEN_PCLK (SCREEN_HSYNC_PERIOD * SCREEN_VSYNC_PERIOD * SCREEN_FPS)
#define GDISP_FPR ((SCREEN_PCLK * 1048576)/100000000)
#endif
/** @} */

74
drivers/gdisp/RA8875/gdisp_lld_panel_example.h
View file

@ -1,74 +0,0 @@
/*
* This file is subject to the terms of the GFX License, v1.0. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://chibios-gfx.com/license.html
*/
/**
* @file drivers/gdisp/SSD1963/gdisp_lld_panel_example.h
* @brief TFT LCD panel properties.
*
* @addtogroup GDISP
* @{
*/
#ifndef _GDISP_LLD_PANEL_H
#define _GDISP_LLD_PANEL_H
/* LCD panel specs */
/* The timings need to follow the datasheet for your particular TFT/LCD screen (the actual screen, not the controller)
*** Datasheets normally use a specific set of timings and acronyms, their value refers to the number of pixel clocks
** Non-display periods refer to pulses/timings that occur before or after the timings that actually put pixels on the screen
** Display periods refer to pulses/timings that directly put pixels on the screen
HDP: Horizontal Display Period, normally the width - 1
HT: Horizontal Total period (display + non-display)
HPS: non-display period between the start of the horizontal sync (LLINE) signal and the first display data
LPS: horizontal sync pulse (LLINE) start location in pixel clocks
HPW: Horizontal sync Pulse Width
VDP: Vertical Display period, normally height - 1
VT: Vertical Total period (display + non-display)
VPS: non-display period in lines between the start of the frame and the first display data in number of lines
FPS: vertical sync pulse (LFRAME) start location in lines.
VPW: Vertical sync Pulse Width
*** Here's how to convert them:
HPS = SCREEN_HSYNC_PULSE + SCREEN_HSYNC_BACK_PORCH
HT - HPS = GDISP_SCREEN_WIDTH + SCREEN_HSYNC_FRONT_PORCH
=> SCREEN_HSYNC_FRONT_PORCH = ( HT - HPS ) - GDISP_SCREEN_WIDTH
SCREEN_HSYNC_PULSE = HPW
SCREEN_HSYNC_BACK_PORCH = HPS - HPW
SCREEN_HSYNC_PERIOD = HT
VPS = SCREEN_VSYNC_PULSE + SCREEN_VSYNC_BACK_PORCH
VT - VPS = GDISP_SCREEN_HEIGHT + SCREEN_VSYNC_FRONT_PORCH
=> SCREEN_VSYNC_FRONT_PORCH = ( VT - VPS ) - GDISP_SCREEN_HEIGHT
SCREEN_VSYNC_PULSE = VPW
SCREEN_VSYNC_BACK_PORCH = VPS - LPS
SCREEN_VSYNC_PERIOD = VT
*/
#define SCREEN_FPS 60ULL
//The following values are for a 4.3" TFT LCD
#define GDISP_SCREEN_WIDTH 480
#define GDISP_SCREEN_HEIGHT 272
#define SCREEN_HSYNC_BACK_PORCH 2
#define SCREEN_HSYNC_FRONT_PORCH 2
#define SCREEN_HSYNC_PULSE 41
#define SCREEN_VSYNC_BACK_PORCH 2
#define SCREEN_VSYNC_FRONT_PORCH 2
#define SCREEN_VSYNC_PULSE 10
#define SCREEN_HSYNC_PERIOD (SCREEN_HSYNC_PULSE + SCREEN_HSYNC_BACK_PORCH + GDISP_SCREEN_WIDTH + SCREEN_HSYNC_FRONT_PORCH)
#define SCREEN_VSYNC_PERIOD (SCREEN_VSYNC_PULSE + SCREEN_VSYNC_BACK_PORCH + GDISP_SCREEN_HEIGHT + SCREEN_VSYNC_FRONT_PORCH)
#define SCREEN_PCLK (SCREEN_HSYNC_PERIOD * SCREEN_VSYNC_PERIOD * SCREEN_FPS)
#define GDISP_FPR ((SCREEN_PCLK * 1048576)/100000000)
#endif
/** @} */

38
drivers/gdisp/RA8875/readme.txt
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@ -1,38 +0,0 @@
To use this driver:
1. Add in your halconf.h:
a) #define GFX_USE_GDISP TRUE
b) Any optional high level driver defines (see gdisp.h) eg: #define GDISP_NEED_MULTITHREAD TRUE
c) One (only) of:
#define GDISP_USE_GPIO
#define GDISP_USE_FSMC
d) If you want to use DMA (only works with FSMC):
#define GDISP_USE_DMA
#define GDISP_DMA_STREAM STM32_DMA2_STREAM6 //You can change the DMA channel according to your needs
2. Edit gdisp_lld_panel.h with your panel properties
3. To your makefile add the following lines:
include $(GFXLIB)/drivers/gdisp/RA8875/gdisp_lld.mk
Example FSMC config with DMA:
#define GDISP_SCREEN_WIDTH 480
#define GDISP_SCREEN_HEIGHT 272
#define GDISP_USE_FSMC
#define GDISP_USE_DMA
#define GDISP_DMA_STREAM STM32_DMA2_STREAM6
#if defined(GDISP_USE_GPIO)
#define GDISP_CMD_PORT GPIOC
#define GDISP_DATA_PORT GPIOD
#define GDISP_CS 0
#define GDISP_RS 1
#define GDISP_WR 2
#define GDISP_RD 3
#endif