From f3f7eba73cb199c0222440ea50052b77975f170a Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Thu, 24 Oct 2013 14:08:35 +0200 Subject: [PATCH 1/2] fixed board file name (all the others are upper case as well) --- drivers/gdisp/RA8875/gdisp_lld.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gdisp/RA8875/gdisp_lld.c b/drivers/gdisp/RA8875/gdisp_lld.c index b0508b58..fb81c43a 100644 --- a/drivers/gdisp/RA8875/gdisp_lld.c +++ b/drivers/gdisp/RA8875/gdisp_lld.c @@ -19,7 +19,7 @@ #include "gdisp/lld/gdisp_lld.h" /* include the users board interface */ -#include "board_ra8875.h" +#include "board_RA8875.h" /*===========================================================================*/ /* Driver local definitions. */ From af3963d341f14fd46a2eaa26f53f44de641299dc Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Thu, 24 Oct 2013 14:49:00 +0200 Subject: [PATCH 2/2] fixed RA8875 board file for marlin --- drivers/gdisp/RA8875/board_RA8875_marlin.h | 64 +++++++++++++--------- 1 file changed, 39 insertions(+), 25 deletions(-) diff --git a/drivers/gdisp/RA8875/board_RA8875_marlin.h b/drivers/gdisp/RA8875/board_RA8875_marlin.h index e6c19d34..b1d55a92 100644 --- a/drivers/gdisp/RA8875/board_RA8875_marlin.h +++ b/drivers/gdisp/RA8875/board_RA8875_marlin.h @@ -10,52 +10,62 @@ * @brief GDISP Graphic Driver subsystem board interface for the RA8875 display. */ -#ifndef _GDISP_LLD_BOARD_H -#define _GDISP_LLD_BOARD_H +#ifndef _BOARD_RA8875_H +#define _BOARD_RA8875_H // For a multiple display configuration we would put all this in a structure and then -// set g->board to that structure. +// set g->board to that structure. #define GDISP_RAM (*((volatile uint16_t *) 0x68000000)) /* RS = 0 */ #define GDISP_REG (*((volatile uint16_t *) 0x68020000)) /* RS = 1 */ #define FSMC_BANK 4 static inline void init_board(GDisplay *g) { - // As we are not using multiple displays we set g->board to NULL as we don't use it. g->board = 0; switch(g->controllerdisplay) { - case 0: // Set up for Display 0 - /* set pins to FSMC mode */ - IOBus busD = {GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) | (1 << 8) | - (1 << 9) | (1 << 10) | (1 << 11) | (1 << 14) | (1 << 15), 0}; + // setup for display 0 + case 0: { - IOBus busE = {GPIOE, (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) | - (1 << 13) | (1 << 14) | (1 << 15), 0}; + // enable the FSMC peripheral + rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0); - IOBus busG = {GPIOG, (1 << 10), 0}; + // setup the pin modes for FSMC + IOBus busD = {GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) | (1 << 8) | + (1 << 9) | (1 << 10) | (1 << 11) | (1 << 14) | (1 << 15), 0}; - palSetBusMode(&busD, PAL_MODE_ALTERNATE(12)); - palSetBusMode(&busE, PAL_MODE_ALTERNATE(12)); - palSetBusMode(&busG, PAL_MODE_ALTERNATE(12)); + IOBus busE = {GPIOE, (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) | + (1 << 13) | (1 << 14) | (1 << 15), 0}; - /* FSMC timing */ - FSMC_Bank1->BTCR[FSMC_BANK+1] = (FSMC_BTR1_ADDSET_1 | FSMC_BTR1_ADDSET_3) \ - | (FSMC_BTR1_DATAST_1 | FSMC_BTR1_DATAST_3) \ - | (FSMC_BTR1_BUSTURN_1 | FSMC_BTR1_BUSTURN_3) ; + IOBus busG = {GPIOG, (1 << 10), 0}; - /* Bank1 NOR/SRAM control register configuration - * This is actually not needed as already set by default after reset */ - FSMC_Bank1->BTCR[FSMC_BANK] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN; - break; + palSetBusMode(&busD, PAL_MODE_ALTERNATE(12)); + palSetBusMode(&busE, PAL_MODE_ALTERNATE(12)); + palSetBusMode(&busG, PAL_MODE_ALTERNATE(12)); + + // FSMC timing + FSMC_Bank1->BTCR[FSMC_BANK+1] = (FSMC_BTR1_ADDSET_1 | FSMC_BTR1_ADDSET_3) \ + | (FSMC_BTR1_DATAST_1 | FSMC_BTR1_DATAST_3) \ + | (FSMC_BTR1_BUSTURN_1 | FSMC_BTR1_BUSTURN_3) ; + + // Bank1 NOR/SRAM control register configuration + // This is actually not needed as already set by default after reset + FSMC_Bank1->BTCR[FSMC_BANK] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN; + + break; + } + + // marlin does not have any secondary display so far + default: + break; } } static inline void post_init_board(GDisplay *g) { (void) g; - - /* FSMC delay reduced as the controller now runs at full speed */ + + // FSMC delay reduced as the controller now runs at full speed FSMC_Bank1->BTCR[2+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0 ; FSMC_Bank1->BTCR[2] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN; } @@ -75,11 +85,13 @@ static inline void release_bus(GDisplay *g) { static inline void write_index(GDisplay *g, uint16_t index) { (void) g; + GDISP_REG = index; } static inline void write_data(GDisplay *g, uint16_t data) { (void) g; + GDISP_RAM = data; } @@ -93,7 +105,9 @@ static inline void setwritemode(GDisplay *g) { static inline uint16_t read_data(GDisplay *g) { (void) g; + return GDISP_RAM; } -#endif /* _GDISP_LLD_BOARD_H */ +#endif /* _BOARD_RA8875_H */ +