From 3936c630612c9aff74f3bc21984e486f81d3f7da Mon Sep 17 00:00:00 2001 From: inmarket Date: Mon, 15 Dec 2014 18:17:52 +1000 Subject: [PATCH] Updates for the EMBEST board and a small fix to the SSD2119 driver. --- boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h | 11 +++++++---- .../Embest-STM32-DMSTF4BB/gmouse_lld_STMPE811_board.h | 2 +- drivers/gdisp/SSD2119/gdisp_lld_SSD2119.c | 10 +++++----- 3 files changed, 13 insertions(+), 10 deletions(-) diff --git a/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h b/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h index 2b1aa27d..a8b42239 100644 --- a/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h +++ b/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h @@ -29,8 +29,8 @@ * the PWM frequency should be somewhere between 200 Hz to 200 kHz. */ static const PWMConfig pwmcfg = { - 1000000, /* 1 MHz PWM clock frequency. */ - 100, /* PWM period is 100 cycles. */ + 20000, /* 20 KHz PWM clock frequency. */ + 100, /* PWM period is 100 cycles. */ 0, { {PWM_OUTPUT_ACTIVE_HIGH, 0}, @@ -75,8 +75,11 @@ static inline void init_board(GDisplay *g) { palSetBusMode(&busE, PAL_MODE_ALTERNATE(12)); /* FSMC timing register configuration */ - FSMC_Bank1->BTCR[0 + 1] = (FSMC_BTR1_ADDSET_2 | FSMC_BTR1_ADDSET_1) \ - | (FSMC_BTR1_DATAST_2 | FSMC_BTR1_DATAST_1) \ +// FSMC_Bank1->BTCR[0 + 1] = (FSMC_BTR1_ADDSET_2 | FSMC_BTR1_ADDSET_1) \ +// | (FSMC_BTR1_DATAST_2 | FSMC_BTR1_DATAST_1) \ +// | FSMC_BTR1_BUSTURN_0; + FSMC_Bank1->BTCR[0 + 1] = (FSMC_BTR1_ADDSET_3 | FSMC_BTR1_ADDSET_0) \ + | (FSMC_BTR1_DATAST_3 | FSMC_BTR1_DATAST_0) \ | FSMC_BTR1_BUSTURN_0; /* Bank1 NOR/PSRAM control register configuration diff --git a/boards/base/Embest-STM32-DMSTF4BB/gmouse_lld_STMPE811_board.h b/boards/base/Embest-STM32-DMSTF4BB/gmouse_lld_STMPE811_board.h index bbb17010..43a8ad18 100644 --- a/boards/base/Embest-STM32-DMSTF4BB/gmouse_lld_STMPE811_board.h +++ b/boards/base/Embest-STM32-DMSTF4BB/gmouse_lld_STMPE811_board.h @@ -39,7 +39,7 @@ static const I2CConfig i2ccfg = { OPMODE_I2C, - 400000, + 200000, // Conservative please FAST_DUTY_CYCLE_2, }; diff --git a/drivers/gdisp/SSD2119/gdisp_lld_SSD2119.c b/drivers/gdisp/SSD2119/gdisp_lld_SSD2119.c index 08cddf96..36deeb90 100644 --- a/drivers/gdisp/SSD2119/gdisp_lld_SSD2119.c +++ b/drivers/gdisp/SSD2119/gdisp_lld_SSD2119.c @@ -152,7 +152,7 @@ LLDSPEC bool_t gdisp_lld_init(GDisplay* g) { gfxSleepMicroseconds(5); // Configure pixel color format and MCU interface parameters. - write_reg(g, SSD2119_REG_ENTRY_MODE, 0x6830); // ENTRY_MODE_DEFAULT + write_reg(g, SSD2119_REG_ENTRY_MODE, 0x6838); // ENTRY_MODE_DEFAULT gfxSleepMicroseconds(5); // Set analog parameters. @@ -267,7 +267,7 @@ LLDSPEC bool_t gdisp_lld_init(GDisplay* g) { #if GDISP_HARDWARE_FILLS && defined(GDISP_USE_DMA) LLDSPEC void gdisp_lld_fill_area(GDisplay* g) { - uint16_t c; + LLDCOLOR_TYPE c; c = gdispColor2Native(g->p.color); acquire_bus(g); @@ -285,7 +285,7 @@ LLDSPEC bool_t gdisp_lld_init(GDisplay* g) { LLDSPEC void gdisp_lld_blit_area(GDisplay* g) { pixel_t* buffer; - coord_t ynct; + coord_t ycnt; buffer = (pixel_t*)g->p.ptr + g->p.x1 + g->p.y1 * g->p.x2; @@ -355,8 +355,8 @@ LLDSPEC bool_t gdisp_lld_init(GDisplay* g) { switch((orientation_t)g->p.ptr) { case GDISP_ROTATE_0: acquire_bus(g); - /* ID = 11 AM = 0 */ - write_reg(g, SSD2119_REG_ENTRY_MODE, 0x6830); + /* ID = 11 AM = 1 */ + write_reg(g, SSD2119_REG_ENTRY_MODE, 0x6838); release_bus(g); g->g.Height = GDISP_SCREEN_HEIGHT; g->g.Width = GDISP_SCREEN_WIDTH;