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STM32F429i-Discovery board is now a supported board with an example project. 

New gdisp driver (currently non-accelerated)
Mouse and other drivers still to come.
The board file is currently ChibiOS specific however the gdisp driver is suitable for any OS.
ugfx_release_2.6
inmarket 2014-11-05 19:32:47 +10:00
parent 665d998f43
commit 2284e5e9cf
18 changed files with 5864 additions and 0 deletions
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8
boards/base/STM32F429i-Discovery/board.mk 100644
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GFXINC += $(GFXLIB)/boards/base/STM32F429i-Discovery
GFXSRC += $(GFXLIB)/boards/base/STM32F429i-Discovery/stm32f429i_discovery_sdram.c \
$(GFXLIB)/boards/base/STM32F429i-Discovery/stm32f4xx_fmc.c
GFXDEFS += -DGFX_USE_OS_CHIBIOS=TRUE
include $(GFXLIB)/drivers/gdisp/STM32F429iDiscovery/driver.mk
#include $(GFXLIB)/drivers/ginput/touch/MCU/driver.mk
#include $(GFXLIB)/drivers/gaudio/vs1053/driver.mk

153
boards/base/STM32F429i-Discovery/board_STM32F429iDiscovery.h 100644
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/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.org/license.html
*/
#ifndef _GDISP_LLD_BOARD_H
#define _GDISP_LLD_BOARD_H
#include "stm32f4xx_fmc.h"
#include "stm32f429i_discovery_sdram.h"
#include <string.h>
#define SPI_PORT &SPID5
#define DC_PORT GPIOD
#define DC_PIN GPIOD_LCD_WRX
static const SPIConfig spi_cfg = {
NULL,
GPIOC,
GPIOC_SPI5_LCD_CS,
((1 << 3) & SPI_CR1_BR) | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR
};
static const ltdcConfig driverCfg = {
240, 320,
10, 2,
20, 2,
10, 4,
0,
0x000000,
{
(LLDCOLOR_TYPE *)SDRAM_BANK_ADDR, // frame
240, 320, // width, height
240 * LTDC_PIXELBYTES, // pitch
LTDC_PIXELFORMAT, // fmt
0, 0, // x, y
240, 320, // cx, cy
LTDC_COLOR_FUCHSIA, // defcolor
0x980088, // keycolor
LTDC_BLEND_FIX1_FIX2, // blending
0, // palette
0, // palettelen
0xFF, // alpha
LTDC_LEF_ENABLE // flags
},
LTDC_UNUSED_LAYER_CONFIG
};
static inline void init_board(GDisplay *g) {
// As we are not using multiple displays we set g->board to NULL as we don't use it.
g->board = 0;
switch(g->controllerdisplay) {
case 0: // Set up for Display 0
palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); // UART_TX
palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7)); // UART_RX
palSetPadMode(GPIOF, GPIOF_LCD_DCX, PAL_MODE_ALTERNATE(5));
palSetPadMode(GPIOF, GPIOF_LCD_DE, PAL_MODE_ALTERNATE(14));
#define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */
#define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */
#define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */
#define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */
#define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */
#define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */
#define STM32_PLLSAIN_VALUE 192
#define STM32_PLLSAIQ_VALUE 7
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIR_POST STM32_SAIR_DIV4
/* PLLSAI activation.*/
RCC->PLLSAICFGR = (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24);
RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST;
RCC->CR |= RCC_CR_PLLSAION;
// Initialise the SDRAM
SDRAM_Init();
// Clear the SDRAM
memset((void *)SDRAM_BANK_ADDR, 0, 0x400000);
spiStart(SPI_PORT, &spi_cfg);
break;
}
}
static inline void post_init_board(GDisplay *g) {
(void) g;
}
static inline void setpin_reset(GDisplay *g, bool_t state) {
(void) g;
(void) state;
/*
if(state) {
// reset lcd
palClearPad(GPIOE, GPIOE_LCD_RST);
} else {
palSetPad(GPIOE, GPIOE_LCD_RST);
}
*/
}
static inline void set_backlight(GDisplay *g, uint8_t percent) {
(void) g;
(void) percent;
// TODO: can probably pwm this
/*
if(percent) {
// turn back light on
palSetPad(GPIOE, GPIOE_LCD_BLED);
} else {
// turn off
palClearPad(GPIOE, GPIOE_LCD_BLED);
}
*/
}
static inline void acquire_bus(GDisplay *g) {
(void) g;
spiSelect(SPI_PORT);
}
static inline void release_bus(GDisplay *g) {
(void) g;
spiUnselect(SPI_PORT);
}
static inline void write_index(GDisplay *g, uint8_t index) {
static uint8_t sindex;
(void) g;
palClearPad(DC_PORT, DC_PIN);
sindex = index;
spiSend(SPI_PORT, 1, &sindex);
}
static inline void write_data(GDisplay *g, uint8_t data) {
static uint8_t sdata;
(void) g;
palSetPad(DC_PORT, DC_PIN);
sdata = data;
spiSend(SPI_PORT, 1, &sdata);
}
#endif /* _GDISP_LLD_BOARD_H */

56
boards/base/STM32F429i-Discovery/example_chibios_2.x/Makefile 100644
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# Possible Targets: all clean Debug cleanDebug Release cleanRelease
##############################################################################################
# Settings
#
# General settings
# See $(GFXLIB)/tools/gmake_scripts/readme.txt for the list of variables
OPT_OS = chibios
OPT_THUMB = yes
OPT_LINK_OPTIMIZE = yes
OPT_CPU = stm32m4
# uGFX settings
# See $(GFXLIB)/tools/gmake_scripts/library_ugfx.mk for the list of variables
GFXLIB = ../uGFX
GFXBOARD = STM32F429i-Discovery
GFXDEMO = modules/gdisp/basics
# ChibiOS settings
ifeq ($(OPT_OS),chibios)
# See $(GFXLIB)/tools/gmake_scripts/os_chibios.mk for the list of variables
CHIBIOS = ../ChibiOS
CHIBIOS_BOARD = ST_STM32F429I_DISCOVERY
CHIBIOS_PLATFORM = STM32F4xx
CHIBIOS_PORT = GCC/ARMCMx/STM32F4xx
CHIBIOS_LDSCRIPT = STM32F407xG.ld
endif
##############################################################################################
# Set these for your project
#
ARCH = arm-none-eabi-
SRCFLAGS = -ggdb -O0
CFLAGS =
CXXFLAGS = -fno-rtti
ASFLAGS =
LDFLAGS =
SRC =
OBJS =
DEFS =
LIBS =
INCPATH =
LIBPATH =
LDSCRIPT =
##############################################################################################
# These should be at the end
#
include $(GFXLIB)/tools/gmake_scripts/library_ugfx.mk
include $(GFXLIB)/tools/gmake_scripts/os_$(OPT_OS).mk
include $(GFXLIB)/tools/gmake_scripts/compiler_gcc.mk
# *** EOF ***

531
boards/base/STM32F429i-Discovery/example_chibios_2.x/chconf.h 100644
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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/chconf.h
* @brief Configuration file template.
* @details A copy of this file must be placed in each project directory, it
* contains the application specific kernel settings.
*
* @addtogroup config
* @details Kernel related settings and hooks.
* @{
*/
#ifndef _CHCONF_H_
#define _CHCONF_H_
/*===========================================================================*/
/**
* @name Kernel parameters and options
* @{
*/
/*===========================================================================*/
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
#define CH_FREQUENCY 1000
#endif
/**
* @brief Round robin interval.
* @details This constant is the number of system ticks allowed for the
* threads before preemption occurs. Setting this value to zero
* disables the preemption for threads with equal priority and the
* round robin becomes cooperative. Note that higher priority
* threads can still preempt, the kernel is always preemptive.
*
* @note Disabling the round robin preemption makes the kernel more compact
* and generally faster.
*/
#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
#define CH_TIME_QUANTUM 20
#endif
/**
* @brief Managed RAM size.
* @details Size of the RAM area to be managed by the OS. If set to zero
* then the whole available RAM is used. The core memory is made
* available to the heap allocator and/or can be used directly through
* the simplified core memory allocator.
*
* @note In order to let the OS manage the whole RAM the linker script must
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_USE_MEMCORE.
*/
#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
#define CH_MEMCORE_SIZE 0
#endif
/**
* @brief Idle thread automatic spawn suppression.
* @details When this option is activated the function @p chSysInit()
* does not spawn the idle thread automatically. The application has
* then the responsibility to do one of the following:
* - Spawn a custom idle thread at priority @p IDLEPRIO.
* - Change the main() thread priority to @p IDLEPRIO then enter
* an endless loop. In this scenario the @p main() thread acts as
* the idle thread.
* .
* @note Unless an idle thread is spawned the @p main() thread must not
* enter a sleep state.
*/
#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
#define CH_NO_IDLE_THREAD FALSE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Performance options
* @{
*/
/*===========================================================================*/
/**
* @brief OS optimization.
* @details If enabled then time efficient rather than space efficient code
* is used when two possible implementations exist.
*
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
#define CH_OPTIMIZE_SPEED TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Subsystem options
* @{
*/
/*===========================================================================*/
/**
* @brief Threads registry APIs.
* @details If enabled then the registry APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
#define CH_USE_REGISTRY TRUE
#endif
/**
* @brief Threads synchronization APIs.
* @details If enabled then the @p chThdWait() function is included in
* the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
#define CH_USE_WAITEXIT TRUE
#endif
/**
* @brief Semaphores APIs.
* @details If enabled then the Semaphores APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES TRUE
#endif
/**
* @brief Semaphores queuing mode.
* @details If enabled then the threads are enqueued on semaphores by
* priority rather than in FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_SEMAPHORES_PRIORITY FALSE
#endif
/**
* @brief Atomic semaphore API.
* @details If enabled then the semaphores the @p chSemSignalWait() API
* is included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
#define CH_USE_SEMSW TRUE
#endif
/**
* @brief Mutexes APIs.
* @details If enabled then the mutexes APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
#define CH_USE_MUTEXES TRUE
#endif
/**
* @brief Conditional Variables APIs.
* @details If enabled then the conditional variables APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MUTEXES.
*/
#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS TRUE
#endif
/**
* @brief Conditional Variables APIs with timeout.
* @details If enabled then the conditional variables APIs with timeout
* specification are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_CONDVARS.
*/
#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_CONDVARS_TIMEOUT TRUE
#endif
/**
* @brief Events Flags APIs.
* @details If enabled then the event flags APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
#define CH_USE_EVENTS TRUE
#endif
/**
* @brief Events Flags APIs with timeout.
* @details If enabled then the events APIs with timeout specification
* are included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_EVENTS.
*/
#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
#define CH_USE_EVENTS_TIMEOUT TRUE
#endif
/**
* @brief Synchronous Messages APIs.
* @details If enabled then the synchronous messages APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES TRUE
#endif
/**
* @brief Synchronous Messages queuing mode.
* @details If enabled then messages are served by priority rather than in
* FIFO order.
*
* @note The default is @p FALSE. Enable this if you have special requirements.
* @note Requires @p CH_USE_MESSAGES.
*/
#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
#define CH_USE_MESSAGES_PRIORITY FALSE
#endif
/**
* @brief Mailboxes APIs.
* @details If enabled then the asynchronous messages (mailboxes) APIs are
* included in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_SEMAPHORES.
*/
#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
#define CH_USE_MAILBOXES TRUE
#endif
/**
* @brief I/O Queues APIs.
* @details If enabled then the I/O queues APIs are included in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
#define CH_USE_QUEUES TRUE
#endif
/**
* @brief Core Memory Manager APIs.
* @details If enabled then the core memory manager APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
#define CH_USE_MEMCORE TRUE
#endif
/**
* @brief Heap Allocator APIs.
* @details If enabled then the memory heap allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
* @p CH_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
#define CH_USE_HEAP TRUE
#endif
/**
* @brief C-runtime allocator.
* @details If enabled the the heap allocator APIs just wrap the C-runtime
* @p malloc() and @p free() functions.
*
* @note The default is @p FALSE.
* @note Requires @p CH_USE_HEAP.
* @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
* appropriate documentation.
*/
#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
#define CH_USE_MALLOC_HEAP FALSE
#endif
/**
* @brief Memory Pools Allocator APIs.
* @details If enabled then the memory pools allocator APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
*/
#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
#define CH_USE_MEMPOOLS TRUE
#endif
/**
* @brief Dynamic Threads APIs.
* @details If enabled then the dynamic threads creation APIs are included
* in the kernel.
*
* @note The default is @p TRUE.
* @note Requires @p CH_USE_WAITEXIT.
* @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
*/
#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
#define CH_USE_DYNAMIC TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Debug options
* @{
*/
/*===========================================================================*/
/**
* @brief Debug option, system state check.
* @details If enabled the correct call protocol for system APIs is checked
* at runtime.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_SYSTEM_STATE_CHECK FALSE
#endif
/**
* @brief Debug option, parameters checks.
* @details If enabled then the checks on the API functions input
* parameters are activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_CHECKS FALSE
#endif
/**
* @brief Debug option, consistency checks.
* @details If enabled then all the assertions in the kernel code are
* activated. This includes consistency checks inside the kernel,
* runtime anomalies and port-defined checks.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_ASSERTS FALSE
#endif
/**
* @brief Debug option, trace buffer.
* @details If enabled then the context switch circular trace buffer is
* activated.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_TRACE FALSE
#endif
/**
* @brief Debug option, stack checks.
* @details If enabled then a runtime stack check is performed.
*
* @note The default is @p FALSE.
* @note The stack check is performed in a architecture/port dependent way.
* It may not be implemented or some ports.
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
#define CH_DBG_ENABLE_STACK_CHECK FALSE
#endif
/**
* @brief Debug option, stacks initialization.
* @details If enabled then the threads working area is filled with a byte
* value when a thread is created. This can be useful for the
* runtime measurement of the used stack.
*
* @note The default is @p FALSE.
*/
#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
#define CH_DBG_FILL_THREADS FALSE
#endif
/**
* @brief Debug option, threads profiling.
* @details If enabled then a field is added to the @p Thread structure that
* counts the system ticks occurred while executing the thread.
*
* @note The default is @p TRUE.
* @note This debug option is defaulted to TRUE because it is required by
* some test cases into the test suite.
*/
#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
#define CH_DBG_THREADS_PROFILING TRUE
#endif
/** @} */
/*===========================================================================*/
/**
* @name Kernel hooks
* @{
*/
/*===========================================================================*/
/**
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p Thread structure.
*/
#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
#define THREAD_EXT_FIELDS \
/* Add threads custom fields here.*/
#endif
/**
* @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
* @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_INIT_HOOK(tp) { \
/* Add threads initialization code here.*/ \
}
#endif
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*
* @note It is inserted into lock zone.
* @note It is also invoked when the threads simply return in order to
* terminate.
*/
#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
#define THREAD_EXT_EXIT_HOOK(tp) { \
/* Add threads finalization code here.*/ \
}
#endif
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \
/* System halt code here.*/ \
}
#endif
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
#define IDLE_LOOP_HOOK() { \
/* Idle loop code here.*/ \
}
#endif
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_TICK_EVENT_HOOK() { \
/* System tick event code here.*/ \
}
#endif
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
#define SYSTEM_HALT_HOOK() { \
/* System halt code here.*/ \
}
#endif
/** @} */
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
#endif /* _CHCONF_H_ */
/** @} */

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boards/base/STM32F429i-Discovery/example_chibios_2.x/halconf.h 100644
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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file templates/halconf.h
* @brief HAL configuration header.
* @details HAL configuration file, this file allows to enable or disable the
* various device drivers from your application. You may also use
* this file in order to override the device drivers default settings.
*
* @addtogroup HAL_CONF
* @{
*/
#ifndef _HALCONF_H_
#define _HALCONF_H_
#include "mcuconf.h"
/**
* @brief Enables the TM subsystem.
*/
#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
#define HAL_USE_TM FALSE
#endif
/**
* @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
#define HAL_USE_PAL TRUE
#endif
/**
* @brief Enables the ADC subsystem.
*/
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
#define HAL_USE_ADC FALSE
#endif
/**
* @brief Enables the CAN subsystem.
*/
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
#define HAL_USE_CAN FALSE
#endif
/**
* @brief Enables the EXT subsystem.
*/
#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
#define HAL_USE_EXT FALSE
#endif
/**
* @brief Enables the GPT subsystem.
*/
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
#define HAL_USE_GPT FALSE
#endif
/**
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#define HAL_USE_I2C FALSE
#endif
/**
* @brief Enables the ICU subsystem.
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#define HAL_USE_ICU FALSE
#endif
/**
* @brief Enables the MAC subsystem.
*/
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
#define HAL_USE_MAC FALSE
#endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
#define HAL_USE_MMC_SPI FALSE
#endif
/**
* @brief Enables the PWM subsystem.
*/
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
#define HAL_USE_PWM FALSE
#endif
/**
* @brief Enables the RTC subsystem.
*/
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
#define HAL_USE_RTC FALSE
#endif
/**
* @brief Enables the SDC subsystem.
*/
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
#define HAL_USE_SDC FALSE
#endif
/**
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL FALSE
#endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#endif
/**
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI TRUE
#endif
/**
* @brief Enables the UART subsystem.
*/
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
#define HAL_USE_UART FALSE
#endif
/**
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB FALSE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
#define ADC_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define ADC_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* CAN driver related settings. */
/*===========================================================================*/
/**
* @brief Sleep mode related APIs inclusion switch.
*/
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
#define CAN_USE_SLEEP_MODE TRUE
#endif
/*===========================================================================*/
/* I2C driver related settings. */
/*===========================================================================*/
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define I2C_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* MAC driver related settings. */
/*===========================================================================*/
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
#define MAC_USE_ZERO_COPY FALSE
#endif
/**
* @brief Enables an event sources for incoming packets.
*/
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
#define MAC_USE_EVENTS TRUE
#endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
#define MMC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SDC driver related settings. */
/*===========================================================================*/
/**
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
#endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
#define SDC_MMC_SUPPORT FALSE
#endif
/**
* @brief Delays insertions.
* @details If enabled this options inserts delays into the MMC waiting
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
#define SDC_NICE_WAITING TRUE
#endif
/*===========================================================================*/
/* SERIAL driver related settings. */
/*===========================================================================*/
/**
* @brief Default bit rate.
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
* @brief Serial buffers size.
* @details Configuration parameter, you can change the depth of the queue
* buffers depending on the requirements of your application.
* @note The default is 64 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_BUFFERS_SIZE 16
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
#define SPI_USE_WAIT TRUE
#endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
#endif /* _HALCONF_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F4xx_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 8
#define STM32_PLLN_VALUE 336
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 7
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_RTCSEL STM32_RTCSEL_LSI
#define STM32_RTCPRE_VALUE 8
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
#define STM32_I2SSRC STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
/*
* CAN driver system settings.
*/
#define STM32_CAN_USE_CAN1 FALSE
#define STM32_CAN_USE_CAN2 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
/*
* EXT driver system settings.
*/
#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM6 FALSE
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM11 FALSE
#define STM32_GPT_USE_TIM12 FALSE
#define STM32_GPT_USE_TIM14 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
#define STM32_GPT_TIM6_IRQ_PRIORITY 7
#define STM32_GPT_TIM7_IRQ_PRIORITY 7
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
#define STM32_GPT_TIM9_IRQ_PRIORITY 7
#define STM32_GPT_TIM11_IRQ_PRIORITY 7
#define STM32_GPT_TIM12_IRQ_PRIORITY 7
#define STM32_GPT_TIM14_IRQ_PRIORITY 7
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C2 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt()
#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt()
#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt()
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#define STM32_ICU_USE_TIM5 FALSE
#define STM32_ICU_USE_TIM8 FALSE
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
#define STM32_ICU_TIM9_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#define STM32_PWM_USE_TIM2 FALSE
#define STM32_PWM_USE_TIM3 FALSE
#define STM32_PWM_USE_TIM4 FALSE
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
#define STM32_PWM_TIM9_IRQ_PRIORITY 7
/*
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_USART3 FALSE
#define STM32_SERIAL_USE_UART4 FALSE
#define STM32_SERIAL_USE_UART5 FALSE
#define STM32_SERIAL_USE_USART6 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART3_PRIORITY 12
#define STM32_SERIAL_UART4_PRIORITY 12
#define STM32_SERIAL_UART5_PRIORITY 12
#define STM32_SERIAL_USART6_PRIORITY 12
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_USE_SPI4 FALSE
#define STM32_SPI_USE_SPI5 TRUE
#define STM32_SPI_USE_SPI6 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI4_DMA_PRIORITY 1
#define STM32_SPI_SPI5_DMA_PRIORITY 1
#define STM32_SPI_SPI6_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_SPI4_IRQ_PRIORITY 10
#define STM32_SPI_SPI5_IRQ_PRIORITY 10
#define STM32_SPI_SPI6_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_USART3 FALSE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
/*
* USB driver system settings.
*/
#define STM32_USB_USE_OTG1 FALSE
#define STM32_USB_USE_OTG2 TRUE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG2_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
#define STM32_USB_OTG_THREAD_STACK_SIZE 128
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0

81
boards/base/STM32F429i-Discovery/example_chibios_2.x/openocd.cfg 100644
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@ -0,0 +1,81 @@
# This is a script file for OpenOCD 0.7.0
#
# It is set up for the Mikromedia-STM32M4 board using the ST-Link JTAG adaptor.
#
# Assuming the current directory is your project directory containing this openocd.cfg file...
#
# To program your device:
#
# openocd -f openocd.cfg -c "Burn yourfile.bin" -c shutdown
#
# To debug your device:
#
# openocd
# (This will run openocd in gdb server debug mode. Leave it running in the background)
#
# gdb yourfile.elf
# (To start gdb. Then run the following commands in gdb...)
#
# target remote 127.0.0.1:3333
# monitor Debug
# stepi
# (This last stepi resynchronizes gdb).
#
# If you want to reprogram from within gdb:
#
# monitor Burn yourfile.bin
#
echo ""
echo "##### Loading debugger..."
source [find interface/stlink-v2.cfg]
echo ""
echo "##### Loading CPU..."
source [find target/stm32f4x_stlink.cfg]
echo ""
echo "##### Configuring..."
reset_config srst_only srst_nogate
#cortex_m maskisr (auto|on|off)
#cortex_m vector_catch [all|none|list]
#cortex_m reset_config (srst|sysresetreq|vectreset)
#gdb_breakpoint_override hard
proc Debug { } {
echo ""
echo "##### Debug Session Connected..."
reset init
echo "Ready..."
}
proc Burn {file} {
echo ""
echo "##### Burning $file to device..."
halt
# Due to an issue with the combination of the ST-Link adapters and OpenOCD
# applying the stm32f2x unlock 0 command actaully applies read protection - VERY BAD!
# If this happens to you - use the ST-Link utility to set the option byte back to normal.
# If you are using a different debugger eg a FT2232 based adapter you can uncomment the line below.
#stm32f2x unlock 0
flash protect 0 0 last off
reset init
flash write_image erase $file 0x08000000
verify_image $file 0x0
#flash protect 0 0 last on
reset
echo "Burning Complete!"
}
echo ""
echo "##### Leaving Configuration Mode..."
init
reset init
flash probe 0
flash banks
#flash info 0
echo ""
echo "##### Waiting for debug connections..."

332
boards/base/STM32F429i-Discovery/stm32f429i_discovery_sdram.c 100644
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#include "stm32f429i_discovery_sdram.h"
#include "stm32f4xx_fmc.h"
#include "ch.h"
#include "hal.h"
/**
* @brief Configures the FMC and GPIOs to interface with the SDRAM memory.
* This function must be called before any read/write operation
* on the SDRAM.
* @param None
* @retval None
*/
void SDRAM_Init(void)
{
FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure;
FMC_SDRAMTimingInitTypeDef FMC_SDRAMTimingInitStructure;
/* Enable FMC clock */
rccEnableAHB3(RCC_AHB3ENR_FMCEN, FALSE);
/* FMC Configuration ---------------------------------------------------------*/
/* FMC SDRAM Bank configuration */
/* Timing configuration for 84 Mhz of SD clock frequency (168Mhz/2) */
/* TMRD: 2 Clock cycles */
FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;
/* TXSR: min=70ns (6x11.90ns) */
FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 7;
/* TRAS: min=42ns (4x11.90ns) max=120k (ns) */
FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;
/* TRC: min=63 (6x11.90ns) */
FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 7;
/* TWR: 2 Clock cycles */
FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;
/* TRP: 15ns => 2x11.90ns */
FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;
/* TRCD: 15ns => 2x11.90ns */
FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;
/* FMC SDRAM control configuration */
FMC_SDRAMInitStructure.FMC_Bank = FMC_Bank2_SDRAM;
/* Row addressing: [7:0] */
FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
/* Column addressing: [11:0] */
FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_12b;
FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = SDRAM_MEMORY_WIDTH;
FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
FMC_SDRAMInitStructure.FMC_CASLatency = SDRAM_CAS_LATENCY;
FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
FMC_SDRAMInitStructure.FMC_SDClockPeriod = SDCLOCK_PERIOD;
FMC_SDRAMInitStructure.FMC_ReadBurst = SDRAM_READBURST;
FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;
FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
/* FMC SDRAM bank initialization */
FMC_SDRAMInit(&FMC_SDRAMInitStructure);
/* FMC SDRAM device initialization sequence */
SDRAM_InitSequence();
}
/*-- GPIOs Configuration -----------------------------------------------------*/
/*
+-------------------+--------------------+--------------------+--------------------+
+ SDRAM pins assignment +
+-------------------+--------------------+--------------------+--------------------+
| PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 |
| PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 |
| PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF2 <-> FMC_A2 | PG8 <-> FMC_SDCLK |
| PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF3 <-> FMC_A3 | PG15 <-> FMC_NCAS |
| PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF4 <-> FMC_A4 |--------------------+
| PD14 <-> FMC_D0 | PE10 <-> FMC_D7 | PF5 <-> FMC_A5 |
| PD15 <-> FMC_D1 | PE11 <-> FMC_D8 | PF11 <-> FMC_NRAS |
+-------------------| PE12 <-> FMC_D9 | PF12 <-> FMC_A6 |
| PE13 <-> FMC_D10 | PF13 <-> FMC_A7 |
| PE14 <-> FMC_D11 | PF14 <-> FMC_A8 |
| PE15 <-> FMC_D12 | PF15 <-> FMC_A9 |
+-------------------+--------------------+--------------------+
| PB5 <-> FMC_SDCKE1|
| PB6 <-> FMC_SDNE1 |
| PC0 <-> FMC_SDNWE |
+-------------------+
*/
// /* Common GPIO configuration */
// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
// GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
// GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
//
// /* GPIOB configuration */
// GPIO_PinAFConfig(GPIOB, GPIO_PinSource5 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOB, GPIO_PinSource6 , GPIO_AF_FMC);
//
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6;
//
// GPIO_Init(GPIOB, &GPIO_InitStructure);
//
// /* GPIOC configuration */
// GPIO_PinAFConfig(GPIOC, GPIO_PinSource0 , GPIO_AF_FMC);
//
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
//
// GPIO_Init(GPIOC, &GPIO_InitStructure);
//
// /* GPIOD configuration */
// GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FMC);
//
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 |
// GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 |
// GPIO_Pin_15;
//
// GPIO_Init(GPIOD, &GPIO_InitStructure);
//
// /* GPIOE configuration */
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource0 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource1 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FMC);
//
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_7 |
// GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
// GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
// GPIO_Pin_14 | GPIO_Pin_15;
//
// GPIO_Init(GPIOE, &GPIO_InitStructure);
//
// /* GPIOF configuration */
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource0 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource1 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource2 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource3 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource4 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource5 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource11 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource12 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource13 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource14 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOF, GPIO_PinSource15 , GPIO_AF_FMC);
//
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 |
// GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 |
// GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
// GPIO_Pin_14 | GPIO_Pin_15;
//
// GPIO_Init(GPIOF, &GPIO_InitStructure);
//
// /* GPIOG configuration */
// GPIO_PinAFConfig(GPIOG, GPIO_PinSource0 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOG, GPIO_PinSource1 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOG, GPIO_PinSource4 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOG, GPIO_PinSource5 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOG, GPIO_PinSource8 , GPIO_AF_FMC);
// GPIO_PinAFConfig(GPIOG, GPIO_PinSource15 , GPIO_AF_FMC);
//
//
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 |
// GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_15;
//
// GPIO_Init(GPIOG, &GPIO_InitStructure);
/**
* @brief Executes the SDRAM memory initialization sequence.
* @param None.
* @retval None.
*/
void SDRAM_InitSequence(void)
{
FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
uint32_t tmpr = 0;
/* Step 3 --------------------------------------------------------------------*/
/* Configure a clock configuration enable command */
FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled;
FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
/* Send the command */
FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
//In the ST example, this is 100ms, but the 429 RM says 100us is typical, and
//the ISSI datasheet confirms this. 1ms seems plenty, and is much shorter than
//refresh interval, meaning we won't risk losing contents if the SDRAM is in self-refresh
//mode
/* Step 4 --------------------------------------------------------------------*/
/* Insert 1 ms delay */
chThdSleepMilliseconds(1);
/* Step 5 --------------------------------------------------------------------*/
/* Configure a PALL (precharge all) command */
FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL;
FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
/* Send the command */
FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
/* Step 6 --------------------------------------------------------------------*/
/* Configure a Auto-Refresh command */
FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh;
FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 4;
FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
/* Send the first command */
FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
/* Send the second command */
FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
/* Step 7 --------------------------------------------------------------------*/
/* Program the external memory mode register */
tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 |
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
SDRAM_MODEREG_CAS_LATENCY_3 |
SDRAM_MODEREG_OPERATING_MODE_STANDARD |
SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
/* Configure a load Mode register command*/
FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode;
FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr;
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
/* Send the command */
FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
/* Step 8 --------------------------------------------------------------------*/
/* Set the refresh rate counter */
/* (7.81 us x Freq) - 20 */
/* Set the device refresh counter */
FMC_SetRefreshCount(683);
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
}
/**
* @brief Writes a Entire-word buffer to the SDRAM memory.
* @param pBuffer: pointer to buffer.
* @param uwWriteAddress: SDRAM memory internal address from which the data will be
* written.
* @param uwBufferSize: number of words to write.
* @retval None.
*/
void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize)
{
__IO uint32_t write_pointer = (uint32_t)uwWriteAddress;
/* Disable write protection */
FMC_SDRAMWriteProtectionConfig(FMC_Bank2_SDRAM, DISABLE);
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
/* While there is data to write */
for (; uwBufferSize != 0; uwBufferSize--)
{
/* Transfer data to the memory */
*(uint32_t *) (SDRAM_BANK_ADDR + write_pointer) = *pBuffer++;
/* Increment the address*/
write_pointer += 4;
}
}
/**
* @brief Reads data buffer from the SDRAM memory.
* @param pBuffer: pointer to buffer.
* @param ReadAddress: SDRAM memory internal address from which the data will be
* read.
* @param uwBufferSize: number of words to write.
* @retval None.
*/
void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize)
{
__IO uint32_t write_pointer = (uint32_t)uwReadAddress;
/* Wait until the SDRAM controller is ready */
while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
{
}
/* Read data */
for(; uwBufferSize != 0x00; uwBufferSize--)
{
*pBuffer++ = *(__IO uint32_t *)(SDRAM_BANK_ADDR + write_pointer );
/* Increment the address*/
write_pointer += 4;
}
}

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boards/base/STM32F429i-Discovery/stm32f429i_discovery_sdram.h 100644
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/**
******************************************************************************
* @file stm32f429i_discovery_sdram.h
* @author MCD Application Team
* @version V1.0.0
* @date 20-September-2013
* @brief This file contains all the functions prototypes for the
* stm324x9i_disco_sdram.c driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32429I_DISCO_SDRAM_H
#define __STM32429I_DISCO_SDRAM_H
#ifdef __cplusplus
extern "C" {
#endif
//FIXME this should not be needed
#define STM32F429_439xx
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"
/**
* @brief FMC SDRAM Bank address
*/
#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000)
/**
* @brief FMC SDRAM Memory Width
*/
/* #define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_8b */
#define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_16b
/**
* @brief FMC SDRAM CAS Latency
*/
/* #define SDRAM_CAS_LATENCY FMC_CAS_Latency_2 */
#define SDRAM_CAS_LATENCY FMC_CAS_Latency_3
/**
* @brief FMC SDRAM Memory clock period
*/
#define SDCLOCK_PERIOD FMC_SDClock_Period_2 /* Default configuration used with LCD */
/* #define SDCLOCK_PERIOD FMC_SDClock_Period_3 */
/**
* @brief FMC SDRAM Memory Read Burst feature
*/
#define SDRAM_READBURST FMC_Read_Burst_Disable /* Default configuration used with LCD */
/* #define SDRAM_READBURST FMC_Read_Burst_Enable */
/**
* @brief FMC SDRAM Mode definition register defines
*/
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
void SDRAM_Init(void);
void SDRAM_InitSequence(void);
void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize);
void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize);
#ifdef __cplusplus
}
#endif
#endif

1376
boards/base/STM32F429i-Discovery/stm32f4xx_fmc.c 100644
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File diff suppressed because it is too large Load Diff

1140
boards/base/STM32F429i-Discovery/stm32f4xx_fmc.h 100644
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File diff suppressed because it is too large Load Diff

66
drivers/gdisp/STM32F429iDiscovery/board_STM32F429iDiscovery_template.h 100644
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/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.org/license.html
*/
#ifndef _GDISP_LLD_BOARD_H
#define _GDISP_LLD_BOARD_H
static const ltdcConfig driverCfg = {
240, 320,
10, 2,
20, 2,
10, 4,
0,
0x000000,
{
(LLDCOLOR_TYPE *)SDRAM_BANK_ADDR, // frame
240, 320, // width, height
240 * LTDC_PIXELBYTES, // pitch
LTDC_PIXELFORMAT, // fmt
0, 0, // x, y
240, 320, // cx, cy
LTDC_COLOR_FUCHSIA, // defcolor
0x980088, // keycolor
LTDC_BLEND_FIX1_FIX2, // blending
0, // palette
0, // palettelen
0xFF, // alpha
LTDC_LEF_ENABLE // flags
},
LTDC_UNUSED_LAYER_CONFIG
};
static inline void init_board(GDisplay *g) {
// As we are not using multiple displays we set g->board to NULL as we don't use it.
g->board = 0;
switch(g->controllerdisplay) {
case 0: // Set up for Display 0
// Your init here
break;
}
}
static inline void post_init_board(GDisplay *g) {
}
static inline void set_backlight(GDisplay *g, uint8_t percent) {
}
static inline void acquire_bus(GDisplay *g) {
}
static inline void release_bus(GDisplay *g) {
}
static inline void write_index(GDisplay *g, uint8_t index) {
}
static inline void write_data(GDisplay *g, uint8_t data) {
}
#endif /* _GDISP_LLD_BOARD_H */

2
drivers/gdisp/STM32F429iDiscovery/driver.mk 100644
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GFXINC += $(GFXLIB)/drivers/gdisp/STM32F429iDiscovery
GFXSRC += $(GFXLIB)/drivers/gdisp/STM32F429iDiscovery/gdisp_lld_STM32F429iDiscovery.c

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drivers/gdisp/STM32F429iDiscovery/gdisp_lld_STM32F429iDiscovery.c 100644
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/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.org/license.html
*/
#include "gfx.h"
#if GFX_USE_GDISP
#if defined(GDISP_SCREEN_HEIGHT)
#warning "GDISP: This low level driver does not support setting a screen size. It is being ignored."
#undef GISP_SCREEN_HEIGHT
#endif
#if defined(GDISP_SCREEN_WIDTH)
#warning "GDISP: This low level driver does not support setting a screen size. It is being ignored."
#undef GDISP_SCREEN_WIDTH
#endif
#define GDISP_DRIVER_VMT GDISPVMT_STM32F429iDiscovery
#include "drivers/gdisp/STM32F429iDiscovery/gdisp_lld_config.h"
#include "src/gdisp/driver.h"
#include "stm32_ltdc.h"
typedef struct ltdcLayerConfig {
// frame
LLDCOLOR_TYPE *frame; // Frame buffer address
coord_t width, height; // Frame size in pixels
coord_t pitch; // Line pitch, in bytes
ltdc_pixfmt_t fmt; // Pixel format in LTDC format
// window
coord_t x, y; // Start pixel position of the virtual layer
coord_t cx, cy; // Size of the virtual layer
uint32_t defcolor; // Default color, ARGB8888
uint32_t keycolor; // Color key, RGB888
uint32_t blending; // Blending factors
const uint32_t *palette; // The palette, RGB888 (can be NULL)
uint16_t palettelen; // Palette length
uint8_t alpha; // Constant alpha factor
uint8_t layerflags; // Layer configuration
} ltdcLayerConfig;
#define LTDC_UNUSED_LAYER_CONFIG { 0, 1, 1, 1, LTDC_FMT_L8, 0, 0, 1, 1, 0x000000, 0x000000, LTDC_BLEND_FIX1_FIX2, 0, 0, 0, 0 }
typedef struct ltdcConfig {
coord_t width, height; // Screen size
coord_t hsync, vsync; // Horizontal and Vertical sync pixels
coord_t hbackporch, vbackporch; // Horizontal and Vertical back porch pixels
coord_t hfrontporch, vfrontporch; // Horizontal and Vertical front porch pixels
uint8_t syncflags; // Sync flags
uint32_t bgcolor; // Clear screen color RGB888
ltdcLayerConfig bglayer; // Background layer config
ltdcLayerConfig fglayer; // Foreground layer config
} ltdcConfig;
#if GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB565
#define LTDC_PIXELFORMAT LTDC_FMT_RGB565
#define LTDC_PIXELBYTES 2
#define LTDC_PIXELBITS 16
#elif GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB888
#define LTDC_PIXELFORMAT LTDC_FMT_RGB888
#define LTDC_PIXELBYTES 3
#define LTDC_PIXELBITS 24
#else
#error "GDISP: STM32F4iDiscovery - unsupported pixel format"
#endif
#include "board_STM32F429iDiscovery.h"
#include "ili9341.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
#ifndef GDISP_INITIAL_CONTRAST
#define GDISP_INITIAL_CONTRAST 50
#endif
#ifndef GDISP_INITIAL_BACKLIGHT
#define GDISP_INITIAL_BACKLIGHT 100
#endif
/*===========================================================================*/
/* Driver local routines . */
/*===========================================================================*/
#define PIXIL_POS(g, x, y) ((y) * driverCfg.bglayer.pitch + (x) * LTDC_PIXELBYTES)
#define PIXEL_ADDR(g, pos) ((LLDCOLOR_TYPE *)((uint8_t *)driverCfg.bglayer.frame+pos))
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
static void InitController(GDisplay *g) {
#define REG_TYPEMASK 0xFF00
#define REG_DATAMASK 0x00FF
#define REG_DATA 0x0000
#define REG_COMMAND 0x0100
#define REG_DELAY 0x0200
static const uint16_t initdata[] = {
REG_COMMAND | ILI9341_CMD_RESET,
REG_DELAY | 5,
REG_COMMAND | ILI9341_CMD_DISPLAY_OFF,
REG_COMMAND | ILI9341_SET_FRAME_CTL_NORMAL, 0x00, 0x1B,
REG_COMMAND | ILI9341_SET_FUNCTION_CTL, 0x0A, 0xA2,
REG_COMMAND | ILI9341_SET_POWER_CTL_1, 0x10,
REG_COMMAND | ILI9341_SET_POWER_CTL_2, 0x10,
REG_COMMAND | ILI9341_SET_VCOM_CTL_1, 0x45, 0x15,
REG_COMMAND | ILI9341_SET_VCOM_CTL_2, 0x90,
REG_COMMAND | ILI9341_SET_MEM_ACS_CTL, 0xC8,
REG_COMMAND | ILI9341_SET_RGB_IF_SIG_CTL, 0xC2,
REG_COMMAND | ILI9341_SET_FUNCTION_CTL, 0x0A, 0xA7, 0x27, 0x04,
REG_COMMAND | ILI9341_SET_COL_ADDR, 0x00, 0x00, 0x00, 0xEF,
REG_COMMAND | ILI9341_SET_PAGE_ADDR, 0x00, 0x00, 0x01, 0x3F,
REG_COMMAND | ILI9341_SET_IF_CTL, 0x01, 0x00, 0x06,
REG_COMMAND | ILI9341_SET_GAMMA, 0x01,
REG_COMMAND | ILI9341_SET_PGAMMA,
0x0F, 0x29, 0x24, 0x0C, 0x0E, 0x09, 0x4E, 0x78,
0x3C, 0x09, 0x13, 0x05, 0x17, 0x11, 0x00,
REG_COMMAND | ILI9341_SET_NGAMMA,
0x00, 0x16, 0x1B, 0x04, 0x11, 0x07, 0x31, 0x33,
0x42, 0x05, 0x0C, 0x0A, 0x28, 0x2F, 0x0F,
REG_COMMAND | ILI9341_CMD_SLEEP_OFF,
REG_DELAY | 10,
REG_COMMAND | ILI9341_CMD_DISPLAY_ON,
REG_COMMAND | ILI9341_SET_MEM
};
const uint16_t *p;
acquire_bus(g);
for(p = initdata; p < &initdata[sizeof(initdata)/sizeof(initdata[0])]; p++) {
switch(*p & REG_TYPEMASK) {
case REG_DATA: write_data(g, *p); break;
case REG_COMMAND: write_index(g, *p); break;
case REG_DELAY: gfxSleepMilliseconds(*p & 0xFF); break;
}
}
release_bus(g);
}
static void LTDC_Reload(void) {
LTDC->SRCR |= LTDC_SRCR_IMR;
while (LTDC->SRCR & (LTDC_SRCR_IMR | LTDC_SRCR_VBR))
gfxYield();
}
static void LTDC_LayerInit(LTDC_Layer_TypeDef *pLayReg, const ltdcLayerConfig * pCfg) {
static const uint8_t fmt2Bpp[] = {
4, /* LTDC_FMT_ARGB8888 */
3, /* LTDC_FMT_RGB888 */
2, /* LTDC_FMT_RGB565 */
2, /* LTDC_FMT_ARGB1555 */
2, /* LTDC_FMT_ARGB4444 */
1, /* LTDC_FMT_L8 */
1, /* LTDC_FMT_AL44 */
2 /* LTDC_FMT_AL88 */
};
uint32_t start, stop;
// Set the framebuffer dimensions and format
pLayReg->PFCR = (pLayReg->PFCR & ~LTDC_LxPFCR_PF) | ((uint32_t)pCfg->fmt & LTDC_LxPFCR_PF);
pLayReg->CFBAR = (uint32_t)pCfg->frame & LTDC_LxCFBAR_CFBADD;
pLayReg->CFBLR = ((((uint32_t)pCfg->pitch << 16) & LTDC_LxCFBLR_CFBP) | (((uint32_t)fmt2Bpp[pCfg->fmt] * pCfg->width + 3) & LTDC_LxCFBLR_CFBLL));
pLayReg->CFBLNR = (uint32_t)pCfg->height & LTDC_LxCFBLNR_CFBLNBR;
// Set the display window boundaries
start = (uint32_t)pCfg->x + driverCfg.hsync + driverCfg.hbackporch;
stop = start + pCfg->cx - 1;
pLayReg->WHPCR = ((start << 0) & LTDC_LxWHPCR_WHSTPOS) | ((stop << 16) & LTDC_LxWHPCR_WHSPPOS);
start = (uint32_t)pCfg->y + driverCfg.vsync + driverCfg.vbackporch;
stop = start + pCfg->cy - 1;
pLayReg->WVPCR = ((start << 0) & LTDC_LxWVPCR_WVSTPOS) | ((stop << 16) & LTDC_LxWVPCR_WVSPPOS);
// Set colors
pLayReg->DCCR = pCfg->defcolor;
pLayReg->CKCR = (pLayReg->CKCR & ~0x00FFFFFF) | (pCfg->keycolor & 0x00FFFFFF);
pLayReg->CACR = (pLayReg->CACR & ~LTDC_LxCACR_CONSTA) | ((uint32_t)pCfg->alpha & LTDC_LxCACR_CONSTA);
pLayReg->BFCR = (pLayReg->BFCR & ~(LTDC_LxBFCR_BF1 | LTDC_LxBFCR_BF2)) | ((uint32_t)pCfg->blending & (LTDC_LxBFCR_BF1 | LTDC_LxBFCR_BF2));
for (start = 0; start < pCfg->palettelen; start++)
pLayReg->CLUTWR = ((uint32_t)start << 24) | (pCfg->palette[start] & 0x00FFFFFF);
// Final flags
pLayReg->CR = (pLayReg->CR & ~LTDC_LEF_MASK) | ((uint32_t)pCfg->layerflags & LTDC_LEF_MASK);
}
static void LTDC_Init(void) {
// Set up the display scanning
uint32_t hacc, vacc;
/* Reset the LTDC hardware module.*/
RCC->APB2RSTR |= RCC_APB2RSTR_LTDCRST;
RCC->APB2RSTR = 0;
/* Enable the LTDC clock.*/
RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | (2 << 16); /* /8 */
// Enable the module
RCC->APB2ENR |= RCC_APB2ENR_LTDCEN;
// Turn off the controller and its interrupts.
LTDC->GCR = 0;
LTDC->IER = 0;
LTDC_Reload();
// Set synchronization params
hacc = driverCfg.hsync - 1;
vacc = driverCfg.vsync - 1;
LTDC->SSCR = ((hacc << 16) & LTDC_SSCR_HSW) | ((vacc << 0) & LTDC_SSCR_VSH);
// Set accumulated back porch params
hacc += driverCfg.hbackporch;
vacc += driverCfg.vbackporch;
LTDC->BPCR = ((hacc << 16) & LTDC_BPCR_AHBP) | ((vacc << 0) & LTDC_BPCR_AVBP);
// Set accumulated active params
hacc += driverCfg.width;
vacc += driverCfg.height;
LTDC->AWCR = ((hacc << 16) & LTDC_AWCR_AAW) | ((vacc << 0) & LTDC_AWCR_AAH);
// Set accumulated total params
hacc += driverCfg.hfrontporch;
vacc += driverCfg.vfrontporch;
LTDC->TWCR = ((hacc << 16) & LTDC_TWCR_TOTALW) | ((vacc << 0) & LTDC_TWCR_TOTALH);
// Set signal polarities and other flags
LTDC->GCR = driverCfg.syncflags & (LTDC_EF_MASK & ~LTDC_EF_ENABLE);
// Set background color
LTDC->BCCR = (LTDC->BCCR & ~0x00FFFFFF) | (driverCfg.bgcolor & 0x00FFFFFF);
// Load the background layer
LTDC_LayerInit(LTDC_Layer1, &driverCfg.bglayer);
// Load the foreground layer
LTDC_LayerInit(LTDC_Layer2, &driverCfg.fglayer);
// Interrupt handling
//nvicEnableVector(STM32_LTDC_EV_NUMBER, CORTEX_PRIORITY_MASK(STM32_LTDC_EV_IRQ_PRIORITY));
//nvicEnableVector(STM32_LTDC_ER_NUMBER, CORTEX_PRIORITY_MASK(STM32_LTDC_ER_IRQ_PRIORITY));
// Possible flags - LTDC_IER_RRIE, LTDC_IER_LIE, LTDC_IER_FUIE, LTDC_IER_TERRIE etc
LTDC->IER = 0;
// Set everything going
LTDC_Reload();
LTDC->GCR |= LTDC_GCR_LTDCEN;
LTDC_Reload();
}
LLDSPEC bool_t gdisp_lld_init(GDisplay *g) {
// Initialize the private structure
g->priv = 0;
g->board = 0;
//if (!(g->priv = gfxAlloc(sizeof(fbPriv))))
// gfxHalt("GDISP Framebuffer: Failed to allocate private memory");
// Init the board
init_board(g);
//((fbPriv *)g->priv)->fbi.cfg = init_board(g);
// Initialise the ILI9341 controller
InitController(g);
// Initialise the LTDC controller
LTDC_Init();
// Initialise DMA2D
//dma2dStart(&DMA2DD1, &dma2d_cfg);
//dma2d_test();
// Finish Init the board
post_init_board(g);
/* Turn on the back-light */
set_backlight(g, GDISP_INITIAL_BACKLIGHT);
/* Initialise the GDISP structure */
g->g.Width = driverCfg.bglayer.width;
g->g.Height = driverCfg.bglayer.height;
g->g.Orientation = GDISP_ROTATE_0;
g->g.Powermode = powerOn;
g->g.Backlight = GDISP_INITIAL_BACKLIGHT;
g->g.Contrast = GDISP_INITIAL_CONTRAST;
return TRUE;
}
LLDSPEC void gdisp_lld_draw_pixel(GDisplay *g) {
unsigned pos;
#if GDISP_NEED_CONTROL
switch(g->g.Orientation) {
case GDISP_ROTATE_0:
default:
pos = PIXIL_POS(g, g->p.x, g->p.y);
break;
case GDISP_ROTATE_90:
pos = PIXIL_POS(g, g->p.y, g->g.Width-g->p.x-1);
break;
case GDISP_ROTATE_180:
pos = PIXIL_POS(g, g->g.Width-g->p.x-1, g->g.Height-g->p.y-1);
break;
case GDISP_ROTATE_270:
pos = PIXIL_POS(g, g->g.Height-g->p.y-1, g->p.x);
break;
}
#else
pos = PIXIL_POS(g, g->p.x, g->p.y);
#endif
PIXEL_ADDR(g, pos)[0] = gdispColor2Native(g->p.color);
}
LLDSPEC color_t gdisp_lld_get_pixel_color(GDisplay *g) {
unsigned pos;
LLDCOLOR_TYPE color;
#if GDISP_NEED_CONTROL
switch(g->g.Orientation) {
case GDISP_ROTATE_0:
default:
pos = PIXIL_POS(g, g->p.x, g->p.y);
break;
case GDISP_ROTATE_90:
pos = PIXIL_POS(g, g->p.y, g->g.Width-g->p.x-1);
break;
case GDISP_ROTATE_180:
pos = PIXIL_POS(g, g->g.Width-g->p.x-1, g->g.Height-g->p.y-1);
break;
case GDISP_ROTATE_270:
pos = PIXIL_POS(g, g->g.Height-g->p.y-1, g->p.x);
break;
}
#else
pos = PIXIL_POS(g, g->p.x, g->p.y);
#endif
color = PIXEL_ADDR(g, pos)[0];
return gdispNative2Color(color);
}
#if GDISP_NEED_CONTROL
LLDSPEC void gdisp_lld_control(GDisplay *g) {
switch(g->p.x) {
case GDISP_CONTROL_POWER:
if (g->g.Powermode == (powermode_t)g->p.ptr)
return;
switch((powermode_t)g->p.ptr) {
case powerOff: case powerOn: case powerSleep: case powerDeepSleep:
board_power(g, (powermode_t)g->p.ptr);
break;
default:
return;
}
g->g.Powermode = (powermode_t)g->p.ptr;
return;
case GDISP_CONTROL_ORIENTATION:
if (g->g.Orientation == (orientation_t)g->p.ptr)
return;
switch((orientation_t)g->p.ptr) {
case GDISP_ROTATE_0:
case GDISP_ROTATE_180:
if (g->g.Orientation == GDISP_ROTATE_90 || g->g.Orientation == GDISP_ROTATE_270) {
coord_t tmp;
tmp = g->g.Width;
g->g.Width = g->g.Height;
g->g.Height = tmp;
}
break;
case GDISP_ROTATE_90:
case GDISP_ROTATE_270:
if (g->g.Orientation == GDISP_ROTATE_0 || g->g.Orientation == GDISP_ROTATE_180) {
coord_t tmp;
tmp = g->g.Width;
g->g.Width = g->g.Height;
g->g.Height = tmp;
}
break;
default:
return;
}
g->g.Orientation = (orientation_t)g->p.ptr;
return;
case GDISP_CONTROL_BACKLIGHT:
if ((unsigned)g->p.ptr > 100) g->p.ptr = (void *)100;
board_backlight(g, (unsigned)g->p.ptr);
g->g.Backlight = (unsigned)g->p.ptr;
return;
case GDISP_CONTROL_CONTRAST:
if ((unsigned)g->p.ptr > 100) g->p.ptr = (void *)100;
board_contrast(g, (unsigned)g->p.ptr);
g->g.Contrast = (unsigned)g->p.ptr;
return;
}
}
#endif
#endif /* GFX_USE_GDISP */

24
drivers/gdisp/STM32F429iDiscovery/gdisp_lld_config.h 100644
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@ -0,0 +1,24 @@
/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.org/license.html
*/
#ifndef _GDISP_LLD_CONFIG_H
#define _GDISP_LLD_CONFIG_H
#if GFX_USE_GDISP
/*===========================================================================*/
/* Driver hardware support. */
/*===========================================================================*/
#define GDISP_HARDWARE_DRAWPIXEL TRUE
#define GDISP_HARDWARE_PIXELREAD TRUE
#define GDISP_HARDWARE_CONTROL TRUE
#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_RGB565
#endif /* GFX_USE_GDISP */
#endif /* _GDISP_LLD_CONFIG_H */

412
drivers/gdisp/STM32F429iDiscovery/ili9341.h 100644
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/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.org/license.html
*/
#ifndef ILI9341_H
#define ILI9341_H
// ILI9341 commands
#define ILI9341_CMD_NOP 0x00 /**< No operation.*/
#define ILI9341_CMD_RESET 0x01 /**< Software reset.*/
#define ILI9341_GET_ID_INFO 0x04 /**< Get ID information.*/
#define ILI9341_GET_STATUS 0x09 /**< Get status.*/
#define ILI9341_GET_PWR_MODE 0x0A /**< Get power mode.*/
#define ILI9341_GET_MADCTL 0x0B /**< Get MADCTL.*/
#define ILI9341_GET_PIX_FMT 0x0C /**< Get pixel format.*/
#define ILI9341_GET_IMG_FMT 0x0D /**< Get image format.*/
#define ILI9341_GET_SIG_MODE 0x0E /**< Get signal mode.*/
#define ILI9341_GET_SELF_DIAG 0x0F /**< Get self-diagnostics.*/
#define ILI9341_CMD_SLEEP_ON 0x10 /**< Enter sleep mode.*/
#define ILI9341_CMD_SLEEP_OFF 0x11 /**< Exist sleep mode.*/
#define ILI9341_CMD_PARTIAL_ON 0x12 /**< Enter partial mode.*/
#define ILI9341_CMD_PARTIAL_OFF 0x13 /**< Exit partial mode.*/
#define ILI9341_CMD_INVERT_ON 0x20 /**< Enter inverted mode.*/
#define ILI9341_CMD_INVERT_OFF 0x21 /**< Exit inverted mode.*/
#define ILI9341_SET_GAMMA 0x26 /**< Set gamma params.*/
#define ILI9341_CMD_DISPLAY_OFF 0x28 /**< Disable display.*/
#define ILI9341_CMD_DISPLAY_ON 0x29 /**< Enable display.*/
#define ILI9341_SET_COL_ADDR 0x2A /**< Set column address.*/
#define ILI9341_SET_PAGE_ADDR 0x2B /**< Set page address.*/
#define ILI9341_SET_MEM 0x2C /**< Set memory.*/
#define ILI9341_SET_COLOR 0x2D /**< Set color.*/
#define ILI9341_GET_MEM 0x2E /**< Get memory.*/
#define ILI9341_SET_PARTIAL_AREA 0x30 /**< Set partial area.*/
#define ILI9341_SET_VSCROLL 0x33 /**< Set vertical scroll def.*/
#define ILI9341_CMD_TEARING_ON 0x34 /**< Tearing line enabled.*/
#define ILI9341_CMD_TEARING_OFF 0x35 /**< Tearing line disabled.*/
#define ILI9341_SET_MEM_ACS_CTL 0x36 /**< Set mem access ctl.*/
#define ILI9341_SET_VSCROLL_ADDR 0x37 /**< Set vscroll start addr.*/
#define ILI9341_CMD_IDLE_OFF 0x38 /**< Exit idle mode.*/
#define ILI9341_CMD_IDLE_ON 0x39 /**< Enter idle mode.*/
#define ILI9341_SET_PIX_FMT 0x3A /**< Set pixel format.*/
#define ILI9341_SET_MEM_CONT 0x3C /**< Set memory continue.*/
#define ILI9341_GET_MEM_CONT 0x3E /**< Get memory continue.*/
#define ILI9341_SET_TEAR_SCANLINE 0x44 /**< Set tearing scanline.*/
#define ILI9341_GET_TEAR_SCANLINE 0x45 /**< Get tearing scanline.*/
#define ILI9341_SET_BRIGHTNESS 0x51 /**< Set brightness.*/
#define ILI9341_GET_BRIGHTNESS 0x52 /**< Get brightness.*/
#define ILI9341_SET_DISPLAY_CTL 0x53 /**< Set display ctl.*/
#define ILI9341_GET_DISPLAY_CTL 0x54 /**< Get display ctl.*/
#define ILI9341_SET_CABC 0x55 /**< Set CABC.*/
#define ILI9341_GET_CABC 0x56 /**< Get CABC.*/
#define ILI9341_SET_CABC_MIN 0x5E /**< Set CABC min.*/
#define ILI9341_GET_CABC_MIN 0x5F /**< Set CABC max.*/
#define ILI9341_GET_ID1 0xDA /**< Get ID1.*/
#define ILI9341_GET_ID2 0xDB /**< Get ID2.*/
#define ILI9341_GET_ID3 0xDC /**< Get ID3.*/
// ILI9341 extended commands
#define ILI9341_SET_RGB_IF_SIG_CTL 0xB0 /**< RGB IF signal ctl.*/
#define ILI9341_SET_FRAME_CTL_NORMAL 0xB1 /**< Set frame ctl (normal).*/
#define ILI9341_SET_FRAME_CTL_IDLE 0xB2 /**< Set frame ctl (idle).*/
#define ILI9341_SET_FRAME_CTL_PARTIAL 0xB3 /**< Set frame ctl (partial).*/
#define ILI9341_SET_INVERSION_CTL 0xB4 /**< Set inversion ctl.*/
#define ILI9341_SET_BLANKING_PORCH_CTL 0xB5 /**< Set blanking porch ctl.*/
#define ILI9341_SET_FUNCTION_CTL 0xB6 /**< Set function ctl.*/
#define ILI9341_SET_ENTRY_MODE 0xB7 /**< Set entry mode.*/
#define ILI9341_SET_LIGHT_CTL_1 0xB8 /**< Set backlight ctl 1.*/
#define ILI9341_SET_LIGHT_CTL_2 0xB9 /**< Set backlight ctl 2.*/
#define ILI9341_SET_LIGHT_CTL_3 0xBA /**< Set backlight ctl 3.*/
#define ILI9341_SET_LIGHT_CTL_4 0xBB /**< Set backlight ctl 4.*/
#define ILI9341_SET_LIGHT_CTL_5 0xBC /**< Set backlight ctl 5.*/
#define ILI9341_SET_LIGHT_CTL_7 0xBE /**< Set backlight ctl 7.*/
#define ILI9341_SET_LIGHT_CTL_8 0xBF /**< Set backlight ctl 8.*/
#define ILI9341_SET_POWER_CTL_1 0xC0 /**< Set power ctl 1.*/
#define ILI9341_SET_POWER_CTL_2 0xC1 /**< Set power ctl 2.*/
#define ILI9341_SET_VCOM_CTL_1 0xC5 /**< Set VCOM ctl 1.*/
#define ILI9341_SET_VCOM_CTL_2 0xC6 /**< Set VCOM ctl 2.*/
#define ILI9341_SET_NVMEM 0xD0 /**< Set NVMEM data.*/
#define ILI9341_GET_NVMEM_KEY 0xD1 /**< Get NVMEM protect key.*/
#define ILI9341_GET_NVMEM_STATUS 0xD2 /**< Get NVMEM status.*/
#define ILI9341_GET_ID4 0xD3 /**< Get ID4.*/
#define ILI9341_SET_PGAMMA 0xE0 /**< Set positive gamma.*/
#define ILI9341_SET_NGAMMA 0xE1 /**< Set negative gamma.*/
#define ILI9341_SET_DGAMMA_CTL_1 0xE2 /**< Set digital gamma ctl 1.*/
#define ILI9341_SET_DGAMMA_CTL_2 0xE3 /**< Set digital gamma ctl 2.*/
#define ILI9341_SET_IF_CTL 0xF6 /**< Set interface control.*/
// ILI9341 interface modes
#define ILI9341_IM_3LSI_1 0x5 /**< 3-line serial, mode 1.*/
#define ILI9341_IM_3LSI_2 0xD /**< 3-line serial, mode 2.*/
#define ILI9341_IM_4LSI_1 0x6 /**< 4-line serial, mode 1.*/
#define ILI9341_IM_4LSI_2 0xE /**< 4-line serial, mode 2.*/
// ILI9341 command params (little endian)
#pragma pack(push, 1)
typedef union {
struct ILI9341ParamBits_GET_ID_INFO {
uint8_t reserved_;
uint8_t ID1;
uint8_t ID2;
uint8_t ID3;
} bits;
uint8_t bytes[4];
} ILI9341Params_GET_ID_INFO;
typedef union {
struct ILI9341ParamBits_GET_STATUS {
unsigned _reserved_1 : 5; /* D[ 4: 0] */
unsigned tearing_mode : 1; /* D[ 5] */
unsigned gamma_curve : 3; /* D[ 8: 6] */
unsigned tearing : 1; /* D[ 9] */
unsigned display : 1; /* D[10] */
unsigned all_on : 1; /* D[11] */
unsigned all_off : 1; /* D[12] */
unsigned invert : 1; /* D[13] */
unsigned _reserved_2 : 1; /* D[14] */
unsigned vscroll : 1; /* D[15] */
unsigned normal : 1; /* D[16] */
unsigned sleep : 1; /* D[17] */
unsigned partial : 1; /* D[18] */
unsigned idle : 1; /* D[19] */
unsigned pixel_format : 3; /* D[22:20] */
unsigned _reserved_3 : 2; /* D[24:23] */
unsigned hrefr_rtl_nltr : 1; /* D[25] */
unsigned bgr_nrgb : 1; /* D[26] */
unsigned vrefr_btt_nttb : 1; /* D[27] */
unsigned transpose : 1; /* D[28] */
unsigned coladr_rtl_nltr : 1; /* D[29] */
unsigned rowadr_btt_nttb : 1; /* D[30] */
unsigned booster : 1; /* D[31] */
} bits;
uint8_t bytes[4];
} ILI9341Params_GET_STATUS;
typedef union {
struct ILI9341ParamBits_GET_PWR_MODE {
unsigned _reserved_1 : 2; /* D[1:0] */
unsigned display : 1; /* D[2] */
unsigned normal : 1; /* D[3] */
unsigned sleep : 1; /* D[4] */
unsigned partial : 1; /* D[5] */
unsigned idle : 1; /* D[6] */
unsigned booster : 1; /* D[7] */
} bits;
uint8_t bytes[1];
} ILI9341Params_GET_PWR_MODE;
typedef union {
struct ILI9341ParamBits_GET_MADCTL {
unsigned _reserved_1 : 2; /* D[1:0] */
unsigned refr_rtl_nltr : 1; /* D[2] */
unsigned bgr_nrgb : 1; /* D[3] */
unsigned refr_btt_nttb : 1; /* D[4] */
unsigned invert : 1; /* D[5] */
unsigned rtl_nltr : 1; /* D[6] */
unsigned btt_nttb : 1; /* D[7] */
} bits;
uint8_t bytes[1];
} ILI9341Params_GET_MADCTL;
typedef union {
struct ILI9341ParamBits_GET_PIX_FMT {
unsigned DBI : 3; /* D[2:0] */
unsigned _reserved_1 : 1; /* D[3] */
unsigned DPI : 3; /* D[6:4] */
unsigned RIM : 1; /* D[7] */
} bits;
uint8_t bytes[1];
} ILI9341Params_GET_PIX_FMT;
typedef union {
struct ILI9341ParamBits_GET_IMG_FMT {
unsigned gamma_curve : 3; /* D[2:0] */
unsigned _reserved_1 : 5; /* D[7:3] */
} bits;
uint8_t bytes[1];
} ILI9341Params_GET_IMG_FMT;
typedef union {
struct ILI9341ParamBits_GET_SIG_MODE {
unsigned _reserved_1 : 2; /* D[1:0] */
unsigned data_enable : 1; /* D[2] */
unsigned pixel_clock : 1; /* D[3] */
unsigned vsync : 1; /* D[4] */
unsigned hsync : 1; /* D[5] */
unsigned tearing_mode : 1; /* D[6] */
unsigned tearing : 1; /* D[7] */
} bits;
uint8_t bytes[1];
} ILI9341Params_GET_SIG_MODE;
typedef union {
struct ILI9341ParamBits_GET_SELF_DIAG {
unsigned _reserved_1 : 6; /* D[5:0] */
unsigned func_err : 1; /* D[6] */
unsigned reg_err : 1; /* D[7] */
} bits;
uint8_t bytes[1];
} ILI9341Params_GET_SELF_DIAG;
typedef union {
struct ILI9341ParamBits_SET_GAMMA {
uint8_t gamma_curve; /* D[7:0] */
} bits;
uint8_t bytes[1];
} ILI9341Params_SET_GAMMA;
typedef union {
struct ILI9341ParamBits_SET_COL_ADDR {
uint8_t SC_15_8; /* D[ 7: 0] */
uint8_t SC_7_0; /* D[15: 8] */
uint8_t EC_15_8; /* D[23:16] */
uint8_t EC_7_0; /* D[31:24] */
} bits;
uint8_t bytes[4];
} ILI9341Params_SET_COL_ADDR;
typedef union {
struct ILI9341ParamBits_SET_PAGE_ADDR {
uint8_t SP_15_8; /* D[ 7: 0] */
uint8_t SP_7_0; /* D[15: 8] */
uint8_t EP_15_8; /* D[23:16] */
uint8_t EP_7_0; /* D[31:24] */
} bits;
uint8_t bytes[4];
} ILI9341Params_SET_PAGE_ADDR;
typedef union {
struct ILI9341ParamBits_SET_PARTIAL_AREA {
uint8_t SR_15_8; /* D[ 7: 0] */
uint8_t SR_7_0; /* D[15: 8] */
uint8_t ER_15_8; /* D[23:16] */
uint8_t ER_7_0; /* D[31:24] */
} bits;
uint8_t bytes[4];
} ILI9341Params_SET_PARTIAL_AREA;
typedef union {
struct ILI9341ParamBits_SET_VSCROLL {
uint8_t TFA_15_8; /* D[ 7: 0] */
uint8_t TFA_7_0; /* D[15: 8] */
uint8_t VSA_15_8; /* D[23:16] */
uint8_t VSA_7_0; /* D[31:24] */
uint8_t BFA_15_8; /* D[39:32] */
uint8_t BFA_7_0; /* D[47:40] */
} bits;
uint8_t bytes[6];
} ILI9341Params_SET_VSCROLL;
typedef union {
struct ILI9341ParamBits_CMD_TEARING_ON {
unsigned M : 1; /* D[0] */
unsigned _reserved_1 : 7; /* D[7:1] */
} bits;
uint8_t bytes[1];
} ILI9341Params_CMD_TEARING_ON;
typedef union {
struct ILI9341ParamBits_SET_MEM_ACS_CTL {
unsigned _reserved_1 : 2; /* D[1:0] */
unsigned MH : 1; /* D[2] */
unsigned BGR : 1; /* D[3] */
unsigned ML : 1; /* D[4] */
unsigned MV : 1; /* D[5] */
unsigned MX : 1; /* D[6] */
unsigned MY : 1; /* D[7] */
} bits;
uint8_t bytes[1];
} ILI9341Params_SET_MEM_ACS_CTL;
typedef union {
struct ILI9341ParamBits_SET_VSCROLL_ADDR {
uint8_t VSP_15_8; /* D[ 7: 0] */
uint8_t VSP_7_0; /* D[15: 8] */
} bits;
uint8_t bytes[2];
} ILI9341Params_SET_VSCROLL_ADDR;
typedef union {
struct ILI9341ParamBits_SET_PIX_FMT {
unsigned DBI : 3; /* D[2:0] */
unsigned _reserved_1 : 1; /* D[3] */
unsigned DPI : 3; /* D[4:6] */
unsigned _reserved_2 : 1; /* D[7] */
} bits;
uint8_t bytes[1];
} ILI9341Params_SET_PIX_FMT;
typedef union {
struct ILI9341ParamBits_SET_TEAR_SCANLINE {
uint8_t STS_8; /* D[ 7: 0] */
uint8_t STS_7_0; /* D[15: 8] */
} bits;
uint8_t bytes[4];
} ILI9341Params_SET_TEAR_SCANLINE;
typedef union {
struct ILI9341ParamBits_GET_TEAR_SCANLINE {
uint8_t GTS_9_8; /* D[ 7: 0] */
uint8_t GTS_7_0; /* D[15: 8] */
} bits;
uint8_t bytes[2];
} ILI9341Params_GET_TEAR_SCANLINE;
typedef union {
struct ILI9341ParamBits_SET_BRIGHTNESS {
uint8_t DBV; /* D[7:0] */
} bits;
uint8_t bytes[1];
} ILI9341Params_SET_BRIGHTNESS;
typedef union {
struct ILI9341ParamBits_GET_BRIGHTNESS {
uint8_t DBV; /* D[7:0] */
} bits;
uint8_t bytes[1];
} ILI9341Params_GET_BRIGHTNESS;
typedef union {
struct ILI9341ParamBits_SET_DISPLAY_CTL {
unsigned _reserved_1 : 2; /* D[1:0] */
unsigned BL : 1; /* D[2] */
unsigned DD : 1; /* D[3] */
unsigned _reserved_2 : 1; /* D[4] */
unsigned BCTRL : 1; /* D[5] */
unsigned _reserved_3 : 1; /* D[7:6] */
} bits;
uint8_t bytes[1];
} ILI9341Params_SET_DISPLAY_CTL;
typedef union {
struct ILI9341ParamBits_GET_DISPLAY_CTL {
unsigned _reserved_1 : 2; /* D[1:0] */
unsigned BL : 1; /* D[2] */
unsigned DD : 1; /* D[3] */
unsigned _reserved_2 : 1; /* D[4] */
unsigned BCTRL : 1; /* D[5] */
unsigned _reserved_3 : 1; /* D[7:6] */
} bits;
uint8_t bytes[1];
} ILI9341Params_GET_DISPLAY_CTL;
typedef union {
struct ILI9341ParamBits_SET_CABC {
unsigned C : 2; /* D[1:0] */
unsigned _reserved_1 : 6; /* D[7:2] */
} bits;
uint8_t bytes[1];
} ILI9341Params_SET_CABC;
typedef union {
struct ILI9341ParamBits_GET_CABC {
unsigned C : 2; /* D[1:0] */
unsigned _reserved_1 : 6; /* D[7:2] */
} bits;
uint8_t bytes[1];
} ILI9341Params_GET_CABC;
typedef union {
struct ILI9341ParamBits_SET_CABC_MIN {
uint8_t CMB; /* D[7:0] */
} bits;
uint8_t bytes[1];
} ILI9341Params_SET_CABC_MIN;
typedef union {
struct ILI9341ParamBits_GET_CABC_MIN {
uint8_t CMB; /* D[7:0] */
} bits;
uint8_t bytes[1];
} ILI9341Params_GET_CABC_MIN;
#if 0 /* TODO: Extended command structs.*/
typedef union {
struct ILI9341ParamBits {
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
} bits;
uint8_t bytes[1];
} ILI9341Params_;
typedef union {
struct ILI9341ParamBits {
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
unsigned : 1; /* D[] */
} bits;
uint8_t bytes[1];
} ILI9341Params_;
#endif /*0*/
#pragma pack(pop)
#endif /* ILI9341_H */

11
drivers/gdisp/STM32F429iDiscovery/readme.txt 100644
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@ -0,0 +1,11 @@
To use this driver:
1. Add in your gfxconf.h:
a) #define GFX_USE_GDISP TRUE
2. To your makefile add the following lines:
include $(GFXLIB)/gfx.mk
include $(GFXLIB)/drivers/gdisp/STM32F429iDiscovery/driver.mk
3. Add a board_STM32F429iDiscovery.h to you project directory (or board directory)
base on one of the templates.

551
drivers/gdisp/STM32F429iDiscovery/stm32_ltdc.h 100644
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@ -0,0 +1,551 @@
/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.org/license.html
*/
#ifndef STM32_LTDC_H
#define STM32_LTDC_H
// LTDC enable flags
#define LTDC_EF_ENABLE (1 << 0) /**< LTDC enabled.*/
#define LTDC_EF_DITHER (1 << 16) /**< Dithering enabled.*/
#define LTDC_EF_PIXCLK_INVERT (1 << 28) /**< Inverted pixel clock.*/
#define LTDC_EF_DATAEN_HIGH (1 << 29) /**< Active-high data enable.*/
#define LTDC_EF_VSYNC_HIGH (1 << 30) /**< Active-high vsync.*/
#define LTDC_EF_HSYNC_HIGH (1 << 31) /**< Active-high hsync.*/
#define LTDC_EF_MASK (LTDC_EF_ENABLE | LTDC_EF_DITHER | LTDC_EF_PIXCLK_INVERT | LTDC_EF_DATAEN_HIGH | LTDC_EF_VSYNC_HIGH | LTDC_EF_HSYNC_HIGH)
// LTDC layer enable flags
#define LTDC_LEF_ENABLE (1 << 0) /**< Layer enabled*/
#define LTDC_LEF_KEYING (1 << 1) /**< Color keying enabled.*/
#define LTDC_LEF_PALETTE (1 << 4) /**< Palette enabled.*/
#define LTDC_LEF_MASK (LTDC_LEF_ENABLE | LTDC_LEF_KEYING | LTDC_LEF_PALETTE)
// LTDC pixel formats
#define LTDC_FMT_ARGB8888 0 /**< ARGB-8888 format.*/
#define LTDC_FMT_RGB888 1 /**< RGB-888 format.*/
#define LTDC_FMT_RGB565 2 /**< RGB-565 format.*/
#define LTDC_FMT_ARGB1555 3 /**< ARGB-1555 format.*/
#define LTDC_FMT_ARGB4444 4 /**< ARGB-4444 format.*/
#define LTDC_FMT_L8 5 /**< L-8 format.*/
#define LTDC_FMT_AL44 6 /**< AL-44 format.*/
#define LTDC_FMT_AL88 7 /**< AL-88 format.*/
// LTDC pixel format aliased raw masks
#define LTDC_XMASK_ARGB8888 0xFFFFFFFF /**< ARGB-8888 aliased mask.*/
#define LTDC_XMASK_RGB888 0x00FFFFFF /**< RGB-888 aliased mask.*/
#define LTDC_XMASK_RGB565 0x00F8FCF8 /**< RGB-565 aliased mask.*/
#define LTDC_XMASK_ARGB1555 0x80F8F8F8 /**< ARGB-1555 aliased mask.*/
#define LTDC_XMASK_ARGB4444 0xF0F0F0F0 /**< ARGB-4444 aliased mask.*/
#define LTDC_XMASK_L8 0x000000FF /**< L-8 aliased mask.*/
#define LTDC_XMASK_AL44 0xF00000F0 /**< AL-44 aliased mask.*/
#define LTDC_XMASK_AL88 0xFF0000FF /**< AL-88 aliased mask.*/
// LTDC blending factors
#define LTDC_BLEND_FIX1_FIX2 0x0405 /**< cnst1; 1 - cnst2 */
#define LTDC_BLEND_FIX1_MOD2 0x0407 /**< cnst1; 1 - a2 * cnst2 */
#define LTDC_BLEND_MOD1_FIX2 0x0605 /**< a1 * cnst1; 1 - cnst2 */
#define LTDC_BLEND_MOD1_MOD2 0x0607 /**< a1 * cnst1; 1 - a2 * cnst2 */
// LTDC parameter bounds
#define LTDC_MIN_SCREEN_WIDTH 1
#define LTDC_MIN_SCREEN_HEIGHT 1
#define LTDC_MAX_SCREEN_WIDTH 800
#define LTDC_MAX_SCREEN_HEIGHT 600
#define LTDC_MIN_HSYNC_WIDTH 1
#define LTDC_MIN_VSYNC_HEIGHT 1
#define LTDC_MAX_HSYNC_WIDTH (1 << 12)
#define LTDC_MAX_VSYNC_HEIGHT (1 << 11)
#define LTDC_MIN_HBP_WIDTH 0
#define LTDC_MIN_VBP_HEIGHT 0
#define LTDC_MAX_HBP_WIDTH (1 << 12)
#define LTDC_MAX_VBP_HEIGHT (1 << 11)
#define LTDC_MIN_ACC_HBP_WIDTH 1
#define LTDC_MIN_ACC_VBP_HEIGHT 1
#define LTDC_MAX_ACC_HBP_WIDTH (1 << 12)
#define LTDC_MAX_ACC_VBP_HEIGHT (1 << 11)
#define LTDC_MIN_HFP_WIDTH 0
#define LTDC_MIN_VFP_HEIGHT 0
#define LTDC_MAX_HFP_WIDTH (1 << 12)
#define LTDC_MAX_VFP_HEIGHT (1 << 11)
#define LTDC_MIN_ACTIVE_WIDTH 0
#define LTDC_MIN_ACTIVE_HEIGHT 0
#define LTDC_MAX_ACTIVE_WIDTH (1 << 12)
#define LTDC_MAX_ACTIVE_HEIGHT (1 << 11)
#define LTDC_MIN_ACC_ACTIVE_WIDTH 1
#define LTDC_MIN_ACC_ACTIVE_HEIGHT 1
#define LTDC_MAX_ACC_ACTIVE_WIDTH (1 << 12)
#define LTDC_MAX_ACC_ACTIVE_HEIGHT (1 << 11)
#define LTDC_MIN_ACC_TOTAL_WIDTH 1
#define LTDC_MIN_ACC_TOTAL_HEIGHT 1
#define LTDC_MAX_ACC_TOTAL_WIDTH (1 << 12)
#define LTDC_MAX_ACC_TOTAL_HEIGHT (1 << 11)
#define LTDC_MIN_LINE_INTERRUPT_POS 0
#define LTDC_MAX_LINE_INTERRUPT_POS ((1 << 11) - 1)
#define LTDC_MIN_WINDOW_HSTART 0
#define LTDC_MIN_WINDOW_HSTART 0
#define LTDC_MAX_WINDOW_HSTOP ((1 << 12) - 1)
#define LTDC_MAX_WINDOW_HSTOP ((1 << 12) - 1)
#define LTDC_MIN_WINDOW_VSTART 0
#define LTDC_MIN_WINDOW_VSTART 0
#define LTDC_MAX_WINDOW_VSTOP ((1 << 11) - 1)
#define LTDC_MAX_WINDOW_VSTOP ((1 << 11) - 1)
#define LTDC_MIN_FRAME_WIDTH_BYTES 0
#define LTDC_MIN_FRAME_HEIGHT_LINES 0
#define LTDC_MIN_FRAME_PITCH_BYTES 0
#define LTDC_MAX_FRAME_WIDTH_BYTES ((1 << 13) - 1 - 3)
#define LTDC_MAX_FRAME_HEIGHT_LINES ((1 << 11) - 1)
#define LTDC_MAX_FRAME_PITCH_BYTES ((1 << 13) - 1)
#define LTDC_MIN_PIXFMT_ID 0
#define LTDC_MAX_PIXFMT_ID 7
#define LTDC_MAX_PALETTE_LENGTH 256
// LTDC basic ARGB-8888 colors.
#define LTDC_COLOR_BLACK 0xFF000000
#define LTDC_COLOR_MAROON 0xFF800000
#define LTDC_COLOR_GREEN 0xFF008000
#define LTDC_COLOR_OLIVE 0xFF808000
#define LTDC_COLOR_NAVY 0xFF000080
#define LTDC_COLOR_PURPLE 0xFF800080
#define LTDC_COLOR_TEAL 0xFF008080
#define LTDC_COLOR_SILVER 0xFFC0C0C0
#define LTDC_COLOR_GRAY 0xFF808080
#define LTDC_COLOR_RED 0xFFFF0000
#define LTDC_COLOR_LIME 0xFF00FF00
#define LTDC_COLOR_YELLOW 0xFFFFFF00
#define LTDC_COLOR_BLUE 0xFF0000FF
#define LTDC_COLOR_FUCHSIA 0xFFFF00FF
#define LTDC_COLOR_AQUA 0xFF00FFFF
#define LTDC_COLOR_WHITE 0xFFFFFFFF
/**/
#define STM32_LTDC_EV_HANDLER LTDC_EV_IRQHandler
#define STM32_LTDC_ER_HANDLER LTDC_ER_IRQHandler
#define STM32_LTDC_EV_NUMBER LTDC_IRQn
#define STM32_LTDC_ER_NUMBER LTDC_ER_IRQn
#define LTDC_EV_IRQHandler Vector1A0
#define LTDC_ER_IRQHandler Vector1A4
#define STM32_LTDC_EV_IRQ_PRIORITY 11
#define STM32_LTDC_ER_IRQ_PRIORITY 11
#define LTDC_USE_WAIT TRUE
#define LTDC_USE_SOFTWARE_CONVERSIONS TRUE
#ifndef STM32F429_439xx
#error "Currently only STM32F429xx and STM32F439xx are supported"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/* Complex types forwarding.*/
typedef union ltdc_coloralias_t ltdc_coloralias_t;
typedef struct ltdc_window_t ltdc_window_t;
typedef struct ltdc_frame_t ltdc_frame_t;
typedef struct ltdc_laycfg_t ltdc_laycfg_t;
typedef struct LTDCConfig LTDCConfig;
typedef enum ltdc_state_t ltdc_state_t;
typedef struct LTDCDriver LTDCDriver;
/**
* @name LTDC Data types
* @{
*/
/**
* @brief LTDC generic color.
*/
typedef uint32_t ltdc_color_t;
/**
* @brief LTDC color aliases.
* @detail Mapped with ARGB-8888, except for luminance (L mapped onto B).
* Padding fields prefixed with <tt>'x'</tt>, which should be clear
* (all 0) before compression and set (all 1) after expansion.
*/
typedef union ltdc_coloralias_t {
struct {
unsigned b : 8;
unsigned g : 8;
unsigned r : 8;
unsigned a : 8;
} argb8888; /**< Mapped ARGB-8888 bits.*/
struct {
unsigned b : 8;
unsigned g : 8;
unsigned r : 8;
unsigned xa : 8;
} rgb888; /**< Mapped RGB-888 bits.*/
struct {
unsigned xb : 3;
unsigned b : 5;
unsigned xg : 2;
unsigned g : 6;
unsigned xr : 3;
unsigned r : 5;
unsigned xa : 8;
} rgb565; /**< Mapped RGB-565 bits.*/
struct {
unsigned xb : 3;
unsigned b : 5;
unsigned xg : 3;
unsigned g : 5;
unsigned xr : 3;
unsigned r : 5;
unsigned xa : 7;
unsigned a : 1;
} argb1555; /**< Mapped ARGB-1555 values.*/
struct {
unsigned xb : 4;
unsigned b : 4;
unsigned xg : 4;
unsigned g : 4;
unsigned xr : 4;
unsigned r : 4;
unsigned xa : 4;
unsigned a : 4;
} argb4444; /**< Mapped ARGB-4444 values.*/
struct {
unsigned l : 8;
unsigned x : 16;
unsigned xa : 8;
} l8; /**< Mapped L-8 bits.*/
struct {
unsigned xl : 4;
unsigned l : 4;
unsigned x : 16;
unsigned xa : 4;
unsigned a : 4;
} al44; /**< Mapped AL-44 bits.*/
struct {
unsigned l : 8;
unsigned x : 16;
unsigned a : 8;
} al88; /**< Mapped AL-88 bits.*/
ltdc_color_t aliased; /**< Aliased raw bits.*/
} ltdc_coloralias_t;
/**
* @brief LTDC layer identifier.
*/
typedef uint32_t ltdc_layerid_t;
/**
* @brief LTDC pixel format.
*/
typedef uint32_t ltdc_pixfmt_t;
/**
* @brief LTDC blending factor.
*/
typedef uint32_t ltdc_blendf_t;
/**
* @brief LTDC ISR callback.
*/
typedef void (*ltdc_isrcb_t)(LTDCDriver *ltdcp);
/**
* @brief LTDC window specifications.
*/
typedef struct ltdc_window_t {
uint16_t hstart; /**< Horizontal start pixel (left).*/
uint16_t hstop; /**< Horizontal stop pixel (right).*/
uint16_t vstart; /**< Vertical start pixel (top).*/
uint16_t vstop; /**< Vertical stop pixel (bottom).*/
} ltdc_window_t;
/**
* @brief LTDC frame specifications.
*/
typedef struct ltdc_frame_t {
void *bufferp; /**< Frame buffer address.*/
uint16_t width; /**< Frame width, in pixels.*/
uint16_t height; /**< Frame height, in pixels.*/
size_t pitch; /**< Line pitch, in bytes.*/
ltdc_pixfmt_t fmt; /**< Pixel format.*/
} ltdc_frame_t;
/**
* @brief LTDC configuration flags.
*/
typedef uint8_t ltdc_flags_t;
/**
* @brief LTDC startup layer configuration.
*/
typedef struct ltdc_laycfg_t {
const ltdc_frame_t *frame; /**< Frame buffer specifications.*/
const ltdc_window_t *window; /**< Window specifications.*/
ltdc_color_t def_color; /**< Default color, ARGB-8888.*/
uint8_t const_alpha; /**< Constant alpha factor.*/
ltdc_color_t key_color; /**< Color key.*/
const ltdc_color_t *pal_colors; /**< Palette colors, or @p NULL.*/
uint16_t pal_length; /**< Palette length, or @p 0.*/
ltdc_blendf_t blending; /**< Blending factors.*/
ltdc_flags_t flags; /**< Layer configuration flags.*/
} ltdc_laycfg_t;
/**
* @brief LTDC driver configuration.
*/
typedef struct LTDCConfig {
/* Display specifications.*/
uint16_t screen_width; /**< Screen pixel width.*/
uint16_t screen_height; /**< Screen pixel height.*/
uint16_t hsync_width; /**< Horizontal sync pixel width.*/
uint16_t vsync_height; /**< Vertical sync pixel height.*/
uint16_t hbp_width; /**< Horizontal back porch pixel width.*/
uint16_t vbp_height; /**< Vertical back porch pixel height.*/
uint16_t hfp_width; /**< Horizontal front porch pixel width.*/
uint16_t vfp_height; /**< Vertical front porch pixel height.*/
ltdc_flags_t flags; /**< Driver configuration flags.*/
/* ISR callbacks.*/
ltdc_isrcb_t line_isr; /**< Line Interrupt ISR, or @p NULL.*/
ltdc_isrcb_t rr_isr; /**< Register Reload ISR, or @p NULL.*/
ltdc_isrcb_t fuerr_isr; /**< FIFO Underrun ISR, or @p NULL.*/
ltdc_isrcb_t terr_isr; /**< Transfer Error ISR, or @p NULL.*/
/* Layer and color settings.*/
ltdc_color_t clear_color; /**< Clear screen color, RGB-888.*/
const ltdc_laycfg_t *bg_laycfg; /**< Background layer specs, or @p NULL.*/
const ltdc_laycfg_t *fg_laycfg; /**< Foreground layer specs, or @p NULL.*/
} LTDCConfig;
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @brief Makes an ARGB-8888 value from byte components.
*
* @param[in] a alpha byte component
* @param[in] r red byte component
* @param[in] g green byte component
* @param[in] b blue byte component
*
* @return color in ARGB-8888 format
*
* @api
*/
#define ltdcMakeARGB8888(a, r, g, b) \
((((ltdc_color_t)(a) & 0xFF) << 24) | \
(((ltdc_color_t)(r) & 0xFF) << 16) | \
(((ltdc_color_t)(g) & 0xFF) << 8) | \
(((ltdc_color_t)(b) & 0xFF) << 0))
/**
* @brief Compute bytes per pixel.
* @details Computes the bytes per pixel for the specified pixel format.
* Rounds to the ceiling.
*
* @param[in] fmt pixel format
*
* @return bytes per pixel
*
* @api
*/
#define ltdcBytesPerPixel(fmt) \
((ltdcBitsPerPixel(fmt) + 7) >> 3)
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
/* Global methods.*/
ltdc_flags_t ltdcGetEnableFlagsI(LTDCDriver *ltdcp);
ltdc_flags_t ltdcGetEnableFlags(LTDCDriver *ltdcp);
void ltdcSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags);
void ltdcSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags);
bool_t ltdcIsReloadingI(LTDCDriver *ltdcp);
bool_t ltdcIsReloading(LTDCDriver *ltdcp);
void ltdcStartReloadI(LTDCDriver *ltdcp, bool_t immediately);
void ltdcStartReload(LTDCDriver *ltdcp, bool_t immediately);
void ltdcReloadS(LTDCDriver *ltdcp, bool_t immediately);
void ltdcReload(LTDCDriver *ltdcp, bool_t immediately);
bool_t ltdcIsDitheringEnabledI(LTDCDriver *ltdcp);
bool_t ltdcIsDitheringEnabled(LTDCDriver *ltdcp);
void ltdcEnableDitheringI(LTDCDriver *ltdcp);
void ltdcEnableDithering(LTDCDriver *ltdcp);
void ltdcDisableDitheringI(LTDCDriver *ltdcp);
void ltdcDisableDithering(LTDCDriver *ltdcp);
ltdc_color_t ltdcGetClearColorI(LTDCDriver *ltdcp);
ltdc_color_t ltdcGetClearColor(LTDCDriver *ltdcp);
void ltdcSetClearColorI(LTDCDriver *ltdcp, ltdc_color_t c);
void ltdcSetClearColor(LTDCDriver *ltdcp, ltdc_color_t c);
uint16_t ltdcGetLineInterruptPosI(LTDCDriver *ltdcp);
uint16_t ltdcGetLineInterruptPos(LTDCDriver *ltdcp);
void ltdcSetLineInterruptPosI(LTDCDriver *ltdcp, uint16_t line);
void ltdcSetLineInterruptPos(LTDCDriver *ltdcp, uint16_t line);
bool_t ltdcIsLineInterruptEnabledI(LTDCDriver *ltdcp);
bool_t ltdcIsLineInterruptEnabled(LTDCDriver *ltdcp);
void ltdcEnableLineInterruptI(LTDCDriver *ltdcp);
void ltdcEnableLineInterrupt(LTDCDriver *ltdcp);
void ltdcDisableLineInterruptI(LTDCDriver *ltdcp);
void ltdcDisableLineInterrupt(LTDCDriver *ltdcp);
void ltdcGetCurrentPosI(LTDCDriver *ltdcp, uint16_t *xp, uint16_t *yp);
void ltdcGetCurrentPos(LTDCDriver *ltdcp, uint16_t *xp, uint16_t *yp);
/* Background layer methods.*/
ltdc_flags_t ltdcBgGetEnableFlagsI(LTDCDriver *ltdcp);
ltdc_flags_t ltdcBgGetEnableFlags(LTDCDriver *ltdcp);
void ltdcBgSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags);
void ltdcBgSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags);
bool_t ltdcBgIsEnabledI(LTDCDriver *ltdcp);
bool_t ltdcBgIsEnabled(LTDCDriver *ltdcp);
void ltdcBgEnableI(LTDCDriver *ltdcp);
void ltdcBgEnable(LTDCDriver *ltdcp);
void ltdcBgDisableI(LTDCDriver *ltdcp);
void ltdcBgDisable(LTDCDriver *ltdcp);
bool_t ltdcBgIsPaletteEnabledI(LTDCDriver *ltdcp);
bool_t ltdcBgIsPaletteEnabled(LTDCDriver *ltdcp);
void ltdcBgEnablePaletteI(LTDCDriver *ltdcp);
void ltdcBgEnablePalette(LTDCDriver *ltdcp);
void ltdcBgDisablePaletteI(LTDCDriver *ltdcp);
void ltdcBgDisablePalette(LTDCDriver *ltdcp);
void ltdcBgSetPaletteColorI(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c);
void ltdcBgSetPaletteColor(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c);
void ltdcBgSetPaletteI(LTDCDriver *ltdcp, const ltdc_color_t colors[],
uint16_t length);
void ltdcBgSetPalette(LTDCDriver *ltdcp, const ltdc_color_t colors[],
uint16_t length);
ltdc_pixfmt_t ltdcBgGetPixelFormatI(LTDCDriver *ltdcp);
ltdc_pixfmt_t ltdcBgGetPixelFormat(LTDCDriver *ltdcp);
void ltdcBgSetPixelFormatI(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt);
void ltdcBgSetPixelFormat(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt);
bool_t ltdcBgIsKeyingEnabledI(LTDCDriver *ltdcp);
bool_t ltdcBgIsKeyingEnabled(LTDCDriver *ltdcp);
void ltdcBgEnableKeyingI(LTDCDriver *ltdcp);
void ltdcBgEnableKeying(LTDCDriver *ltdcp);
void ltdcBgDisableKeyingI(LTDCDriver *ltdcp);
void ltdcBgDisableKeying(LTDCDriver *ltdcp);
ltdc_color_t ltdcBgGetKeyingColorI(LTDCDriver *ltdcp);
ltdc_color_t ltdcBgGetKeyingColor(LTDCDriver *ltdcp);
void ltdcBgSetKeyingColorI(LTDCDriver *ltdcp, ltdc_color_t c);
void ltdcBgSetKeyingColor(LTDCDriver *ltdcp, ltdc_color_t c);
uint8_t ltdcBgGetConstantAlphaI(LTDCDriver *ltdcp);
uint8_t ltdcBgGetConstantAlpha(LTDCDriver *ltdcp);
void ltdcBgSetConstantAlphaI(LTDCDriver *ltdcp, uint8_t a);
void ltdcBgSetConstantAlpha(LTDCDriver *ltdcp, uint8_t a);
ltdc_color_t ltdcBgGetDefaultColorI(LTDCDriver *ltdcp);
ltdc_color_t ltdcBgGetDefaultColor(LTDCDriver *ltdcp);
void ltdcBgSetDefaultColorI(LTDCDriver *ltdcp, ltdc_color_t c);
void ltdcBgSetDefaultColor(LTDCDriver *ltdcp, ltdc_color_t c);
ltdc_blendf_t ltdcBgGetBlendingFactorsI(LTDCDriver *ltdcp);
ltdc_blendf_t ltdcBgGetBlendingFactors(LTDCDriver *ltdcp);
void ltdcBgSetBlendingFactorsI(LTDCDriver *ltdcp, ltdc_blendf_t bf);
void ltdcBgSetBlendingFactors(LTDCDriver *ltdcp, ltdc_blendf_t bf);
void ltdcBgGetWindowI(LTDCDriver *ltdcp, ltdc_window_t *windowp);
void ltdcBgGetWindow(LTDCDriver *ltdcp, ltdc_window_t *windowp);
void ltdcBgSetWindowI(LTDCDriver *ltdcp, const ltdc_window_t *windowp);
void ltdcBgSetWindow(LTDCDriver *ltdcp, const ltdc_window_t *windowp);
void ltdcBgSetInvalidWindowI(LTDCDriver *ltdcp);
void ltdcBgSetInvalidWindow(LTDCDriver *ltdcp);
void ltdcBgGetFrameI(LTDCDriver *ltdcp, ltdc_frame_t *framep);
void ltdcBgGetFrame(LTDCDriver *ltdcp, ltdc_frame_t *framep);
void ltdcBgSetFrameI(LTDCDriver *ltdcp, const ltdc_frame_t *framep);
void ltdcBgSetFrame(LTDCDriver *ltdcp, const ltdc_frame_t *framep);
void *ltdcBgGetFrameAddressI(LTDCDriver *ltdcp);
void *ltdcBgGetFrameAddress(LTDCDriver *ltdcp);
void ltdcBgSetFrameAddressI(LTDCDriver *ltdcp, void *bufferp);
void ltdcBgSetFrameAddress(LTDCDriver *ltdcp, void *bufferp);
void ltdcBgGetLayerI(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp);
void ltdcBgGetLayer(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp);
void ltdcBgSetConfigI(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp);
void ltdcBgSetConfig(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp);
/* Foreground layer methods.*/
ltdc_flags_t ltdcFgGetEnableFlagsI(LTDCDriver *ltdcp);
ltdc_flags_t ltdcFgGetEnableFlags(LTDCDriver *ltdcp);
void ltdcFgSetEnableFlagsI(LTDCDriver *ltdcp, ltdc_flags_t flags);
void ltdcFgSetEnableFlags(LTDCDriver *ltdcp, ltdc_flags_t flags);
bool_t ltdcFgIsEnabledI(LTDCDriver *ltdcp);
bool_t ltdcFgIsEnabled(LTDCDriver *ltdcp);
void ltdcFgEnableI(LTDCDriver *ltdcp);
void ltdcFgEnable(LTDCDriver *ltdcp);
void ltdcFgDisableI(LTDCDriver *ltdcp);
void ltdcFgDisable(LTDCDriver *ltdcp);
bool_t ltdcFgIsPaletteEnabledI(LTDCDriver *ltdcp);
bool_t ltdcFgIsPaletteEnabled(LTDCDriver *ltdcp);
void ltdcFgEnablePaletteI(LTDCDriver *ltdcp);
void ltdcFgEnablePalette(LTDCDriver *ltdcp);
void ltdcFgDisablePaletteI(LTDCDriver *ltdcp);
void ltdcFgDisablePalette(LTDCDriver *ltdcp);
void ltdcFgSetPaletteColorI(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c);
void ltdcFgSetPaletteColor(LTDCDriver *ltdcp, uint8_t slot, ltdc_color_t c);
void ltdcFgSetPaletteI(LTDCDriver *ltdcp, const ltdc_color_t colors[],
uint16_t length);
void ltdcFgSetPalette(LTDCDriver *ltdcp, const ltdc_color_t colors[],
uint16_t length);
ltdc_pixfmt_t ltdcFgGetPixelFormatI(LTDCDriver *ltdcp);
ltdc_pixfmt_t ltdcFgGetPixelFormat(LTDCDriver *ltdcp);
void ltdcFgSetPixelFormatI(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt);
void ltdcFgSetPixelFormat(LTDCDriver *ltdcp, ltdc_pixfmt_t fmt);
bool_t ltdcFgIsKeyingEnabledI(LTDCDriver *ltdcp);
bool_t ltdcFgIsKeyingEnabled(LTDCDriver *ltdcp);
void ltdcFgEnableKeyingI(LTDCDriver *ltdcp);
void ltdcFgEnableKeying(LTDCDriver *ltdcp);
void ltdcFgDisableKeyingI(LTDCDriver *ltdcp);
void ltdcFgDisableKeying(LTDCDriver *ltdcp);
ltdc_color_t ltdcFgGetKeyingColorI(LTDCDriver *ltdcp);
ltdc_color_t ltdcFgGetKeyingColor(LTDCDriver *ltdcp);
void ltdcFgSetKeyingColorI(LTDCDriver *ltdcp, ltdc_color_t c);
void ltdcFgSetKeyingColor(LTDCDriver *ltdcp, ltdc_color_t c);
uint8_t ltdcFgGetConstantAlphaI(LTDCDriver *ltdcp);
uint8_t ltdcFgGetConstantAlpha(LTDCDriver *ltdcp);
void ltdcFgSetConstantAlphaI(LTDCDriver *ltdcp, uint8_t a);
void ltdcFgSetConstantAlpha(LTDCDriver *ltdcp, uint8_t a);
ltdc_color_t ltdcFgGetDefaultColorI(LTDCDriver *ltdcp);
ltdc_color_t ltdcFgGetDefaultColor(LTDCDriver *ltdcp);
void ltdcFgSetDefaultColorI(LTDCDriver *ltdcp, ltdc_color_t c);
void ltdcFgSetDefaultColor(LTDCDriver *ltdcp, ltdc_color_t c);
ltdc_blendf_t ltdcFgGetBlendingFactorsI(LTDCDriver *ltdcp);
ltdc_blendf_t ltdcFgGetBlendingFactors(LTDCDriver *ltdcp);
void ltdcFgSetBlendingFactorsI(LTDCDriver *ltdcp, ltdc_blendf_t bf);
void ltdcFgSetBlendingFactors(LTDCDriver *ltdcp, ltdc_blendf_t bf);
void ltdcFgGetWindowI(LTDCDriver *ltdcp, ltdc_window_t *windowp);
void ltdcFgGetWindow(LTDCDriver *ltdcp, ltdc_window_t *windowp);
void ltdcFgSetWindowI(LTDCDriver *ltdcp, const ltdc_window_t *windowp);
void ltdcFgSetWindow(LTDCDriver *ltdcp, const ltdc_window_t *windowp);
void ltdcFgSetInvalidWindowI(LTDCDriver *ltdcp);
void ltdcFgSetInvalidWindow(LTDCDriver *ltdcp);
void ltdcFgGetFrameI(LTDCDriver *ltdcp, ltdc_frame_t *framep);
void ltdcFgGetFrame(LTDCDriver *ltdcp, ltdc_frame_t *framep);
void ltdcFgSetFrameI(LTDCDriver *ltdcp, const ltdc_frame_t *framep);
void ltdcFgSetFrame(LTDCDriver *ltdcp, const ltdc_frame_t *framep);
void *ltdcFgGetFrameAddressI(LTDCDriver *ltdcp);
void *ltdcFgGetFrameAddress(LTDCDriver *ltdcp);
void ltdcFgSetFrameAddressI(LTDCDriver *ltdcp, void *bufferp);
void ltdcFgSetFrameAddress(LTDCDriver *ltdcp, void *bufferp);
void ltdcFgGetLayerI(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp);
void ltdcFgGetLayer(LTDCDriver *ltdcp, ltdc_laycfg_t *cfgp);
void ltdcFgSetConfigI(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp);
void ltdcFgSetConfig(LTDCDriver *ltdcp, const ltdc_laycfg_t *cfgp);
/* Helper functions.*/
size_t ltdcBitsPerPixel(ltdc_pixfmt_t fmt);
#if LTDC_USE_SOFTWARE_CONVERSIONS || defined(__DOXYGEN__)
ltdc_color_t ltdcFromARGB8888(ltdc_color_t c, ltdc_pixfmt_t fmt);
ltdc_color_t ltdcToARGB8888(ltdc_color_t c, ltdc_pixfmt_t fmt);
#endif /* LTDC_USE_SOFTWARE_CONVERSIONS */
#endif /* STM32_LTDC_H */