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Merged in ambihelical/ugfx/ssd1306 (pull request #15) 

Some improvements to the SSD1306 driver
ugfx_release_2.6
Joel Bodenman 2014-12-13 15:57:45 +01:00
parent 21a26eb762 bdfafbcf9f
commit 262db64844
4 changed files with 90 additions and 93 deletions
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149
boards/addons/gdisp/board_SSD1306_spi.h
View File

@ -16,65 +16,60 @@
#ifndef _GDISP_LLD_BOARD_H
#define _GDISP_LLD_BOARD_H
// The command byte to put on the front of each page line
#define SSD1306_PAGE_PREFIX 0x40 // Co = 0, D/C = 1
// Pin & SPI setup
// For a multiple display configuration we would put all this in a structure and then
// set g->board to that structure.
#define SSD1306_RESET_PORT GPIOB
#define SSD1306_RESET_PIN 5
#define SSD1306_MISO_PORT GPIOB
#define SSD1306_MISO_PIN 8
#define SSD1306_MOSI_PORT GPIOB
#define SSD1306_MOSI_PIN 7
#define SSD1306_SCK_PORT GPIOB
#define SSD1306_SCK_PIN 6
#define SSD1306_CS_PORT GPIOB
#define SSD1306_CS_PIN 5
#define SET_RST palSetPad(SSD1306_RESET_PORT, SSD1306_RESET_PIN);
#define CLR_RST palClearPad(SSD1306_RESET_PORT, SSD1306_RESET_PIN);
#define SPI_DRIVER (&SPID2)
#define SPI_PORT GPIOB
#define SCK_PAD 13
#define MISO_PAD 14
#define MOSI_PAD 15
/*
* SPI1 configuration structure.
* Speed 42MHz, CPHA=0, CPOL=0, 8bits frames, MSb transmitted first.
* The slave select line is the pin 4 on the port GPIOA.
*/
static const SPIConfig spi1config = {
0,
/* HW dependent part.*/
SSD1306_MISO_PORT,
SSD1306_MISO_PIN,
0
//SPI_CR1_BR_0
};
#define CS_PORT GPIOC
#define RESET_PORT GPIOC
#define DNC_PORT GPIOC
#define CS_PAD 7 // 0 = chip selected
#define RESET_PAD 8 // 0 = reset
#define DNC_PAD 9 // control=0, data=1
#if GFX_USE_OS_CHIBIOS
static int32_t thdPriority = 0;
#endif
static SPIConfig spi_cfg = { NULL, CS_PORT, CS_PAD, 0 };
static inline void init_board(GDisplay *g) {
unsigned i;
// As we are not using multiple displays we set g->board to NULL as we don't use it.
g->board = 0;
switch(g->controllerdisplay) {
case 0: // Set up for Display 0
// RESET pin.
palSetPadMode(SSD1306_RESET_PORT, SSD1306_RESET_PIN, PAL_MODE_OUTPUT_PUSHPULL);
palSetPadMode(SSD1306_MISO_PORT, SSD1306_MISO_PIN, PAL_MODE_ALTERNATE(1)|
PAL_STM32_OSPEED_HIGHEST);
palSetPadMode(SSD1306_MOSI_PORT, SSD1306_MOSI_PIN, PAL_MODE_ALTERNATE(1)|
PAL_STM32_OSPEED_HIGHEST);
palSetPadMode(SSD1306_SCK_PORT, SSD1306_SCK_PIN, PAL_MODE_ALTERNATE(1)|
PAL_STM32_OSPEED_HIGHEST);
palSetPad(SSD1306_CS_PORT, SSD1306_CS_PIN);
palSetPadMode(SSD1306_CS_PORT, SSD1306_CS_PIN, PAL_MODE_ALTERNATE(1)|
PAL_STM32_OSPEED_HIGHEST);
spiInit();
break;
(void) g;
g->board = 0;
// Maximum speed of SSD1306 is 10Mhz, so set SPI speed less or = to that.
//
// STM32 specific setup
// STM32_PCLK1 is APB1 frequence in hertz.
// STM32_PCLK2 is APB2 frequence in hertz.
// See manual clock diagram to determine APB1 or APB2 for spi in use.
// SPI2 uses APB1 clock on stm32151
// BR bits divide PCLK as follows
// 000 /2 = 16 MHz
// 001 /4 = 8 MHz
// 010 /8 = 4 MHz
// 011 /16 = 2 MHz
// 100 /32 = 1 MHz
// 101 /64 = 500 kHz
// 110 /128 = 250 kHz
// 111 /256 = 125 kHz
unsigned long spi_clk = STM32_PCLK1 / 2;
unsigned code = 0;
while (spi_clk > 10000000) {
code++;
spi_clk /= 2;
}
spi_cfg.cr1 |= (code << 3);
if (g->controllerdisplay == 0) {
palSetPadMode(SPI_PORT, SCK_PAD, PAL_MODE_ALTERNATE(5)|PAL_STM32_OTYPE_PUSHPULL|PAL_STM32_OSPEED_MID2);
palSetPadMode(SPI_PORT, MOSI_PAD, PAL_MODE_ALTERNATE(5)|PAL_STM32_OTYPE_PUSHPULL|PAL_STM32_OSPEED_MID2);
palSetPadMode(SPI_PORT, MISO_PAD, PAL_MODE_ALTERNATE(5));
palSetPadMode(RESET_PORT, RESET_PAD, PAL_MODE_OUTPUT_PUSHPULL);
palSetPadMode(CS_PORT, CS_PAD, PAL_MODE_OUTPUT_PUSHPULL);
palSetPadMode(DNC_PORT, DNC_PAD, PAL_MODE_OUTPUT_PUSHPULL);
palSetPad(CS_PORT, CS_PAD);
palSetPad(RESET_PORT, RESET_PAD);
palClearPad(DNC_PORT, DNC_PAD);
}
}
@ -82,55 +77,39 @@ static inline void post_init_board(GDisplay *g) {
(void) g;
}
static inline void setpin_reset(GDisplay *g, bool_t state) {
(void) g;
if(state)
CLR_RST
else
SET_RST
palWritePad(RESET_PORT, RESET_PAD, !state);
}
static inline void acquire_bus(GDisplay *g) {
(void) g;
#if GFX_USE_OS_CHIBIOS
thdPriority = (int32_t)chThdGetPriority();
chThdSetPriority(HIGHPRIO);
#endif
spiAcquireBus(&SPID1);
spiAcquireBus(SPI_DRIVER);
spiStart(SPI_DRIVER, &spi_cfg);
spiSelect(SPI_DRIVER);
}
static inline void release_bus(GDisplay *g) {
(void) g;
#if GFX_USE_OS_CHIBIOS
chThdSetPriority(thdPriority);
#endif
spiReleaseBus(&SPID1);
spiUnselect(SPI_DRIVER);
spiStop(SPI_DRIVER);
spiReleaseBus(SPI_DRIVER);
}
static inline void write_cmd(GDisplay *g, uint8_t cmd) {
uint8_t command[2];
(void) g;
command[0] = 0x00; // Co = 0, D/C = 0
command[1] = cmd;
spiStart(&SPID1, &spi1config);
spiSelect(&SPID1);
spiStartSend(&SPID1, 2, command);
spiUnselect(&SPID1);
spiStop(&SPID1);
(void) g;
static uint8_t buf;
palClearPad(DNC_PORT, DNC_PAD);
buf = cmd;
spiSend(SPI_DRIVER, 1, &buf);
}
static inline void write_data(GDisplay *g, uint8_t* data, uint16_t length) {
(void) g;
spiStart(&SPID1, &spi1config);
spiSelect(&SPID1);
spiStartSend(&SPID1, length, data);
spiUnselect(&SPID1);
spiStop(&SPID1);
palSetPad(DNC_PORT, DNC_PAD);
spiSend(SPI_DRIVER, length, data);
}
#endif /* _GDISP_LLD_BOARD_H */

29
drivers/gdisp/SSD1306/gdisp_lld_SSD1306.c
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@ -14,6 +14,7 @@
#include "src/gdisp/driver.h"
#include "board_SSD1306.h"
#include <string.h> // for memset
/*===========================================================================*/
/* Driver local definitions. */
@ -136,16 +137,32 @@ LLDSPEC bool_t gdisp_lld_init(GDisplay *g) {
#if GDISP_HARDWARE_FLUSH
LLDSPEC void gdisp_lld_flush(GDisplay *g) {
unsigned i;
uint8_t * ram;
unsigned pages;
// Don't flush if we don't need it.
if (!(g->flags & GDISP_FLG_NEEDFLUSH))
return;
ram = RAM(g);
pages = GDISP_SCREEN_HEIGHT/8;
acquire_bus(g);
write_cmd(g, SSD1306_SETSTARTLINE | 0);
for(i=0; i < GDISP_SCREEN_HEIGHT/8 * SSD1306_PAGE_WIDTH; i+=SSD1306_PAGE_WIDTH)
write_data(g, RAM(g)+i, SSD1306_PAGE_WIDTH);
while (pages--) {
write_data(g, ram, SSD1306_PAGE_WIDTH);
ram += SSD1306_PAGE_WIDTH;
}
release_bus(g);
}
#endif
#if GDISP_HARDWARE_CLEARS
LLDSPEC void gdisp_lld_clear(GDisplay *g) {
uint8_t fill = (g->p.color == Black) ? 0 : 0xff;
int bytes = GDISP_SCREEN_WIDTH * GDISP_SCREEN_HEIGHT/8;
memset(RAM(g), fill, bytes);
g->flags |= GDISP_FLG_NEEDFLUSH;
}
#endif
@ -168,8 +185,8 @@ LLDSPEC bool_t gdisp_lld_init(GDisplay *g) {
y = GDISP_SCREEN_HEIGHT-1 - g->p.y;
break;
case GDISP_ROTATE_270:
x = GDISP_SCREEN_HEIGHT-1 - g->p.y;
x = g->p.x;
x = GDISP_SCREEN_WIDTH-1 - g->p.y;
y = g->p.x;
break;
}
if (gdispColor2Native(g->p.color) != Black)
@ -199,7 +216,7 @@ LLDSPEC bool_t gdisp_lld_init(GDisplay *g) {
y = GDISP_SCREEN_HEIGHT-1 - g->p.y;
break;
case GDISP_ROTATE_270:
x = GDISP_SCREEN_HEIGHT-1 - g->p.y;
x = GDISP_SCREEN_WIDTH-1 - g->p.y;
y = g->p.x;
break;
}

3
drivers/gdisp/SSD1306/gdisp_lld_config.h
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@ -17,7 +17,8 @@
#define GDISP_HARDWARE_FLUSH TRUE // This controller requires flushing
#define GDISP_HARDWARE_DRAWPIXEL TRUE
#define GDISP_HARDWARE_PIXELREAD TRUE
#define GDISP_HARDWARE_CONTROL TRUE
#define GDISP_HARDWARE_CONTROL TRUE
#define GDISP_HARDWARE_CLEARS TRUE
#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_MONO

2
src/gos/gos_chibios.h
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@ -29,7 +29,7 @@
*/
#if CH_KERNEL_MAJOR == 3
typedef char bool_t;
typedef bool bool_t;
#endif
typedef systime_t delaytime_t;