Merged in ambihelical/ugfx/ssd1306 (pull request #15)
Some improvements to the SSD1306 driver
This commit is contained in:
commit
262db64844
4 changed files with 90 additions and 93 deletions
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@ -16,65 +16,60 @@
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#ifndef _GDISP_LLD_BOARD_H
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#define _GDISP_LLD_BOARD_H
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// The command byte to put on the front of each page line
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#define SSD1306_PAGE_PREFIX 0x40 // Co = 0, D/C = 1
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// Pin & SPI setup
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// For a multiple display configuration we would put all this in a structure and then
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// set g->board to that structure.
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#define SSD1306_RESET_PORT GPIOB
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#define SSD1306_RESET_PIN 5
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#define SSD1306_MISO_PORT GPIOB
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#define SSD1306_MISO_PIN 8
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#define SSD1306_MOSI_PORT GPIOB
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#define SSD1306_MOSI_PIN 7
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#define SSD1306_SCK_PORT GPIOB
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#define SSD1306_SCK_PIN 6
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#define SSD1306_CS_PORT GPIOB
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#define SSD1306_CS_PIN 5
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#define SET_RST palSetPad(SSD1306_RESET_PORT, SSD1306_RESET_PIN);
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#define CLR_RST palClearPad(SSD1306_RESET_PORT, SSD1306_RESET_PIN);
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#define SPI_DRIVER (&SPID2)
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#define SPI_PORT GPIOB
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#define SCK_PAD 13
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#define MISO_PAD 14
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#define MOSI_PAD 15
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/*
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* SPI1 configuration structure.
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* Speed 42MHz, CPHA=0, CPOL=0, 8bits frames, MSb transmitted first.
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* The slave select line is the pin 4 on the port GPIOA.
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*/
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static const SPIConfig spi1config = {
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0,
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/* HW dependent part.*/
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SSD1306_MISO_PORT,
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SSD1306_MISO_PIN,
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0
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//SPI_CR1_BR_0
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};
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#define CS_PORT GPIOC
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#define RESET_PORT GPIOC
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#define DNC_PORT GPIOC
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#define CS_PAD 7 // 0 = chip selected
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#define RESET_PAD 8 // 0 = reset
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#define DNC_PAD 9 // control=0, data=1
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#if GFX_USE_OS_CHIBIOS
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static int32_t thdPriority = 0;
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#endif
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static SPIConfig spi_cfg = { NULL, CS_PORT, CS_PAD, 0 };
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static inline void init_board(GDisplay *g) {
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unsigned i;
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// As we are not using multiple displays we set g->board to NULL as we don't use it.
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g->board = 0;
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switch(g->controllerdisplay) {
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case 0: // Set up for Display 0
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// RESET pin.
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palSetPadMode(SSD1306_RESET_PORT, SSD1306_RESET_PIN, PAL_MODE_OUTPUT_PUSHPULL);
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palSetPadMode(SSD1306_MISO_PORT, SSD1306_MISO_PIN, PAL_MODE_ALTERNATE(1)|
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PAL_STM32_OSPEED_HIGHEST);
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palSetPadMode(SSD1306_MOSI_PORT, SSD1306_MOSI_PIN, PAL_MODE_ALTERNATE(1)|
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PAL_STM32_OSPEED_HIGHEST);
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palSetPadMode(SSD1306_SCK_PORT, SSD1306_SCK_PIN, PAL_MODE_ALTERNATE(1)|
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PAL_STM32_OSPEED_HIGHEST);
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palSetPad(SSD1306_CS_PORT, SSD1306_CS_PIN);
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palSetPadMode(SSD1306_CS_PORT, SSD1306_CS_PIN, PAL_MODE_ALTERNATE(1)|
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PAL_STM32_OSPEED_HIGHEST);
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spiInit();
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break;
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(void) g;
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g->board = 0;
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// Maximum speed of SSD1306 is 10Mhz, so set SPI speed less or = to that.
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//
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// STM32 specific setup
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// STM32_PCLK1 is APB1 frequence in hertz.
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// STM32_PCLK2 is APB2 frequence in hertz.
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// See manual clock diagram to determine APB1 or APB2 for spi in use.
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// SPI2 uses APB1 clock on stm32151
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// BR bits divide PCLK as follows
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// 000 /2 = 16 MHz
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// 001 /4 = 8 MHz
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// 010 /8 = 4 MHz
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// 011 /16 = 2 MHz
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// 100 /32 = 1 MHz
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// 101 /64 = 500 kHz
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// 110 /128 = 250 kHz
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// 111 /256 = 125 kHz
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unsigned long spi_clk = STM32_PCLK1 / 2;
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unsigned code = 0;
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while (spi_clk > 10000000) {
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code++;
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spi_clk /= 2;
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}
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spi_cfg.cr1 |= (code << 3);
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if (g->controllerdisplay == 0) {
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palSetPadMode(SPI_PORT, SCK_PAD, PAL_MODE_ALTERNATE(5)|PAL_STM32_OTYPE_PUSHPULL|PAL_STM32_OSPEED_MID2);
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palSetPadMode(SPI_PORT, MOSI_PAD, PAL_MODE_ALTERNATE(5)|PAL_STM32_OTYPE_PUSHPULL|PAL_STM32_OSPEED_MID2);
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palSetPadMode(SPI_PORT, MISO_PAD, PAL_MODE_ALTERNATE(5));
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palSetPadMode(RESET_PORT, RESET_PAD, PAL_MODE_OUTPUT_PUSHPULL);
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palSetPadMode(CS_PORT, CS_PAD, PAL_MODE_OUTPUT_PUSHPULL);
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palSetPadMode(DNC_PORT, DNC_PAD, PAL_MODE_OUTPUT_PUSHPULL);
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palSetPad(CS_PORT, CS_PAD);
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palSetPad(RESET_PORT, RESET_PAD);
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palClearPad(DNC_PORT, DNC_PAD);
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}
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}
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@ -82,55 +77,39 @@ static inline void post_init_board(GDisplay *g) {
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(void) g;
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}
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static inline void setpin_reset(GDisplay *g, bool_t state) {
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(void) g;
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if(state)
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CLR_RST
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else
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SET_RST
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palWritePad(RESET_PORT, RESET_PAD, !state);
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}
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static inline void acquire_bus(GDisplay *g) {
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(void) g;
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#if GFX_USE_OS_CHIBIOS
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thdPriority = (int32_t)chThdGetPriority();
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chThdSetPriority(HIGHPRIO);
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#endif
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spiAcquireBus(&SPID1);
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spiAcquireBus(SPI_DRIVER);
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spiStart(SPI_DRIVER, &spi_cfg);
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spiSelect(SPI_DRIVER);
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}
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static inline void release_bus(GDisplay *g) {
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(void) g;
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#if GFX_USE_OS_CHIBIOS
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chThdSetPriority(thdPriority);
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#endif
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spiReleaseBus(&SPID1);
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spiUnselect(SPI_DRIVER);
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spiStop(SPI_DRIVER);
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spiReleaseBus(SPI_DRIVER);
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}
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static inline void write_cmd(GDisplay *g, uint8_t cmd) {
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uint8_t command[2];
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(void) g;
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command[0] = 0x00; // Co = 0, D/C = 0
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command[1] = cmd;
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spiStart(&SPID1, &spi1config);
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spiSelect(&SPID1);
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spiStartSend(&SPID1, 2, command);
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spiUnselect(&SPID1);
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spiStop(&SPID1);
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(void) g;
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static uint8_t buf;
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palClearPad(DNC_PORT, DNC_PAD);
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buf = cmd;
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spiSend(SPI_DRIVER, 1, &buf);
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}
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static inline void write_data(GDisplay *g, uint8_t* data, uint16_t length) {
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(void) g;
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spiStart(&SPID1, &spi1config);
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spiSelect(&SPID1);
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spiStartSend(&SPID1, length, data);
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spiUnselect(&SPID1);
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spiStop(&SPID1);
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palSetPad(DNC_PORT, DNC_PAD);
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spiSend(SPI_DRIVER, length, data);
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}
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#endif /* _GDISP_LLD_BOARD_H */
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@ -14,6 +14,7 @@
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#include "src/gdisp/driver.h"
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#include "board_SSD1306.h"
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#include <string.h> // for memset
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/*===========================================================================*/
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/* Driver local definitions. */
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@ -136,16 +137,32 @@ LLDSPEC bool_t gdisp_lld_init(GDisplay *g) {
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#if GDISP_HARDWARE_FLUSH
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LLDSPEC void gdisp_lld_flush(GDisplay *g) {
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unsigned i;
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uint8_t * ram;
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unsigned pages;
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// Don't flush if we don't need it.
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if (!(g->flags & GDISP_FLG_NEEDFLUSH))
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return;
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ram = RAM(g);
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pages = GDISP_SCREEN_HEIGHT/8;
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acquire_bus(g);
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write_cmd(g, SSD1306_SETSTARTLINE | 0);
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for(i=0; i < GDISP_SCREEN_HEIGHT/8 * SSD1306_PAGE_WIDTH; i+=SSD1306_PAGE_WIDTH)
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write_data(g, RAM(g)+i, SSD1306_PAGE_WIDTH);
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while (pages--) {
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write_data(g, ram, SSD1306_PAGE_WIDTH);
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ram += SSD1306_PAGE_WIDTH;
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}
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release_bus(g);
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}
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#endif
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#if GDISP_HARDWARE_CLEARS
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LLDSPEC void gdisp_lld_clear(GDisplay *g) {
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uint8_t fill = (g->p.color == Black) ? 0 : 0xff;
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int bytes = GDISP_SCREEN_WIDTH * GDISP_SCREEN_HEIGHT/8;
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memset(RAM(g), fill, bytes);
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g->flags |= GDISP_FLG_NEEDFLUSH;
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}
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#endif
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@ -168,8 +185,8 @@ LLDSPEC bool_t gdisp_lld_init(GDisplay *g) {
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y = GDISP_SCREEN_HEIGHT-1 - g->p.y;
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break;
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case GDISP_ROTATE_270:
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x = GDISP_SCREEN_HEIGHT-1 - g->p.y;
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x = g->p.x;
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x = GDISP_SCREEN_WIDTH-1 - g->p.y;
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y = g->p.x;
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break;
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}
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if (gdispColor2Native(g->p.color) != Black)
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@ -199,7 +216,7 @@ LLDSPEC bool_t gdisp_lld_init(GDisplay *g) {
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y = GDISP_SCREEN_HEIGHT-1 - g->p.y;
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break;
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case GDISP_ROTATE_270:
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x = GDISP_SCREEN_HEIGHT-1 - g->p.y;
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x = GDISP_SCREEN_WIDTH-1 - g->p.y;
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y = g->p.x;
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break;
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}
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@ -17,7 +17,8 @@
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#define GDISP_HARDWARE_FLUSH TRUE // This controller requires flushing
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#define GDISP_HARDWARE_DRAWPIXEL TRUE
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#define GDISP_HARDWARE_PIXELREAD TRUE
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#define GDISP_HARDWARE_CONTROL TRUE
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#define GDISP_HARDWARE_CONTROL TRUE
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#define GDISP_HARDWARE_CLEARS TRUE
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#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_MONO
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@ -29,7 +29,7 @@
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*/
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#if CH_KERNEL_MAJOR == 3
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typedef char bool_t;
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typedef bool bool_t;
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#endif
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typedef systime_t delaytime_t;
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