diff --git a/boards/base/FireBull-STM32F103-FB/chibios_board/board.mk b/boards/base/FireBull-STM32F103-FB/chibios_board/board.mk
index 25a30fae..5e3e9a35 100755
--- a/boards/base/FireBull-STM32F103-FB/chibios_board/board.mk
+++ b/boards/base/FireBull-STM32F103-FB/chibios_board/board.mk
@@ -1,3 +1,3 @@
-BOARDINC = $(GFXLIB)/boards/base/FireBull-STM32F103-FB/chibios_board
-BOARDSRC = $(BOARDINC)/board.c \
-
+BOARDINC = $(GFXLIB)/boards/base/FireBull-STM32F103-FB/chibios_board
+BOARDSRC = $(BOARDINC)/board.c \
+
diff --git a/boards/base/Marlin/chibios_board/board.c b/boards/base/Marlin/chibios_board/board.c
index 68eccdd6..b1b0db12 100644
--- a/boards/base/Marlin/chibios_board/board.c
+++ b/boards/base/Marlin/chibios_board/board.c
@@ -1,88 +1,88 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-*/
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-/**
- * @brief PAL setup.
- * @details Digital I/O ports static configuration as defined in @p board.h.
- * This variable is used by the HAL when initializing the PAL driver.
- */
-const PALConfig pal_default_config =
-{
- {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
- VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
- {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
- VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
- {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
- VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
- {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
- VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
- {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
- VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
- {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
- VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
- {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
- VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
- {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
- VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
- {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
- VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
-};
-#endif
-
-/**
- * @brief Early initialization code.
- * @details This initialization must be performed just after stack setup
- * and before any other initialization.
- */
-void __early_init(void) {
-
- stm32_clock_init();
-}
-
-#if HAL_USE_SDC
-/*
-* Card detection through the card internal pull-up on D3.
-*/
-bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
-
-(void)sdcp;
-return (bool_t)!palReadPad(GPIOD, GPIOD_SDIO_CD_N);
-}
-
-/*
-* Card write protection detection is not possible, the card is always
-* reported as not protected.
-*/
-bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
-
-(void)sdcp;
-return 0;
-}
-#endif /* HAL_USE_SDC */
-
-/**
- * @brief Board-specific initialization code.
- */
-void boardInit(void) {
-}
+/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC
+/*
+* Card detection through the card internal pull-up on D3.
+*/
+bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+(void)sdcp;
+return (bool_t)!palReadPad(GPIOD, GPIOD_SDIO_CD_N);
+}
+
+/*
+* Card write protection detection is not possible, the card is always
+* reported as not protected.
+*/
+bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+(void)sdcp;
+return 0;
+}
+#endif /* HAL_USE_SDC */
+
+/**
+ * @brief Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/boards/base/Marlin/chibios_board/board.h b/boards/base/Marlin/chibios_board/board.h
index fda33f99..46552496 100644
--- a/boards/base/Marlin/chibios_board/board.h
+++ b/boards/base/Marlin/chibios_board/board.h
@@ -1,1302 +1,1302 @@
-/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see .
-*/
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/*
- * Setup for a generic STM32F4xx board.
- */
-
-/*
- * Board identifier.
- */
-#define BOARD_MARLIN_STM32F417
-#define BOARD_NAME "Marlin STM32F417 board"
-
-/*
- * Ethernet PHY type.
- */
-#define MII_KSZ8051RNL_ID 0x00221550
-#define BOARD_PHY_ID MII_KSZ8051RNL_ID
-#define BOARD_PHY_RMII
-
-/*
- * Board oscillators-related settings.
- */
-#define STM32_LSECLK 0
-#define STM32_HSECLK 16000000
-#define STM32_HSECLK_BYPASS
-
-/*
- * Board voltages.
- * Required for performance limits calculation.
- */
-#define STM32_VDD 300
-
-/*
- * MCU type as defined in the ST header file stm32f4xx.h.
- */
-#define STM32F4XX
-
-/*
- * IO pins assignments.
- */
-#define GPIOA_HEATER_0 0
-#define GPIOA_ETH_REFCLK 1
-#define GPIOA_ETH_MDIO 2
-#define GPIOA_HEATER_1 3
-#define GPIOA_BL 4
-#define GPIOA_CLK 5
-#define GPIOA_Y_B 6
-#define GPIOA_ETH_CRS_DV 7
-#define GPIOA_HBP 8
-#define GPIOA_INTERLOCK 9
-#define GPIOA_PWM_0 10
-#define GPIOA_HD_N 11
-#define GPIOA_HD_P 12
-#define GPIOA_SWDIO 13
-#define GPIOA_SWCLK 14
-#define GPIOA_X_B 15
-
-#define GPIOB_DIR_Z 0
-#define GPIOB_STEP_Z 1
-#define GPIOB_HOME_Y 2
-#define GPIOB_X_A 3
-#define GPIOB_MISO 4
-#define GPIOB_MOSI 5
-#define GPIOB_MB_UART1_TX 6
-#define GPIOB_MB_UART1_RX 7
-#define GPIOB_CAN_RX 8
-#define GPIOB_CAN_TX 9
-#define GPIOB_I2S_SCK 10
-#define GPIOB_NOT_USED_1 11
-#define GPIOB_I2S_WS 12
-#define GPIOB_VBUS_D 13
-#define GPIOB_DD_N 14
-#define GPIOB_DD_P 15
-
-#define GPIOC_ANALOG_1 0
-#define GPIOC_ETH_MDC 1
-#define GPIOC_HOME_Z 2
-#define GPIOC_I2S_SD 3
-#define GPIOC_ETH_RXD0 4
-#define GPIOC_ETH_RXD1 5
-#define GPIOC_SDI_ST 6
-#define GPIOC_Y_A 7
-#define GPIOC_SDIO_D0 8
-#define GPIOC_SDIO_D1 9
-#define GPIOC_SDIO_D2 10
-#define GPIOC_SDIO_D3 11
-#define GPIOC_SDIO_SK 12
-#define GPIOC_PIN13 13
-#define GPIOC_PIN14 14
-#define GPIOC_PIN15 15
-
-#define GPIOD_D2 0
-#define GPIOD_D3 1
-#define GPIOD_SDIO_CMD 2
-#define GPIOD_SDIO_CD_N 3
-#define GPIOD_RDN 4
-#define GPIOD_WRN 5
-#define GPIOD_STEPPER_EN_N 6
-#define GPIOD_POWER_OUT_EN_N 7
-#define GPIOD_D13 8
-#define GPIOD_D14 9
-#define GPIOD_D15 10
-#define GPIOD_P_CN 11
-#define GPIOD_HEATER_2 12
-#define GPIOD_PWM_1 13
-#define GPIOD_D0 14
-#define GPIOD_D1 15
-
-#define GPIOE_STEP_E2 0
-#define GPIOE_DIR_E2 1
-#define GPIOE_INT 2
-#define GPIOE_VMOT_EN 3
-#define GPIOE_LED_STS_1 4
-#define GPIOE_FAN_0 5
-#define GPIOE_FAN_1 6
-#define GPIOE_D4 7
-#define GPIOE_D5 8
-#define GPIOE_D6 9
-#define GPIOE_D7 10
-#define GPIOE_D8 11
-#define GPIOE_D9 12
-#define GPIOE_D10 13
-#define GPIOE_D11 14
-#define GPIOE_D12 15
-
-#define GPIOF_SDA 0
-#define GPIOF_SCL 1
-#define GPIOF_PRE_CHARGE 2
-#define GPIOF_VMOT_MEAS 3
-#define GPIOF_CURR_OUT 4
-#define GPIOF_VIN_MEAS 5
-#define GPIOF_TEMP_E2 6
-#define GPIOF_TEMP_E1 7
-#define GPIOF_TEMP_E0 8
-#define GPIOF_TEMP_HPB 9
-#define GPIOF_PIN10 10
-#define GPIOF_DIR_Y 11
-#define GPIOF_STEP_Y 12
-#define GPIOF_HOME_X 13
-#define GPIOF_MB_CS0_N 14
-#define GPIOF_MB_CS1_N 15
-
-#define GPIOG_DIR_X 0
-#define GPIOG_STEP_X 1
-#define GPIOG_STEP_E0 2
-#define GPIOG_DIR_E0 3
-#define GPIOG_STEP_E1 4
-#define GPIOG_DIR_E1 5
-#define GPIOG_LED_STS_2 6
-#define GPIOG_SCK_ST 7
-#define GPIOG_PIN8 8
-#define GPIOG_SDO_ST 9
-#define GPIOG_CS_N 10
-#define GPIOG_ETH_TXEN 11
-#define GPIOG_CS_ST_N 12
-#define GPIOG_ETH_TXD0 13
-#define GPIOG_ETH_TXD1 14
-#define GPIOG_PIN15 15
-
-#define GPIOH_PIN0 0
-#define GPIOH_PIN1 1
-#define GPIOH_PIN2 2
-#define GPIOH_PIN3 3
-#define GPIOH_PIN4 4
-#define GPIOH_PIN5 5
-#define GPIOH_PIN6 6
-#define GPIOH_PIN7 7
-#define GPIOH_PIN8 8
-#define GPIOH_PIN9 9
-#define GPIOH_PIN10 10
-#define GPIOH_PIN11 11
-#define GPIOH_PIN12 12
-#define GPIOH_PIN13 13
-#define GPIOH_PIN14 14
-#define GPIOH_PIN15 15
-
-#define GPIOI_PIN0 0
-#define GPIOI_PIN1 1
-#define GPIOI_PIN2 2
-#define GPIOI_PIN3 3
-#define GPIOI_PIN4 4
-#define GPIOI_PIN5 5
-#define GPIOI_PIN6 6
-#define GPIOI_PIN7 7
-#define GPIOI_PIN8 8
-#define GPIOI_PIN9 9
-#define GPIOI_PIN10 10
-#define GPIOI_PIN11 11
-#define GPIOI_PIN12 12
-#define GPIOI_PIN13 13
-#define GPIOI_PIN14 14
-#define GPIOI_PIN15 15
-
-
-/*
- * I/O ports initial setup, this configuration is established soon after reset
- * in the initialization code.
- * Please refer to the STM32 Reference Manual for details.
- */
-#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
-#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
-#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
-#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
-#define PIN_ODR_LOW(n) (0U << (n))
-#define PIN_ODR_HIGH(n) (1U << (n))
-#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
-#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
-#define PIN_OSPEED_2M(n) (0U << ((n) * 2))
-#define PIN_OSPEED_25M(n) (1U << ((n) * 2))
-#define PIN_OSPEED_50M(n) (2U << ((n) * 2))
-#define PIN_OSPEED_100M(n) (3U << ((n) * 2))
-#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2))
-#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2))
-#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2))
-#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))
-
-/*
- * GPIOA setup:
- *
- * PA0 - HEATER_0 (output pushpull 2mhz).
- * PA1 - ETH_REFCLK (alternate 11).
- * PA2 - ETH_MDIO (alternate 11).
- * PA3 - HEATER_1 (output pushpull 2mhz).
- * PA4 - BL (output pushpull 2mhz).
- * PA5 - CLK (alternate 5).
- * PA6 - Y_B (alternate 0).
- * PA7 - ETH_CRS_DV (alternate 11).
- * PA8 - HBP (output pushpull 2mhz).
- * PA9 - INTERLOCK (input pull-up).
- * PA10 - PWM_0 (output pushpull 2mhz).
- * PA11 - HD_N (alternate 6).
- * PA12 - HD_P (alternate 10).
- * PA13 - SWDIO (alternate 0).
- * PA14 - SWCLK (alternate 0).
- * PA15 - X_B (alternate 1).
- */
-#define VAL_GPIOA_MODER (PIN_MODE_ALTERNATE(GPIOA_HEATER_0) | \
- PIN_MODE_ALTERNATE(GPIOA_ETH_REFCLK) | \
- PIN_MODE_ALTERNATE(GPIOA_ETH_MDIO) | \
- PIN_MODE_ALTERNATE(GPIOA_HEATER_1) | \
- PIN_MODE_OUTPUT(GPIOA_BL) | \
- PIN_MODE_ALTERNATE(GPIOA_CLK) | \
- PIN_MODE_ALTERNATE(GPIOA_Y_B) | \
- PIN_MODE_ALTERNATE(GPIOA_ETH_CRS_DV) | \
- PIN_MODE_ALTERNATE(GPIOA_HBP) | \
- PIN_MODE_INPUT(GPIOA_INTERLOCK) | \
- PIN_MODE_ALTERNATE(GPIOA_PWM_0) | \
- PIN_MODE_ALTERNATE(GPIOA_HD_N) | \
- PIN_MODE_ALTERNATE(GPIOA_HD_P) | \
- PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
- PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
- PIN_MODE_ALTERNATE(GPIOA_X_B))
-#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_HEATER_0) | \
- PIN_OTYPE_PUSHPULL(GPIOA_ETH_REFCLK) | \
- PIN_OTYPE_PUSHPULL(GPIOA_ETH_MDIO) | \
- PIN_OTYPE_PUSHPULL(GPIOA_HEATER_1) | \
- PIN_OTYPE_PUSHPULL(GPIOA_BL) | \
- PIN_OTYPE_PUSHPULL(GPIOA_CLK) | \
- PIN_OTYPE_PUSHPULL(GPIOA_Y_B) | \
- PIN_OTYPE_PUSHPULL(GPIOA_ETH_CRS_DV) | \
- PIN_OTYPE_PUSHPULL(GPIOA_HBP) | \
- PIN_OTYPE_PUSHPULL(GPIOA_INTERLOCK) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PWM_0) | \
- PIN_OTYPE_PUSHPULL(GPIOA_HD_N) | \
- PIN_OTYPE_PUSHPULL(GPIOA_HD_P) | \
- PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
- PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
- PIN_OTYPE_PUSHPULL(GPIOA_X_B))
-#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_2M(GPIOA_HEATER_0) | \
- PIN_OSPEED_50M(GPIOA_ETH_REFCLK) | \
- PIN_OSPEED_25M(GPIOA_ETH_MDIO) | \
- PIN_OSPEED_2M(GPIOA_HEATER_1) | \
- PIN_OSPEED_2M(GPIOA_BL) | \
- PIN_OSPEED_100M(GPIOA_CLK) | \
- PIN_OSPEED_50M(GPIOA_Y_B) | \
- PIN_OSPEED_50M(GPIOA_ETH_CRS_DV) | \
- PIN_OSPEED_2M(GPIOA_HBP) | \
- PIN_OSPEED_50M(GPIOA_INTERLOCK) | \
- PIN_OSPEED_2M(GPIOA_PWM_0) | \
- PIN_OSPEED_50M(GPIOA_HD_N) | \
- PIN_OSPEED_50M(GPIOA_HD_P) | \
- PIN_OSPEED_50M(GPIOA_SWDIO) | \
- PIN_OSPEED_50M(GPIOA_SWCLK) | \
- PIN_OSPEED_50M(GPIOA_X_B))
-#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_HEATER_0) | \
- PIN_PUPDR_FLOATING(GPIOA_ETH_REFCLK) | \
- PIN_PUPDR_FLOATING(GPIOA_ETH_MDIO) | \
- PIN_PUPDR_FLOATING(GPIOA_HEATER_1) | \
- PIN_PUPDR_FLOATING(GPIOA_BL) | \
- PIN_PUPDR_FLOATING(GPIOA_CLK) | \
- PIN_PUPDR_FLOATING(GPIOA_Y_B) | \
- PIN_PUPDR_FLOATING(GPIOA_ETH_CRS_DV) | \
- PIN_PUPDR_FLOATING(GPIOA_HBP) | \
- PIN_PUPDR_PULLUP(GPIOA_INTERLOCK) | \
- PIN_PUPDR_FLOATING(GPIOA_PWM_0) | \
- PIN_PUPDR_FLOATING(GPIOA_HD_N) | \
- PIN_PUPDR_FLOATING(GPIOA_HD_P) | \
- PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \
- PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \
- PIN_PUPDR_FLOATING(GPIOA_X_B))
-#define VAL_GPIOA_ODR (PIN_ODR_LOW(GPIOA_HEATER_0) | \
- PIN_ODR_LOW(GPIOA_ETH_REFCLK) | \
- PIN_ODR_LOW(GPIOA_ETH_MDIO) | \
- PIN_ODR_LOW(GPIOA_HEATER_1) | \
- PIN_ODR_LOW(GPIOA_BL) | \
- PIN_ODR_LOW(GPIOA_CLK) | \
- PIN_ODR_LOW(GPIOA_Y_B) | \
- PIN_ODR_LOW(GPIOA_ETH_CRS_DV) | \
- PIN_ODR_LOW(GPIOA_HBP) | \
- PIN_ODR_LOW(GPIOA_INTERLOCK) | \
- PIN_ODR_LOW(GPIOA_PWM_0) | \
- PIN_ODR_LOW(GPIOA_HD_N) | \
- PIN_ODR_LOW(GPIOA_HD_P) | \
- PIN_ODR_LOW(GPIOA_SWDIO) | \
- PIN_ODR_LOW(GPIOA_SWCLK) | \
- PIN_ODR_LOW(GPIOA_X_B))
-#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_HEATER_0, 2) | \
- PIN_AFIO_AF(GPIOA_ETH_REFCLK, 11) | \
- PIN_AFIO_AF(GPIOA_ETH_MDIO, 11) | \
- PIN_AFIO_AF(GPIOA_HEATER_1, 2) | \
- PIN_AFIO_AF(GPIOA_BL, 0) | \
- PIN_AFIO_AF(GPIOA_CLK, 5) | \
- PIN_AFIO_AF(GPIOA_Y_B, 0) | \
- PIN_AFIO_AF(GPIOA_ETH_CRS_DV, 11))
-#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_HBP, 1) | \
- PIN_AFIO_AF(GPIOA_INTERLOCK, 0) | \
- PIN_AFIO_AF(GPIOA_PWM_0, 1) | \
- PIN_AFIO_AF(GPIOA_HD_N, 10) | \
- PIN_AFIO_AF(GPIOA_HD_P, 10) | \
- PIN_AFIO_AF(GPIOA_SWDIO, 0) | \
- PIN_AFIO_AF(GPIOA_SWCLK, 0) | \
- PIN_AFIO_AF(GPIOA_X_B, 1))
-
-/*
- * GPIOB setup:
- *
- * PB0 - DIR_Z (output pushpull 2mhz).
- * PB1 - STEP_Z (output pushpull 2mhz).
- * PB2 - HOME_Y (input floating).
- * PB3 - X_A (alternate 1).
- * PB4 - MISO (alternate 5).
- * PB5 - MOSI (alternate 5).
- * PB6 - MB_SCL (alternate 7).
- * PB7 - MB_SDA (alternate 7).
- * PB8 - CAN_RX (input floating).
- * PB9 - CAN_TX (input floating).
- * PB10 - I2S_SCK (alternate 5).
- * PB11 - NOT_USED_1 (input floating).
- * PB12 - I2S_WS (alternate 5).
- * PB13 - VBUS_D (input pull-up).
- * PB14 - DD_N (alternate 12).
- * PB15 - DD_P (alternate 12).
- */
-#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_DIR_Z) | \
- PIN_MODE_OUTPUT(GPIOB_STEP_Z) | \
- PIN_MODE_INPUT(GPIOB_HOME_Y) | \
- PIN_MODE_ALTERNATE(GPIOB_X_A) | \
- PIN_MODE_ALTERNATE(GPIOB_MISO) | \
- PIN_MODE_ALTERNATE(GPIOB_MOSI) | \
- PIN_MODE_ALTERNATE(GPIOB_MB_UART1_TX) |\
- PIN_MODE_ALTERNATE(GPIOB_MB_UART1_RX) |\
- PIN_MODE_INPUT(GPIOB_CAN_RX) | \
- PIN_MODE_INPUT(GPIOB_CAN_TX) | \
- PIN_MODE_ALTERNATE(GPIOB_I2S_SCK) | \
- PIN_MODE_INPUT(GPIOB_NOT_USED_1) | \
- PIN_MODE_ALTERNATE(GPIOB_I2S_WS) | \
- PIN_MODE_INPUT(GPIOB_VBUS_D) | \
- PIN_MODE_ALTERNATE(GPIOB_DD_N) | \
- PIN_MODE_ALTERNATE(GPIOB_DD_P))
-#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_DIR_Z) | \
- PIN_OTYPE_PUSHPULL(GPIOB_STEP_Z) | \
- PIN_OTYPE_PUSHPULL(GPIOB_HOME_Y) | \
- PIN_OTYPE_PUSHPULL(GPIOB_X_A) | \
- PIN_OTYPE_PUSHPULL(GPIOB_MISO) | \
- PIN_OTYPE_PUSHPULL(GPIOB_MOSI) | \
- PIN_OTYPE_OPENDRAIN(GPIOB_MB_UART1_TX) |\
- PIN_OTYPE_OPENDRAIN(GPIOB_MB_UART1_RX) |\
- PIN_OTYPE_PUSHPULL(GPIOB_CAN_RX) | \
- PIN_OTYPE_PUSHPULL(GPIOB_CAN_TX) | \
- PIN_OTYPE_PUSHPULL(GPIOB_I2S_SCK) | \
- PIN_OTYPE_PUSHPULL(GPIOB_NOT_USED_1) | \
- PIN_OTYPE_PUSHPULL(GPIOB_I2S_WS) | \
- PIN_OTYPE_PUSHPULL(GPIOB_VBUS_D) | \
- PIN_OTYPE_PUSHPULL(GPIOB_DD_N) | \
- PIN_OTYPE_PUSHPULL(GPIOB_DD_P))
-#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_2M(GPIOB_DIR_Z) | \
- PIN_OSPEED_2M(GPIOB_STEP_Z) | \
- PIN_OSPEED_50M(GPIOB_HOME_Y) | \
- PIN_OSPEED_50M(GPIOB_X_A) | \
- PIN_OSPEED_100M(GPIOB_MISO) | \
- PIN_OSPEED_100M(GPIOB_MOSI) | \
- PIN_OSPEED_50M(GPIOB_MB_UART1_TX) | \
- PIN_OSPEED_50M(GPIOB_MB_UART1_RX) | \
- PIN_OSPEED_50M(GPIOB_CAN_RX) | \
- PIN_OSPEED_50M(GPIOB_CAN_TX) | \
- PIN_OSPEED_50M(GPIOB_I2S_SCK) | \
- PIN_OSPEED_50M(GPIOB_NOT_USED_1) | \
- PIN_OSPEED_50M(GPIOB_I2S_WS) | \
- PIN_OSPEED_50M(GPIOB_VBUS_D) | \
- PIN_OSPEED_50M(GPIOB_DD_N) | \
- PIN_OSPEED_50M(GPIOB_DD_P))
-#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_DIR_Z) | \
- PIN_PUPDR_FLOATING(GPIOB_STEP_Z) | \
- PIN_PUPDR_FLOATING(GPIOB_HOME_Y) | \
- PIN_PUPDR_FLOATING(GPIOB_X_A) | \
- PIN_PUPDR_FLOATING(GPIOB_MISO) | \
- PIN_PUPDR_FLOATING(GPIOB_MOSI) | \
- PIN_PUPDR_FLOATING(GPIOB_MB_UART1_TX) |\
- PIN_PUPDR_FLOATING(GPIOB_MB_UART1_RX) |\
- PIN_PUPDR_FLOATING(GPIOB_CAN_RX) | \
- PIN_PUPDR_FLOATING(GPIOB_CAN_TX) | \
- PIN_PUPDR_FLOATING(GPIOB_I2S_SCK) | \
- PIN_PUPDR_FLOATING(GPIOB_NOT_USED_1) | \
- PIN_PUPDR_FLOATING(GPIOB_I2S_WS) | \
- PIN_PUPDR_PULLUP(GPIOB_VBUS_D) | \
- PIN_PUPDR_FLOATING(GPIOB_DD_N) | \
- PIN_PUPDR_FLOATING(GPIOB_DD_P))
-#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_DIR_Z) | \
- PIN_ODR_LOW(GPIOB_STEP_Z) | \
- PIN_ODR_LOW(GPIOB_HOME_Y) | \
- PIN_ODR_LOW(GPIOB_X_A) | \
- PIN_ODR_LOW(GPIOB_MISO) | \
- PIN_ODR_LOW(GPIOB_MOSI) | \
- PIN_ODR_LOW(GPIOB_MB_UART1_TX) | \
- PIN_ODR_LOW(GPIOB_MB_UART1_RX) | \
- PIN_ODR_LOW(GPIOB_CAN_RX) | \
- PIN_ODR_LOW(GPIOB_CAN_TX) | \
- PIN_ODR_LOW(GPIOB_I2S_SCK) | \
- PIN_ODR_LOW(GPIOB_NOT_USED_1) | \
- PIN_ODR_LOW(GPIOB_I2S_WS) | \
- PIN_ODR_LOW(GPIOB_VBUS_D) | \
- PIN_ODR_LOW(GPIOB_DD_N) | \
- PIN_ODR_LOW(GPIOB_DD_P))
-#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_DIR_Z, 0) | \
- PIN_AFIO_AF(GPIOB_STEP_Z, 0) | \
- PIN_AFIO_AF(GPIOB_HOME_Y, 0) | \
- PIN_AFIO_AF(GPIOB_X_A, 1) | \
- PIN_AFIO_AF(GPIOB_MISO, 5) | \
- PIN_AFIO_AF(GPIOB_MOSI, 5) | \
- PIN_AFIO_AF(GPIOB_MB_UART1_TX, 4) | \
- PIN_AFIO_AF(GPIOB_MB_UART1_RX, 4))
-#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_CAN_RX, 0) | \
- PIN_AFIO_AF(GPIOB_CAN_TX, 0) | \
- PIN_AFIO_AF(GPIOB_I2S_SCK, 5) | \
- PIN_AFIO_AF(GPIOB_NOT_USED_1, 0) | \
- PIN_AFIO_AF(GPIOB_I2S_WS, 5) | \
- PIN_AFIO_AF(GPIOB_VBUS_D, 0) | \
- PIN_AFIO_AF(GPIOB_DD_N, 12) | \
- PIN_AFIO_AF(GPIOB_DD_P, 12))
-
-/*
- * GPIOC setup:
- *
- * PC0 - ANALOG_1 (input floating).
- * PC1 - ETH_MDC (alternate 11).
- * PC2 - HOME_Z (input floating).
- * PC3 - I2S_SD (alternate 5).
- * PC4 - ETH_RXD0 (alternate 11).
- * PC5 - ETH_RXD1 (alternate 11).
- * PC6 - SDI_ST (alternate 8).
- * PC7 - Y_A (alternate 2).
- * PC8 - SDIO_D0 (alternate 12).
- * PC9 - SDIO_D1 (alternate 12).
- * PC10 - SDIO_D2 (alternate 12).
- * PC11 - SDIO_D3 (alternate 12).
- * PC12 - SDIO_SK (alternate 12).
- * PC13 - P (input floating).
- * PC14 - P (input floating).
- * PC15 - P (input floating).
- */
-#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_ANALOG_1) | \
- PIN_MODE_ALTERNATE(GPIOC_ETH_MDC) | \
- PIN_MODE_INPUT(GPIOC_HOME_Z) | \
- PIN_MODE_ALTERNATE(GPIOC_I2S_SD) | \
- PIN_MODE_ALTERNATE(GPIOC_ETH_RXD0) | \
- PIN_MODE_ALTERNATE(GPIOC_ETH_RXD1) | \
- PIN_MODE_ALTERNATE(GPIOC_SDI_ST) | \
- PIN_MODE_ALTERNATE(GPIOC_Y_A) | \
- PIN_MODE_ALTERNATE(GPIOC_SDIO_D0) | \
- PIN_MODE_ALTERNATE(GPIOC_SDIO_D1) | \
- PIN_MODE_ALTERNATE(GPIOC_SDIO_D2) | \
- PIN_MODE_ALTERNATE(GPIOC_SDIO_D3) | \
- PIN_MODE_ALTERNATE(GPIOC_SDIO_SK) | \
- PIN_MODE_INPUT(GPIOC_PIN13) | \
- PIN_MODE_INPUT(GPIOC_PIN14) | \
- PIN_MODE_INPUT(GPIOC_PIN15))
-#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ANALOG_1) | \
- PIN_OTYPE_PUSHPULL(GPIOC_ETH_MDC) | \
- PIN_OTYPE_PUSHPULL(GPIOC_HOME_Z) | \
- PIN_OTYPE_PUSHPULL(GPIOC_I2S_SD) | \
- PIN_OTYPE_PUSHPULL(GPIOC_ETH_RXD0) | \
- PIN_OTYPE_PUSHPULL(GPIOC_ETH_RXD1) | \
- PIN_OTYPE_PUSHPULL(GPIOC_SDI_ST) | \
- PIN_OTYPE_PUSHPULL(GPIOC_Y_A) | \
- PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D0) | \
- PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D1) | \
- PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D2) | \
- PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D3) | \
- PIN_OTYPE_PUSHPULL(GPIOC_SDIO_SK) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
-#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_50M(GPIOC_ANALOG_1) | \
- PIN_OSPEED_50M(GPIOC_ETH_MDC) | \
- PIN_OSPEED_50M(GPIOC_HOME_Z) | \
- PIN_OSPEED_50M(GPIOC_I2S_SD) | \
- PIN_OSPEED_50M(GPIOC_ETH_RXD0) | \
- PIN_OSPEED_50M(GPIOC_ETH_RXD1) | \
- PIN_OSPEED_50M(GPIOC_SDI_ST) | \
- PIN_OSPEED_50M(GPIOC_Y_A) | \
- PIN_OSPEED_50M(GPIOC_SDIO_D0) | \
- PIN_OSPEED_50M(GPIOC_SDIO_D1) | \
- PIN_OSPEED_50M(GPIOC_SDIO_D2) | \
- PIN_OSPEED_50M(GPIOC_SDIO_D3) | \
- PIN_OSPEED_50M(GPIOC_SDIO_SK) | \
- PIN_OSPEED_50M(GPIOC_PIN13) | \
- PIN_OSPEED_50M(GPIOC_PIN14) | \
- PIN_OSPEED_50M(GPIOC_PIN15))
-#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_ANALOG_1) | \
- PIN_PUPDR_FLOATING(GPIOC_ETH_MDC) | \
- PIN_PUPDR_FLOATING(GPIOC_HOME_Z) | \
- PIN_PUPDR_FLOATING(GPIOC_I2S_SD) | \
- PIN_PUPDR_FLOATING(GPIOC_ETH_RXD0) | \
- PIN_PUPDR_FLOATING(GPIOC_ETH_RXD1) | \
- PIN_PUPDR_FLOATING(GPIOC_SDI_ST) | \
- PIN_PUPDR_FLOATING(GPIOC_Y_A) | \
- PIN_PUPDR_FLOATING(GPIOC_SDIO_D0) | \
- PIN_PUPDR_FLOATING(GPIOC_SDIO_D1) | \
- PIN_PUPDR_FLOATING(GPIOC_SDIO_D2) | \
- PIN_PUPDR_FLOATING(GPIOC_SDIO_D3) | \
- PIN_PUPDR_FLOATING(GPIOC_SDIO_SK) | \
- PIN_PUPDR_FLOATING(GPIOC_PIN13) | \
- PIN_PUPDR_FLOATING(GPIOC_PIN14) | \
- PIN_PUPDR_FLOATING(GPIOC_PIN15))
-#define VAL_GPIOC_ODR (PIN_ODR_LOW(GPIOC_ANALOG_1) | \
- PIN_ODR_LOW(GPIOC_ETH_MDC) | \
- PIN_ODR_LOW(GPIOC_HOME_Z) | \
- PIN_ODR_LOW(GPIOC_I2S_SD) | \
- PIN_ODR_LOW(GPIOC_ETH_RXD0) | \
- PIN_ODR_LOW(GPIOC_ETH_RXD1) | \
- PIN_ODR_LOW(GPIOC_SDI_ST) | \
- PIN_ODR_LOW(GPIOC_Y_A) | \
- PIN_ODR_LOW(GPIOC_SDIO_D0) | \
- PIN_ODR_LOW(GPIOC_SDIO_D1) | \
- PIN_ODR_LOW(GPIOC_SDIO_D2) | \
- PIN_ODR_LOW(GPIOC_SDIO_D3) | \
- PIN_ODR_LOW(GPIOC_SDIO_SK) | \
- PIN_ODR_LOW(GPIOC_PIN13) | \
- PIN_ODR_LOW(GPIOC_PIN14) | \
- PIN_ODR_LOW(GPIOC_PIN15))
-#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ANALOG_1, 0) | \
- PIN_AFIO_AF(GPIOC_ETH_MDC, 11) | \
- PIN_AFIO_AF(GPIOC_HOME_Z, 0) | \
- PIN_AFIO_AF(GPIOC_I2S_SD, 5) | \
- PIN_AFIO_AF(GPIOC_ETH_RXD0, 11) | \
- PIN_AFIO_AF(GPIOC_ETH_RXD1, 11) | \
- PIN_AFIO_AF(GPIOC_SDI_ST, 8) | \
- PIN_AFIO_AF(GPIOC_Y_A, 2))
-#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SDIO_D0, 12) | \
- PIN_AFIO_AF(GPIOC_SDIO_D1, 12) | \
- PIN_AFIO_AF(GPIOC_SDIO_D2, 12) | \
- PIN_AFIO_AF(GPIOC_SDIO_D3, 12) | \
- PIN_AFIO_AF(GPIOC_SDIO_SK, 12) | \
- PIN_AFIO_AF(GPIOC_PIN13, 0) | \
- PIN_AFIO_AF(GPIOC_PIN14, 0) | \
- PIN_AFIO_AF(GPIOC_PIN15, 0))
-
-/*
- * GPIOD setup:
- *
- * PD0 - D2 (alternate 12).
- * PD1 - D3 (alternate 12).
- * PD2 - SDIO_CMD (alternate 12).
- * PD3 - SDIO_CD_N (input floating).
- * PD4 - RDN (alternate 12).
- * PD5 - WRN (alternate 12).
- * PD6 - STEPPER_EN (output pushpull 2mhz).
- * PD7 - POWER_OUT_EN_N (output pushpull 2mhz).
- * PD8 - D13 (alternate 12).
- * PD9 - D14 (alternate 12).
- * PD10 - D15 (alternate 12).
- * PD11 - P_CN (alternate 12).
- * PD12 - HEATER_2 (output pushpull 2mhz).
- * PD13 - PWM_1 (output pushpull 2mhz).
- * PD14 - D0 (alternate 12).
- * PD15 - D1 (alternate 12).
- */
-#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(GPIOD_D2) | \
- PIN_MODE_ALTERNATE(GPIOD_D3) | \
- PIN_MODE_ALTERNATE(GPIOD_SDIO_CMD) | \
- PIN_MODE_INPUT(GPIOD_SDIO_CD_N) | \
- PIN_MODE_ALTERNATE(GPIOD_RDN) | \
- PIN_MODE_ALTERNATE(GPIOD_WRN) | \
- PIN_MODE_OUTPUT(GPIOD_STEPPER_EN_N) | \
- PIN_MODE_OUTPUT(GPIOD_POWER_OUT_EN_N) |\
- PIN_MODE_ALTERNATE(GPIOD_D13) | \
- PIN_MODE_ALTERNATE(GPIOD_D14) | \
- PIN_MODE_ALTERNATE(GPIOD_D15) | \
- PIN_MODE_ALTERNATE(GPIOD_P_CN) | \
- PIN_MODE_ALTERNATE(GPIOD_HEATER_2) | \
- PIN_MODE_ALTERNATE(GPIOD_PWM_1) | \
- PIN_MODE_ALTERNATE(GPIOD_D0) | \
- PIN_MODE_ALTERNATE(GPIOD_D1))
-#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_D2) | \
- PIN_OTYPE_PUSHPULL(GPIOD_D3) | \
- PIN_OTYPE_PUSHPULL(GPIOD_SDIO_CMD) | \
- PIN_OTYPE_PUSHPULL(GPIOD_SDIO_CD_N) | \
- PIN_OTYPE_PUSHPULL(GPIOD_RDN) | \
- PIN_OTYPE_PUSHPULL(GPIOD_WRN) | \
- PIN_OTYPE_PUSHPULL(GPIOD_STEPPER_EN_N) |\
- PIN_OTYPE_PUSHPULL(GPIOD_POWER_OUT_EN_N) |\
- PIN_OTYPE_PUSHPULL(GPIOD_D13) | \
- PIN_OTYPE_PUSHPULL(GPIOD_D14) | \
- PIN_OTYPE_PUSHPULL(GPIOD_D15) | \
- PIN_OTYPE_PUSHPULL(GPIOD_P_CN) | \
- PIN_OTYPE_PUSHPULL(GPIOD_HEATER_2) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PWM_1) | \
- PIN_OTYPE_PUSHPULL(GPIOD_D0) | \
- PIN_OTYPE_PUSHPULL(GPIOD_D1))
-#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_50M(GPIOD_D2) | \
- PIN_OSPEED_50M(GPIOD_D3) | \
- PIN_OSPEED_50M(GPIOD_SDIO_CMD) | \
- PIN_OSPEED_50M(GPIOD_SDIO_CD_N) | \
- PIN_OSPEED_50M(GPIOD_RDN) | \
- PIN_OSPEED_50M(GPIOD_WRN) | \
- PIN_OSPEED_2M(GPIOD_STEPPER_EN_N) | \
- PIN_OSPEED_2M(GPIOD_POWER_OUT_EN_N) | \
- PIN_OSPEED_50M(GPIOD_D13) | \
- PIN_OSPEED_50M(GPIOD_D14) | \
- PIN_OSPEED_50M(GPIOD_D15) | \
- PIN_OSPEED_50M(GPIOD_P_CN) | \
- PIN_OSPEED_2M(GPIOD_HEATER_2) | \
- PIN_OSPEED_2M(GPIOD_PWM_1) | \
- PIN_OSPEED_50M(GPIOD_D0) | \
- PIN_OSPEED_50M(GPIOD_D1))
-#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_D2) | \
- PIN_PUPDR_FLOATING(GPIOD_D3) | \
- PIN_PUPDR_FLOATING(GPIOD_SDIO_CMD) | \
- PIN_PUPDR_FLOATING(GPIOD_SDIO_CD_N) | \
- PIN_PUPDR_FLOATING(GPIOD_RDN) | \
- PIN_PUPDR_FLOATING(GPIOD_WRN) | \
- PIN_PUPDR_FLOATING(GPIOD_STEPPER_EN_N) |\
- PIN_PUPDR_FLOATING(GPIOD_POWER_OUT_EN_N) |\
- PIN_PUPDR_FLOATING(GPIOD_D13) | \
- PIN_PUPDR_FLOATING(GPIOD_D14) | \
- PIN_PUPDR_FLOATING(GPIOD_D15) | \
- PIN_PUPDR_FLOATING(GPIOD_P_CN) | \
- PIN_PUPDR_FLOATING(GPIOD_HEATER_2) | \
- PIN_PUPDR_FLOATING(GPIOD_PWM_1) | \
- PIN_PUPDR_FLOATING(GPIOD_D0) | \
- PIN_PUPDR_FLOATING(GPIOD_D1))
-#define VAL_GPIOD_ODR (PIN_ODR_LOW(GPIOD_D2) | \
- PIN_ODR_LOW(GPIOD_D3) | \
- PIN_ODR_LOW(GPIOD_SDIO_CMD) | \
- PIN_ODR_LOW(GPIOD_SDIO_CD_N) | \
- PIN_ODR_LOW(GPIOD_RDN) | \
- PIN_ODR_LOW(GPIOD_WRN) | \
- PIN_ODR_LOW(GPIOD_STEPPER_EN_N) | \
- PIN_ODR_HIGH(GPIOD_POWER_OUT_EN_N) | \
- PIN_ODR_LOW(GPIOD_D13) | \
- PIN_ODR_LOW(GPIOD_D14) | \
- PIN_ODR_LOW(GPIOD_D15) | \
- PIN_ODR_LOW(GPIOD_P_CN) | \
- PIN_ODR_LOW(GPIOD_HEATER_2) | \
- PIN_ODR_LOW(GPIOD_PWM_1) | \
- PIN_ODR_LOW(GPIOD_D0) | \
- PIN_ODR_LOW(GPIOD_D1))
-#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_D2, 12) | \
- PIN_AFIO_AF(GPIOD_D3, 12) | \
- PIN_AFIO_AF(GPIOD_SDIO_CMD, 12) | \
- PIN_AFIO_AF(GPIOD_SDIO_CD_N, 0) | \
- PIN_AFIO_AF(GPIOD_RDN, 12) | \
- PIN_AFIO_AF(GPIOD_WRN, 12) | \
- PIN_AFIO_AF(GPIOD_STEPPER_EN_N, 0) | \
- PIN_AFIO_AF(GPIOD_POWER_OUT_EN_N, 0))
-#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_D13, 12) | \
- PIN_AFIO_AF(GPIOD_D14, 12) | \
- PIN_AFIO_AF(GPIOD_D15, 12) | \
- PIN_AFIO_AF(GPIOD_P_CN, 12) | \
- PIN_AFIO_AF(GPIOD_HEATER_2, 2) | \
- PIN_AFIO_AF(GPIOD_PWM_1, 2) | \
- PIN_AFIO_AF(GPIOD_D0, 12) | \
- PIN_AFIO_AF(GPIOD_D1, 12))
-
-/*
- * GPIOE setup:
- *
- * PE0 - STEP_E2 (output pushpull 2mhz).
- * PE1 - DIR_E2 (output pushpull 2mhz).
- * PE2 - INT (input pull-up).
- * PE3 - VMOT_EN (output pushpull 2mhz).
- * PE4 - LED_STS_1 (output pushpull 2mhz).
- * PE5 - FAN_0 (output pushpull 2mhz).
- * PE6 - FAN_1 (output pushpull 2mhz).
- * PE7 - D4 (alternate 12).
- * PE8 - D5 (alternate 12).
- * PE9 - D6 (alternate 12).
- * PE10 - D7 (alternate 12).
- * PE11 - D8 (alternate 12).
- * PE12 - D9 (alternate 12).
- * PE13 - D10 (alternate 12).
- * PE14 - D11 (alternate 12).
- * PE15 - D12 (alternate 12).
- */
-#define VAL_GPIOE_MODER (PIN_MODE_OUTPUT(GPIOE_STEP_E2) | \
- PIN_MODE_OUTPUT(GPIOE_DIR_E2) | \
- PIN_MODE_INPUT(GPIOE_INT) | \
- PIN_MODE_OUTPUT(GPIOE_VMOT_EN) | \
- PIN_MODE_OUTPUT(GPIOE_LED_STS_1) | \
- PIN_MODE_ALTERNATE(GPIOE_FAN_0) | \
- PIN_MODE_ALTERNATE(GPIOE_FAN_1) | \
- PIN_MODE_ALTERNATE(GPIOE_D4) | \
- PIN_MODE_ALTERNATE(GPIOE_D5) | \
- PIN_MODE_ALTERNATE(GPIOE_D6) | \
- PIN_MODE_ALTERNATE(GPIOE_D7) | \
- PIN_MODE_ALTERNATE(GPIOE_D8) | \
- PIN_MODE_ALTERNATE(GPIOE_D9) | \
- PIN_MODE_ALTERNATE(GPIOE_D10) | \
- PIN_MODE_ALTERNATE(GPIOE_D11) | \
- PIN_MODE_ALTERNATE(GPIOE_D12))
-#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_STEP_E2) | \
- PIN_OTYPE_PUSHPULL(GPIOE_DIR_E2) | \
- PIN_OTYPE_PUSHPULL(GPIOE_INT) | \
- PIN_OTYPE_PUSHPULL(GPIOE_VMOT_EN) | \
- PIN_OTYPE_PUSHPULL(GPIOE_LED_STS_1) | \
- PIN_OTYPE_PUSHPULL(GPIOE_FAN_0) | \
- PIN_OTYPE_PUSHPULL(GPIOE_FAN_1) | \
- PIN_OTYPE_PUSHPULL(GPIOE_D4) | \
- PIN_OTYPE_PUSHPULL(GPIOE_D5) | \
- PIN_OTYPE_PUSHPULL(GPIOE_D6) | \
- PIN_OTYPE_PUSHPULL(GPIOE_D7) | \
- PIN_OTYPE_PUSHPULL(GPIOE_D8) | \
- PIN_OTYPE_PUSHPULL(GPIOE_D9) | \
- PIN_OTYPE_PUSHPULL(GPIOE_D10) | \
- PIN_OTYPE_PUSHPULL(GPIOE_D11) | \
- PIN_OTYPE_PUSHPULL(GPIOE_D12))
-#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_2M(GPIOE_STEP_E2) | \
- PIN_OSPEED_2M(GPIOE_DIR_E2) | \
- PIN_OSPEED_50M(GPIOE_INT) | \
- PIN_OSPEED_2M(GPIOE_VMOT_EN) | \
- PIN_OSPEED_2M(GPIOE_LED_STS_1) | \
- PIN_OSPEED_2M(GPIOE_FAN_0) | \
- PIN_OSPEED_2M(GPIOE_FAN_1) | \
- PIN_OSPEED_50M(GPIOE_D4) | \
- PIN_OSPEED_50M(GPIOE_D5) | \
- PIN_OSPEED_50M(GPIOE_D6) | \
- PIN_OSPEED_50M(GPIOE_D7) | \
- PIN_OSPEED_50M(GPIOE_D8) | \
- PIN_OSPEED_50M(GPIOE_D9) | \
- PIN_OSPEED_50M(GPIOE_D10) | \
- PIN_OSPEED_50M(GPIOE_D11) | \
- PIN_OSPEED_50M(GPIOE_D12))
-#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_STEP_E2) | \
- PIN_PUPDR_FLOATING(GPIOE_DIR_E2) | \
- PIN_PUPDR_PULLUP(GPIOE_INT) | \
- PIN_PUPDR_FLOATING(GPIOE_VMOT_EN) | \
- PIN_PUPDR_FLOATING(GPIOE_LED_STS_1) | \
- PIN_PUPDR_FLOATING(GPIOE_FAN_0) | \
- PIN_PUPDR_FLOATING(GPIOE_FAN_1) | \
- PIN_PUPDR_FLOATING(GPIOE_D4) | \
- PIN_PUPDR_FLOATING(GPIOE_D5) | \
- PIN_PUPDR_FLOATING(GPIOE_D6) | \
- PIN_PUPDR_FLOATING(GPIOE_D7) | \
- PIN_PUPDR_FLOATING(GPIOE_D8) | \
- PIN_PUPDR_FLOATING(GPIOE_D9) | \
- PIN_PUPDR_FLOATING(GPIOE_D10) | \
- PIN_PUPDR_FLOATING(GPIOE_D11) | \
- PIN_PUPDR_FLOATING(GPIOE_D12))
-#define VAL_GPIOE_ODR (PIN_ODR_LOW(GPIOE_STEP_E2) | \
- PIN_ODR_LOW(GPIOE_DIR_E2) | \
- PIN_ODR_LOW(GPIOE_INT) | \
- PIN_ODR_LOW(GPIOE_VMOT_EN) | \
- PIN_ODR_HIGH(GPIOE_LED_STS_1) | \
- PIN_ODR_LOW(GPIOE_FAN_0) | \
- PIN_ODR_LOW(GPIOE_FAN_1) | \
- PIN_ODR_LOW(GPIOE_D4) | \
- PIN_ODR_LOW(GPIOE_D5) | \
- PIN_ODR_LOW(GPIOE_D6) | \
- PIN_ODR_LOW(GPIOE_D7) | \
- PIN_ODR_LOW(GPIOE_D8) | \
- PIN_ODR_LOW(GPIOE_D9) | \
- PIN_ODR_LOW(GPIOE_D10) | \
- PIN_ODR_LOW(GPIOE_D11) | \
- PIN_ODR_LOW(GPIOE_D12))
-#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_STEP_E2, 0) | \
- PIN_AFIO_AF(GPIOE_DIR_E2, 0) | \
- PIN_AFIO_AF(GPIOE_INT, 0) | \
- PIN_AFIO_AF(GPIOE_VMOT_EN, 0) | \
- PIN_AFIO_AF(GPIOE_LED_STS_1, 0) | \
- PIN_AFIO_AF(GPIOE_FAN_0, 3) | \
- PIN_AFIO_AF(GPIOE_FAN_1, 3) | \
- PIN_AFIO_AF(GPIOE_D4, 12))
-#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_D5, 12) | \
- PIN_AFIO_AF(GPIOE_D6, 12) | \
- PIN_AFIO_AF(GPIOE_D7, 12) | \
- PIN_AFIO_AF(GPIOE_D8, 12) | \
- PIN_AFIO_AF(GPIOE_D9, 12) | \
- PIN_AFIO_AF(GPIOE_D10, 12) | \
- PIN_AFIO_AF(GPIOE_D11, 12) | \
- PIN_AFIO_AF(GPIOE_D12, 12))
-
-/*
- * GPIOF setup:
- *
- * PF0 - SDA (alternate 4).
- * PF1 - SCL (alternate 4).
- * PF2 - PRE_CHARGE (output pushpull 2mhz).
- * PF3 - VMOT_MEAS (analog).
- * PF4 - CURR_OUT (analog).
- * PF5 - VIN_MEAS (analog).
- * PF6 - TEMP_E2 (analog).
- * PF7 - TEMP_E1 (analog).
- * PF8 - TEMP_E0 (analog).
- * PF9 - TEMP_HPB (analog).
- * PF10 - P (input pull-up).
- * PF11 - DIR_Y (output pushpull 2mhz).
- * PF12 - STEP_Y (output pushpull 2mhz).
- * PF13 - HOME_X (input floating).
- * PF14 - MB_CS0_N (output pushpull 25mhz).
- * PF15 - MB_CS1_N (output pushpull 25mhz).
- */
-#define VAL_GPIOF_MODER (PIN_MODE_ALTERNATE(GPIOF_SDA) | \
- PIN_MODE_ALTERNATE(GPIOF_SCL) | \
- PIN_MODE_OUTPUT(GPIOF_PRE_CHARGE) | \
- PIN_MODE_ANALOG(GPIOF_VMOT_MEAS) | \
- PIN_MODE_ANALOG(GPIOF_CURR_OUT) | \
- PIN_MODE_ANALOG(GPIOF_VIN_MEAS) | \
- PIN_MODE_ANALOG(GPIOF_TEMP_E2) | \
- PIN_MODE_ANALOG(GPIOF_TEMP_E1) | \
- PIN_MODE_ANALOG(GPIOF_TEMP_E0) | \
- PIN_MODE_ANALOG(GPIOF_TEMP_HPB) | \
- PIN_MODE_INPUT(GPIOF_PIN10) | \
- PIN_MODE_OUTPUT(GPIOF_DIR_Y) | \
- PIN_MODE_OUTPUT(GPIOF_STEP_Y) | \
- PIN_MODE_INPUT(GPIOF_HOME_X) | \
- PIN_MODE_OUTPUT(GPIOF_MB_CS0_N) | \
- PIN_MODE_OUTPUT(GPIOF_MB_CS1_N))
-#define VAL_GPIOF_OTYPER (PIN_OTYPE_OPENDRAIN(GPIOF_SDA) | \
- PIN_OTYPE_OPENDRAIN(GPIOF_SCL) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PRE_CHARGE) | \
- PIN_OTYPE_PUSHPULL(GPIOF_VMOT_MEAS) | \
- PIN_OTYPE_PUSHPULL(GPIOF_CURR_OUT) | \
- PIN_OTYPE_PUSHPULL(GPIOF_VIN_MEAS) | \
- PIN_OTYPE_PUSHPULL(GPIOF_TEMP_E2) | \
- PIN_OTYPE_PUSHPULL(GPIOF_TEMP_E1) | \
- PIN_OTYPE_PUSHPULL(GPIOF_TEMP_E0) | \
- PIN_OTYPE_PUSHPULL(GPIOF_TEMP_HPB) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOF_DIR_Y) | \
- PIN_OTYPE_PUSHPULL(GPIOF_STEP_Y) | \
- PIN_OTYPE_PUSHPULL(GPIOF_HOME_X) | \
- PIN_OTYPE_PUSHPULL(GPIOF_MB_CS0_N) | \
- PIN_OTYPE_PUSHPULL(GPIOF_MB_CS1_N))
-#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_50M(GPIOF_SDA) | \
- PIN_OSPEED_50M(GPIOF_SCL) | \
- PIN_OSPEED_2M(GPIOF_PRE_CHARGE) | \
- PIN_OSPEED_50M(GPIOF_VMOT_MEAS) | \
- PIN_OSPEED_50M(GPIOF_CURR_OUT) | \
- PIN_OSPEED_50M(GPIOF_VIN_MEAS) | \
- PIN_OSPEED_50M(GPIOF_TEMP_E2) | \
- PIN_OSPEED_50M(GPIOF_TEMP_E1) | \
- PIN_OSPEED_50M(GPIOF_TEMP_E0) | \
- PIN_OSPEED_50M(GPIOF_TEMP_HPB) | \
- PIN_OSPEED_2M(GPIOF_PIN10) | \
- PIN_OSPEED_2M(GPIOF_DIR_Y) | \
- PIN_OSPEED_2M(GPIOF_STEP_Y) | \
- PIN_OSPEED_50M(GPIOF_HOME_X) | \
- PIN_OSPEED_100M(GPIOF_MB_CS0_N) | \
- PIN_OSPEED_25M(GPIOF_MB_CS1_N))
-#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_SDA) | \
- PIN_PUPDR_FLOATING(GPIOF_SCL) | \
- PIN_PUPDR_FLOATING(GPIOF_PRE_CHARGE) | \
- PIN_PUPDR_FLOATING(GPIOF_VMOT_MEAS) | \
- PIN_PUPDR_FLOATING(GPIOF_CURR_OUT) | \
- PIN_PUPDR_FLOATING(GPIOF_VIN_MEAS) | \
- PIN_PUPDR_FLOATING(GPIOF_TEMP_E2) | \
- PIN_PUPDR_FLOATING(GPIOF_TEMP_E1) | \
- PIN_PUPDR_FLOATING(GPIOF_TEMP_E0) | \
- PIN_PUPDR_FLOATING(GPIOF_TEMP_HPB) | \
- PIN_PUPDR_PULLUP(GPIOF_PIN10) | \
- PIN_PUPDR_FLOATING(GPIOF_DIR_Y) | \
- PIN_PUPDR_FLOATING(GPIOF_STEP_Y) | \
- PIN_PUPDR_FLOATING(GPIOF_HOME_X) | \
- PIN_PUPDR_FLOATING(GPIOF_MB_CS0_N) | \
- PIN_PUPDR_FLOATING(GPIOF_MB_CS1_N))
-#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_SDA) | \
- PIN_ODR_HIGH(GPIOF_SCL) | \
- PIN_ODR_LOW(GPIOF_PRE_CHARGE) | \
- PIN_ODR_LOW(GPIOF_VMOT_MEAS) | \
- PIN_ODR_LOW(GPIOF_CURR_OUT) | \
- PIN_ODR_LOW(GPIOF_VIN_MEAS) | \
- PIN_ODR_LOW(GPIOF_TEMP_E2) | \
- PIN_ODR_LOW(GPIOF_TEMP_E1) | \
- PIN_ODR_LOW(GPIOF_TEMP_E0) | \
- PIN_ODR_LOW(GPIOF_TEMP_HPB) | \
- PIN_ODR_LOW(GPIOF_PIN10) | \
- PIN_ODR_LOW(GPIOF_DIR_Y) | \
- PIN_ODR_LOW(GPIOF_STEP_Y) | \
- PIN_ODR_LOW(GPIOF_HOME_X) | \
- PIN_ODR_HIGH(GPIOF_MB_CS0_N) | \
- PIN_ODR_LOW(GPIOF_MB_CS1_N))
-#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_SDA, 4) | \
- PIN_AFIO_AF(GPIOF_SCL, 4) | \
- PIN_AFIO_AF(GPIOF_PRE_CHARGE, 0) | \
- PIN_AFIO_AF(GPIOF_VMOT_MEAS, 0) | \
- PIN_AFIO_AF(GPIOF_CURR_OUT, 0) | \
- PIN_AFIO_AF(GPIOF_VIN_MEAS, 0) | \
- PIN_AFIO_AF(GPIOF_TEMP_E2, 0) | \
- PIN_AFIO_AF(GPIOF_TEMP_E1, 0))
-#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_TEMP_E0, 0) | \
- PIN_AFIO_AF(GPIOF_TEMP_HPB, 0) | \
- PIN_AFIO_AF(GPIOF_PIN10, 0) | \
- PIN_AFIO_AF(GPIOF_DIR_Y, 0) | \
- PIN_AFIO_AF(GPIOF_STEP_Y, 0) | \
- PIN_AFIO_AF(GPIOF_HOME_X, 0) | \
- PIN_AFIO_AF(GPIOF_MB_CS0_N, 0) | \
- PIN_AFIO_AF(GPIOF_MB_CS1_N, 0))
-
-/*
- * GPIOG setup:
- *
- * PG0 - DIR_X (output pushpull 2mhz).
- * PG1 - STEP_X (output pushpull 2mhz).
- * PG2 - STEP_E0 (output pushpull 2mhz).
- * PG3 - DIR_E0 (output pushpull 2mhz).
- * PG4 - STEP_E1 (output pushpull 2mhz).
- * PG5 - DIR_E1 (output pushpull 2mhz).
- * PG6 - LED_STS_2 (output pushpull 2mhz).
- * PG7 - SCK_ST (alternate 8).
- * PG8 - P (input floating).
- * PG9 - SDO_ST (alternate 8).
- * PG10 - CS_N (input floating).
- * PG11 - ETH_TXEN (alternate 11).
- * PG12 - CS_ST_N (output pushpull 25mhz).
- * PG13 - ETH_TXD0 (alternate 11).
- * PG14 - ETH_TXD1 (alternate 11).
- * PG15 - P (input pull-up).
- */
-#define VAL_GPIOG_MODER (PIN_MODE_OUTPUT(GPIOG_DIR_X) | \
- PIN_MODE_OUTPUT(GPIOG_STEP_X) | \
- PIN_MODE_OUTPUT(GPIOG_STEP_E0) | \
- PIN_MODE_OUTPUT(GPIOG_DIR_E0) | \
- PIN_MODE_OUTPUT(GPIOG_STEP_E1) | \
- PIN_MODE_OUTPUT(GPIOG_DIR_E1) | \
- PIN_MODE_OUTPUT(GPIOG_LED_STS_2) | \
- PIN_MODE_ALTERNATE(GPIOG_SCK_ST) | \
- PIN_MODE_INPUT(GPIOG_PIN8) | \
- PIN_MODE_ALTERNATE(GPIOG_SDO_ST) | \
- PIN_MODE_INPUT(GPIOG_CS_N) | \
- PIN_MODE_ALTERNATE(GPIOG_ETH_TXEN) | \
- PIN_MODE_OUTPUT(GPIOG_CS_ST_N) | \
- PIN_MODE_ALTERNATE(GPIOG_ETH_TXD0) | \
- PIN_MODE_ALTERNATE(GPIOG_ETH_TXD1) | \
- PIN_MODE_INPUT(GPIOG_PIN15))
-#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_DIR_X) | \
- PIN_OTYPE_PUSHPULL(GPIOG_STEP_X) | \
- PIN_OTYPE_PUSHPULL(GPIOG_STEP_E0) | \
- PIN_OTYPE_PUSHPULL(GPIOG_DIR_E0) | \
- PIN_OTYPE_PUSHPULL(GPIOG_STEP_E1) | \
- PIN_OTYPE_PUSHPULL(GPIOG_DIR_E1) | \
- PIN_OTYPE_PUSHPULL(GPIOG_LED_STS_2) | \
- PIN_OTYPE_PUSHPULL(GPIOG_SCK_ST) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOG_SDO_ST) | \
- PIN_OTYPE_PUSHPULL(GPIOG_CS_N) | \
- PIN_OTYPE_PUSHPULL(GPIOG_ETH_TXEN) | \
- PIN_OTYPE_PUSHPULL(GPIOG_CS_ST_N) | \
- PIN_OTYPE_PUSHPULL(GPIOG_ETH_TXD0) | \
- PIN_OTYPE_PUSHPULL(GPIOG_ETH_TXD1) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
-#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_2M(GPIOG_DIR_X) | \
- PIN_OSPEED_2M(GPIOG_STEP_X) | \
- PIN_OSPEED_2M(GPIOG_STEP_E0) | \
- PIN_OSPEED_2M(GPIOG_DIR_E0) | \
- PIN_OSPEED_2M(GPIOG_STEP_E1) | \
- PIN_OSPEED_2M(GPIOG_DIR_E1) | \
- PIN_OSPEED_2M(GPIOG_LED_STS_2) | \
- PIN_OSPEED_50M(GPIOG_SCK_ST) | \
- PIN_OSPEED_50M(GPIOG_PIN8) | \
- PIN_OSPEED_50M(GPIOG_SDO_ST) | \
- PIN_OSPEED_50M(GPIOG_CS_N) | \
- PIN_OSPEED_50M(GPIOG_ETH_TXEN) | \
- PIN_OSPEED_25M(GPIOG_CS_ST_N) | \
- PIN_OSPEED_50M(GPIOG_ETH_TXD0) | \
- PIN_OSPEED_50M(GPIOG_ETH_TXD1) | \
- PIN_OSPEED_2M(GPIOG_PIN15))
-#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_DIR_X) | \
- PIN_PUPDR_FLOATING(GPIOG_STEP_X) | \
- PIN_PUPDR_FLOATING(GPIOG_STEP_E0) | \
- PIN_PUPDR_FLOATING(GPIOG_DIR_E0) | \
- PIN_PUPDR_FLOATING(GPIOG_STEP_E1) | \
- PIN_PUPDR_FLOATING(GPIOG_DIR_E1) | \
- PIN_PUPDR_FLOATING(GPIOG_LED_STS_2) | \
- PIN_PUPDR_FLOATING(GPIOG_SCK_ST) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN8) | \
- PIN_PUPDR_FLOATING(GPIOG_SDO_ST) | \
- PIN_PUPDR_FLOATING(GPIOG_CS_N) | \
- PIN_PUPDR_FLOATING(GPIOG_ETH_TXEN) | \
- PIN_PUPDR_FLOATING(GPIOG_CS_ST_N) | \
- PIN_PUPDR_FLOATING(GPIOG_ETH_TXD0) | \
- PIN_PUPDR_FLOATING(GPIOG_ETH_TXD1) | \
- PIN_PUPDR_PULLUP(GPIOG_PIN15))
-#define VAL_GPIOG_ODR (PIN_ODR_LOW(GPIOG_DIR_X) | \
- PIN_ODR_LOW(GPIOG_STEP_X) | \
- PIN_ODR_LOW(GPIOG_STEP_E0) | \
- PIN_ODR_LOW(GPIOG_DIR_E0) | \
- PIN_ODR_LOW(GPIOG_STEP_E1) | \
- PIN_ODR_LOW(GPIOG_DIR_E1) | \
- PIN_ODR_LOW(GPIOG_LED_STS_2) | \
- PIN_ODR_LOW(GPIOG_SCK_ST) | \
- PIN_ODR_LOW(GPIOG_PIN8) | \
- PIN_ODR_LOW(GPIOG_SDO_ST) | \
- PIN_ODR_LOW(GPIOG_CS_N) | \
- PIN_ODR_LOW(GPIOG_ETH_TXEN) | \
- PIN_ODR_HIGH(GPIOG_CS_ST_N) | \
- PIN_ODR_LOW(GPIOG_ETH_TXD0) | \
- PIN_ODR_LOW(GPIOG_ETH_TXD1) | \
- PIN_ODR_LOW(GPIOG_PIN15))
-#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_DIR_X, 0) | \
- PIN_AFIO_AF(GPIOG_STEP_X, 0) | \
- PIN_AFIO_AF(GPIOG_STEP_E0, 0) | \
- PIN_AFIO_AF(GPIOG_DIR_E0, 0) | \
- PIN_AFIO_AF(GPIOG_STEP_E1, 0) | \
- PIN_AFIO_AF(GPIOG_DIR_E1, 0) | \
- PIN_AFIO_AF(GPIOG_LED_STS_2, 0) | \
- PIN_AFIO_AF(GPIOG_SCK_ST, 8))
-#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \
- PIN_AFIO_AF(GPIOG_SDO_ST, 8) | \
- PIN_AFIO_AF(GPIOG_CS_N, 12) | \
- PIN_AFIO_AF(GPIOG_ETH_TXEN, 11) | \
- PIN_AFIO_AF(GPIOG_CS_ST_N, 0) | \
- PIN_AFIO_AF(GPIOG_ETH_TXD0, 11) | \
- PIN_AFIO_AF(GPIOG_ETH_TXD1, 11) | \
- PIN_AFIO_AF(GPIOG_PIN15, 0))
-
-/*
- * GPIOH setup:
- *
- * PH0 - P (input pull-up).
- * PH1 - P (input pull-up).
- * PH2 - P (input pull-up).
- * PH3 - P (input pull-up).
- * PH4 - P (input pull-up).
- * PH5 - P (input pull-up).
- * PH6 - P (input pull-up).
- * PH7 - P (input pull-up).
- * PH8 - P (input pull-up).
- * PH9 - P (input pull-up).
- * PH10 - P (input pull-up).
- * PH11 - P (input pull-up).
- * PH12 - P (input pull-up).
- * PH13 - P (input pull-up).
- * PH14 - P (input pull-up).
- * PH15 - P (input pull-up).
- */
-#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_PIN0) | \
- PIN_MODE_INPUT(GPIOH_PIN1) | \
- PIN_MODE_INPUT(GPIOH_PIN2) | \
- PIN_MODE_INPUT(GPIOH_PIN3) | \
- PIN_MODE_INPUT(GPIOH_PIN4) | \
- PIN_MODE_INPUT(GPIOH_PIN5) | \
- PIN_MODE_INPUT(GPIOH_PIN6) | \
- PIN_MODE_INPUT(GPIOH_PIN7) | \
- PIN_MODE_INPUT(GPIOH_PIN8) | \
- PIN_MODE_INPUT(GPIOH_PIN9) | \
- PIN_MODE_INPUT(GPIOH_PIN10) | \
- PIN_MODE_INPUT(GPIOH_PIN11) | \
- PIN_MODE_INPUT(GPIOH_PIN12) | \
- PIN_MODE_INPUT(GPIOH_PIN13) | \
- PIN_MODE_INPUT(GPIOH_PIN14) | \
- PIN_MODE_INPUT(GPIOH_PIN15))
-#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_PIN0) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
-#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_2M(GPIOH_PIN0) | \
- PIN_OSPEED_2M(GPIOH_PIN1) | \
- PIN_OSPEED_2M(GPIOH_PIN2) | \
- PIN_OSPEED_2M(GPIOH_PIN3) | \
- PIN_OSPEED_2M(GPIOH_PIN4) | \
- PIN_OSPEED_2M(GPIOH_PIN5) | \
- PIN_OSPEED_2M(GPIOH_PIN6) | \
- PIN_OSPEED_2M(GPIOH_PIN7) | \
- PIN_OSPEED_2M(GPIOH_PIN8) | \
- PIN_OSPEED_2M(GPIOH_PIN9) | \
- PIN_OSPEED_2M(GPIOH_PIN10) | \
- PIN_OSPEED_2M(GPIOH_PIN11) | \
- PIN_OSPEED_2M(GPIOH_PIN12) | \
- PIN_OSPEED_2M(GPIOH_PIN13) | \
- PIN_OSPEED_2M(GPIOH_PIN14) | \
- PIN_OSPEED_2M(GPIOH_PIN15))
-#define VAL_GPIOH_PUPDR (PIN_PUPDR_PULLUP(GPIOH_PIN0) | \
- PIN_PUPDR_PULLUP(GPIOH_PIN1) | \
- PIN_PUPDR_PULLUP(GPIOH_PIN2) | \
- PIN_PUPDR_PULLUP(GPIOH_PIN3) | \
- PIN_PUPDR_PULLUP(GPIOH_PIN4) | \
- PIN_PUPDR_PULLUP(GPIOH_PIN5) | \
- PIN_PUPDR_PULLUP(GPIOH_PIN6) | \
- PIN_PUPDR_PULLUP(GPIOH_PIN7) | \
- PIN_PUPDR_PULLUP(GPIOH_PIN8) | \
- PIN_PUPDR_PULLUP(GPIOH_PIN9) | \
- PIN_PUPDR_PULLUP(GPIOH_PIN10) | \
- PIN_PUPDR_PULLUP(GPIOH_PIN11) | \
- PIN_PUPDR_PULLUP(GPIOH_PIN12) | \
- PIN_PUPDR_PULLUP(GPIOH_PIN13) | \
- PIN_PUPDR_PULLUP(GPIOH_PIN14) | \
- PIN_PUPDR_PULLUP(GPIOH_PIN15))
-#define VAL_GPIOH_ODR (PIN_ODR_LOW(GPIOH_PIN0) | \
- PIN_ODR_LOW(GPIOH_PIN1) | \
- PIN_ODR_LOW(GPIOH_PIN2) | \
- PIN_ODR_LOW(GPIOH_PIN3) | \
- PIN_ODR_LOW(GPIOH_PIN4) | \
- PIN_ODR_LOW(GPIOH_PIN5) | \
- PIN_ODR_LOW(GPIOH_PIN6) | \
- PIN_ODR_LOW(GPIOH_PIN7) | \
- PIN_ODR_LOW(GPIOH_PIN8) | \
- PIN_ODR_LOW(GPIOH_PIN9) | \
- PIN_ODR_LOW(GPIOH_PIN10) | \
- PIN_ODR_LOW(GPIOH_PIN11) | \
- PIN_ODR_LOW(GPIOH_PIN12) | \
- PIN_ODR_LOW(GPIOH_PIN13) | \
- PIN_ODR_LOW(GPIOH_PIN14) | \
- PIN_ODR_LOW(GPIOH_PIN15))
-#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_PIN0, 0) | \
- PIN_AFIO_AF(GPIOH_PIN1, 0) | \
- PIN_AFIO_AF(GPIOH_PIN2, 0) | \
- PIN_AFIO_AF(GPIOH_PIN3, 0) | \
- PIN_AFIO_AF(GPIOH_PIN4, 0) | \
- PIN_AFIO_AF(GPIOH_PIN5, 0) | \
- PIN_AFIO_AF(GPIOH_PIN6, 0) | \
- PIN_AFIO_AF(GPIOH_PIN7, 0))
-#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \
- PIN_AFIO_AF(GPIOH_PIN9, 0) | \
- PIN_AFIO_AF(GPIOH_PIN10, 0) | \
- PIN_AFIO_AF(GPIOH_PIN11, 0) | \
- PIN_AFIO_AF(GPIOH_PIN12, 0) | \
- PIN_AFIO_AF(GPIOH_PIN13, 0) | \
- PIN_AFIO_AF(GPIOH_PIN14, 0) | \
- PIN_AFIO_AF(GPIOH_PIN15, 0))
-
-/*
- * GPIOI setup:
- *
- * PI0 - P (input pull-up).
- * PI1 - P (input pull-up).
- * PI2 - P (input pull-up).
- * PI3 - P (input pull-up).
- * PI4 - P (input pull-up).
- * PI5 - P (input pull-up).
- * PI6 - P (input pull-up).
- * PI7 - P (input pull-up).
- * PI8 - P (input pull-up).
- * PI9 - P (input pull-up).
- * PI10 - P (input pull-up).
- * PI11 - P (input pull-up).
- * PI12 - P (input pull-up).
- * PI13 - P (input pull-up).
- * PI14 - P (input pull-up).
- * PI15 - P (input pull-up).
- */
-#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \
- PIN_MODE_INPUT(GPIOI_PIN1) | \
- PIN_MODE_INPUT(GPIOI_PIN2) | \
- PIN_MODE_INPUT(GPIOI_PIN3) | \
- PIN_MODE_INPUT(GPIOI_PIN4) | \
- PIN_MODE_INPUT(GPIOI_PIN5) | \
- PIN_MODE_INPUT(GPIOI_PIN6) | \
- PIN_MODE_INPUT(GPIOI_PIN7) | \
- PIN_MODE_INPUT(GPIOI_PIN8) | \
- PIN_MODE_INPUT(GPIOI_PIN9) | \
- PIN_MODE_INPUT(GPIOI_PIN10) | \
- PIN_MODE_INPUT(GPIOI_PIN11) | \
- PIN_MODE_INPUT(GPIOI_PIN12) | \
- PIN_MODE_INPUT(GPIOI_PIN13) | \
- PIN_MODE_INPUT(GPIOI_PIN14) | \
- PIN_MODE_INPUT(GPIOI_PIN15))
-#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
-#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_2M(GPIOI_PIN0) | \
- PIN_OSPEED_2M(GPIOI_PIN1) | \
- PIN_OSPEED_2M(GPIOI_PIN2) | \
- PIN_OSPEED_2M(GPIOI_PIN3) | \
- PIN_OSPEED_2M(GPIOI_PIN4) | \
- PIN_OSPEED_2M(GPIOI_PIN5) | \
- PIN_OSPEED_2M(GPIOI_PIN6) | \
- PIN_OSPEED_2M(GPIOI_PIN7) | \
- PIN_OSPEED_2M(GPIOI_PIN8) | \
- PIN_OSPEED_2M(GPIOI_PIN9) | \
- PIN_OSPEED_2M(GPIOI_PIN10) | \
- PIN_OSPEED_2M(GPIOI_PIN11) | \
- PIN_OSPEED_2M(GPIOI_PIN12) | \
- PIN_OSPEED_2M(GPIOI_PIN13) | \
- PIN_OSPEED_2M(GPIOI_PIN14) | \
- PIN_OSPEED_2M(GPIOI_PIN15))
-#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \
- PIN_PUPDR_PULLUP(GPIOI_PIN1) | \
- PIN_PUPDR_PULLUP(GPIOI_PIN2) | \
- PIN_PUPDR_PULLUP(GPIOI_PIN3) | \
- PIN_PUPDR_PULLUP(GPIOI_PIN4) | \
- PIN_PUPDR_PULLUP(GPIOI_PIN5) | \
- PIN_PUPDR_PULLUP(GPIOI_PIN6) | \
- PIN_PUPDR_PULLUP(GPIOI_PIN7) | \
- PIN_PUPDR_PULLUP(GPIOI_PIN8) | \
- PIN_PUPDR_PULLUP(GPIOI_PIN9) | \
- PIN_PUPDR_PULLUP(GPIOI_PIN10) | \
- PIN_PUPDR_PULLUP(GPIOI_PIN11) | \
- PIN_PUPDR_PULLUP(GPIOI_PIN12) | \
- PIN_PUPDR_PULLUP(GPIOI_PIN13) | \
- PIN_PUPDR_PULLUP(GPIOI_PIN14) | \
- PIN_PUPDR_PULLUP(GPIOI_PIN15))
-#define VAL_GPIOI_ODR (PIN_ODR_LOW(GPIOI_PIN0) | \
- PIN_ODR_LOW(GPIOI_PIN1) | \
- PIN_ODR_LOW(GPIOI_PIN2) | \
- PIN_ODR_LOW(GPIOI_PIN3) | \
- PIN_ODR_LOW(GPIOI_PIN4) | \
- PIN_ODR_LOW(GPIOI_PIN5) | \
- PIN_ODR_LOW(GPIOI_PIN6) | \
- PIN_ODR_LOW(GPIOI_PIN7) | \
- PIN_ODR_LOW(GPIOI_PIN8) | \
- PIN_ODR_LOW(GPIOI_PIN9) | \
- PIN_ODR_LOW(GPIOI_PIN10) | \
- PIN_ODR_LOW(GPIOI_PIN11) | \
- PIN_ODR_LOW(GPIOI_PIN12) | \
- PIN_ODR_LOW(GPIOI_PIN13) | \
- PIN_ODR_LOW(GPIOI_PIN14) | \
- PIN_ODR_LOW(GPIOI_PIN15))
-#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \
- PIN_AFIO_AF(GPIOI_PIN1, 0) | \
- PIN_AFIO_AF(GPIOI_PIN2, 0) | \
- PIN_AFIO_AF(GPIOI_PIN3, 0) | \
- PIN_AFIO_AF(GPIOI_PIN4, 0) | \
- PIN_AFIO_AF(GPIOI_PIN5, 0) | \
- PIN_AFIO_AF(GPIOI_PIN6, 0) | \
- PIN_AFIO_AF(GPIOI_PIN7, 0))
-#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \
- PIN_AFIO_AF(GPIOI_PIN9, 0) | \
- PIN_AFIO_AF(GPIOI_PIN10, 0) | \
- PIN_AFIO_AF(GPIOI_PIN11, 0) | \
- PIN_AFIO_AF(GPIOI_PIN12, 0) | \
- PIN_AFIO_AF(GPIOI_PIN13, 0) | \
- PIN_AFIO_AF(GPIOI_PIN14, 0) | \
- PIN_AFIO_AF(GPIOI_PIN15, 0))
-
-
-#if !defined(_FROM_ASM_)
-#ifdef __cplusplus
-extern "C" {
-#endif
- void boardInit(void);
-#ifdef __cplusplus
-}
-#endif
-#endif /* _FROM_ASM_ */
-
-#endif /* _BOARD_H_ */
+/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see .
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for a generic STM32F4xx board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_MARLIN_STM32F417
+#define BOARD_NAME "Marlin STM32F417 board"
+
+/*
+ * Ethernet PHY type.
+ */
+#define MII_KSZ8051RNL_ID 0x00221550
+#define BOARD_PHY_ID MII_KSZ8051RNL_ID
+#define BOARD_PHY_RMII
+
+/*
+ * Board oscillators-related settings.
+ */
+#define STM32_LSECLK 0
+#define STM32_HSECLK 16000000
+#define STM32_HSECLK_BYPASS
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD 300
+
+/*
+ * MCU type as defined in the ST header file stm32f4xx.h.
+ */
+#define STM32F4XX
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_HEATER_0 0
+#define GPIOA_ETH_REFCLK 1
+#define GPIOA_ETH_MDIO 2
+#define GPIOA_HEATER_1 3
+#define GPIOA_BL 4
+#define GPIOA_CLK 5
+#define GPIOA_Y_B 6
+#define GPIOA_ETH_CRS_DV 7
+#define GPIOA_HBP 8
+#define GPIOA_INTERLOCK 9
+#define GPIOA_PWM_0 10
+#define GPIOA_HD_N 11
+#define GPIOA_HD_P 12
+#define GPIOA_SWDIO 13
+#define GPIOA_SWCLK 14
+#define GPIOA_X_B 15
+
+#define GPIOB_DIR_Z 0
+#define GPIOB_STEP_Z 1
+#define GPIOB_HOME_Y 2
+#define GPIOB_X_A 3
+#define GPIOB_MISO 4
+#define GPIOB_MOSI 5
+#define GPIOB_MB_UART1_TX 6
+#define GPIOB_MB_UART1_RX 7
+#define GPIOB_CAN_RX 8
+#define GPIOB_CAN_TX 9
+#define GPIOB_I2S_SCK 10
+#define GPIOB_NOT_USED_1 11
+#define GPIOB_I2S_WS 12
+#define GPIOB_VBUS_D 13
+#define GPIOB_DD_N 14
+#define GPIOB_DD_P 15
+
+#define GPIOC_ANALOG_1 0
+#define GPIOC_ETH_MDC 1
+#define GPIOC_HOME_Z 2
+#define GPIOC_I2S_SD 3
+#define GPIOC_ETH_RXD0 4
+#define GPIOC_ETH_RXD1 5
+#define GPIOC_SDI_ST 6
+#define GPIOC_Y_A 7
+#define GPIOC_SDIO_D0 8
+#define GPIOC_SDIO_D1 9
+#define GPIOC_SDIO_D2 10
+#define GPIOC_SDIO_D3 11
+#define GPIOC_SDIO_SK 12
+#define GPIOC_PIN13 13
+#define GPIOC_PIN14 14
+#define GPIOC_PIN15 15
+
+#define GPIOD_D2 0
+#define GPIOD_D3 1
+#define GPIOD_SDIO_CMD 2
+#define GPIOD_SDIO_CD_N 3
+#define GPIOD_RDN 4
+#define GPIOD_WRN 5
+#define GPIOD_STEPPER_EN_N 6
+#define GPIOD_POWER_OUT_EN_N 7
+#define GPIOD_D13 8
+#define GPIOD_D14 9
+#define GPIOD_D15 10
+#define GPIOD_P_CN 11
+#define GPIOD_HEATER_2 12
+#define GPIOD_PWM_1 13
+#define GPIOD_D0 14
+#define GPIOD_D1 15
+
+#define GPIOE_STEP_E2 0
+#define GPIOE_DIR_E2 1
+#define GPIOE_INT 2
+#define GPIOE_VMOT_EN 3
+#define GPIOE_LED_STS_1 4
+#define GPIOE_FAN_0 5
+#define GPIOE_FAN_1 6
+#define GPIOE_D4 7
+#define GPIOE_D5 8
+#define GPIOE_D6 9
+#define GPIOE_D7 10
+#define GPIOE_D8 11
+#define GPIOE_D9 12
+#define GPIOE_D10 13
+#define GPIOE_D11 14
+#define GPIOE_D12 15
+
+#define GPIOF_SDA 0
+#define GPIOF_SCL 1
+#define GPIOF_PRE_CHARGE 2
+#define GPIOF_VMOT_MEAS 3
+#define GPIOF_CURR_OUT 4
+#define GPIOF_VIN_MEAS 5
+#define GPIOF_TEMP_E2 6
+#define GPIOF_TEMP_E1 7
+#define GPIOF_TEMP_E0 8
+#define GPIOF_TEMP_HPB 9
+#define GPIOF_PIN10 10
+#define GPIOF_DIR_Y 11
+#define GPIOF_STEP_Y 12
+#define GPIOF_HOME_X 13
+#define GPIOF_MB_CS0_N 14
+#define GPIOF_MB_CS1_N 15
+
+#define GPIOG_DIR_X 0
+#define GPIOG_STEP_X 1
+#define GPIOG_STEP_E0 2
+#define GPIOG_DIR_E0 3
+#define GPIOG_STEP_E1 4
+#define GPIOG_DIR_E1 5
+#define GPIOG_LED_STS_2 6
+#define GPIOG_SCK_ST 7
+#define GPIOG_PIN8 8
+#define GPIOG_SDO_ST 9
+#define GPIOG_CS_N 10
+#define GPIOG_ETH_TXEN 11
+#define GPIOG_CS_ST_N 12
+#define GPIOG_ETH_TXD0 13
+#define GPIOG_ETH_TXD1 14
+#define GPIOG_PIN15 15
+
+#define GPIOH_PIN0 0
+#define GPIOH_PIN1 1
+#define GPIOH_PIN2 2
+#define GPIOH_PIN3 3
+#define GPIOH_PIN4 4
+#define GPIOH_PIN5 5
+#define GPIOH_PIN6 6
+#define GPIOH_PIN7 7
+#define GPIOH_PIN8 8
+#define GPIOH_PIN9 9
+#define GPIOH_PIN10 10
+#define GPIOH_PIN11 11
+#define GPIOH_PIN12 12
+#define GPIOH_PIN13 13
+#define GPIOH_PIN14 14
+#define GPIOH_PIN15 15
+
+#define GPIOI_PIN0 0
+#define GPIOI_PIN1 1
+#define GPIOI_PIN2 2
+#define GPIOI_PIN3 3
+#define GPIOI_PIN4 4
+#define GPIOI_PIN5 5
+#define GPIOI_PIN6 6
+#define GPIOI_PIN7 7
+#define GPIOI_PIN8 8
+#define GPIOI_PIN9 9
+#define GPIOI_PIN10 10
+#define GPIOI_PIN11 11
+#define GPIOI_PIN12 12
+#define GPIOI_PIN13 13
+#define GPIOI_PIN14 14
+#define GPIOI_PIN15 15
+
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_2M(n) (0U << ((n) * 2))
+#define PIN_OSPEED_25M(n) (1U << ((n) * 2))
+#define PIN_OSPEED_50M(n) (2U << ((n) * 2))
+#define PIN_OSPEED_100M(n) (3U << ((n) * 2))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - HEATER_0 (output pushpull 2mhz).
+ * PA1 - ETH_REFCLK (alternate 11).
+ * PA2 - ETH_MDIO (alternate 11).
+ * PA3 - HEATER_1 (output pushpull 2mhz).
+ * PA4 - BL (output pushpull 2mhz).
+ * PA5 - CLK (alternate 5).
+ * PA6 - Y_B (alternate 0).
+ * PA7 - ETH_CRS_DV (alternate 11).
+ * PA8 - HBP (output pushpull 2mhz).
+ * PA9 - INTERLOCK (input pull-up).
+ * PA10 - PWM_0 (output pushpull 2mhz).
+ * PA11 - HD_N (alternate 6).
+ * PA12 - HD_P (alternate 10).
+ * PA13 - SWDIO (alternate 0).
+ * PA14 - SWCLK (alternate 0).
+ * PA15 - X_B (alternate 1).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_ALTERNATE(GPIOA_HEATER_0) | \
+ PIN_MODE_ALTERNATE(GPIOA_ETH_REFCLK) | \
+ PIN_MODE_ALTERNATE(GPIOA_ETH_MDIO) | \
+ PIN_MODE_ALTERNATE(GPIOA_HEATER_1) | \
+ PIN_MODE_OUTPUT(GPIOA_BL) | \
+ PIN_MODE_ALTERNATE(GPIOA_CLK) | \
+ PIN_MODE_ALTERNATE(GPIOA_Y_B) | \
+ PIN_MODE_ALTERNATE(GPIOA_ETH_CRS_DV) | \
+ PIN_MODE_ALTERNATE(GPIOA_HBP) | \
+ PIN_MODE_INPUT(GPIOA_INTERLOCK) | \
+ PIN_MODE_ALTERNATE(GPIOA_PWM_0) | \
+ PIN_MODE_ALTERNATE(GPIOA_HD_N) | \
+ PIN_MODE_ALTERNATE(GPIOA_HD_P) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
+ PIN_MODE_ALTERNATE(GPIOA_X_B))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_HEATER_0) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ETH_REFCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ETH_MDIO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_HEATER_1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_BL) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_CLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_Y_B) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_ETH_CRS_DV) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_HBP) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_INTERLOCK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PWM_0) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_HD_N) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_HD_P) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_X_B))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_2M(GPIOA_HEATER_0) | \
+ PIN_OSPEED_50M(GPIOA_ETH_REFCLK) | \
+ PIN_OSPEED_25M(GPIOA_ETH_MDIO) | \
+ PIN_OSPEED_2M(GPIOA_HEATER_1) | \
+ PIN_OSPEED_2M(GPIOA_BL) | \
+ PIN_OSPEED_100M(GPIOA_CLK) | \
+ PIN_OSPEED_50M(GPIOA_Y_B) | \
+ PIN_OSPEED_50M(GPIOA_ETH_CRS_DV) | \
+ PIN_OSPEED_2M(GPIOA_HBP) | \
+ PIN_OSPEED_50M(GPIOA_INTERLOCK) | \
+ PIN_OSPEED_2M(GPIOA_PWM_0) | \
+ PIN_OSPEED_50M(GPIOA_HD_N) | \
+ PIN_OSPEED_50M(GPIOA_HD_P) | \
+ PIN_OSPEED_50M(GPIOA_SWDIO) | \
+ PIN_OSPEED_50M(GPIOA_SWCLK) | \
+ PIN_OSPEED_50M(GPIOA_X_B))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_HEATER_0) | \
+ PIN_PUPDR_FLOATING(GPIOA_ETH_REFCLK) | \
+ PIN_PUPDR_FLOATING(GPIOA_ETH_MDIO) | \
+ PIN_PUPDR_FLOATING(GPIOA_HEATER_1) | \
+ PIN_PUPDR_FLOATING(GPIOA_BL) | \
+ PIN_PUPDR_FLOATING(GPIOA_CLK) | \
+ PIN_PUPDR_FLOATING(GPIOA_Y_B) | \
+ PIN_PUPDR_FLOATING(GPIOA_ETH_CRS_DV) | \
+ PIN_PUPDR_FLOATING(GPIOA_HBP) | \
+ PIN_PUPDR_PULLUP(GPIOA_INTERLOCK) | \
+ PIN_PUPDR_FLOATING(GPIOA_PWM_0) | \
+ PIN_PUPDR_FLOATING(GPIOA_HD_N) | \
+ PIN_PUPDR_FLOATING(GPIOA_HD_P) | \
+ PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \
+ PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \
+ PIN_PUPDR_FLOATING(GPIOA_X_B))
+#define VAL_GPIOA_ODR (PIN_ODR_LOW(GPIOA_HEATER_0) | \
+ PIN_ODR_LOW(GPIOA_ETH_REFCLK) | \
+ PIN_ODR_LOW(GPIOA_ETH_MDIO) | \
+ PIN_ODR_LOW(GPIOA_HEATER_1) | \
+ PIN_ODR_LOW(GPIOA_BL) | \
+ PIN_ODR_LOW(GPIOA_CLK) | \
+ PIN_ODR_LOW(GPIOA_Y_B) | \
+ PIN_ODR_LOW(GPIOA_ETH_CRS_DV) | \
+ PIN_ODR_LOW(GPIOA_HBP) | \
+ PIN_ODR_LOW(GPIOA_INTERLOCK) | \
+ PIN_ODR_LOW(GPIOA_PWM_0) | \
+ PIN_ODR_LOW(GPIOA_HD_N) | \
+ PIN_ODR_LOW(GPIOA_HD_P) | \
+ PIN_ODR_LOW(GPIOA_SWDIO) | \
+ PIN_ODR_LOW(GPIOA_SWCLK) | \
+ PIN_ODR_LOW(GPIOA_X_B))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_HEATER_0, 2) | \
+ PIN_AFIO_AF(GPIOA_ETH_REFCLK, 11) | \
+ PIN_AFIO_AF(GPIOA_ETH_MDIO, 11) | \
+ PIN_AFIO_AF(GPIOA_HEATER_1, 2) | \
+ PIN_AFIO_AF(GPIOA_BL, 0) | \
+ PIN_AFIO_AF(GPIOA_CLK, 5) | \
+ PIN_AFIO_AF(GPIOA_Y_B, 0) | \
+ PIN_AFIO_AF(GPIOA_ETH_CRS_DV, 11))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_HBP, 1) | \
+ PIN_AFIO_AF(GPIOA_INTERLOCK, 0) | \
+ PIN_AFIO_AF(GPIOA_PWM_0, 1) | \
+ PIN_AFIO_AF(GPIOA_HD_N, 10) | \
+ PIN_AFIO_AF(GPIOA_HD_P, 10) | \
+ PIN_AFIO_AF(GPIOA_SWDIO, 0) | \
+ PIN_AFIO_AF(GPIOA_SWCLK, 0) | \
+ PIN_AFIO_AF(GPIOA_X_B, 1))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - DIR_Z (output pushpull 2mhz).
+ * PB1 - STEP_Z (output pushpull 2mhz).
+ * PB2 - HOME_Y (input floating).
+ * PB3 - X_A (alternate 1).
+ * PB4 - MISO (alternate 5).
+ * PB5 - MOSI (alternate 5).
+ * PB6 - MB_SCL (alternate 7).
+ * PB7 - MB_SDA (alternate 7).
+ * PB8 - CAN_RX (input floating).
+ * PB9 - CAN_TX (input floating).
+ * PB10 - I2S_SCK (alternate 5).
+ * PB11 - NOT_USED_1 (input floating).
+ * PB12 - I2S_WS (alternate 5).
+ * PB13 - VBUS_D (input pull-up).
+ * PB14 - DD_N (alternate 12).
+ * PB15 - DD_P (alternate 12).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_DIR_Z) | \
+ PIN_MODE_OUTPUT(GPIOB_STEP_Z) | \
+ PIN_MODE_INPUT(GPIOB_HOME_Y) | \
+ PIN_MODE_ALTERNATE(GPIOB_X_A) | \
+ PIN_MODE_ALTERNATE(GPIOB_MISO) | \
+ PIN_MODE_ALTERNATE(GPIOB_MOSI) | \
+ PIN_MODE_ALTERNATE(GPIOB_MB_UART1_TX) |\
+ PIN_MODE_ALTERNATE(GPIOB_MB_UART1_RX) |\
+ PIN_MODE_INPUT(GPIOB_CAN_RX) | \
+ PIN_MODE_INPUT(GPIOB_CAN_TX) | \
+ PIN_MODE_ALTERNATE(GPIOB_I2S_SCK) | \
+ PIN_MODE_INPUT(GPIOB_NOT_USED_1) | \
+ PIN_MODE_ALTERNATE(GPIOB_I2S_WS) | \
+ PIN_MODE_INPUT(GPIOB_VBUS_D) | \
+ PIN_MODE_ALTERNATE(GPIOB_DD_N) | \
+ PIN_MODE_ALTERNATE(GPIOB_DD_P))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_DIR_Z) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_STEP_Z) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_HOME_Y) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_X_A) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_MISO) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_MOSI) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_MB_UART1_TX) |\
+ PIN_OTYPE_OPENDRAIN(GPIOB_MB_UART1_RX) |\
+ PIN_OTYPE_PUSHPULL(GPIOB_CAN_RX) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_CAN_TX) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_I2S_SCK) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_NOT_USED_1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_I2S_WS) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_VBUS_D) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_DD_N) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_DD_P))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_2M(GPIOB_DIR_Z) | \
+ PIN_OSPEED_2M(GPIOB_STEP_Z) | \
+ PIN_OSPEED_50M(GPIOB_HOME_Y) | \
+ PIN_OSPEED_50M(GPIOB_X_A) | \
+ PIN_OSPEED_100M(GPIOB_MISO) | \
+ PIN_OSPEED_100M(GPIOB_MOSI) | \
+ PIN_OSPEED_50M(GPIOB_MB_UART1_TX) | \
+ PIN_OSPEED_50M(GPIOB_MB_UART1_RX) | \
+ PIN_OSPEED_50M(GPIOB_CAN_RX) | \
+ PIN_OSPEED_50M(GPIOB_CAN_TX) | \
+ PIN_OSPEED_50M(GPIOB_I2S_SCK) | \
+ PIN_OSPEED_50M(GPIOB_NOT_USED_1) | \
+ PIN_OSPEED_50M(GPIOB_I2S_WS) | \
+ PIN_OSPEED_50M(GPIOB_VBUS_D) | \
+ PIN_OSPEED_50M(GPIOB_DD_N) | \
+ PIN_OSPEED_50M(GPIOB_DD_P))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_DIR_Z) | \
+ PIN_PUPDR_FLOATING(GPIOB_STEP_Z) | \
+ PIN_PUPDR_FLOATING(GPIOB_HOME_Y) | \
+ PIN_PUPDR_FLOATING(GPIOB_X_A) | \
+ PIN_PUPDR_FLOATING(GPIOB_MISO) | \
+ PIN_PUPDR_FLOATING(GPIOB_MOSI) | \
+ PIN_PUPDR_FLOATING(GPIOB_MB_UART1_TX) |\
+ PIN_PUPDR_FLOATING(GPIOB_MB_UART1_RX) |\
+ PIN_PUPDR_FLOATING(GPIOB_CAN_RX) | \
+ PIN_PUPDR_FLOATING(GPIOB_CAN_TX) | \
+ PIN_PUPDR_FLOATING(GPIOB_I2S_SCK) | \
+ PIN_PUPDR_FLOATING(GPIOB_NOT_USED_1) | \
+ PIN_PUPDR_FLOATING(GPIOB_I2S_WS) | \
+ PIN_PUPDR_PULLUP(GPIOB_VBUS_D) | \
+ PIN_PUPDR_FLOATING(GPIOB_DD_N) | \
+ PIN_PUPDR_FLOATING(GPIOB_DD_P))
+#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_DIR_Z) | \
+ PIN_ODR_LOW(GPIOB_STEP_Z) | \
+ PIN_ODR_LOW(GPIOB_HOME_Y) | \
+ PIN_ODR_LOW(GPIOB_X_A) | \
+ PIN_ODR_LOW(GPIOB_MISO) | \
+ PIN_ODR_LOW(GPIOB_MOSI) | \
+ PIN_ODR_LOW(GPIOB_MB_UART1_TX) | \
+ PIN_ODR_LOW(GPIOB_MB_UART1_RX) | \
+ PIN_ODR_LOW(GPIOB_CAN_RX) | \
+ PIN_ODR_LOW(GPIOB_CAN_TX) | \
+ PIN_ODR_LOW(GPIOB_I2S_SCK) | \
+ PIN_ODR_LOW(GPIOB_NOT_USED_1) | \
+ PIN_ODR_LOW(GPIOB_I2S_WS) | \
+ PIN_ODR_LOW(GPIOB_VBUS_D) | \
+ PIN_ODR_LOW(GPIOB_DD_N) | \
+ PIN_ODR_LOW(GPIOB_DD_P))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_DIR_Z, 0) | \
+ PIN_AFIO_AF(GPIOB_STEP_Z, 0) | \
+ PIN_AFIO_AF(GPIOB_HOME_Y, 0) | \
+ PIN_AFIO_AF(GPIOB_X_A, 1) | \
+ PIN_AFIO_AF(GPIOB_MISO, 5) | \
+ PIN_AFIO_AF(GPIOB_MOSI, 5) | \
+ PIN_AFIO_AF(GPIOB_MB_UART1_TX, 4) | \
+ PIN_AFIO_AF(GPIOB_MB_UART1_RX, 4))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_CAN_RX, 0) | \
+ PIN_AFIO_AF(GPIOB_CAN_TX, 0) | \
+ PIN_AFIO_AF(GPIOB_I2S_SCK, 5) | \
+ PIN_AFIO_AF(GPIOB_NOT_USED_1, 0) | \
+ PIN_AFIO_AF(GPIOB_I2S_WS, 5) | \
+ PIN_AFIO_AF(GPIOB_VBUS_D, 0) | \
+ PIN_AFIO_AF(GPIOB_DD_N, 12) | \
+ PIN_AFIO_AF(GPIOB_DD_P, 12))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - ANALOG_1 (input floating).
+ * PC1 - ETH_MDC (alternate 11).
+ * PC2 - HOME_Z (input floating).
+ * PC3 - I2S_SD (alternate 5).
+ * PC4 - ETH_RXD0 (alternate 11).
+ * PC5 - ETH_RXD1 (alternate 11).
+ * PC6 - SDI_ST (alternate 8).
+ * PC7 - Y_A (alternate 2).
+ * PC8 - SDIO_D0 (alternate 12).
+ * PC9 - SDIO_D1 (alternate 12).
+ * PC10 - SDIO_D2 (alternate 12).
+ * PC11 - SDIO_D3 (alternate 12).
+ * PC12 - SDIO_SK (alternate 12).
+ * PC13 - P (input floating).
+ * PC14 - P (input floating).
+ * PC15 - P (input floating).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_ANALOG_1) | \
+ PIN_MODE_ALTERNATE(GPIOC_ETH_MDC) | \
+ PIN_MODE_INPUT(GPIOC_HOME_Z) | \
+ PIN_MODE_ALTERNATE(GPIOC_I2S_SD) | \
+ PIN_MODE_ALTERNATE(GPIOC_ETH_RXD0) | \
+ PIN_MODE_ALTERNATE(GPIOC_ETH_RXD1) | \
+ PIN_MODE_ALTERNATE(GPIOC_SDI_ST) | \
+ PIN_MODE_ALTERNATE(GPIOC_Y_A) | \
+ PIN_MODE_ALTERNATE(GPIOC_SDIO_D0) | \
+ PIN_MODE_ALTERNATE(GPIOC_SDIO_D1) | \
+ PIN_MODE_ALTERNATE(GPIOC_SDIO_D2) | \
+ PIN_MODE_ALTERNATE(GPIOC_SDIO_D3) | \
+ PIN_MODE_ALTERNATE(GPIOC_SDIO_SK) | \
+ PIN_MODE_INPUT(GPIOC_PIN13) | \
+ PIN_MODE_INPUT(GPIOC_PIN14) | \
+ PIN_MODE_INPUT(GPIOC_PIN15))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ANALOG_1) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ETH_MDC) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_HOME_Z) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_I2S_SD) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ETH_RXD0) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_ETH_RXD1) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SDI_ST) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_Y_A) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D0) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D1) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SDIO_D3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SDIO_SK) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_50M(GPIOC_ANALOG_1) | \
+ PIN_OSPEED_50M(GPIOC_ETH_MDC) | \
+ PIN_OSPEED_50M(GPIOC_HOME_Z) | \
+ PIN_OSPEED_50M(GPIOC_I2S_SD) | \
+ PIN_OSPEED_50M(GPIOC_ETH_RXD0) | \
+ PIN_OSPEED_50M(GPIOC_ETH_RXD1) | \
+ PIN_OSPEED_50M(GPIOC_SDI_ST) | \
+ PIN_OSPEED_50M(GPIOC_Y_A) | \
+ PIN_OSPEED_50M(GPIOC_SDIO_D0) | \
+ PIN_OSPEED_50M(GPIOC_SDIO_D1) | \
+ PIN_OSPEED_50M(GPIOC_SDIO_D2) | \
+ PIN_OSPEED_50M(GPIOC_SDIO_D3) | \
+ PIN_OSPEED_50M(GPIOC_SDIO_SK) | \
+ PIN_OSPEED_50M(GPIOC_PIN13) | \
+ PIN_OSPEED_50M(GPIOC_PIN14) | \
+ PIN_OSPEED_50M(GPIOC_PIN15))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_ANALOG_1) | \
+ PIN_PUPDR_FLOATING(GPIOC_ETH_MDC) | \
+ PIN_PUPDR_FLOATING(GPIOC_HOME_Z) | \
+ PIN_PUPDR_FLOATING(GPIOC_I2S_SD) | \
+ PIN_PUPDR_FLOATING(GPIOC_ETH_RXD0) | \
+ PIN_PUPDR_FLOATING(GPIOC_ETH_RXD1) | \
+ PIN_PUPDR_FLOATING(GPIOC_SDI_ST) | \
+ PIN_PUPDR_FLOATING(GPIOC_Y_A) | \
+ PIN_PUPDR_FLOATING(GPIOC_SDIO_D0) | \
+ PIN_PUPDR_FLOATING(GPIOC_SDIO_D1) | \
+ PIN_PUPDR_FLOATING(GPIOC_SDIO_D2) | \
+ PIN_PUPDR_FLOATING(GPIOC_SDIO_D3) | \
+ PIN_PUPDR_FLOATING(GPIOC_SDIO_SK) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOC_PIN15))
+#define VAL_GPIOC_ODR (PIN_ODR_LOW(GPIOC_ANALOG_1) | \
+ PIN_ODR_LOW(GPIOC_ETH_MDC) | \
+ PIN_ODR_LOW(GPIOC_HOME_Z) | \
+ PIN_ODR_LOW(GPIOC_I2S_SD) | \
+ PIN_ODR_LOW(GPIOC_ETH_RXD0) | \
+ PIN_ODR_LOW(GPIOC_ETH_RXD1) | \
+ PIN_ODR_LOW(GPIOC_SDI_ST) | \
+ PIN_ODR_LOW(GPIOC_Y_A) | \
+ PIN_ODR_LOW(GPIOC_SDIO_D0) | \
+ PIN_ODR_LOW(GPIOC_SDIO_D1) | \
+ PIN_ODR_LOW(GPIOC_SDIO_D2) | \
+ PIN_ODR_LOW(GPIOC_SDIO_D3) | \
+ PIN_ODR_LOW(GPIOC_SDIO_SK) | \
+ PIN_ODR_LOW(GPIOC_PIN13) | \
+ PIN_ODR_LOW(GPIOC_PIN14) | \
+ PIN_ODR_LOW(GPIOC_PIN15))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ANALOG_1, 0) | \
+ PIN_AFIO_AF(GPIOC_ETH_MDC, 11) | \
+ PIN_AFIO_AF(GPIOC_HOME_Z, 0) | \
+ PIN_AFIO_AF(GPIOC_I2S_SD, 5) | \
+ PIN_AFIO_AF(GPIOC_ETH_RXD0, 11) | \
+ PIN_AFIO_AF(GPIOC_ETH_RXD1, 11) | \
+ PIN_AFIO_AF(GPIOC_SDI_ST, 8) | \
+ PIN_AFIO_AF(GPIOC_Y_A, 2))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SDIO_D0, 12) | \
+ PIN_AFIO_AF(GPIOC_SDIO_D1, 12) | \
+ PIN_AFIO_AF(GPIOC_SDIO_D2, 12) | \
+ PIN_AFIO_AF(GPIOC_SDIO_D3, 12) | \
+ PIN_AFIO_AF(GPIOC_SDIO_SK, 12) | \
+ PIN_AFIO_AF(GPIOC_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN15, 0))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - D2 (alternate 12).
+ * PD1 - D3 (alternate 12).
+ * PD2 - SDIO_CMD (alternate 12).
+ * PD3 - SDIO_CD_N (input floating).
+ * PD4 - RDN (alternate 12).
+ * PD5 - WRN (alternate 12).
+ * PD6 - STEPPER_EN (output pushpull 2mhz).
+ * PD7 - POWER_OUT_EN_N (output pushpull 2mhz).
+ * PD8 - D13 (alternate 12).
+ * PD9 - D14 (alternate 12).
+ * PD10 - D15 (alternate 12).
+ * PD11 - P_CN (alternate 12).
+ * PD12 - HEATER_2 (output pushpull 2mhz).
+ * PD13 - PWM_1 (output pushpull 2mhz).
+ * PD14 - D0 (alternate 12).
+ * PD15 - D1 (alternate 12).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(GPIOD_D2) | \
+ PIN_MODE_ALTERNATE(GPIOD_D3) | \
+ PIN_MODE_ALTERNATE(GPIOD_SDIO_CMD) | \
+ PIN_MODE_INPUT(GPIOD_SDIO_CD_N) | \
+ PIN_MODE_ALTERNATE(GPIOD_RDN) | \
+ PIN_MODE_ALTERNATE(GPIOD_WRN) | \
+ PIN_MODE_OUTPUT(GPIOD_STEPPER_EN_N) | \
+ PIN_MODE_OUTPUT(GPIOD_POWER_OUT_EN_N) |\
+ PIN_MODE_ALTERNATE(GPIOD_D13) | \
+ PIN_MODE_ALTERNATE(GPIOD_D14) | \
+ PIN_MODE_ALTERNATE(GPIOD_D15) | \
+ PIN_MODE_ALTERNATE(GPIOD_P_CN) | \
+ PIN_MODE_ALTERNATE(GPIOD_HEATER_2) | \
+ PIN_MODE_ALTERNATE(GPIOD_PWM_1) | \
+ PIN_MODE_ALTERNATE(GPIOD_D0) | \
+ PIN_MODE_ALTERNATE(GPIOD_D1))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_D2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_D3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_SDIO_CMD) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_SDIO_CD_N) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_RDN) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_WRN) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_STEPPER_EN_N) |\
+ PIN_OTYPE_PUSHPULL(GPIOD_POWER_OUT_EN_N) |\
+ PIN_OTYPE_PUSHPULL(GPIOD_D13) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_D14) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_D15) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_P_CN) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_HEATER_2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PWM_1) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_D0) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_D1))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_50M(GPIOD_D2) | \
+ PIN_OSPEED_50M(GPIOD_D3) | \
+ PIN_OSPEED_50M(GPIOD_SDIO_CMD) | \
+ PIN_OSPEED_50M(GPIOD_SDIO_CD_N) | \
+ PIN_OSPEED_50M(GPIOD_RDN) | \
+ PIN_OSPEED_50M(GPIOD_WRN) | \
+ PIN_OSPEED_2M(GPIOD_STEPPER_EN_N) | \
+ PIN_OSPEED_2M(GPIOD_POWER_OUT_EN_N) | \
+ PIN_OSPEED_50M(GPIOD_D13) | \
+ PIN_OSPEED_50M(GPIOD_D14) | \
+ PIN_OSPEED_50M(GPIOD_D15) | \
+ PIN_OSPEED_50M(GPIOD_P_CN) | \
+ PIN_OSPEED_2M(GPIOD_HEATER_2) | \
+ PIN_OSPEED_2M(GPIOD_PWM_1) | \
+ PIN_OSPEED_50M(GPIOD_D0) | \
+ PIN_OSPEED_50M(GPIOD_D1))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_D2) | \
+ PIN_PUPDR_FLOATING(GPIOD_D3) | \
+ PIN_PUPDR_FLOATING(GPIOD_SDIO_CMD) | \
+ PIN_PUPDR_FLOATING(GPIOD_SDIO_CD_N) | \
+ PIN_PUPDR_FLOATING(GPIOD_RDN) | \
+ PIN_PUPDR_FLOATING(GPIOD_WRN) | \
+ PIN_PUPDR_FLOATING(GPIOD_STEPPER_EN_N) |\
+ PIN_PUPDR_FLOATING(GPIOD_POWER_OUT_EN_N) |\
+ PIN_PUPDR_FLOATING(GPIOD_D13) | \
+ PIN_PUPDR_FLOATING(GPIOD_D14) | \
+ PIN_PUPDR_FLOATING(GPIOD_D15) | \
+ PIN_PUPDR_FLOATING(GPIOD_P_CN) | \
+ PIN_PUPDR_FLOATING(GPIOD_HEATER_2) | \
+ PIN_PUPDR_FLOATING(GPIOD_PWM_1) | \
+ PIN_PUPDR_FLOATING(GPIOD_D0) | \
+ PIN_PUPDR_FLOATING(GPIOD_D1))
+#define VAL_GPIOD_ODR (PIN_ODR_LOW(GPIOD_D2) | \
+ PIN_ODR_LOW(GPIOD_D3) | \
+ PIN_ODR_LOW(GPIOD_SDIO_CMD) | \
+ PIN_ODR_LOW(GPIOD_SDIO_CD_N) | \
+ PIN_ODR_LOW(GPIOD_RDN) | \
+ PIN_ODR_LOW(GPIOD_WRN) | \
+ PIN_ODR_LOW(GPIOD_STEPPER_EN_N) | \
+ PIN_ODR_HIGH(GPIOD_POWER_OUT_EN_N) | \
+ PIN_ODR_LOW(GPIOD_D13) | \
+ PIN_ODR_LOW(GPIOD_D14) | \
+ PIN_ODR_LOW(GPIOD_D15) | \
+ PIN_ODR_LOW(GPIOD_P_CN) | \
+ PIN_ODR_LOW(GPIOD_HEATER_2) | \
+ PIN_ODR_LOW(GPIOD_PWM_1) | \
+ PIN_ODR_LOW(GPIOD_D0) | \
+ PIN_ODR_LOW(GPIOD_D1))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_D2, 12) | \
+ PIN_AFIO_AF(GPIOD_D3, 12) | \
+ PIN_AFIO_AF(GPIOD_SDIO_CMD, 12) | \
+ PIN_AFIO_AF(GPIOD_SDIO_CD_N, 0) | \
+ PIN_AFIO_AF(GPIOD_RDN, 12) | \
+ PIN_AFIO_AF(GPIOD_WRN, 12) | \
+ PIN_AFIO_AF(GPIOD_STEPPER_EN_N, 0) | \
+ PIN_AFIO_AF(GPIOD_POWER_OUT_EN_N, 0))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_D13, 12) | \
+ PIN_AFIO_AF(GPIOD_D14, 12) | \
+ PIN_AFIO_AF(GPIOD_D15, 12) | \
+ PIN_AFIO_AF(GPIOD_P_CN, 12) | \
+ PIN_AFIO_AF(GPIOD_HEATER_2, 2) | \
+ PIN_AFIO_AF(GPIOD_PWM_1, 2) | \
+ PIN_AFIO_AF(GPIOD_D0, 12) | \
+ PIN_AFIO_AF(GPIOD_D1, 12))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0 - STEP_E2 (output pushpull 2mhz).
+ * PE1 - DIR_E2 (output pushpull 2mhz).
+ * PE2 - INT (input pull-up).
+ * PE3 - VMOT_EN (output pushpull 2mhz).
+ * PE4 - LED_STS_1 (output pushpull 2mhz).
+ * PE5 - FAN_0 (output pushpull 2mhz).
+ * PE6 - FAN_1 (output pushpull 2mhz).
+ * PE7 - D4 (alternate 12).
+ * PE8 - D5 (alternate 12).
+ * PE9 - D6 (alternate 12).
+ * PE10 - D7 (alternate 12).
+ * PE11 - D8 (alternate 12).
+ * PE12 - D9 (alternate 12).
+ * PE13 - D10 (alternate 12).
+ * PE14 - D11 (alternate 12).
+ * PE15 - D12 (alternate 12).
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_OUTPUT(GPIOE_STEP_E2) | \
+ PIN_MODE_OUTPUT(GPIOE_DIR_E2) | \
+ PIN_MODE_INPUT(GPIOE_INT) | \
+ PIN_MODE_OUTPUT(GPIOE_VMOT_EN) | \
+ PIN_MODE_OUTPUT(GPIOE_LED_STS_1) | \
+ PIN_MODE_ALTERNATE(GPIOE_FAN_0) | \
+ PIN_MODE_ALTERNATE(GPIOE_FAN_1) | \
+ PIN_MODE_ALTERNATE(GPIOE_D4) | \
+ PIN_MODE_ALTERNATE(GPIOE_D5) | \
+ PIN_MODE_ALTERNATE(GPIOE_D6) | \
+ PIN_MODE_ALTERNATE(GPIOE_D7) | \
+ PIN_MODE_ALTERNATE(GPIOE_D8) | \
+ PIN_MODE_ALTERNATE(GPIOE_D9) | \
+ PIN_MODE_ALTERNATE(GPIOE_D10) | \
+ PIN_MODE_ALTERNATE(GPIOE_D11) | \
+ PIN_MODE_ALTERNATE(GPIOE_D12))
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_STEP_E2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_DIR_E2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_INT) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_VMOT_EN) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_LED_STS_1) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_FAN_0) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_FAN_1) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_D4) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_D5) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_D6) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_D7) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_D8) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_D9) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_D10) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_D11) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_D12))
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_2M(GPIOE_STEP_E2) | \
+ PIN_OSPEED_2M(GPIOE_DIR_E2) | \
+ PIN_OSPEED_50M(GPIOE_INT) | \
+ PIN_OSPEED_2M(GPIOE_VMOT_EN) | \
+ PIN_OSPEED_2M(GPIOE_LED_STS_1) | \
+ PIN_OSPEED_2M(GPIOE_FAN_0) | \
+ PIN_OSPEED_2M(GPIOE_FAN_1) | \
+ PIN_OSPEED_50M(GPIOE_D4) | \
+ PIN_OSPEED_50M(GPIOE_D5) | \
+ PIN_OSPEED_50M(GPIOE_D6) | \
+ PIN_OSPEED_50M(GPIOE_D7) | \
+ PIN_OSPEED_50M(GPIOE_D8) | \
+ PIN_OSPEED_50M(GPIOE_D9) | \
+ PIN_OSPEED_50M(GPIOE_D10) | \
+ PIN_OSPEED_50M(GPIOE_D11) | \
+ PIN_OSPEED_50M(GPIOE_D12))
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_STEP_E2) | \
+ PIN_PUPDR_FLOATING(GPIOE_DIR_E2) | \
+ PIN_PUPDR_PULLUP(GPIOE_INT) | \
+ PIN_PUPDR_FLOATING(GPIOE_VMOT_EN) | \
+ PIN_PUPDR_FLOATING(GPIOE_LED_STS_1) | \
+ PIN_PUPDR_FLOATING(GPIOE_FAN_0) | \
+ PIN_PUPDR_FLOATING(GPIOE_FAN_1) | \
+ PIN_PUPDR_FLOATING(GPIOE_D4) | \
+ PIN_PUPDR_FLOATING(GPIOE_D5) | \
+ PIN_PUPDR_FLOATING(GPIOE_D6) | \
+ PIN_PUPDR_FLOATING(GPIOE_D7) | \
+ PIN_PUPDR_FLOATING(GPIOE_D8) | \
+ PIN_PUPDR_FLOATING(GPIOE_D9) | \
+ PIN_PUPDR_FLOATING(GPIOE_D10) | \
+ PIN_PUPDR_FLOATING(GPIOE_D11) | \
+ PIN_PUPDR_FLOATING(GPIOE_D12))
+#define VAL_GPIOE_ODR (PIN_ODR_LOW(GPIOE_STEP_E2) | \
+ PIN_ODR_LOW(GPIOE_DIR_E2) | \
+ PIN_ODR_LOW(GPIOE_INT) | \
+ PIN_ODR_LOW(GPIOE_VMOT_EN) | \
+ PIN_ODR_HIGH(GPIOE_LED_STS_1) | \
+ PIN_ODR_LOW(GPIOE_FAN_0) | \
+ PIN_ODR_LOW(GPIOE_FAN_1) | \
+ PIN_ODR_LOW(GPIOE_D4) | \
+ PIN_ODR_LOW(GPIOE_D5) | \
+ PIN_ODR_LOW(GPIOE_D6) | \
+ PIN_ODR_LOW(GPIOE_D7) | \
+ PIN_ODR_LOW(GPIOE_D8) | \
+ PIN_ODR_LOW(GPIOE_D9) | \
+ PIN_ODR_LOW(GPIOE_D10) | \
+ PIN_ODR_LOW(GPIOE_D11) | \
+ PIN_ODR_LOW(GPIOE_D12))
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_STEP_E2, 0) | \
+ PIN_AFIO_AF(GPIOE_DIR_E2, 0) | \
+ PIN_AFIO_AF(GPIOE_INT, 0) | \
+ PIN_AFIO_AF(GPIOE_VMOT_EN, 0) | \
+ PIN_AFIO_AF(GPIOE_LED_STS_1, 0) | \
+ PIN_AFIO_AF(GPIOE_FAN_0, 3) | \
+ PIN_AFIO_AF(GPIOE_FAN_1, 3) | \
+ PIN_AFIO_AF(GPIOE_D4, 12))
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_D5, 12) | \
+ PIN_AFIO_AF(GPIOE_D6, 12) | \
+ PIN_AFIO_AF(GPIOE_D7, 12) | \
+ PIN_AFIO_AF(GPIOE_D8, 12) | \
+ PIN_AFIO_AF(GPIOE_D9, 12) | \
+ PIN_AFIO_AF(GPIOE_D10, 12) | \
+ PIN_AFIO_AF(GPIOE_D11, 12) | \
+ PIN_AFIO_AF(GPIOE_D12, 12))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0 - SDA (alternate 4).
+ * PF1 - SCL (alternate 4).
+ * PF2 - PRE_CHARGE (output pushpull 2mhz).
+ * PF3 - VMOT_MEAS (analog).
+ * PF4 - CURR_OUT (analog).
+ * PF5 - VIN_MEAS (analog).
+ * PF6 - TEMP_E2 (analog).
+ * PF7 - TEMP_E1 (analog).
+ * PF8 - TEMP_E0 (analog).
+ * PF9 - TEMP_HPB (analog).
+ * PF10 - P (input pull-up).
+ * PF11 - DIR_Y (output pushpull 2mhz).
+ * PF12 - STEP_Y (output pushpull 2mhz).
+ * PF13 - HOME_X (input floating).
+ * PF14 - MB_CS0_N (output pushpull 25mhz).
+ * PF15 - MB_CS1_N (output pushpull 25mhz).
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_ALTERNATE(GPIOF_SDA) | \
+ PIN_MODE_ALTERNATE(GPIOF_SCL) | \
+ PIN_MODE_OUTPUT(GPIOF_PRE_CHARGE) | \
+ PIN_MODE_ANALOG(GPIOF_VMOT_MEAS) | \
+ PIN_MODE_ANALOG(GPIOF_CURR_OUT) | \
+ PIN_MODE_ANALOG(GPIOF_VIN_MEAS) | \
+ PIN_MODE_ANALOG(GPIOF_TEMP_E2) | \
+ PIN_MODE_ANALOG(GPIOF_TEMP_E1) | \
+ PIN_MODE_ANALOG(GPIOF_TEMP_E0) | \
+ PIN_MODE_ANALOG(GPIOF_TEMP_HPB) | \
+ PIN_MODE_INPUT(GPIOF_PIN10) | \
+ PIN_MODE_OUTPUT(GPIOF_DIR_Y) | \
+ PIN_MODE_OUTPUT(GPIOF_STEP_Y) | \
+ PIN_MODE_INPUT(GPIOF_HOME_X) | \
+ PIN_MODE_OUTPUT(GPIOF_MB_CS0_N) | \
+ PIN_MODE_OUTPUT(GPIOF_MB_CS1_N))
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_OPENDRAIN(GPIOF_SDA) | \
+ PIN_OTYPE_OPENDRAIN(GPIOF_SCL) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PRE_CHARGE) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_VMOT_MEAS) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_CURR_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_VIN_MEAS) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_TEMP_E2) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_TEMP_E1) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_TEMP_E0) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_TEMP_HPB) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_DIR_Y) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_STEP_Y) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_HOME_X) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_MB_CS0_N) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_MB_CS1_N))
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_50M(GPIOF_SDA) | \
+ PIN_OSPEED_50M(GPIOF_SCL) | \
+ PIN_OSPEED_2M(GPIOF_PRE_CHARGE) | \
+ PIN_OSPEED_50M(GPIOF_VMOT_MEAS) | \
+ PIN_OSPEED_50M(GPIOF_CURR_OUT) | \
+ PIN_OSPEED_50M(GPIOF_VIN_MEAS) | \
+ PIN_OSPEED_50M(GPIOF_TEMP_E2) | \
+ PIN_OSPEED_50M(GPIOF_TEMP_E1) | \
+ PIN_OSPEED_50M(GPIOF_TEMP_E0) | \
+ PIN_OSPEED_50M(GPIOF_TEMP_HPB) | \
+ PIN_OSPEED_2M(GPIOF_PIN10) | \
+ PIN_OSPEED_2M(GPIOF_DIR_Y) | \
+ PIN_OSPEED_2M(GPIOF_STEP_Y) | \
+ PIN_OSPEED_50M(GPIOF_HOME_X) | \
+ PIN_OSPEED_100M(GPIOF_MB_CS0_N) | \
+ PIN_OSPEED_25M(GPIOF_MB_CS1_N))
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_SDA) | \
+ PIN_PUPDR_FLOATING(GPIOF_SCL) | \
+ PIN_PUPDR_FLOATING(GPIOF_PRE_CHARGE) | \
+ PIN_PUPDR_FLOATING(GPIOF_VMOT_MEAS) | \
+ PIN_PUPDR_FLOATING(GPIOF_CURR_OUT) | \
+ PIN_PUPDR_FLOATING(GPIOF_VIN_MEAS) | \
+ PIN_PUPDR_FLOATING(GPIOF_TEMP_E2) | \
+ PIN_PUPDR_FLOATING(GPIOF_TEMP_E1) | \
+ PIN_PUPDR_FLOATING(GPIOF_TEMP_E0) | \
+ PIN_PUPDR_FLOATING(GPIOF_TEMP_HPB) | \
+ PIN_PUPDR_PULLUP(GPIOF_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOF_DIR_Y) | \
+ PIN_PUPDR_FLOATING(GPIOF_STEP_Y) | \
+ PIN_PUPDR_FLOATING(GPIOF_HOME_X) | \
+ PIN_PUPDR_FLOATING(GPIOF_MB_CS0_N) | \
+ PIN_PUPDR_FLOATING(GPIOF_MB_CS1_N))
+#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_SDA) | \
+ PIN_ODR_HIGH(GPIOF_SCL) | \
+ PIN_ODR_LOW(GPIOF_PRE_CHARGE) | \
+ PIN_ODR_LOW(GPIOF_VMOT_MEAS) | \
+ PIN_ODR_LOW(GPIOF_CURR_OUT) | \
+ PIN_ODR_LOW(GPIOF_VIN_MEAS) | \
+ PIN_ODR_LOW(GPIOF_TEMP_E2) | \
+ PIN_ODR_LOW(GPIOF_TEMP_E1) | \
+ PIN_ODR_LOW(GPIOF_TEMP_E0) | \
+ PIN_ODR_LOW(GPIOF_TEMP_HPB) | \
+ PIN_ODR_LOW(GPIOF_PIN10) | \
+ PIN_ODR_LOW(GPIOF_DIR_Y) | \
+ PIN_ODR_LOW(GPIOF_STEP_Y) | \
+ PIN_ODR_LOW(GPIOF_HOME_X) | \
+ PIN_ODR_HIGH(GPIOF_MB_CS0_N) | \
+ PIN_ODR_LOW(GPIOF_MB_CS1_N))
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_SDA, 4) | \
+ PIN_AFIO_AF(GPIOF_SCL, 4) | \
+ PIN_AFIO_AF(GPIOF_PRE_CHARGE, 0) | \
+ PIN_AFIO_AF(GPIOF_VMOT_MEAS, 0) | \
+ PIN_AFIO_AF(GPIOF_CURR_OUT, 0) | \
+ PIN_AFIO_AF(GPIOF_VIN_MEAS, 0) | \
+ PIN_AFIO_AF(GPIOF_TEMP_E2, 0) | \
+ PIN_AFIO_AF(GPIOF_TEMP_E1, 0))
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_TEMP_E0, 0) | \
+ PIN_AFIO_AF(GPIOF_TEMP_HPB, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOF_DIR_Y, 0) | \
+ PIN_AFIO_AF(GPIOF_STEP_Y, 0) | \
+ PIN_AFIO_AF(GPIOF_HOME_X, 0) | \
+ PIN_AFIO_AF(GPIOF_MB_CS0_N, 0) | \
+ PIN_AFIO_AF(GPIOF_MB_CS1_N, 0))
+
+/*
+ * GPIOG setup:
+ *
+ * PG0 - DIR_X (output pushpull 2mhz).
+ * PG1 - STEP_X (output pushpull 2mhz).
+ * PG2 - STEP_E0 (output pushpull 2mhz).
+ * PG3 - DIR_E0 (output pushpull 2mhz).
+ * PG4 - STEP_E1 (output pushpull 2mhz).
+ * PG5 - DIR_E1 (output pushpull 2mhz).
+ * PG6 - LED_STS_2 (output pushpull 2mhz).
+ * PG7 - SCK_ST (alternate 8).
+ * PG8 - P (input floating).
+ * PG9 - SDO_ST (alternate 8).
+ * PG10 - CS_N (input floating).
+ * PG11 - ETH_TXEN (alternate 11).
+ * PG12 - CS_ST_N (output pushpull 25mhz).
+ * PG13 - ETH_TXD0 (alternate 11).
+ * PG14 - ETH_TXD1 (alternate 11).
+ * PG15 - P (input pull-up).
+ */
+#define VAL_GPIOG_MODER (PIN_MODE_OUTPUT(GPIOG_DIR_X) | \
+ PIN_MODE_OUTPUT(GPIOG_STEP_X) | \
+ PIN_MODE_OUTPUT(GPIOG_STEP_E0) | \
+ PIN_MODE_OUTPUT(GPIOG_DIR_E0) | \
+ PIN_MODE_OUTPUT(GPIOG_STEP_E1) | \
+ PIN_MODE_OUTPUT(GPIOG_DIR_E1) | \
+ PIN_MODE_OUTPUT(GPIOG_LED_STS_2) | \
+ PIN_MODE_ALTERNATE(GPIOG_SCK_ST) | \
+ PIN_MODE_INPUT(GPIOG_PIN8) | \
+ PIN_MODE_ALTERNATE(GPIOG_SDO_ST) | \
+ PIN_MODE_INPUT(GPIOG_CS_N) | \
+ PIN_MODE_ALTERNATE(GPIOG_ETH_TXEN) | \
+ PIN_MODE_OUTPUT(GPIOG_CS_ST_N) | \
+ PIN_MODE_ALTERNATE(GPIOG_ETH_TXD0) | \
+ PIN_MODE_ALTERNATE(GPIOG_ETH_TXD1) | \
+ PIN_MODE_INPUT(GPIOG_PIN15))
+#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_DIR_X) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_STEP_X) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_STEP_E0) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_DIR_E0) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_STEP_E1) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_DIR_E1) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_LED_STS_2) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_SCK_ST) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_SDO_ST) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_CS_N) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_ETH_TXEN) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_CS_ST_N) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_ETH_TXD0) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_ETH_TXD1) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
+#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_2M(GPIOG_DIR_X) | \
+ PIN_OSPEED_2M(GPIOG_STEP_X) | \
+ PIN_OSPEED_2M(GPIOG_STEP_E0) | \
+ PIN_OSPEED_2M(GPIOG_DIR_E0) | \
+ PIN_OSPEED_2M(GPIOG_STEP_E1) | \
+ PIN_OSPEED_2M(GPIOG_DIR_E1) | \
+ PIN_OSPEED_2M(GPIOG_LED_STS_2) | \
+ PIN_OSPEED_50M(GPIOG_SCK_ST) | \
+ PIN_OSPEED_50M(GPIOG_PIN8) | \
+ PIN_OSPEED_50M(GPIOG_SDO_ST) | \
+ PIN_OSPEED_50M(GPIOG_CS_N) | \
+ PIN_OSPEED_50M(GPIOG_ETH_TXEN) | \
+ PIN_OSPEED_25M(GPIOG_CS_ST_N) | \
+ PIN_OSPEED_50M(GPIOG_ETH_TXD0) | \
+ PIN_OSPEED_50M(GPIOG_ETH_TXD1) | \
+ PIN_OSPEED_2M(GPIOG_PIN15))
+#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_DIR_X) | \
+ PIN_PUPDR_FLOATING(GPIOG_STEP_X) | \
+ PIN_PUPDR_FLOATING(GPIOG_STEP_E0) | \
+ PIN_PUPDR_FLOATING(GPIOG_DIR_E0) | \
+ PIN_PUPDR_FLOATING(GPIOG_STEP_E1) | \
+ PIN_PUPDR_FLOATING(GPIOG_DIR_E1) | \
+ PIN_PUPDR_FLOATING(GPIOG_LED_STS_2) | \
+ PIN_PUPDR_FLOATING(GPIOG_SCK_ST) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOG_SDO_ST) | \
+ PIN_PUPDR_FLOATING(GPIOG_CS_N) | \
+ PIN_PUPDR_FLOATING(GPIOG_ETH_TXEN) | \
+ PIN_PUPDR_FLOATING(GPIOG_CS_ST_N) | \
+ PIN_PUPDR_FLOATING(GPIOG_ETH_TXD0) | \
+ PIN_PUPDR_FLOATING(GPIOG_ETH_TXD1) | \
+ PIN_PUPDR_PULLUP(GPIOG_PIN15))
+#define VAL_GPIOG_ODR (PIN_ODR_LOW(GPIOG_DIR_X) | \
+ PIN_ODR_LOW(GPIOG_STEP_X) | \
+ PIN_ODR_LOW(GPIOG_STEP_E0) | \
+ PIN_ODR_LOW(GPIOG_DIR_E0) | \
+ PIN_ODR_LOW(GPIOG_STEP_E1) | \
+ PIN_ODR_LOW(GPIOG_DIR_E1) | \
+ PIN_ODR_LOW(GPIOG_LED_STS_2) | \
+ PIN_ODR_LOW(GPIOG_SCK_ST) | \
+ PIN_ODR_LOW(GPIOG_PIN8) | \
+ PIN_ODR_LOW(GPIOG_SDO_ST) | \
+ PIN_ODR_LOW(GPIOG_CS_N) | \
+ PIN_ODR_LOW(GPIOG_ETH_TXEN) | \
+ PIN_ODR_HIGH(GPIOG_CS_ST_N) | \
+ PIN_ODR_LOW(GPIOG_ETH_TXD0) | \
+ PIN_ODR_LOW(GPIOG_ETH_TXD1) | \
+ PIN_ODR_LOW(GPIOG_PIN15))
+#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_DIR_X, 0) | \
+ PIN_AFIO_AF(GPIOG_STEP_X, 0) | \
+ PIN_AFIO_AF(GPIOG_STEP_E0, 0) | \
+ PIN_AFIO_AF(GPIOG_DIR_E0, 0) | \
+ PIN_AFIO_AF(GPIOG_STEP_E1, 0) | \
+ PIN_AFIO_AF(GPIOG_DIR_E1, 0) | \
+ PIN_AFIO_AF(GPIOG_LED_STS_2, 0) | \
+ PIN_AFIO_AF(GPIOG_SCK_ST, 8))
+#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOG_SDO_ST, 8) | \
+ PIN_AFIO_AF(GPIOG_CS_N, 12) | \
+ PIN_AFIO_AF(GPIOG_ETH_TXEN, 11) | \
+ PIN_AFIO_AF(GPIOG_CS_ST_N, 0) | \
+ PIN_AFIO_AF(GPIOG_ETH_TXD0, 11) | \
+ PIN_AFIO_AF(GPIOG_ETH_TXD1, 11) | \
+ PIN_AFIO_AF(GPIOG_PIN15, 0))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0 - P (input pull-up).
+ * PH1 - P (input pull-up).
+ * PH2 - P (input pull-up).
+ * PH3 - P (input pull-up).
+ * PH4 - P (input pull-up).
+ * PH5 - P (input pull-up).
+ * PH6 - P (input pull-up).
+ * PH7 - P (input pull-up).
+ * PH8 - P (input pull-up).
+ * PH9 - P (input pull-up).
+ * PH10 - P (input pull-up).
+ * PH11 - P (input pull-up).
+ * PH12 - P (input pull-up).
+ * PH13 - P (input pull-up).
+ * PH14 - P (input pull-up).
+ * PH15 - P (input pull-up).
+ */
+#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_PIN0) | \
+ PIN_MODE_INPUT(GPIOH_PIN1) | \
+ PIN_MODE_INPUT(GPIOH_PIN2) | \
+ PIN_MODE_INPUT(GPIOH_PIN3) | \
+ PIN_MODE_INPUT(GPIOH_PIN4) | \
+ PIN_MODE_INPUT(GPIOH_PIN5) | \
+ PIN_MODE_INPUT(GPIOH_PIN6) | \
+ PIN_MODE_INPUT(GPIOH_PIN7) | \
+ PIN_MODE_INPUT(GPIOH_PIN8) | \
+ PIN_MODE_INPUT(GPIOH_PIN9) | \
+ PIN_MODE_INPUT(GPIOH_PIN10) | \
+ PIN_MODE_INPUT(GPIOH_PIN11) | \
+ PIN_MODE_INPUT(GPIOH_PIN12) | \
+ PIN_MODE_INPUT(GPIOH_PIN13) | \
+ PIN_MODE_INPUT(GPIOH_PIN14) | \
+ PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_2M(GPIOH_PIN0) | \
+ PIN_OSPEED_2M(GPIOH_PIN1) | \
+ PIN_OSPEED_2M(GPIOH_PIN2) | \
+ PIN_OSPEED_2M(GPIOH_PIN3) | \
+ PIN_OSPEED_2M(GPIOH_PIN4) | \
+ PIN_OSPEED_2M(GPIOH_PIN5) | \
+ PIN_OSPEED_2M(GPIOH_PIN6) | \
+ PIN_OSPEED_2M(GPIOH_PIN7) | \
+ PIN_OSPEED_2M(GPIOH_PIN8) | \
+ PIN_OSPEED_2M(GPIOH_PIN9) | \
+ PIN_OSPEED_2M(GPIOH_PIN10) | \
+ PIN_OSPEED_2M(GPIOH_PIN11) | \
+ PIN_OSPEED_2M(GPIOH_PIN12) | \
+ PIN_OSPEED_2M(GPIOH_PIN13) | \
+ PIN_OSPEED_2M(GPIOH_PIN14) | \
+ PIN_OSPEED_2M(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR (PIN_PUPDR_PULLUP(GPIOH_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOH_PIN15))
+#define VAL_GPIOH_ODR (PIN_ODR_LOW(GPIOH_PIN0) | \
+ PIN_ODR_LOW(GPIOH_PIN1) | \
+ PIN_ODR_LOW(GPIOH_PIN2) | \
+ PIN_ODR_LOW(GPIOH_PIN3) | \
+ PIN_ODR_LOW(GPIOH_PIN4) | \
+ PIN_ODR_LOW(GPIOH_PIN5) | \
+ PIN_ODR_LOW(GPIOH_PIN6) | \
+ PIN_ODR_LOW(GPIOH_PIN7) | \
+ PIN_ODR_LOW(GPIOH_PIN8) | \
+ PIN_ODR_LOW(GPIOH_PIN9) | \
+ PIN_ODR_LOW(GPIOH_PIN10) | \
+ PIN_ODR_LOW(GPIOH_PIN11) | \
+ PIN_ODR_LOW(GPIOH_PIN12) | \
+ PIN_ODR_LOW(GPIOH_PIN13) | \
+ PIN_ODR_LOW(GPIOH_PIN14) | \
+ PIN_ODR_LOW(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN7, 0))
+#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN15, 0))
+
+/*
+ * GPIOI setup:
+ *
+ * PI0 - P (input pull-up).
+ * PI1 - P (input pull-up).
+ * PI2 - P (input pull-up).
+ * PI3 - P (input pull-up).
+ * PI4 - P (input pull-up).
+ * PI5 - P (input pull-up).
+ * PI6 - P (input pull-up).
+ * PI7 - P (input pull-up).
+ * PI8 - P (input pull-up).
+ * PI9 - P (input pull-up).
+ * PI10 - P (input pull-up).
+ * PI11 - P (input pull-up).
+ * PI12 - P (input pull-up).
+ * PI13 - P (input pull-up).
+ * PI14 - P (input pull-up).
+ * PI15 - P (input pull-up).
+ */
+#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \
+ PIN_MODE_INPUT(GPIOI_PIN1) | \
+ PIN_MODE_INPUT(GPIOI_PIN2) | \
+ PIN_MODE_INPUT(GPIOI_PIN3) | \
+ PIN_MODE_INPUT(GPIOI_PIN4) | \
+ PIN_MODE_INPUT(GPIOI_PIN5) | \
+ PIN_MODE_INPUT(GPIOI_PIN6) | \
+ PIN_MODE_INPUT(GPIOI_PIN7) | \
+ PIN_MODE_INPUT(GPIOI_PIN8) | \
+ PIN_MODE_INPUT(GPIOI_PIN9) | \
+ PIN_MODE_INPUT(GPIOI_PIN10) | \
+ PIN_MODE_INPUT(GPIOI_PIN11) | \
+ PIN_MODE_INPUT(GPIOI_PIN12) | \
+ PIN_MODE_INPUT(GPIOI_PIN13) | \
+ PIN_MODE_INPUT(GPIOI_PIN14) | \
+ PIN_MODE_INPUT(GPIOI_PIN15))
+#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
+#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_2M(GPIOI_PIN0) | \
+ PIN_OSPEED_2M(GPIOI_PIN1) | \
+ PIN_OSPEED_2M(GPIOI_PIN2) | \
+ PIN_OSPEED_2M(GPIOI_PIN3) | \
+ PIN_OSPEED_2M(GPIOI_PIN4) | \
+ PIN_OSPEED_2M(GPIOI_PIN5) | \
+ PIN_OSPEED_2M(GPIOI_PIN6) | \
+ PIN_OSPEED_2M(GPIOI_PIN7) | \
+ PIN_OSPEED_2M(GPIOI_PIN8) | \
+ PIN_OSPEED_2M(GPIOI_PIN9) | \
+ PIN_OSPEED_2M(GPIOI_PIN10) | \
+ PIN_OSPEED_2M(GPIOI_PIN11) | \
+ PIN_OSPEED_2M(GPIOI_PIN12) | \
+ PIN_OSPEED_2M(GPIOI_PIN13) | \
+ PIN_OSPEED_2M(GPIOI_PIN14) | \
+ PIN_OSPEED_2M(GPIOI_PIN15))
+#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOI_PIN15))
+#define VAL_GPIOI_ODR (PIN_ODR_LOW(GPIOI_PIN0) | \
+ PIN_ODR_LOW(GPIOI_PIN1) | \
+ PIN_ODR_LOW(GPIOI_PIN2) | \
+ PIN_ODR_LOW(GPIOI_PIN3) | \
+ PIN_ODR_LOW(GPIOI_PIN4) | \
+ PIN_ODR_LOW(GPIOI_PIN5) | \
+ PIN_ODR_LOW(GPIOI_PIN6) | \
+ PIN_ODR_LOW(GPIOI_PIN7) | \
+ PIN_ODR_LOW(GPIOI_PIN8) | \
+ PIN_ODR_LOW(GPIOI_PIN9) | \
+ PIN_ODR_LOW(GPIOI_PIN10) | \
+ PIN_ODR_LOW(GPIOI_PIN11) | \
+ PIN_ODR_LOW(GPIOI_PIN12) | \
+ PIN_ODR_LOW(GPIOI_PIN13) | \
+ PIN_ODR_LOW(GPIOI_PIN14) | \
+ PIN_ODR_LOW(GPIOI_PIN15))
+#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN7, 0))
+#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN15, 0))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/base/Marlin/chibios_board/board.mk b/boards/base/Marlin/chibios_board/board.mk
index 089f8de8..05a93398 100644
--- a/boards/base/Marlin/chibios_board/board.mk
+++ b/boards/base/Marlin/chibios_board/board.mk
@@ -1,3 +1,3 @@
-BOARDINC = $(GFXLIB)/boards/base/Marlin/chibios_board
-BOARDSRC = $(BOARDINC)/board.c \
-
+BOARDINC = $(GFXLIB)/boards/base/Marlin/chibios_board
+BOARDSRC = $(BOARDINC)/board.c \
+
diff --git a/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.c b/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.c
index cdac2a79..f20adbec 100644
--- a/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.c
+++ b/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.c
@@ -1,106 +1,106 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-/**
- * @brief PAL setup.
- * @details Digital I/O ports static configuration as defined in @p board.h.
- * This variable is used by the HAL when initializing the PAL driver.
- */
-const PALConfig pal_default_config =
-{
- {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
- VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
- {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
- VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
- {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
- VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
- {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
- VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
- {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
- VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
- {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
- VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
- {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
- VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
- {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
- VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
- {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
- VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
-};
-#endif
-
-/**
- * @brief Early initialization code.
- * @details This initialization must be performed just after stack setup
- * and before any other initialization.
- */
-void __early_init(void) {
-
- stm32_clock_init();
-}
-
-#if HAL_USE_SDC || defined(__DOXYGEN__)
-/**
- * @brief SDC card detection.
- */
-bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
-
- (void)sdcp;
- /* TODO: Fill the implementation.*/
- return TRUE;
-}
-
-/**
- * @brief SDC card write protection detection.
- */
-bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
-
- (void)sdcp;
- /* TODO: Fill the implementation.*/
- return FALSE;
-}
-#endif /* HAL_USE_SDC */
-
-#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
-/**
- * @brief MMC_SPI card detection.
- */
-bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
-
- (void)mmcp;
- return !palReadPad(GPIOD, GPIOD_SD_CD);
-}
-
-/**
- * @brief MMC_SPI card write protection detection.
- */
-bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
-
- (void)mmcp;
- /* Board has no write protection detection */
- return FALSE;
-}
-#endif
-
-/**
- * @brief Board-specific initialization code.
- * @todo Add your board-specific code, if any.
- */
-void boardInit(void) {
-}
+/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* TODO: Fill the implementation.*/
+ return TRUE;
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* TODO: Fill the implementation.*/
+ return FALSE;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ return !palReadPad(GPIOD, GPIOD_SD_CD);
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* Board has no write protection detection */
+ return FALSE;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.h b/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.h
index b5ee34ad..4d9c66ec 100644
--- a/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.h
+++ b/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.h
@@ -1,1296 +1,1296 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/*
- * Setup for mikromedia STM32-M4 board.
- */
-
-/*
- * Board identifier.
- */
-#define BOARD_MIKROE_MIKROMEDIA_M4
-#define BOARD_NAME "mikromedia STM32-M4"
-
-
-/*
- * Board oscillators-related settings.
- */
-#if !defined(STM32_LSECLK)
-#define STM32_LSECLK 32768
-#endif
-
-#if !defined(STM32_HSECLK)
-#define STM32_HSECLK 16000000
-#endif
-
-/*
- * Board voltages.
- * Required for performance limits calculation.
- */
-#define STM32_VDD 330
-
-/*
- * MCU type as defined in the ST header.
- */
-#define STM32F40_41xxx
-#define STM32F407xx
-
-/*
- * IO pins assignments.
- */
-#define GPIOA_VSENSE 0
-#define GPIOA_PIN1 1
-#define GPIOA_PIN2 2
-#define GPIOA_PIN3 3
-#define GPIOA_PIN4 4
-#define GPIOA_PIN5 5
-#define GPIOA_PIN6 6
-#define GPIOA_PIN7 7
-#define GPIOA_PIN8 8
-#define GPIOA_VBUS_FS 9
-#define GPIOA_PIN10 10
-#define GPIOA_OTG_FS_DM 11
-#define GPIOA_OTG_FS_DP 12
-#define GPIOA_TMS 13
-#define GPIOA_TCK 14
-#define GPIOA_TDI 15
-
-#define GPIOB_LCD_YD 0
-#define GPIOB_LCD_XL 1
-#define GPIOB_PIN2 2
-#define GPIOB_TDO 3
-#define GPIOB_TRST 4
-#define GPIOB_PIN5 5
-#define GPIOB_SCL1 6
-#define GPIOB_SDA1 7
-#define GPIOB_DRIVEA 8
-#define GPIOB_DRIVEB 9
-#define GPIOB_SCL2 10
-#define GPIOB_SDA2 11
-#define GPIOB_PIN12 12
-#define GPIOB_SCK2 13
-#define GPIOB_MISO2 14
-#define GPIOB_MOSI2 15
-
-#define GPIOC_PIN0 0
-#define GPIOC_PIN1 1
-#define GPIOC_PIN2 2
-#define GPIOC_PIN3 3
-#define GPIOC_PIN4 4
-#define GPIOC_PIN5 5
-#define GPIOC_MP3_DREQ 6
-#define GPIOC_MP3_RST 7
-#define GPIOC_MP3_CS 8
-#define GPIOC_MP3_DCS 9
-#define GPIOC_SCK3 10
-#define GPIOC_MISO3 11
-#define GPIOC_MOSI3 12
-#define GPIOC_STAT 13
-#define GPIOC_PIN14 14
-#define GPIOC_PIN15 15
-
-#define GPIOD_PIN0 0
-#define GPIOD_PIN1 1
-#define GPIOD_PIN2 2
-#define GPIOD_SD_CS 3
-#define GPIOD_PIN4 4
-#define GPIOD_TX2 5
-#define GPIOD_RX2 6
-#define GPIOD_FLASH_CS 7
-#define GPIOD_PIN8 8
-#define GPIOD_PIN9 9
-#define GPIOD_PIN10 10
-#define GPIOD_PIN11 11
-#define GPIOD_PIN12 12
-#define GPIOD_PIN13 13
-#define GPIOD_PIN14 14
-#define GPIOD_SD_CD 15
-
-#define GPIOE_TD0 0
-#define GPIOE_TD1 1
-#define GPIOE_TD2 2
-#define GPIOE_TD3 3
-#define GPIOE_TD4 4
-#define GPIOE_TD5 5
-#define GPIOE_TD6 6
-#define GPIOE_TD7 7
-#define GPIOE_LCD_RST 8
-#define GPIOE_LCD_BLED 9
-#define GPIOE_PMRD 10
-#define GPIOE_PMWR 11
-#define GPIOE_LCD_RS 12
-#define GPIOE_PIN13 13
-#define GPIOE_PIN14 14
-#define GPIOE_LCD_CS 15
-
-#define GPIOF_PIN0 0
-#define GPIOF_PIN1 1
-#define GPIOF_PIN2 2
-#define GPIOF_PIN3 3
-#define GPIOF_PIN4 4
-#define GPIOF_PIN5 5
-#define GPIOF_PIN6 6
-#define GPIOF_PIN7 7
-#define GPIOF_PIN8 8
-#define GPIOF_PIN9 9
-#define GPIOF_PIN10 10
-#define GPIOF_PIN11 11
-#define GPIOF_PIN12 12
-#define GPIOF_PIN13 13
-#define GPIOF_PIN14 14
-#define GPIOF_PIN15 15
-
-#define GPIOG_PIN0 0
-#define GPIOG_PIN1 1
-#define GPIOG_PIN2 2
-#define GPIOG_PIN3 3
-#define GPIOG_PIN4 4
-#define GPIOG_PIN5 5
-#define GPIOG_PIN6 6
-#define GPIOG_PIN7 7
-#define GPIOG_PIN8 8
-#define GPIOG_PIN9 9
-#define GPIOG_PIN10 10
-#define GPIOG_PIN11 11
-#define GPIOG_PIN12 12
-#define GPIOG_PIN13 13
-#define GPIOG_PIN14 14
-#define GPIOG_PIN15 15
-
-#define GPIOH_OSC_IN 0
-#define GPIOH_OSC_OUT 1
-#define GPIOH_PIN2 2
-#define GPIOH_PIN3 3
-#define GPIOH_PIN4 4
-#define GPIOH_PIN5 5
-#define GPIOH_PIN6 6
-#define GPIOH_PIN7 7
-#define GPIOH_PIN8 8
-#define GPIOH_PIN9 9
-#define GPIOH_PIN10 10
-#define GPIOH_PIN11 11
-#define GPIOH_PIN12 12
-#define GPIOH_PIN13 13
-#define GPIOH_PIN14 14
-#define GPIOH_PIN15 15
-
-#define GPIOI_PIN0 0
-#define GPIOI_PIN1 1
-#define GPIOI_PIN2 2
-#define GPIOI_PIN3 3
-#define GPIOI_PIN4 4
-#define GPIOI_PIN5 5
-#define GPIOI_PIN6 6
-#define GPIOI_PIN7 7
-#define GPIOI_PIN8 8
-#define GPIOI_PIN9 9
-#define GPIOI_PIN10 10
-#define GPIOI_PIN11 11
-#define GPIOI_PIN12 12
-#define GPIOI_PIN13 13
-#define GPIOI_PIN14 14
-#define GPIOI_PIN15 15
-
-/*
- * I/O ports initial setup, this configuration is established soon after reset
- * in the initialization code.
- * Please refer to the STM32 Reference Manual for details.
- */
-#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
-#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
-#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
-#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
-#define PIN_ODR_LOW(n) (0U << (n))
-#define PIN_ODR_HIGH(n) (1U << (n))
-#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
-#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
-#define PIN_OSPEED_2M(n) (0U << ((n) * 2))
-#define PIN_OSPEED_25M(n) (1U << ((n) * 2))
-#define PIN_OSPEED_50M(n) (2U << ((n) * 2))
-#define PIN_OSPEED_100M(n) (3U << ((n) * 2))
-#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2))
-#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2))
-#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2))
-#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))
-
-/*
- * GPIOA setup:
- *
- * PA0 - VSENSE (analog).
- * PA1 - PIN1 (input pullup).
- * PA2 - PIN2 (input pullup).
- * PA3 - PIN3 (input pullup).
- * PA4 - PIN4 (alternate 6).
- * PA5 - PIN5 (alternate 5).
- * PA6 - PIN6 (alternate 5).
- * PA7 - PIN7 (alternate 5).
- * PA8 - PIN8 (input pullup).
- * PA9 - VBUS_FS (input floating).
- * PA10 - PIN10 (input floating).
- * PA11 - OTG_FS_DM (alternate 10).
- * PA12 - OTG_FS_DP (alternate 10).
- * PA13 - TMS (alternate 0).
- * PA14 - TCK (alternate 0).
- * PA15 - TDI (input pullup).
- */
-#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_VSENSE) | \
- PIN_MODE_INPUT(GPIOA_PIN1) | \
- PIN_MODE_INPUT(GPIOA_PIN2) | \
- PIN_MODE_INPUT(GPIOA_PIN3) | \
- PIN_MODE_ALTERNATE(GPIOA_PIN4) | \
- PIN_MODE_ALTERNATE(GPIOA_PIN5) | \
- PIN_MODE_ALTERNATE(GPIOA_PIN6) | \
- PIN_MODE_ALTERNATE(GPIOA_PIN7) | \
- PIN_MODE_INPUT(GPIOA_PIN8) | \
- PIN_MODE_INPUT(GPIOA_VBUS_FS) | \
- PIN_MODE_INPUT(GPIOA_PIN10) | \
- PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \
- PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \
- PIN_MODE_ALTERNATE(GPIOA_TMS) | \
- PIN_MODE_ALTERNATE(GPIOA_TCK) | \
- PIN_MODE_INPUT(GPIOA_TDI))
-#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_VSENSE) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOA_VBUS_FS) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \
- PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \
- PIN_OTYPE_PUSHPULL(GPIOA_TMS) | \
- PIN_OTYPE_PUSHPULL(GPIOA_TCK) | \
- PIN_OTYPE_PUSHPULL(GPIOA_TDI))
-#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_100M(GPIOA_VSENSE) | \
- PIN_OSPEED_100M(GPIOA_PIN1) | \
- PIN_OSPEED_100M(GPIOA_PIN2) | \
- PIN_OSPEED_100M(GPIOA_PIN3) | \
- PIN_OSPEED_100M(GPIOA_PIN4) | \
- PIN_OSPEED_50M(GPIOA_PIN5) | \
- PIN_OSPEED_50M(GPIOA_PIN6) | \
- PIN_OSPEED_50M(GPIOA_PIN7) | \
- PIN_OSPEED_100M(GPIOA_PIN8) | \
- PIN_OSPEED_100M(GPIOA_VBUS_FS) | \
- PIN_OSPEED_100M(GPIOA_PIN10) | \
- PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \
- PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \
- PIN_OSPEED_100M(GPIOA_TMS) | \
- PIN_OSPEED_100M(GPIOA_TCK) | \
- PIN_OSPEED_100M(GPIOA_TDI))
-#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_VSENSE) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN1) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN2) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN3) | \
- PIN_PUPDR_FLOATING(GPIOA_PIN4) | \
- PIN_PUPDR_FLOATING(GPIOA_PIN5) | \
- PIN_PUPDR_FLOATING(GPIOA_PIN6) | \
- PIN_PUPDR_FLOATING(GPIOA_PIN7) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN8) | \
- PIN_PUPDR_FLOATING(GPIOA_VBUS_FS) | \
- PIN_PUPDR_FLOATING(GPIOA_PIN10) | \
- PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \
- PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \
- PIN_PUPDR_FLOATING(GPIOA_TMS) | \
- PIN_PUPDR_FLOATING(GPIOA_TCK) | \
- PIN_PUPDR_PULLUP(GPIOA_TDI))
-#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_VSENSE) | \
- PIN_ODR_HIGH(GPIOA_PIN1) | \
- PIN_ODR_HIGH(GPIOA_PIN2) | \
- PIN_ODR_HIGH(GPIOA_PIN3) | \
- PIN_ODR_HIGH(GPIOA_PIN4) | \
- PIN_ODR_HIGH(GPIOA_PIN5) | \
- PIN_ODR_HIGH(GPIOA_PIN6) | \
- PIN_ODR_HIGH(GPIOA_PIN7) | \
- PIN_ODR_HIGH(GPIOA_PIN8) | \
- PIN_ODR_HIGH(GPIOA_VBUS_FS) | \
- PIN_ODR_HIGH(GPIOA_PIN10) | \
- PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \
- PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \
- PIN_ODR_HIGH(GPIOA_TMS) | \
- PIN_ODR_HIGH(GPIOA_TCK) | \
- PIN_ODR_HIGH(GPIOA_TDI))
-#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_VSENSE, 0) | \
- PIN_AFIO_AF(GPIOA_PIN1, 0) | \
- PIN_AFIO_AF(GPIOA_PIN2, 0) | \
- PIN_AFIO_AF(GPIOA_PIN3, 0) | \
- PIN_AFIO_AF(GPIOA_PIN4, 6) | \
- PIN_AFIO_AF(GPIOA_PIN5, 5) | \
- PIN_AFIO_AF(GPIOA_PIN6, 5) | \
- PIN_AFIO_AF(GPIOA_PIN7, 5))
-#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \
- PIN_AFIO_AF(GPIOA_VBUS_FS, 0) | \
- PIN_AFIO_AF(GPIOA_PIN10, 0) | \
- PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \
- PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \
- PIN_AFIO_AF(GPIOA_TMS, 0) | \
- PIN_AFIO_AF(GPIOA_TCK, 0) | \
- PIN_AFIO_AF(GPIOA_TDI, 0))
-
-/*
- * GPIOB setup:
- *
- * PB0 - LCD_YD (analog).
- * PB1 - LCD_XL (analog).
- * PB2 - PIN2 (input pullup).
- * PB3 - TDO (alternate 0).
- * PB4 - TRST (input pullup).
- * PB5 - PIN5 (input pullup).
- * PB6 - SCL1 (alternate 4).
- * PB7 - SDA1 (input pullup).
- * PB8 - DRIVEA (output pushpull maximum).
- * PB9 - DRIVEB (output opendrain maximum).
- * PB10 - SCL2 (input pullup).
- * PB11 - SDA2 (input pullup).
- * PB12 - PIN12 (input pullup).
- * PB13 - SCK2 (input pullup).
- * PB14 - MISO2 (input pullup).
- * PB15 - MOSI2 (input pullup).
- */
-#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_LCD_YD) | \
- PIN_MODE_ANALOG(GPIOB_LCD_XL) | \
- PIN_MODE_INPUT(GPIOB_PIN2) | \
- PIN_MODE_ALTERNATE(GPIOB_TDO) | \
- PIN_MODE_INPUT(GPIOB_TRST) | \
- PIN_MODE_INPUT(GPIOB_PIN5) | \
- PIN_MODE_ALTERNATE(GPIOB_SCL1) | \
- PIN_MODE_INPUT(GPIOB_SDA1) | \
- PIN_MODE_OUTPUT(GPIOB_DRIVEA) | \
- PIN_MODE_OUTPUT(GPIOB_DRIVEB) | \
- PIN_MODE_INPUT(GPIOB_SCL2) | \
- PIN_MODE_INPUT(GPIOB_SDA2) | \
- PIN_MODE_INPUT(GPIOB_PIN12) | \
- PIN_MODE_INPUT(GPIOB_SCK2) | \
- PIN_MODE_INPUT(GPIOB_MISO2) | \
- PIN_MODE_INPUT(GPIOB_MOSI2))
-#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_LCD_YD) | \
- PIN_OTYPE_PUSHPULL(GPIOB_LCD_XL) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOB_TDO) | \
- PIN_OTYPE_PUSHPULL(GPIOB_TRST) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
- PIN_OTYPE_OPENDRAIN(GPIOB_SCL1) | \
- PIN_OTYPE_PUSHPULL(GPIOB_SDA1) | \
- PIN_OTYPE_PUSHPULL(GPIOB_DRIVEA) | \
- PIN_OTYPE_OPENDRAIN(GPIOB_DRIVEB) | \
- PIN_OTYPE_PUSHPULL(GPIOB_SCL2) | \
- PIN_OTYPE_PUSHPULL(GPIOB_SDA2) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOB_SCK2) | \
- PIN_OTYPE_PUSHPULL(GPIOB_MISO2) | \
- PIN_OTYPE_PUSHPULL(GPIOB_MOSI2))
-#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_LCD_YD) | \
- PIN_OSPEED_100M(GPIOB_LCD_XL) | \
- PIN_OSPEED_100M(GPIOB_PIN2) | \
- PIN_OSPEED_100M(GPIOB_TDO) | \
- PIN_OSPEED_100M(GPIOB_TRST) | \
- PIN_OSPEED_100M(GPIOB_PIN5) | \
- PIN_OSPEED_100M(GPIOB_SCL1) | \
- PIN_OSPEED_100M(GPIOB_SDA1) | \
- PIN_OSPEED_100M(GPIOB_DRIVEA) | \
- PIN_OSPEED_100M(GPIOB_DRIVEB) | \
- PIN_OSPEED_100M(GPIOB_SCL2) | \
- PIN_OSPEED_100M(GPIOB_SDA2) | \
- PIN_OSPEED_100M(GPIOB_PIN12) | \
- PIN_OSPEED_100M(GPIOB_SCK2) | \
- PIN_OSPEED_100M(GPIOB_MISO2) | \
- PIN_OSPEED_100M(GPIOB_MOSI2))
-#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_LCD_YD) | \
- PIN_PUPDR_FLOATING(GPIOB_LCD_XL) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
- PIN_PUPDR_FLOATING(GPIOB_TDO) | \
- PIN_PUPDR_PULLUP(GPIOB_TRST) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
- PIN_PUPDR_FLOATING(GPIOB_SCL1) | \
- PIN_PUPDR_PULLUP(GPIOB_SDA1) | \
- PIN_PUPDR_FLOATING(GPIOB_DRIVEA) | \
- PIN_PUPDR_FLOATING(GPIOB_DRIVEB) | \
- PIN_PUPDR_PULLUP(GPIOB_SCL2) | \
- PIN_PUPDR_PULLUP(GPIOB_SDA2) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
- PIN_PUPDR_PULLUP(GPIOB_SCK2) | \
- PIN_PUPDR_PULLUP(GPIOB_MISO2) | \
- PIN_PUPDR_PULLUP(GPIOB_MOSI2))
-#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_LCD_YD) | \
- PIN_ODR_HIGH(GPIOB_LCD_XL) | \
- PIN_ODR_HIGH(GPIOB_PIN2) | \
- PIN_ODR_HIGH(GPIOB_TDO) | \
- PIN_ODR_HIGH(GPIOB_TRST) | \
- PIN_ODR_HIGH(GPIOB_PIN5) | \
- PIN_ODR_HIGH(GPIOB_SCL1) | \
- PIN_ODR_HIGH(GPIOB_SDA1) | \
- PIN_ODR_HIGH(GPIOB_DRIVEA) | \
- PIN_ODR_HIGH(GPIOB_DRIVEB) | \
- PIN_ODR_HIGH(GPIOB_SCL2) | \
- PIN_ODR_HIGH(GPIOB_SDA2) | \
- PIN_ODR_HIGH(GPIOB_PIN12) | \
- PIN_ODR_HIGH(GPIOB_SCK2) | \
- PIN_ODR_HIGH(GPIOB_MISO2) | \
- PIN_ODR_HIGH(GPIOB_MOSI2))
-#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_LCD_YD, 0) | \
- PIN_AFIO_AF(GPIOB_LCD_XL, 0) | \
- PIN_AFIO_AF(GPIOB_PIN2, 0) | \
- PIN_AFIO_AF(GPIOB_TDO, 0) | \
- PIN_AFIO_AF(GPIOB_TRST, 0) | \
- PIN_AFIO_AF(GPIOB_PIN5, 0) | \
- PIN_AFIO_AF(GPIOB_SCL1, 4) | \
- PIN_AFIO_AF(GPIOB_SDA1, 4))
-#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_DRIVEA, 0) | \
- PIN_AFIO_AF(GPIOB_DRIVEB, 0) | \
- PIN_AFIO_AF(GPIOB_SCL2, 0) | \
- PIN_AFIO_AF(GPIOB_SDA2, 0) | \
- PIN_AFIO_AF(GPIOB_PIN12, 0) | \
- PIN_AFIO_AF(GPIOB_SCK2, 0) | \
- PIN_AFIO_AF(GPIOB_MISO2, 0) | \
- PIN_AFIO_AF(GPIOB_MOSI2, 0))
-
-/*
- * GPIOC setup:
- *
- * PC0 - PIN0 (output pushpull maximum).
- * PC1 - PIN1 (input pullup).
- * PC2 - PIN2 (input pullup).
- * PC3 - PIN3 (input pullup).
- * PC4 - PIN4 (input pullup).
- * PC5 - PIN5 (input pullup).
- * PC6 - MP3_DREQ (input pullup).
- * PC7 - MP3_RST (alternate 6).
- * PC8 - MP3_CS (output pushpull maximum).
- * PC9 - MP3_DCS (input pullup).
- * PC10 - SCK3 (alternate 6).
- * PC11 - MISO3 (alternate 6).
- * PC12 - MOSI3 (alternate 6).
- * PC13 - STAT (input pullup).
- * PC14 - PIN14 (input pullup).
- * PC15 - PIN15 (input pullup).
- */
-#define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_PIN0) | \
- PIN_MODE_INPUT(GPIOC_PIN1) | \
- PIN_MODE_INPUT(GPIOC_PIN2) | \
- PIN_MODE_INPUT(GPIOC_PIN3) | \
- PIN_MODE_INPUT(GPIOC_PIN4) | \
- PIN_MODE_INPUT(GPIOC_PIN5) | \
- PIN_MODE_INPUT(GPIOC_MP3_DREQ) | \
- PIN_MODE_ALTERNATE(GPIOC_MP3_RST) | \
- PIN_MODE_OUTPUT(GPIOC_MP3_CS) | \
- PIN_MODE_INPUT(GPIOC_MP3_DCS) | \
- PIN_MODE_ALTERNATE(GPIOC_SCK3) | \
- PIN_MODE_ALTERNATE(GPIOC_MISO3) | \
- PIN_MODE_ALTERNATE(GPIOC_MOSI3) | \
- PIN_MODE_INPUT(GPIOC_STAT) | \
- PIN_MODE_INPUT(GPIOC_PIN14) | \
- PIN_MODE_INPUT(GPIOC_PIN15))
-#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOC_MP3_DREQ) | \
- PIN_OTYPE_PUSHPULL(GPIOC_MP3_RST) | \
- PIN_OTYPE_PUSHPULL(GPIOC_MP3_CS) | \
- PIN_OTYPE_PUSHPULL(GPIOC_MP3_DCS) | \
- PIN_OTYPE_PUSHPULL(GPIOC_SCK3) | \
- PIN_OTYPE_PUSHPULL(GPIOC_MISO3) | \
- PIN_OTYPE_PUSHPULL(GPIOC_MOSI3) | \
- PIN_OTYPE_PUSHPULL(GPIOC_STAT) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
-#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(GPIOC_PIN0) | \
- PIN_OSPEED_100M(GPIOC_PIN1) | \
- PIN_OSPEED_100M(GPIOC_PIN2) | \
- PIN_OSPEED_100M(GPIOC_PIN3) | \
- PIN_OSPEED_100M(GPIOC_PIN4) | \
- PIN_OSPEED_100M(GPIOC_PIN5) | \
- PIN_OSPEED_100M(GPIOC_MP3_DREQ) | \
- PIN_OSPEED_100M(GPIOC_MP3_RST) | \
- PIN_OSPEED_100M(GPIOC_MP3_CS) | \
- PIN_OSPEED_100M(GPIOC_MP3_DCS) | \
- PIN_OSPEED_100M(GPIOC_SCK3) | \
- PIN_OSPEED_100M(GPIOC_MISO3) | \
- PIN_OSPEED_100M(GPIOC_MOSI3) | \
- PIN_OSPEED_100M(GPIOC_STAT) | \
- PIN_OSPEED_100M(GPIOC_PIN14) | \
- PIN_OSPEED_100M(GPIOC_PIN15))
-#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_PIN0) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN1) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN2) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN3) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN4) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN5) | \
- PIN_PUPDR_PULLUP(GPIOC_MP3_DREQ) | \
- PIN_PUPDR_FLOATING(GPIOC_MP3_RST) | \
- PIN_PUPDR_PULLUP(GPIOC_MP3_CS) | \
- PIN_PUPDR_PULLUP(GPIOC_MP3_DCS) | \
- PIN_PUPDR_FLOATING(GPIOC_SCK3) | \
- PIN_PUPDR_FLOATING(GPIOC_MISO3) | \
- PIN_PUPDR_FLOATING(GPIOC_MOSI3) | \
- PIN_PUPDR_PULLUP(GPIOC_STAT) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN14) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN15))
-#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \
- PIN_ODR_HIGH(GPIOC_PIN1) | \
- PIN_ODR_HIGH(GPIOC_PIN2) | \
- PIN_ODR_HIGH(GPIOC_PIN3) | \
- PIN_ODR_HIGH(GPIOC_PIN4) | \
- PIN_ODR_HIGH(GPIOC_PIN5) | \
- PIN_ODR_HIGH(GPIOC_MP3_DREQ) | \
- PIN_ODR_HIGH(GPIOC_MP3_RST) | \
- PIN_ODR_HIGH(GPIOC_MP3_CS) | \
- PIN_ODR_HIGH(GPIOC_MP3_DCS) | \
- PIN_ODR_HIGH(GPIOC_SCK3) | \
- PIN_ODR_HIGH(GPIOC_MISO3) | \
- PIN_ODR_HIGH(GPIOC_MOSI3) | \
- PIN_ODR_HIGH(GPIOC_STAT) | \
- PIN_ODR_HIGH(GPIOC_PIN14) | \
- PIN_ODR_HIGH(GPIOC_PIN15))
-#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | \
- PIN_AFIO_AF(GPIOC_PIN1, 0) | \
- PIN_AFIO_AF(GPIOC_PIN2, 0) | \
- PIN_AFIO_AF(GPIOC_PIN3, 0) | \
- PIN_AFIO_AF(GPIOC_PIN4, 0) | \
- PIN_AFIO_AF(GPIOC_PIN5, 0) | \
- PIN_AFIO_AF(GPIOC_MP3_DREQ, 0) | \
- PIN_AFIO_AF(GPIOC_MP3_RST, 6))
-#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_MP3_CS, 0) | \
- PIN_AFIO_AF(GPIOC_MP3_DCS, 0) | \
- PIN_AFIO_AF(GPIOC_SCK3, 6) | \
- PIN_AFIO_AF(GPIOC_MISO3, 6) | \
- PIN_AFIO_AF(GPIOC_MOSI3, 6) | \
- PIN_AFIO_AF(GPIOC_STAT, 0) | \
- PIN_AFIO_AF(GPIOC_PIN14, 0) | \
- PIN_AFIO_AF(GPIOC_PIN15, 0))
-
-/*
- * GPIOD setup:
- *
- * PD0 - PIN0 (input pullup).
- * PD1 - PIN1 (input pullup).
- * PD2 - PIN2 (input pullup).
- * PD3 - SD_CS (output pushpull maximum).
- * PD4 - PIN4 (output pushpull maximum).
- * PD5 - TX2 (alternate 7).
- * PD6 - RX2 (alternate 7).
- * PD7 - FLASH_CS (output pushpull maximum).
- * PD8 - PIN8 (input pullup).
- * PD9 - PIN9 (input pullup).
- * PD10 - PIN10 (input pullup).
- * PD11 - PIN11 (input pullup).
- * PD12 - PIN12 (output pushpull maximum).
- * PD13 - PIN13 (output pushpull maximum).
- * PD14 - PIN14 (output pushpull maximum).
- * PD15 - SD_CD (input pullup).
- */
-#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
- PIN_MODE_INPUT(GPIOD_PIN1) | \
- PIN_MODE_INPUT(GPIOD_PIN2) | \
- PIN_MODE_OUTPUT(GPIOD_SD_CS) | \
- PIN_MODE_OUTPUT(GPIOD_PIN4) | \
- PIN_MODE_ALTERNATE(GPIOD_TX2) | \
- PIN_MODE_ALTERNATE(GPIOD_RX2) | \
- PIN_MODE_OUTPUT(GPIOD_FLASH_CS) | \
- PIN_MODE_INPUT(GPIOD_PIN8) | \
- PIN_MODE_INPUT(GPIOD_PIN9) | \
- PIN_MODE_INPUT(GPIOD_PIN10) | \
- PIN_MODE_INPUT(GPIOD_PIN11) | \
- PIN_MODE_OUTPUT(GPIOD_PIN12) | \
- PIN_MODE_OUTPUT(GPIOD_PIN13) | \
- PIN_MODE_OUTPUT(GPIOD_PIN14) | \
- PIN_MODE_INPUT(GPIOD_SD_CD))
-#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOD_SD_CS) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOD_TX2) | \
- PIN_OTYPE_PUSHPULL(GPIOD_RX2) | \
- PIN_OTYPE_PUSHPULL(GPIOD_FLASH_CS) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOD_SD_CD))
-#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_PIN0) | \
- PIN_OSPEED_100M(GPIOD_PIN1) | \
- PIN_OSPEED_100M(GPIOD_PIN2) | \
- PIN_OSPEED_100M(GPIOD_SD_CS) | \
- PIN_OSPEED_100M(GPIOD_PIN4) | \
- PIN_OSPEED_100M(GPIOD_TX2) | \
- PIN_OSPEED_100M(GPIOD_RX2) | \
- PIN_OSPEED_100M(GPIOD_FLASH_CS) | \
- PIN_OSPEED_100M(GPIOD_PIN8) | \
- PIN_OSPEED_100M(GPIOD_PIN9) | \
- PIN_OSPEED_100M(GPIOD_PIN10) | \
- PIN_OSPEED_100M(GPIOD_PIN11) | \
- PIN_OSPEED_100M(GPIOD_PIN12) | \
- PIN_OSPEED_100M(GPIOD_PIN13) | \
- PIN_OSPEED_100M(GPIOD_PIN14) | \
- PIN_OSPEED_100M(GPIOD_SD_CD))
-#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN2) | \
- PIN_PUPDR_FLOATING(GPIOD_SD_CS) | \
- PIN_PUPDR_FLOATING(GPIOD_PIN4) | \
- PIN_PUPDR_FLOATING(GPIOD_TX2) | \
- PIN_PUPDR_PULLUP(GPIOD_RX2) | \
- PIN_PUPDR_PULLUP(GPIOD_FLASH_CS) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
- PIN_PUPDR_FLOATING(GPIOD_PIN12) | \
- PIN_PUPDR_FLOATING(GPIOD_PIN13) | \
- PIN_PUPDR_FLOATING(GPIOD_PIN14) | \
- PIN_PUPDR_PULLUP(GPIOD_SD_CD))
-#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
- PIN_ODR_HIGH(GPIOD_PIN1) | \
- PIN_ODR_HIGH(GPIOD_PIN2) | \
- PIN_ODR_HIGH(GPIOD_SD_CS) | \
- PIN_ODR_HIGH(GPIOD_PIN4) | \
- PIN_ODR_HIGH(GPIOD_TX2) | \
- PIN_ODR_HIGH(GPIOD_RX2) | \
- PIN_ODR_HIGH(GPIOD_FLASH_CS) | \
- PIN_ODR_HIGH(GPIOD_PIN8) | \
- PIN_ODR_HIGH(GPIOD_PIN9) | \
- PIN_ODR_HIGH(GPIOD_PIN10) | \
- PIN_ODR_HIGH(GPIOD_PIN11) | \
- PIN_ODR_LOW(GPIOD_PIN12) | \
- PIN_ODR_LOW(GPIOD_PIN13) | \
- PIN_ODR_LOW(GPIOD_PIN14) | \
- PIN_ODR_LOW(GPIOD_SD_CD))
-#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \
- PIN_AFIO_AF(GPIOD_PIN1, 0) | \
- PIN_AFIO_AF(GPIOD_PIN2, 0) | \
- PIN_AFIO_AF(GPIOD_SD_CS, 0) | \
- PIN_AFIO_AF(GPIOD_PIN4, 0) | \
- PIN_AFIO_AF(GPIOD_TX2, 7) | \
- PIN_AFIO_AF(GPIOD_RX2, 7) | \
- PIN_AFIO_AF(GPIOD_FLASH_CS, 0))
-#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \
- PIN_AFIO_AF(GPIOD_PIN9, 0) | \
- PIN_AFIO_AF(GPIOD_PIN10, 0) | \
- PIN_AFIO_AF(GPIOD_PIN11, 0) | \
- PIN_AFIO_AF(GPIOD_PIN12, 0) | \
- PIN_AFIO_AF(GPIOD_PIN13, 0) | \
- PIN_AFIO_AF(GPIOD_PIN14, 0) | \
- PIN_AFIO_AF(GPIOD_SD_CD, 0))
-
-/*
- * GPIOE setup:
- *
- * PE0 - TD0 (output pushpull maximum).
- * PE1 - TD1 (output pushpull maximum).
- * PE2 - TD2 (output pushpull maximum).
- * PE3 - TD3 (output pushpull maximum).
- * PE4 - TD4 (output pushpull maximum).
- * PE5 - TD5 (output pushpull maximum).
- * PE6 - TD6 (output pushpull maximum).
- * PE7 - TD7 (output pushpull maximum).
- * PE8 - LCD_RST (output pushpull maximum).
- * PE9 - LCD_BLED (output pushpull maximum).
- * PE10 - PMRD (output pushpull maximum).
- * PE11 - PMWR (output pushpull maximum).
- * PE12 - LCD_RS (output pushpull maximum).
- * PE13 - PIN13 (input floating).
- * PE14 - PIN14 (input floating).
- * PE15 - LCD_CS (output pushpull maximum).
- */
-#define VAL_GPIOE_MODER (PIN_MODE_OUTPUT(GPIOE_TD0) | \
- PIN_MODE_OUTPUT(GPIOE_TD1) | \
- PIN_MODE_OUTPUT(GPIOE_TD2) | \
- PIN_MODE_OUTPUT(GPIOE_TD3) | \
- PIN_MODE_OUTPUT(GPIOE_TD4) | \
- PIN_MODE_OUTPUT(GPIOE_TD5) | \
- PIN_MODE_OUTPUT(GPIOE_TD6) | \
- PIN_MODE_OUTPUT(GPIOE_TD7) | \
- PIN_MODE_OUTPUT(GPIOE_LCD_RST) | \
- PIN_MODE_OUTPUT(GPIOE_LCD_BLED) | \
- PIN_MODE_OUTPUT(GPIOE_PMRD) | \
- PIN_MODE_OUTPUT(GPIOE_PMWR) | \
- PIN_MODE_OUTPUT(GPIOE_LCD_RS) | \
- PIN_MODE_INPUT(GPIOE_PIN13) | \
- PIN_MODE_INPUT(GPIOE_PIN14) | \
- PIN_MODE_OUTPUT(GPIOE_LCD_CS))
-#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_TD0) | \
- PIN_OTYPE_PUSHPULL(GPIOE_TD1) | \
- PIN_OTYPE_PUSHPULL(GPIOE_TD2) | \
- PIN_OTYPE_PUSHPULL(GPIOE_TD3) | \
- PIN_OTYPE_PUSHPULL(GPIOE_TD4) | \
- PIN_OTYPE_PUSHPULL(GPIOE_TD5) | \
- PIN_OTYPE_PUSHPULL(GPIOE_TD6) | \
- PIN_OTYPE_PUSHPULL(GPIOE_TD7) | \
- PIN_OTYPE_PUSHPULL(GPIOE_LCD_RST) | \
- PIN_OTYPE_PUSHPULL(GPIOE_LCD_BLED) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PMRD) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PMWR) | \
- PIN_OTYPE_PUSHPULL(GPIOE_LCD_RS) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOE_LCD_CS))
-#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_TD0) | \
- PIN_OSPEED_100M(GPIOE_TD1) | \
- PIN_OSPEED_100M(GPIOE_TD2) | \
- PIN_OSPEED_100M(GPIOE_TD3) | \
- PIN_OSPEED_100M(GPIOE_TD4) | \
- PIN_OSPEED_100M(GPIOE_TD5) | \
- PIN_OSPEED_100M(GPIOE_TD6) | \
- PIN_OSPEED_100M(GPIOE_TD7) | \
- PIN_OSPEED_100M(GPIOE_LCD_RST) | \
- PIN_OSPEED_100M(GPIOE_LCD_BLED) | \
- PIN_OSPEED_100M(GPIOE_PMRD) | \
- PIN_OSPEED_100M(GPIOE_PMWR) | \
- PIN_OSPEED_100M(GPIOE_LCD_RS) | \
- PIN_OSPEED_100M(GPIOE_PIN13) | \
- PIN_OSPEED_100M(GPIOE_PIN14) | \
- PIN_OSPEED_100M(GPIOE_LCD_CS))
-#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_TD0) | \
- PIN_PUPDR_FLOATING(GPIOE_TD1) | \
- PIN_PUPDR_FLOATING(GPIOE_TD2) | \
- PIN_PUPDR_FLOATING(GPIOE_TD3) | \
- PIN_PUPDR_FLOATING(GPIOE_TD4) | \
- PIN_PUPDR_FLOATING(GPIOE_TD5) | \
- PIN_PUPDR_FLOATING(GPIOE_TD6) | \
- PIN_PUPDR_FLOATING(GPIOE_TD7) | \
- PIN_PUPDR_FLOATING(GPIOE_LCD_RST) | \
- PIN_PUPDR_FLOATING(GPIOE_LCD_BLED) | \
- PIN_PUPDR_FLOATING(GPIOE_PMRD) | \
- PIN_PUPDR_FLOATING(GPIOE_PMWR) | \
- PIN_PUPDR_FLOATING(GPIOE_LCD_RS) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN13) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN14) | \
- PIN_PUPDR_FLOATING(GPIOE_LCD_CS))
-#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_TD0) | \
- PIN_ODR_HIGH(GPIOE_TD1) | \
- PIN_ODR_HIGH(GPIOE_TD2) | \
- PIN_ODR_HIGH(GPIOE_TD3) | \
- PIN_ODR_HIGH(GPIOE_TD4) | \
- PIN_ODR_HIGH(GPIOE_TD5) | \
- PIN_ODR_HIGH(GPIOE_TD6) | \
- PIN_ODR_HIGH(GPIOE_TD7) | \
- PIN_ODR_HIGH(GPIOE_LCD_RST) | \
- PIN_ODR_LOW(GPIOE_LCD_BLED) | \
- PIN_ODR_HIGH(GPIOE_PMRD) | \
- PIN_ODR_HIGH(GPIOE_PMWR) | \
- PIN_ODR_HIGH(GPIOE_LCD_RS) | \
- PIN_ODR_HIGH(GPIOE_PIN13) | \
- PIN_ODR_HIGH(GPIOE_PIN14) | \
- PIN_ODR_LOW(GPIOE_LCD_CS))
-#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_TD0, 0) | \
- PIN_AFIO_AF(GPIOE_TD1, 0) | \
- PIN_AFIO_AF(GPIOE_TD2, 0) | \
- PIN_AFIO_AF(GPIOE_TD3, 0) | \
- PIN_AFIO_AF(GPIOE_TD4, 0) | \
- PIN_AFIO_AF(GPIOE_TD5, 0) | \
- PIN_AFIO_AF(GPIOE_TD6, 0) | \
- PIN_AFIO_AF(GPIOE_TD7, 0))
-#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_LCD_RST, 0) | \
- PIN_AFIO_AF(GPIOE_LCD_BLED, 0) | \
- PIN_AFIO_AF(GPIOE_PMRD, 0) | \
- PIN_AFIO_AF(GPIOE_PMWR, 0) | \
- PIN_AFIO_AF(GPIOE_LCD_RS, 0) | \
- PIN_AFIO_AF(GPIOE_PIN13, 0) | \
- PIN_AFIO_AF(GPIOE_PIN14, 0) | \
- PIN_AFIO_AF(GPIOE_LCD_CS, 0))
-
-/*
- * GPIOF setup:
- *
- * PF0 - PIN0 (input floating).
- * PF1 - PIN1 (input floating).
- * PF2 - PIN2 (input floating).
- * PF3 - PIN3 (input floating).
- * PF4 - PIN4 (input floating).
- * PF5 - PIN5 (input floating).
- * PF6 - PIN6 (input floating).
- * PF7 - PIN7 (input floating).
- * PF8 - PIN8 (input floating).
- * PF9 - PIN9 (input floating).
- * PF10 - PIN10 (input floating).
- * PF11 - PIN11 (input floating).
- * PF12 - PIN12 (input floating).
- * PF13 - PIN13 (input floating).
- * PF14 - PIN14 (input floating).
- * PF15 - PIN15 (input floating).
- */
-#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \
- PIN_MODE_INPUT(GPIOF_PIN1) | \
- PIN_MODE_INPUT(GPIOF_PIN2) | \
- PIN_MODE_INPUT(GPIOF_PIN3) | \
- PIN_MODE_INPUT(GPIOF_PIN4) | \
- PIN_MODE_INPUT(GPIOF_PIN5) | \
- PIN_MODE_INPUT(GPIOF_PIN6) | \
- PIN_MODE_INPUT(GPIOF_PIN7) | \
- PIN_MODE_INPUT(GPIOF_PIN8) | \
- PIN_MODE_INPUT(GPIOF_PIN9) | \
- PIN_MODE_INPUT(GPIOF_PIN10) | \
- PIN_MODE_INPUT(GPIOF_PIN11) | \
- PIN_MODE_INPUT(GPIOF_PIN12) | \
- PIN_MODE_INPUT(GPIOF_PIN13) | \
- PIN_MODE_INPUT(GPIOF_PIN14) | \
- PIN_MODE_INPUT(GPIOF_PIN15))
-#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
-#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_PIN0) | \
- PIN_OSPEED_100M(GPIOF_PIN1) | \
- PIN_OSPEED_100M(GPIOF_PIN2) | \
- PIN_OSPEED_100M(GPIOF_PIN3) | \
- PIN_OSPEED_100M(GPIOF_PIN4) | \
- PIN_OSPEED_100M(GPIOF_PIN5) | \
- PIN_OSPEED_100M(GPIOF_PIN6) | \
- PIN_OSPEED_100M(GPIOF_PIN7) | \
- PIN_OSPEED_100M(GPIOF_PIN8) | \
- PIN_OSPEED_100M(GPIOF_PIN9) | \
- PIN_OSPEED_100M(GPIOF_PIN10) | \
- PIN_OSPEED_100M(GPIOF_PIN11) | \
- PIN_OSPEED_100M(GPIOF_PIN12) | \
- PIN_OSPEED_100M(GPIOF_PIN13) | \
- PIN_OSPEED_100M(GPIOF_PIN14) | \
- PIN_OSPEED_100M(GPIOF_PIN15))
-#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN1) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN2) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN3) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN4) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN5) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN6) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN7) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN8) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN9) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN10) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN11) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN12) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN13) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN14) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN15))
-#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \
- PIN_ODR_HIGH(GPIOF_PIN1) | \
- PIN_ODR_HIGH(GPIOF_PIN2) | \
- PIN_ODR_HIGH(GPIOF_PIN3) | \
- PIN_ODR_HIGH(GPIOF_PIN4) | \
- PIN_ODR_HIGH(GPIOF_PIN5) | \
- PIN_ODR_HIGH(GPIOF_PIN6) | \
- PIN_ODR_HIGH(GPIOF_PIN7) | \
- PIN_ODR_HIGH(GPIOF_PIN8) | \
- PIN_ODR_HIGH(GPIOF_PIN9) | \
- PIN_ODR_HIGH(GPIOF_PIN10) | \
- PIN_ODR_HIGH(GPIOF_PIN11) | \
- PIN_ODR_HIGH(GPIOF_PIN12) | \
- PIN_ODR_HIGH(GPIOF_PIN13) | \
- PIN_ODR_HIGH(GPIOF_PIN14) | \
- PIN_ODR_HIGH(GPIOF_PIN15))
-#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \
- PIN_AFIO_AF(GPIOF_PIN1, 0) | \
- PIN_AFIO_AF(GPIOF_PIN2, 0) | \
- PIN_AFIO_AF(GPIOF_PIN3, 0) | \
- PIN_AFIO_AF(GPIOF_PIN4, 0) | \
- PIN_AFIO_AF(GPIOF_PIN5, 0) | \
- PIN_AFIO_AF(GPIOF_PIN6, 0) | \
- PIN_AFIO_AF(GPIOF_PIN7, 0))
-#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \
- PIN_AFIO_AF(GPIOF_PIN9, 0) | \
- PIN_AFIO_AF(GPIOF_PIN10, 0) | \
- PIN_AFIO_AF(GPIOF_PIN11, 0) | \
- PIN_AFIO_AF(GPIOF_PIN12, 0) | \
- PIN_AFIO_AF(GPIOF_PIN13, 0) | \
- PIN_AFIO_AF(GPIOF_PIN14, 0) | \
- PIN_AFIO_AF(GPIOF_PIN15, 0))
-
-/*
- * GPIOG setup:
- *
- * PG0 - PIN0 (input floating).
- * PG1 - PIN1 (input floating).
- * PG2 - PIN2 (input floating).
- * PG3 - PIN3 (input floating).
- * PG4 - PIN4 (input floating).
- * PG5 - PIN5 (input floating).
- * PG6 - PIN6 (input floating).
- * PG7 - PIN7 (input floating).
- * PG8 - PIN8 (input floating).
- * PG9 - PIN9 (input floating).
- * PG10 - PIN10 (input floating).
- * PG11 - PIN11 (input floating).
- * PG12 - PIN12 (input floating).
- * PG13 - PIN13 (input floating).
- * PG14 - PIN14 (input floating).
- * PG15 - PIN15 (input floating).
- */
-#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \
- PIN_MODE_INPUT(GPIOG_PIN1) | \
- PIN_MODE_INPUT(GPIOG_PIN2) | \
- PIN_MODE_INPUT(GPIOG_PIN3) | \
- PIN_MODE_INPUT(GPIOG_PIN4) | \
- PIN_MODE_INPUT(GPIOG_PIN5) | \
- PIN_MODE_INPUT(GPIOG_PIN6) | \
- PIN_MODE_INPUT(GPIOG_PIN7) | \
- PIN_MODE_INPUT(GPIOG_PIN8) | \
- PIN_MODE_INPUT(GPIOG_PIN9) | \
- PIN_MODE_INPUT(GPIOG_PIN10) | \
- PIN_MODE_INPUT(GPIOG_PIN11) | \
- PIN_MODE_INPUT(GPIOG_PIN12) | \
- PIN_MODE_INPUT(GPIOG_PIN13) | \
- PIN_MODE_INPUT(GPIOG_PIN14) | \
- PIN_MODE_INPUT(GPIOG_PIN15))
-#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
-#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(GPIOG_PIN0) | \
- PIN_OSPEED_100M(GPIOG_PIN1) | \
- PIN_OSPEED_100M(GPIOG_PIN2) | \
- PIN_OSPEED_100M(GPIOG_PIN3) | \
- PIN_OSPEED_100M(GPIOG_PIN4) | \
- PIN_OSPEED_100M(GPIOG_PIN5) | \
- PIN_OSPEED_100M(GPIOG_PIN6) | \
- PIN_OSPEED_100M(GPIOG_PIN7) | \
- PIN_OSPEED_100M(GPIOG_PIN8) | \
- PIN_OSPEED_100M(GPIOG_PIN9) | \
- PIN_OSPEED_100M(GPIOG_PIN10) | \
- PIN_OSPEED_100M(GPIOG_PIN11) | \
- PIN_OSPEED_100M(GPIOG_PIN12) | \
- PIN_OSPEED_100M(GPIOG_PIN13) | \
- PIN_OSPEED_100M(GPIOG_PIN14) | \
- PIN_OSPEED_100M(GPIOG_PIN15))
-#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN1) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN2) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN3) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN4) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN5) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN6) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN7) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN8) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN9) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN10) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN11) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN12) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN13) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN14) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN15))
-#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \
- PIN_ODR_HIGH(GPIOG_PIN1) | \
- PIN_ODR_HIGH(GPIOG_PIN2) | \
- PIN_ODR_HIGH(GPIOG_PIN3) | \
- PIN_ODR_HIGH(GPIOG_PIN4) | \
- PIN_ODR_HIGH(GPIOG_PIN5) | \
- PIN_ODR_HIGH(GPIOG_PIN6) | \
- PIN_ODR_HIGH(GPIOG_PIN7) | \
- PIN_ODR_HIGH(GPIOG_PIN8) | \
- PIN_ODR_HIGH(GPIOG_PIN9) | \
- PIN_ODR_HIGH(GPIOG_PIN10) | \
- PIN_ODR_HIGH(GPIOG_PIN11) | \
- PIN_ODR_HIGH(GPIOG_PIN12) | \
- PIN_ODR_HIGH(GPIOG_PIN13) | \
- PIN_ODR_HIGH(GPIOG_PIN14) | \
- PIN_ODR_HIGH(GPIOG_PIN15))
-#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | \
- PIN_AFIO_AF(GPIOG_PIN1, 0) | \
- PIN_AFIO_AF(GPIOG_PIN2, 0) | \
- PIN_AFIO_AF(GPIOG_PIN3, 0) | \
- PIN_AFIO_AF(GPIOG_PIN4, 0) | \
- PIN_AFIO_AF(GPIOG_PIN5, 0) | \
- PIN_AFIO_AF(GPIOG_PIN6, 0) | \
- PIN_AFIO_AF(GPIOG_PIN7, 0))
-#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \
- PIN_AFIO_AF(GPIOG_PIN9, 0) | \
- PIN_AFIO_AF(GPIOG_PIN10, 0) | \
- PIN_AFIO_AF(GPIOG_PIN11, 0) | \
- PIN_AFIO_AF(GPIOG_PIN12, 0) | \
- PIN_AFIO_AF(GPIOG_PIN13, 0) | \
- PIN_AFIO_AF(GPIOG_PIN14, 0) | \
- PIN_AFIO_AF(GPIOG_PIN15, 0))
-
-/*
- * GPIOH setup:
- *
- * PH0 - OSC_IN (input floating).
- * PH1 - OSC_OUT (input floating).
- * PH2 - PIN2 (input floating).
- * PH3 - PIN3 (input floating).
- * PH4 - PIN4 (input floating).
- * PH5 - PIN5 (input floating).
- * PH6 - PIN6 (input floating).
- * PH7 - PIN7 (input floating).
- * PH8 - PIN8 (input floating).
- * PH9 - PIN9 (input floating).
- * PH10 - PIN10 (input floating).
- * PH11 - PIN11 (input floating).
- * PH12 - PIN12 (input floating).
- * PH13 - PIN13 (input floating).
- * PH14 - PIN14 (input floating).
- * PH15 - PIN15 (input floating).
- */
-#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
- PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
- PIN_MODE_INPUT(GPIOH_PIN2) | \
- PIN_MODE_INPUT(GPIOH_PIN3) | \
- PIN_MODE_INPUT(GPIOH_PIN4) | \
- PIN_MODE_INPUT(GPIOH_PIN5) | \
- PIN_MODE_INPUT(GPIOH_PIN6) | \
- PIN_MODE_INPUT(GPIOH_PIN7) | \
- PIN_MODE_INPUT(GPIOH_PIN8) | \
- PIN_MODE_INPUT(GPIOH_PIN9) | \
- PIN_MODE_INPUT(GPIOH_PIN10) | \
- PIN_MODE_INPUT(GPIOH_PIN11) | \
- PIN_MODE_INPUT(GPIOH_PIN12) | \
- PIN_MODE_INPUT(GPIOH_PIN13) | \
- PIN_MODE_INPUT(GPIOH_PIN14) | \
- PIN_MODE_INPUT(GPIOH_PIN15))
-#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \
- PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
-#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(GPIOH_OSC_IN) | \
- PIN_OSPEED_100M(GPIOH_OSC_OUT) | \
- PIN_OSPEED_100M(GPIOH_PIN2) | \
- PIN_OSPEED_100M(GPIOH_PIN3) | \
- PIN_OSPEED_100M(GPIOH_PIN4) | \
- PIN_OSPEED_100M(GPIOH_PIN5) | \
- PIN_OSPEED_100M(GPIOH_PIN6) | \
- PIN_OSPEED_100M(GPIOH_PIN7) | \
- PIN_OSPEED_100M(GPIOH_PIN8) | \
- PIN_OSPEED_100M(GPIOH_PIN9) | \
- PIN_OSPEED_100M(GPIOH_PIN10) | \
- PIN_OSPEED_100M(GPIOH_PIN11) | \
- PIN_OSPEED_100M(GPIOH_PIN12) | \
- PIN_OSPEED_100M(GPIOH_PIN13) | \
- PIN_OSPEED_100M(GPIOH_PIN14) | \
- PIN_OSPEED_100M(GPIOH_PIN15))
-#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \
- PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN2) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN3) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN4) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN5) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN6) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN7) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN8) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN9) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN10) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN11) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN12) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN13) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN14) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN15))
-#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \
- PIN_ODR_HIGH(GPIOH_OSC_OUT) | \
- PIN_ODR_HIGH(GPIOH_PIN2) | \
- PIN_ODR_HIGH(GPIOH_PIN3) | \
- PIN_ODR_HIGH(GPIOH_PIN4) | \
- PIN_ODR_HIGH(GPIOH_PIN5) | \
- PIN_ODR_HIGH(GPIOH_PIN6) | \
- PIN_ODR_HIGH(GPIOH_PIN7) | \
- PIN_ODR_HIGH(GPIOH_PIN8) | \
- PIN_ODR_HIGH(GPIOH_PIN9) | \
- PIN_ODR_HIGH(GPIOH_PIN10) | \
- PIN_ODR_HIGH(GPIOH_PIN11) | \
- PIN_ODR_HIGH(GPIOH_PIN12) | \
- PIN_ODR_HIGH(GPIOH_PIN13) | \
- PIN_ODR_HIGH(GPIOH_PIN14) | \
- PIN_ODR_HIGH(GPIOH_PIN15))
-#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \
- PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \
- PIN_AFIO_AF(GPIOH_PIN2, 0) | \
- PIN_AFIO_AF(GPIOH_PIN3, 0) | \
- PIN_AFIO_AF(GPIOH_PIN4, 0) | \
- PIN_AFIO_AF(GPIOH_PIN5, 0) | \
- PIN_AFIO_AF(GPIOH_PIN6, 0) | \
- PIN_AFIO_AF(GPIOH_PIN7, 0))
-#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \
- PIN_AFIO_AF(GPIOH_PIN9, 0) | \
- PIN_AFIO_AF(GPIOH_PIN10, 0) | \
- PIN_AFIO_AF(GPIOH_PIN11, 0) | \
- PIN_AFIO_AF(GPIOH_PIN12, 0) | \
- PIN_AFIO_AF(GPIOH_PIN13, 0) | \
- PIN_AFIO_AF(GPIOH_PIN14, 0) | \
- PIN_AFIO_AF(GPIOH_PIN15, 0))
-
-/*
- * GPIOI setup:
- *
- * PI0 - PIN0 (input floating).
- * PI1 - PIN1 (input floating).
- * PI2 - PIN2 (input floating).
- * PI3 - PIN3 (input floating).
- * PI4 - PIN4 (input floating).
- * PI5 - PIN5 (input floating).
- * PI6 - PIN6 (input floating).
- * PI7 - PIN7 (input floating).
- * PI8 - PIN8 (input floating).
- * PI9 - PIN9 (input floating).
- * PI10 - PIN10 (input floating).
- * PI11 - PIN11 (input floating).
- * PI12 - PIN12 (input floating).
- * PI13 - PIN13 (input floating).
- * PI14 - PIN14 (input floating).
- * PI15 - PIN15 (input floating).
- */
-#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \
- PIN_MODE_INPUT(GPIOI_PIN1) | \
- PIN_MODE_INPUT(GPIOI_PIN2) | \
- PIN_MODE_INPUT(GPIOI_PIN3) | \
- PIN_MODE_INPUT(GPIOI_PIN4) | \
- PIN_MODE_INPUT(GPIOI_PIN5) | \
- PIN_MODE_INPUT(GPIOI_PIN6) | \
- PIN_MODE_INPUT(GPIOI_PIN7) | \
- PIN_MODE_INPUT(GPIOI_PIN8) | \
- PIN_MODE_INPUT(GPIOI_PIN9) | \
- PIN_MODE_INPUT(GPIOI_PIN10) | \
- PIN_MODE_INPUT(GPIOI_PIN11) | \
- PIN_MODE_INPUT(GPIOI_PIN12) | \
- PIN_MODE_INPUT(GPIOI_PIN13) | \
- PIN_MODE_INPUT(GPIOI_PIN14) | \
- PIN_MODE_INPUT(GPIOI_PIN15))
-#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
-#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_100M(GPIOI_PIN0) | \
- PIN_OSPEED_100M(GPIOI_PIN1) | \
- PIN_OSPEED_100M(GPIOI_PIN2) | \
- PIN_OSPEED_100M(GPIOI_PIN3) | \
- PIN_OSPEED_100M(GPIOI_PIN4) | \
- PIN_OSPEED_100M(GPIOI_PIN5) | \
- PIN_OSPEED_100M(GPIOI_PIN6) | \
- PIN_OSPEED_100M(GPIOI_PIN7) | \
- PIN_OSPEED_100M(GPIOI_PIN8) | \
- PIN_OSPEED_100M(GPIOI_PIN9) | \
- PIN_OSPEED_100M(GPIOI_PIN10) | \
- PIN_OSPEED_100M(GPIOI_PIN11) | \
- PIN_OSPEED_100M(GPIOI_PIN12) | \
- PIN_OSPEED_100M(GPIOI_PIN13) | \
- PIN_OSPEED_100M(GPIOI_PIN14) | \
- PIN_OSPEED_100M(GPIOI_PIN15))
-#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_PIN0) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN1) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN2) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN3) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN4) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN5) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN6) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN7) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN8) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN9) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN10) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN11) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN12) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN13) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN14) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN15))
-#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \
- PIN_ODR_HIGH(GPIOI_PIN1) | \
- PIN_ODR_HIGH(GPIOI_PIN2) | \
- PIN_ODR_HIGH(GPIOI_PIN3) | \
- PIN_ODR_HIGH(GPIOI_PIN4) | \
- PIN_ODR_HIGH(GPIOI_PIN5) | \
- PIN_ODR_HIGH(GPIOI_PIN6) | \
- PIN_ODR_HIGH(GPIOI_PIN7) | \
- PIN_ODR_HIGH(GPIOI_PIN8) | \
- PIN_ODR_HIGH(GPIOI_PIN9) | \
- PIN_ODR_HIGH(GPIOI_PIN10) | \
- PIN_ODR_HIGH(GPIOI_PIN11) | \
- PIN_ODR_HIGH(GPIOI_PIN12) | \
- PIN_ODR_HIGH(GPIOI_PIN13) | \
- PIN_ODR_HIGH(GPIOI_PIN14) | \
- PIN_ODR_HIGH(GPIOI_PIN15))
-#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \
- PIN_AFIO_AF(GPIOI_PIN1, 0) | \
- PIN_AFIO_AF(GPIOI_PIN2, 0) | \
- PIN_AFIO_AF(GPIOI_PIN3, 0) | \
- PIN_AFIO_AF(GPIOI_PIN4, 0) | \
- PIN_AFIO_AF(GPIOI_PIN5, 0) | \
- PIN_AFIO_AF(GPIOI_PIN6, 0) | \
- PIN_AFIO_AF(GPIOI_PIN7, 0))
-#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \
- PIN_AFIO_AF(GPIOI_PIN9, 0) | \
- PIN_AFIO_AF(GPIOI_PIN10, 0) | \
- PIN_AFIO_AF(GPIOI_PIN11, 0) | \
- PIN_AFIO_AF(GPIOI_PIN12, 0) | \
- PIN_AFIO_AF(GPIOI_PIN13, 0) | \
- PIN_AFIO_AF(GPIOI_PIN14, 0) | \
- PIN_AFIO_AF(GPIOI_PIN15, 0))
-
-
-#if !defined(_FROM_ASM_)
-#ifdef __cplusplus
-extern "C" {
-#endif
- void boardInit(void);
-#ifdef __cplusplus
-}
-#endif
-#endif /* _FROM_ASM_ */
-
-#endif /* _BOARD_H_ */
+/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for mikromedia STM32-M4 board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_MIKROE_MIKROMEDIA_M4
+#define BOARD_NAME "mikromedia STM32-M4"
+
+
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 32768
+#endif
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 16000000
+#endif
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD 330
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32F40_41xxx
+#define STM32F407xx
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_VSENSE 0
+#define GPIOA_PIN1 1
+#define GPIOA_PIN2 2
+#define GPIOA_PIN3 3
+#define GPIOA_PIN4 4
+#define GPIOA_PIN5 5
+#define GPIOA_PIN6 6
+#define GPIOA_PIN7 7
+#define GPIOA_PIN8 8
+#define GPIOA_VBUS_FS 9
+#define GPIOA_PIN10 10
+#define GPIOA_OTG_FS_DM 11
+#define GPIOA_OTG_FS_DP 12
+#define GPIOA_TMS 13
+#define GPIOA_TCK 14
+#define GPIOA_TDI 15
+
+#define GPIOB_LCD_YD 0
+#define GPIOB_LCD_XL 1
+#define GPIOB_PIN2 2
+#define GPIOB_TDO 3
+#define GPIOB_TRST 4
+#define GPIOB_PIN5 5
+#define GPIOB_SCL1 6
+#define GPIOB_SDA1 7
+#define GPIOB_DRIVEA 8
+#define GPIOB_DRIVEB 9
+#define GPIOB_SCL2 10
+#define GPIOB_SDA2 11
+#define GPIOB_PIN12 12
+#define GPIOB_SCK2 13
+#define GPIOB_MISO2 14
+#define GPIOB_MOSI2 15
+
+#define GPIOC_PIN0 0
+#define GPIOC_PIN1 1
+#define GPIOC_PIN2 2
+#define GPIOC_PIN3 3
+#define GPIOC_PIN4 4
+#define GPIOC_PIN5 5
+#define GPIOC_MP3_DREQ 6
+#define GPIOC_MP3_RST 7
+#define GPIOC_MP3_CS 8
+#define GPIOC_MP3_DCS 9
+#define GPIOC_SCK3 10
+#define GPIOC_MISO3 11
+#define GPIOC_MOSI3 12
+#define GPIOC_STAT 13
+#define GPIOC_PIN14 14
+#define GPIOC_PIN15 15
+
+#define GPIOD_PIN0 0
+#define GPIOD_PIN1 1
+#define GPIOD_PIN2 2
+#define GPIOD_SD_CS 3
+#define GPIOD_PIN4 4
+#define GPIOD_TX2 5
+#define GPIOD_RX2 6
+#define GPIOD_FLASH_CS 7
+#define GPIOD_PIN8 8
+#define GPIOD_PIN9 9
+#define GPIOD_PIN10 10
+#define GPIOD_PIN11 11
+#define GPIOD_PIN12 12
+#define GPIOD_PIN13 13
+#define GPIOD_PIN14 14
+#define GPIOD_SD_CD 15
+
+#define GPIOE_TD0 0
+#define GPIOE_TD1 1
+#define GPIOE_TD2 2
+#define GPIOE_TD3 3
+#define GPIOE_TD4 4
+#define GPIOE_TD5 5
+#define GPIOE_TD6 6
+#define GPIOE_TD7 7
+#define GPIOE_LCD_RST 8
+#define GPIOE_LCD_BLED 9
+#define GPIOE_PMRD 10
+#define GPIOE_PMWR 11
+#define GPIOE_LCD_RS 12
+#define GPIOE_PIN13 13
+#define GPIOE_PIN14 14
+#define GPIOE_LCD_CS 15
+
+#define GPIOF_PIN0 0
+#define GPIOF_PIN1 1
+#define GPIOF_PIN2 2
+#define GPIOF_PIN3 3
+#define GPIOF_PIN4 4
+#define GPIOF_PIN5 5
+#define GPIOF_PIN6 6
+#define GPIOF_PIN7 7
+#define GPIOF_PIN8 8
+#define GPIOF_PIN9 9
+#define GPIOF_PIN10 10
+#define GPIOF_PIN11 11
+#define GPIOF_PIN12 12
+#define GPIOF_PIN13 13
+#define GPIOF_PIN14 14
+#define GPIOF_PIN15 15
+
+#define GPIOG_PIN0 0
+#define GPIOG_PIN1 1
+#define GPIOG_PIN2 2
+#define GPIOG_PIN3 3
+#define GPIOG_PIN4 4
+#define GPIOG_PIN5 5
+#define GPIOG_PIN6 6
+#define GPIOG_PIN7 7
+#define GPIOG_PIN8 8
+#define GPIOG_PIN9 9
+#define GPIOG_PIN10 10
+#define GPIOG_PIN11 11
+#define GPIOG_PIN12 12
+#define GPIOG_PIN13 13
+#define GPIOG_PIN14 14
+#define GPIOG_PIN15 15
+
+#define GPIOH_OSC_IN 0
+#define GPIOH_OSC_OUT 1
+#define GPIOH_PIN2 2
+#define GPIOH_PIN3 3
+#define GPIOH_PIN4 4
+#define GPIOH_PIN5 5
+#define GPIOH_PIN6 6
+#define GPIOH_PIN7 7
+#define GPIOH_PIN8 8
+#define GPIOH_PIN9 9
+#define GPIOH_PIN10 10
+#define GPIOH_PIN11 11
+#define GPIOH_PIN12 12
+#define GPIOH_PIN13 13
+#define GPIOH_PIN14 14
+#define GPIOH_PIN15 15
+
+#define GPIOI_PIN0 0
+#define GPIOI_PIN1 1
+#define GPIOI_PIN2 2
+#define GPIOI_PIN3 3
+#define GPIOI_PIN4 4
+#define GPIOI_PIN5 5
+#define GPIOI_PIN6 6
+#define GPIOI_PIN7 7
+#define GPIOI_PIN8 8
+#define GPIOI_PIN9 9
+#define GPIOI_PIN10 10
+#define GPIOI_PIN11 11
+#define GPIOI_PIN12 12
+#define GPIOI_PIN13 13
+#define GPIOI_PIN14 14
+#define GPIOI_PIN15 15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_2M(n) (0U << ((n) * 2))
+#define PIN_OSPEED_25M(n) (1U << ((n) * 2))
+#define PIN_OSPEED_50M(n) (2U << ((n) * 2))
+#define PIN_OSPEED_100M(n) (3U << ((n) * 2))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - VSENSE (analog).
+ * PA1 - PIN1 (input pullup).
+ * PA2 - PIN2 (input pullup).
+ * PA3 - PIN3 (input pullup).
+ * PA4 - PIN4 (alternate 6).
+ * PA5 - PIN5 (alternate 5).
+ * PA6 - PIN6 (alternate 5).
+ * PA7 - PIN7 (alternate 5).
+ * PA8 - PIN8 (input pullup).
+ * PA9 - VBUS_FS (input floating).
+ * PA10 - PIN10 (input floating).
+ * PA11 - OTG_FS_DM (alternate 10).
+ * PA12 - OTG_FS_DP (alternate 10).
+ * PA13 - TMS (alternate 0).
+ * PA14 - TCK (alternate 0).
+ * PA15 - TDI (input pullup).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_VSENSE) | \
+ PIN_MODE_INPUT(GPIOA_PIN1) | \
+ PIN_MODE_INPUT(GPIOA_PIN2) | \
+ PIN_MODE_INPUT(GPIOA_PIN3) | \
+ PIN_MODE_ALTERNATE(GPIOA_PIN4) | \
+ PIN_MODE_ALTERNATE(GPIOA_PIN5) | \
+ PIN_MODE_ALTERNATE(GPIOA_PIN6) | \
+ PIN_MODE_ALTERNATE(GPIOA_PIN7) | \
+ PIN_MODE_INPUT(GPIOA_PIN8) | \
+ PIN_MODE_INPUT(GPIOA_VBUS_FS) | \
+ PIN_MODE_INPUT(GPIOA_PIN10) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \
+ PIN_MODE_ALTERNATE(GPIOA_TMS) | \
+ PIN_MODE_ALTERNATE(GPIOA_TCK) | \
+ PIN_MODE_INPUT(GPIOA_TDI))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_VSENSE) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_VBUS_FS) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_TMS) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_TCK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_TDI))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_100M(GPIOA_VSENSE) | \
+ PIN_OSPEED_100M(GPIOA_PIN1) | \
+ PIN_OSPEED_100M(GPIOA_PIN2) | \
+ PIN_OSPEED_100M(GPIOA_PIN3) | \
+ PIN_OSPEED_100M(GPIOA_PIN4) | \
+ PIN_OSPEED_50M(GPIOA_PIN5) | \
+ PIN_OSPEED_50M(GPIOA_PIN6) | \
+ PIN_OSPEED_50M(GPIOA_PIN7) | \
+ PIN_OSPEED_100M(GPIOA_PIN8) | \
+ PIN_OSPEED_100M(GPIOA_VBUS_FS) | \
+ PIN_OSPEED_100M(GPIOA_PIN10) | \
+ PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \
+ PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \
+ PIN_OSPEED_100M(GPIOA_TMS) | \
+ PIN_OSPEED_100M(GPIOA_TCK) | \
+ PIN_OSPEED_100M(GPIOA_TDI))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_VSENSE) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOA_VBUS_FS) | \
+ PIN_PUPDR_FLOATING(GPIOA_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \
+ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \
+ PIN_PUPDR_FLOATING(GPIOA_TMS) | \
+ PIN_PUPDR_FLOATING(GPIOA_TCK) | \
+ PIN_PUPDR_PULLUP(GPIOA_TDI))
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_VSENSE) | \
+ PIN_ODR_HIGH(GPIOA_PIN1) | \
+ PIN_ODR_HIGH(GPIOA_PIN2) | \
+ PIN_ODR_HIGH(GPIOA_PIN3) | \
+ PIN_ODR_HIGH(GPIOA_PIN4) | \
+ PIN_ODR_HIGH(GPIOA_PIN5) | \
+ PIN_ODR_HIGH(GPIOA_PIN6) | \
+ PIN_ODR_HIGH(GPIOA_PIN7) | \
+ PIN_ODR_HIGH(GPIOA_PIN8) | \
+ PIN_ODR_HIGH(GPIOA_VBUS_FS) | \
+ PIN_ODR_HIGH(GPIOA_PIN10) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \
+ PIN_ODR_HIGH(GPIOA_TMS) | \
+ PIN_ODR_HIGH(GPIOA_TCK) | \
+ PIN_ODR_HIGH(GPIOA_TDI))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_VSENSE, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN4, 6) | \
+ PIN_AFIO_AF(GPIOA_PIN5, 5) | \
+ PIN_AFIO_AF(GPIOA_PIN6, 5) | \
+ PIN_AFIO_AF(GPIOA_PIN7, 5))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOA_VBUS_FS, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \
+ PIN_AFIO_AF(GPIOA_TMS, 0) | \
+ PIN_AFIO_AF(GPIOA_TCK, 0) | \
+ PIN_AFIO_AF(GPIOA_TDI, 0))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - LCD_YD (analog).
+ * PB1 - LCD_XL (analog).
+ * PB2 - PIN2 (input pullup).
+ * PB3 - TDO (alternate 0).
+ * PB4 - TRST (input pullup).
+ * PB5 - PIN5 (input pullup).
+ * PB6 - SCL1 (alternate 4).
+ * PB7 - SDA1 (input pullup).
+ * PB8 - DRIVEA (output pushpull maximum).
+ * PB9 - DRIVEB (output opendrain maximum).
+ * PB10 - SCL2 (input pullup).
+ * PB11 - SDA2 (input pullup).
+ * PB12 - PIN12 (input pullup).
+ * PB13 - SCK2 (input pullup).
+ * PB14 - MISO2 (input pullup).
+ * PB15 - MOSI2 (input pullup).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_LCD_YD) | \
+ PIN_MODE_ANALOG(GPIOB_LCD_XL) | \
+ PIN_MODE_INPUT(GPIOB_PIN2) | \
+ PIN_MODE_ALTERNATE(GPIOB_TDO) | \
+ PIN_MODE_INPUT(GPIOB_TRST) | \
+ PIN_MODE_INPUT(GPIOB_PIN5) | \
+ PIN_MODE_ALTERNATE(GPIOB_SCL1) | \
+ PIN_MODE_INPUT(GPIOB_SDA1) | \
+ PIN_MODE_OUTPUT(GPIOB_DRIVEA) | \
+ PIN_MODE_OUTPUT(GPIOB_DRIVEB) | \
+ PIN_MODE_INPUT(GPIOB_SCL2) | \
+ PIN_MODE_INPUT(GPIOB_SDA2) | \
+ PIN_MODE_INPUT(GPIOB_PIN12) | \
+ PIN_MODE_INPUT(GPIOB_SCK2) | \
+ PIN_MODE_INPUT(GPIOB_MISO2) | \
+ PIN_MODE_INPUT(GPIOB_MOSI2))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_LCD_YD) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_LCD_XL) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_TDO) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_TRST) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_SCL1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_SDA1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_DRIVEA) | \
+ PIN_OTYPE_OPENDRAIN(GPIOB_DRIVEB) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_SCL2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_SDA2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_SCK2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_MISO2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_MOSI2))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_LCD_YD) | \
+ PIN_OSPEED_100M(GPIOB_LCD_XL) | \
+ PIN_OSPEED_100M(GPIOB_PIN2) | \
+ PIN_OSPEED_100M(GPIOB_TDO) | \
+ PIN_OSPEED_100M(GPIOB_TRST) | \
+ PIN_OSPEED_100M(GPIOB_PIN5) | \
+ PIN_OSPEED_100M(GPIOB_SCL1) | \
+ PIN_OSPEED_100M(GPIOB_SDA1) | \
+ PIN_OSPEED_100M(GPIOB_DRIVEA) | \
+ PIN_OSPEED_100M(GPIOB_DRIVEB) | \
+ PIN_OSPEED_100M(GPIOB_SCL2) | \
+ PIN_OSPEED_100M(GPIOB_SDA2) | \
+ PIN_OSPEED_100M(GPIOB_PIN12) | \
+ PIN_OSPEED_100M(GPIOB_SCK2) | \
+ PIN_OSPEED_100M(GPIOB_MISO2) | \
+ PIN_OSPEED_100M(GPIOB_MOSI2))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_LCD_YD) | \
+ PIN_PUPDR_FLOATING(GPIOB_LCD_XL) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOB_TDO) | \
+ PIN_PUPDR_PULLUP(GPIOB_TRST) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOB_SCL1) | \
+ PIN_PUPDR_PULLUP(GPIOB_SDA1) | \
+ PIN_PUPDR_FLOATING(GPIOB_DRIVEA) | \
+ PIN_PUPDR_FLOATING(GPIOB_DRIVEB) | \
+ PIN_PUPDR_PULLUP(GPIOB_SCL2) | \
+ PIN_PUPDR_PULLUP(GPIOB_SDA2) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOB_SCK2) | \
+ PIN_PUPDR_PULLUP(GPIOB_MISO2) | \
+ PIN_PUPDR_PULLUP(GPIOB_MOSI2))
+#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_LCD_YD) | \
+ PIN_ODR_HIGH(GPIOB_LCD_XL) | \
+ PIN_ODR_HIGH(GPIOB_PIN2) | \
+ PIN_ODR_HIGH(GPIOB_TDO) | \
+ PIN_ODR_HIGH(GPIOB_TRST) | \
+ PIN_ODR_HIGH(GPIOB_PIN5) | \
+ PIN_ODR_HIGH(GPIOB_SCL1) | \
+ PIN_ODR_HIGH(GPIOB_SDA1) | \
+ PIN_ODR_HIGH(GPIOB_DRIVEA) | \
+ PIN_ODR_HIGH(GPIOB_DRIVEB) | \
+ PIN_ODR_HIGH(GPIOB_SCL2) | \
+ PIN_ODR_HIGH(GPIOB_SDA2) | \
+ PIN_ODR_HIGH(GPIOB_PIN12) | \
+ PIN_ODR_HIGH(GPIOB_SCK2) | \
+ PIN_ODR_HIGH(GPIOB_MISO2) | \
+ PIN_ODR_HIGH(GPIOB_MOSI2))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_LCD_YD, 0) | \
+ PIN_AFIO_AF(GPIOB_LCD_XL, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOB_TDO, 0) | \
+ PIN_AFIO_AF(GPIOB_TRST, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOB_SCL1, 4) | \
+ PIN_AFIO_AF(GPIOB_SDA1, 4))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_DRIVEA, 0) | \
+ PIN_AFIO_AF(GPIOB_DRIVEB, 0) | \
+ PIN_AFIO_AF(GPIOB_SCL2, 0) | \
+ PIN_AFIO_AF(GPIOB_SDA2, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOB_SCK2, 0) | \
+ PIN_AFIO_AF(GPIOB_MISO2, 0) | \
+ PIN_AFIO_AF(GPIOB_MOSI2, 0))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - PIN0 (output pushpull maximum).
+ * PC1 - PIN1 (input pullup).
+ * PC2 - PIN2 (input pullup).
+ * PC3 - PIN3 (input pullup).
+ * PC4 - PIN4 (input pullup).
+ * PC5 - PIN5 (input pullup).
+ * PC6 - MP3_DREQ (input pullup).
+ * PC7 - MP3_RST (alternate 6).
+ * PC8 - MP3_CS (output pushpull maximum).
+ * PC9 - MP3_DCS (input pullup).
+ * PC10 - SCK3 (alternate 6).
+ * PC11 - MISO3 (alternate 6).
+ * PC12 - MOSI3 (alternate 6).
+ * PC13 - STAT (input pullup).
+ * PC14 - PIN14 (input pullup).
+ * PC15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_PIN0) | \
+ PIN_MODE_INPUT(GPIOC_PIN1) | \
+ PIN_MODE_INPUT(GPIOC_PIN2) | \
+ PIN_MODE_INPUT(GPIOC_PIN3) | \
+ PIN_MODE_INPUT(GPIOC_PIN4) | \
+ PIN_MODE_INPUT(GPIOC_PIN5) | \
+ PIN_MODE_INPUT(GPIOC_MP3_DREQ) | \
+ PIN_MODE_ALTERNATE(GPIOC_MP3_RST) | \
+ PIN_MODE_OUTPUT(GPIOC_MP3_CS) | \
+ PIN_MODE_INPUT(GPIOC_MP3_DCS) | \
+ PIN_MODE_ALTERNATE(GPIOC_SCK3) | \
+ PIN_MODE_ALTERNATE(GPIOC_MISO3) | \
+ PIN_MODE_ALTERNATE(GPIOC_MOSI3) | \
+ PIN_MODE_INPUT(GPIOC_STAT) | \
+ PIN_MODE_INPUT(GPIOC_PIN14) | \
+ PIN_MODE_INPUT(GPIOC_PIN15))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_MP3_DREQ) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_MP3_RST) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_MP3_CS) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_MP3_DCS) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_SCK3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_MISO3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_MOSI3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_STAT) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(GPIOC_PIN0) | \
+ PIN_OSPEED_100M(GPIOC_PIN1) | \
+ PIN_OSPEED_100M(GPIOC_PIN2) | \
+ PIN_OSPEED_100M(GPIOC_PIN3) | \
+ PIN_OSPEED_100M(GPIOC_PIN4) | \
+ PIN_OSPEED_100M(GPIOC_PIN5) | \
+ PIN_OSPEED_100M(GPIOC_MP3_DREQ) | \
+ PIN_OSPEED_100M(GPIOC_MP3_RST) | \
+ PIN_OSPEED_100M(GPIOC_MP3_CS) | \
+ PIN_OSPEED_100M(GPIOC_MP3_DCS) | \
+ PIN_OSPEED_100M(GPIOC_SCK3) | \
+ PIN_OSPEED_100M(GPIOC_MISO3) | \
+ PIN_OSPEED_100M(GPIOC_MOSI3) | \
+ PIN_OSPEED_100M(GPIOC_STAT) | \
+ PIN_OSPEED_100M(GPIOC_PIN14) | \
+ PIN_OSPEED_100M(GPIOC_PIN15))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOC_MP3_DREQ) | \
+ PIN_PUPDR_FLOATING(GPIOC_MP3_RST) | \
+ PIN_PUPDR_PULLUP(GPIOC_MP3_CS) | \
+ PIN_PUPDR_PULLUP(GPIOC_MP3_DCS) | \
+ PIN_PUPDR_FLOATING(GPIOC_SCK3) | \
+ PIN_PUPDR_FLOATING(GPIOC_MISO3) | \
+ PIN_PUPDR_FLOATING(GPIOC_MOSI3) | \
+ PIN_PUPDR_PULLUP(GPIOC_STAT) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN15))
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \
+ PIN_ODR_HIGH(GPIOC_PIN1) | \
+ PIN_ODR_HIGH(GPIOC_PIN2) | \
+ PIN_ODR_HIGH(GPIOC_PIN3) | \
+ PIN_ODR_HIGH(GPIOC_PIN4) | \
+ PIN_ODR_HIGH(GPIOC_PIN5) | \
+ PIN_ODR_HIGH(GPIOC_MP3_DREQ) | \
+ PIN_ODR_HIGH(GPIOC_MP3_RST) | \
+ PIN_ODR_HIGH(GPIOC_MP3_CS) | \
+ PIN_ODR_HIGH(GPIOC_MP3_DCS) | \
+ PIN_ODR_HIGH(GPIOC_SCK3) | \
+ PIN_ODR_HIGH(GPIOC_MISO3) | \
+ PIN_ODR_HIGH(GPIOC_MOSI3) | \
+ PIN_ODR_HIGH(GPIOC_STAT) | \
+ PIN_ODR_HIGH(GPIOC_PIN14) | \
+ PIN_ODR_HIGH(GPIOC_PIN15))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOC_MP3_DREQ, 0) | \
+ PIN_AFIO_AF(GPIOC_MP3_RST, 6))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_MP3_CS, 0) | \
+ PIN_AFIO_AF(GPIOC_MP3_DCS, 0) | \
+ PIN_AFIO_AF(GPIOC_SCK3, 6) | \
+ PIN_AFIO_AF(GPIOC_MISO3, 6) | \
+ PIN_AFIO_AF(GPIOC_MOSI3, 6) | \
+ PIN_AFIO_AF(GPIOC_STAT, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN15, 0))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - PIN0 (input pullup).
+ * PD1 - PIN1 (input pullup).
+ * PD2 - PIN2 (input pullup).
+ * PD3 - SD_CS (output pushpull maximum).
+ * PD4 - PIN4 (output pushpull maximum).
+ * PD5 - TX2 (alternate 7).
+ * PD6 - RX2 (alternate 7).
+ * PD7 - FLASH_CS (output pushpull maximum).
+ * PD8 - PIN8 (input pullup).
+ * PD9 - PIN9 (input pullup).
+ * PD10 - PIN10 (input pullup).
+ * PD11 - PIN11 (input pullup).
+ * PD12 - PIN12 (output pushpull maximum).
+ * PD13 - PIN13 (output pushpull maximum).
+ * PD14 - PIN14 (output pushpull maximum).
+ * PD15 - SD_CD (input pullup).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
+ PIN_MODE_INPUT(GPIOD_PIN1) | \
+ PIN_MODE_INPUT(GPIOD_PIN2) | \
+ PIN_MODE_OUTPUT(GPIOD_SD_CS) | \
+ PIN_MODE_OUTPUT(GPIOD_PIN4) | \
+ PIN_MODE_ALTERNATE(GPIOD_TX2) | \
+ PIN_MODE_ALTERNATE(GPIOD_RX2) | \
+ PIN_MODE_OUTPUT(GPIOD_FLASH_CS) | \
+ PIN_MODE_INPUT(GPIOD_PIN8) | \
+ PIN_MODE_INPUT(GPIOD_PIN9) | \
+ PIN_MODE_INPUT(GPIOD_PIN10) | \
+ PIN_MODE_INPUT(GPIOD_PIN11) | \
+ PIN_MODE_OUTPUT(GPIOD_PIN12) | \
+ PIN_MODE_OUTPUT(GPIOD_PIN13) | \
+ PIN_MODE_OUTPUT(GPIOD_PIN14) | \
+ PIN_MODE_INPUT(GPIOD_SD_CD))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_SD_CS) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_TX2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_RX2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_FLASH_CS) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_SD_CD))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_PIN0) | \
+ PIN_OSPEED_100M(GPIOD_PIN1) | \
+ PIN_OSPEED_100M(GPIOD_PIN2) | \
+ PIN_OSPEED_100M(GPIOD_SD_CS) | \
+ PIN_OSPEED_100M(GPIOD_PIN4) | \
+ PIN_OSPEED_100M(GPIOD_TX2) | \
+ PIN_OSPEED_100M(GPIOD_RX2) | \
+ PIN_OSPEED_100M(GPIOD_FLASH_CS) | \
+ PIN_OSPEED_100M(GPIOD_PIN8) | \
+ PIN_OSPEED_100M(GPIOD_PIN9) | \
+ PIN_OSPEED_100M(GPIOD_PIN10) | \
+ PIN_OSPEED_100M(GPIOD_PIN11) | \
+ PIN_OSPEED_100M(GPIOD_PIN12) | \
+ PIN_OSPEED_100M(GPIOD_PIN13) | \
+ PIN_OSPEED_100M(GPIOD_PIN14) | \
+ PIN_OSPEED_100M(GPIOD_SD_CD))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOD_SD_CS) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOD_TX2) | \
+ PIN_PUPDR_PULLUP(GPIOD_RX2) | \
+ PIN_PUPDR_PULLUP(GPIOD_FLASH_CS) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOD_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOD_SD_CD))
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
+ PIN_ODR_HIGH(GPIOD_PIN1) | \
+ PIN_ODR_HIGH(GPIOD_PIN2) | \
+ PIN_ODR_HIGH(GPIOD_SD_CS) | \
+ PIN_ODR_HIGH(GPIOD_PIN4) | \
+ PIN_ODR_HIGH(GPIOD_TX2) | \
+ PIN_ODR_HIGH(GPIOD_RX2) | \
+ PIN_ODR_HIGH(GPIOD_FLASH_CS) | \
+ PIN_ODR_HIGH(GPIOD_PIN8) | \
+ PIN_ODR_HIGH(GPIOD_PIN9) | \
+ PIN_ODR_HIGH(GPIOD_PIN10) | \
+ PIN_ODR_HIGH(GPIOD_PIN11) | \
+ PIN_ODR_LOW(GPIOD_PIN12) | \
+ PIN_ODR_LOW(GPIOD_PIN13) | \
+ PIN_ODR_LOW(GPIOD_PIN14) | \
+ PIN_ODR_LOW(GPIOD_SD_CD))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOD_SD_CS, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOD_TX2, 7) | \
+ PIN_AFIO_AF(GPIOD_RX2, 7) | \
+ PIN_AFIO_AF(GPIOD_FLASH_CS, 0))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOD_SD_CD, 0))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0 - TD0 (output pushpull maximum).
+ * PE1 - TD1 (output pushpull maximum).
+ * PE2 - TD2 (output pushpull maximum).
+ * PE3 - TD3 (output pushpull maximum).
+ * PE4 - TD4 (output pushpull maximum).
+ * PE5 - TD5 (output pushpull maximum).
+ * PE6 - TD6 (output pushpull maximum).
+ * PE7 - TD7 (output pushpull maximum).
+ * PE8 - LCD_RST (output pushpull maximum).
+ * PE9 - LCD_BLED (output pushpull maximum).
+ * PE10 - PMRD (output pushpull maximum).
+ * PE11 - PMWR (output pushpull maximum).
+ * PE12 - LCD_RS (output pushpull maximum).
+ * PE13 - PIN13 (input floating).
+ * PE14 - PIN14 (input floating).
+ * PE15 - LCD_CS (output pushpull maximum).
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_OUTPUT(GPIOE_TD0) | \
+ PIN_MODE_OUTPUT(GPIOE_TD1) | \
+ PIN_MODE_OUTPUT(GPIOE_TD2) | \
+ PIN_MODE_OUTPUT(GPIOE_TD3) | \
+ PIN_MODE_OUTPUT(GPIOE_TD4) | \
+ PIN_MODE_OUTPUT(GPIOE_TD5) | \
+ PIN_MODE_OUTPUT(GPIOE_TD6) | \
+ PIN_MODE_OUTPUT(GPIOE_TD7) | \
+ PIN_MODE_OUTPUT(GPIOE_LCD_RST) | \
+ PIN_MODE_OUTPUT(GPIOE_LCD_BLED) | \
+ PIN_MODE_OUTPUT(GPIOE_PMRD) | \
+ PIN_MODE_OUTPUT(GPIOE_PMWR) | \
+ PIN_MODE_OUTPUT(GPIOE_LCD_RS) | \
+ PIN_MODE_INPUT(GPIOE_PIN13) | \
+ PIN_MODE_INPUT(GPIOE_PIN14) | \
+ PIN_MODE_OUTPUT(GPIOE_LCD_CS))
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_TD0) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_TD1) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_TD2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_TD3) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_TD4) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_TD5) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_TD6) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_TD7) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_LCD_RST) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_LCD_BLED) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PMRD) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PMWR) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_LCD_RS) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_LCD_CS))
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_TD0) | \
+ PIN_OSPEED_100M(GPIOE_TD1) | \
+ PIN_OSPEED_100M(GPIOE_TD2) | \
+ PIN_OSPEED_100M(GPIOE_TD3) | \
+ PIN_OSPEED_100M(GPIOE_TD4) | \
+ PIN_OSPEED_100M(GPIOE_TD5) | \
+ PIN_OSPEED_100M(GPIOE_TD6) | \
+ PIN_OSPEED_100M(GPIOE_TD7) | \
+ PIN_OSPEED_100M(GPIOE_LCD_RST) | \
+ PIN_OSPEED_100M(GPIOE_LCD_BLED) | \
+ PIN_OSPEED_100M(GPIOE_PMRD) | \
+ PIN_OSPEED_100M(GPIOE_PMWR) | \
+ PIN_OSPEED_100M(GPIOE_LCD_RS) | \
+ PIN_OSPEED_100M(GPIOE_PIN13) | \
+ PIN_OSPEED_100M(GPIOE_PIN14) | \
+ PIN_OSPEED_100M(GPIOE_LCD_CS))
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_TD0) | \
+ PIN_PUPDR_FLOATING(GPIOE_TD1) | \
+ PIN_PUPDR_FLOATING(GPIOE_TD2) | \
+ PIN_PUPDR_FLOATING(GPIOE_TD3) | \
+ PIN_PUPDR_FLOATING(GPIOE_TD4) | \
+ PIN_PUPDR_FLOATING(GPIOE_TD5) | \
+ PIN_PUPDR_FLOATING(GPIOE_TD6) | \
+ PIN_PUPDR_FLOATING(GPIOE_TD7) | \
+ PIN_PUPDR_FLOATING(GPIOE_LCD_RST) | \
+ PIN_PUPDR_FLOATING(GPIOE_LCD_BLED) | \
+ PIN_PUPDR_FLOATING(GPIOE_PMRD) | \
+ PIN_PUPDR_FLOATING(GPIOE_PMWR) | \
+ PIN_PUPDR_FLOATING(GPIOE_LCD_RS) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOE_LCD_CS))
+#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_TD0) | \
+ PIN_ODR_HIGH(GPIOE_TD1) | \
+ PIN_ODR_HIGH(GPIOE_TD2) | \
+ PIN_ODR_HIGH(GPIOE_TD3) | \
+ PIN_ODR_HIGH(GPIOE_TD4) | \
+ PIN_ODR_HIGH(GPIOE_TD5) | \
+ PIN_ODR_HIGH(GPIOE_TD6) | \
+ PIN_ODR_HIGH(GPIOE_TD7) | \
+ PIN_ODR_HIGH(GPIOE_LCD_RST) | \
+ PIN_ODR_LOW(GPIOE_LCD_BLED) | \
+ PIN_ODR_HIGH(GPIOE_PMRD) | \
+ PIN_ODR_HIGH(GPIOE_PMWR) | \
+ PIN_ODR_HIGH(GPIOE_LCD_RS) | \
+ PIN_ODR_HIGH(GPIOE_PIN13) | \
+ PIN_ODR_HIGH(GPIOE_PIN14) | \
+ PIN_ODR_LOW(GPIOE_LCD_CS))
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_TD0, 0) | \
+ PIN_AFIO_AF(GPIOE_TD1, 0) | \
+ PIN_AFIO_AF(GPIOE_TD2, 0) | \
+ PIN_AFIO_AF(GPIOE_TD3, 0) | \
+ PIN_AFIO_AF(GPIOE_TD4, 0) | \
+ PIN_AFIO_AF(GPIOE_TD5, 0) | \
+ PIN_AFIO_AF(GPIOE_TD6, 0) | \
+ PIN_AFIO_AF(GPIOE_TD7, 0))
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_LCD_RST, 0) | \
+ PIN_AFIO_AF(GPIOE_LCD_BLED, 0) | \
+ PIN_AFIO_AF(GPIOE_PMRD, 0) | \
+ PIN_AFIO_AF(GPIOE_PMWR, 0) | \
+ PIN_AFIO_AF(GPIOE_LCD_RS, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOE_LCD_CS, 0))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0 - PIN0 (input floating).
+ * PF1 - PIN1 (input floating).
+ * PF2 - PIN2 (input floating).
+ * PF3 - PIN3 (input floating).
+ * PF4 - PIN4 (input floating).
+ * PF5 - PIN5 (input floating).
+ * PF6 - PIN6 (input floating).
+ * PF7 - PIN7 (input floating).
+ * PF8 - PIN8 (input floating).
+ * PF9 - PIN9 (input floating).
+ * PF10 - PIN10 (input floating).
+ * PF11 - PIN11 (input floating).
+ * PF12 - PIN12 (input floating).
+ * PF13 - PIN13 (input floating).
+ * PF14 - PIN14 (input floating).
+ * PF15 - PIN15 (input floating).
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \
+ PIN_MODE_INPUT(GPIOF_PIN1) | \
+ PIN_MODE_INPUT(GPIOF_PIN2) | \
+ PIN_MODE_INPUT(GPIOF_PIN3) | \
+ PIN_MODE_INPUT(GPIOF_PIN4) | \
+ PIN_MODE_INPUT(GPIOF_PIN5) | \
+ PIN_MODE_INPUT(GPIOF_PIN6) | \
+ PIN_MODE_INPUT(GPIOF_PIN7) | \
+ PIN_MODE_INPUT(GPIOF_PIN8) | \
+ PIN_MODE_INPUT(GPIOF_PIN9) | \
+ PIN_MODE_INPUT(GPIOF_PIN10) | \
+ PIN_MODE_INPUT(GPIOF_PIN11) | \
+ PIN_MODE_INPUT(GPIOF_PIN12) | \
+ PIN_MODE_INPUT(GPIOF_PIN13) | \
+ PIN_MODE_INPUT(GPIOF_PIN14) | \
+ PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_PIN0) | \
+ PIN_OSPEED_100M(GPIOF_PIN1) | \
+ PIN_OSPEED_100M(GPIOF_PIN2) | \
+ PIN_OSPEED_100M(GPIOF_PIN3) | \
+ PIN_OSPEED_100M(GPIOF_PIN4) | \
+ PIN_OSPEED_100M(GPIOF_PIN5) | \
+ PIN_OSPEED_100M(GPIOF_PIN6) | \
+ PIN_OSPEED_100M(GPIOF_PIN7) | \
+ PIN_OSPEED_100M(GPIOF_PIN8) | \
+ PIN_OSPEED_100M(GPIOF_PIN9) | \
+ PIN_OSPEED_100M(GPIOF_PIN10) | \
+ PIN_OSPEED_100M(GPIOF_PIN11) | \
+ PIN_OSPEED_100M(GPIOF_PIN12) | \
+ PIN_OSPEED_100M(GPIOF_PIN13) | \
+ PIN_OSPEED_100M(GPIOF_PIN14) | \
+ PIN_OSPEED_100M(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN15))
+#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \
+ PIN_ODR_HIGH(GPIOF_PIN1) | \
+ PIN_ODR_HIGH(GPIOF_PIN2) | \
+ PIN_ODR_HIGH(GPIOF_PIN3) | \
+ PIN_ODR_HIGH(GPIOF_PIN4) | \
+ PIN_ODR_HIGH(GPIOF_PIN5) | \
+ PIN_ODR_HIGH(GPIOF_PIN6) | \
+ PIN_ODR_HIGH(GPIOF_PIN7) | \
+ PIN_ODR_HIGH(GPIOF_PIN8) | \
+ PIN_ODR_HIGH(GPIOF_PIN9) | \
+ PIN_ODR_HIGH(GPIOF_PIN10) | \
+ PIN_ODR_HIGH(GPIOF_PIN11) | \
+ PIN_ODR_HIGH(GPIOF_PIN12) | \
+ PIN_ODR_HIGH(GPIOF_PIN13) | \
+ PIN_ODR_HIGH(GPIOF_PIN14) | \
+ PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN7, 0))
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN15, 0))
+
+/*
+ * GPIOG setup:
+ *
+ * PG0 - PIN0 (input floating).
+ * PG1 - PIN1 (input floating).
+ * PG2 - PIN2 (input floating).
+ * PG3 - PIN3 (input floating).
+ * PG4 - PIN4 (input floating).
+ * PG5 - PIN5 (input floating).
+ * PG6 - PIN6 (input floating).
+ * PG7 - PIN7 (input floating).
+ * PG8 - PIN8 (input floating).
+ * PG9 - PIN9 (input floating).
+ * PG10 - PIN10 (input floating).
+ * PG11 - PIN11 (input floating).
+ * PG12 - PIN12 (input floating).
+ * PG13 - PIN13 (input floating).
+ * PG14 - PIN14 (input floating).
+ * PG15 - PIN15 (input floating).
+ */
+#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \
+ PIN_MODE_INPUT(GPIOG_PIN1) | \
+ PIN_MODE_INPUT(GPIOG_PIN2) | \
+ PIN_MODE_INPUT(GPIOG_PIN3) | \
+ PIN_MODE_INPUT(GPIOG_PIN4) | \
+ PIN_MODE_INPUT(GPIOG_PIN5) | \
+ PIN_MODE_INPUT(GPIOG_PIN6) | \
+ PIN_MODE_INPUT(GPIOG_PIN7) | \
+ PIN_MODE_INPUT(GPIOG_PIN8) | \
+ PIN_MODE_INPUT(GPIOG_PIN9) | \
+ PIN_MODE_INPUT(GPIOG_PIN10) | \
+ PIN_MODE_INPUT(GPIOG_PIN11) | \
+ PIN_MODE_INPUT(GPIOG_PIN12) | \
+ PIN_MODE_INPUT(GPIOG_PIN13) | \
+ PIN_MODE_INPUT(GPIOG_PIN14) | \
+ PIN_MODE_INPUT(GPIOG_PIN15))
+#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
+#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(GPIOG_PIN0) | \
+ PIN_OSPEED_100M(GPIOG_PIN1) | \
+ PIN_OSPEED_100M(GPIOG_PIN2) | \
+ PIN_OSPEED_100M(GPIOG_PIN3) | \
+ PIN_OSPEED_100M(GPIOG_PIN4) | \
+ PIN_OSPEED_100M(GPIOG_PIN5) | \
+ PIN_OSPEED_100M(GPIOG_PIN6) | \
+ PIN_OSPEED_100M(GPIOG_PIN7) | \
+ PIN_OSPEED_100M(GPIOG_PIN8) | \
+ PIN_OSPEED_100M(GPIOG_PIN9) | \
+ PIN_OSPEED_100M(GPIOG_PIN10) | \
+ PIN_OSPEED_100M(GPIOG_PIN11) | \
+ PIN_OSPEED_100M(GPIOG_PIN12) | \
+ PIN_OSPEED_100M(GPIOG_PIN13) | \
+ PIN_OSPEED_100M(GPIOG_PIN14) | \
+ PIN_OSPEED_100M(GPIOG_PIN15))
+#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOG_PIN15))
+#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \
+ PIN_ODR_HIGH(GPIOG_PIN1) | \
+ PIN_ODR_HIGH(GPIOG_PIN2) | \
+ PIN_ODR_HIGH(GPIOG_PIN3) | \
+ PIN_ODR_HIGH(GPIOG_PIN4) | \
+ PIN_ODR_HIGH(GPIOG_PIN5) | \
+ PIN_ODR_HIGH(GPIOG_PIN6) | \
+ PIN_ODR_HIGH(GPIOG_PIN7) | \
+ PIN_ODR_HIGH(GPIOG_PIN8) | \
+ PIN_ODR_HIGH(GPIOG_PIN9) | \
+ PIN_ODR_HIGH(GPIOG_PIN10) | \
+ PIN_ODR_HIGH(GPIOG_PIN11) | \
+ PIN_ODR_HIGH(GPIOG_PIN12) | \
+ PIN_ODR_HIGH(GPIOG_PIN13) | \
+ PIN_ODR_HIGH(GPIOG_PIN14) | \
+ PIN_ODR_HIGH(GPIOG_PIN15))
+#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN7, 0))
+#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOG_PIN15, 0))
+
+/*
+ * GPIOH setup:
+ *
+ * PH0 - OSC_IN (input floating).
+ * PH1 - OSC_OUT (input floating).
+ * PH2 - PIN2 (input floating).
+ * PH3 - PIN3 (input floating).
+ * PH4 - PIN4 (input floating).
+ * PH5 - PIN5 (input floating).
+ * PH6 - PIN6 (input floating).
+ * PH7 - PIN7 (input floating).
+ * PH8 - PIN8 (input floating).
+ * PH9 - PIN9 (input floating).
+ * PH10 - PIN10 (input floating).
+ * PH11 - PIN11 (input floating).
+ * PH12 - PIN12 (input floating).
+ * PH13 - PIN13 (input floating).
+ * PH14 - PIN14 (input floating).
+ * PH15 - PIN15 (input floating).
+ */
+#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
+ PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
+ PIN_MODE_INPUT(GPIOH_PIN2) | \
+ PIN_MODE_INPUT(GPIOH_PIN3) | \
+ PIN_MODE_INPUT(GPIOH_PIN4) | \
+ PIN_MODE_INPUT(GPIOH_PIN5) | \
+ PIN_MODE_INPUT(GPIOH_PIN6) | \
+ PIN_MODE_INPUT(GPIOH_PIN7) | \
+ PIN_MODE_INPUT(GPIOH_PIN8) | \
+ PIN_MODE_INPUT(GPIOH_PIN9) | \
+ PIN_MODE_INPUT(GPIOH_PIN10) | \
+ PIN_MODE_INPUT(GPIOH_PIN11) | \
+ PIN_MODE_INPUT(GPIOH_PIN12) | \
+ PIN_MODE_INPUT(GPIOH_PIN13) | \
+ PIN_MODE_INPUT(GPIOH_PIN14) | \
+ PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(GPIOH_OSC_IN) | \
+ PIN_OSPEED_100M(GPIOH_OSC_OUT) | \
+ PIN_OSPEED_100M(GPIOH_PIN2) | \
+ PIN_OSPEED_100M(GPIOH_PIN3) | \
+ PIN_OSPEED_100M(GPIOH_PIN4) | \
+ PIN_OSPEED_100M(GPIOH_PIN5) | \
+ PIN_OSPEED_100M(GPIOH_PIN6) | \
+ PIN_OSPEED_100M(GPIOH_PIN7) | \
+ PIN_OSPEED_100M(GPIOH_PIN8) | \
+ PIN_OSPEED_100M(GPIOH_PIN9) | \
+ PIN_OSPEED_100M(GPIOH_PIN10) | \
+ PIN_OSPEED_100M(GPIOH_PIN11) | \
+ PIN_OSPEED_100M(GPIOH_PIN12) | \
+ PIN_OSPEED_100M(GPIOH_PIN13) | \
+ PIN_OSPEED_100M(GPIOH_PIN14) | \
+ PIN_OSPEED_100M(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \
+ PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOH_PIN15))
+#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \
+ PIN_ODR_HIGH(GPIOH_OSC_OUT) | \
+ PIN_ODR_HIGH(GPIOH_PIN2) | \
+ PIN_ODR_HIGH(GPIOH_PIN3) | \
+ PIN_ODR_HIGH(GPIOH_PIN4) | \
+ PIN_ODR_HIGH(GPIOH_PIN5) | \
+ PIN_ODR_HIGH(GPIOH_PIN6) | \
+ PIN_ODR_HIGH(GPIOH_PIN7) | \
+ PIN_ODR_HIGH(GPIOH_PIN8) | \
+ PIN_ODR_HIGH(GPIOH_PIN9) | \
+ PIN_ODR_HIGH(GPIOH_PIN10) | \
+ PIN_ODR_HIGH(GPIOH_PIN11) | \
+ PIN_ODR_HIGH(GPIOH_PIN12) | \
+ PIN_ODR_HIGH(GPIOH_PIN13) | \
+ PIN_ODR_HIGH(GPIOH_PIN14) | \
+ PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \
+ PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN7, 0))
+#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOH_PIN15, 0))
+
+/*
+ * GPIOI setup:
+ *
+ * PI0 - PIN0 (input floating).
+ * PI1 - PIN1 (input floating).
+ * PI2 - PIN2 (input floating).
+ * PI3 - PIN3 (input floating).
+ * PI4 - PIN4 (input floating).
+ * PI5 - PIN5 (input floating).
+ * PI6 - PIN6 (input floating).
+ * PI7 - PIN7 (input floating).
+ * PI8 - PIN8 (input floating).
+ * PI9 - PIN9 (input floating).
+ * PI10 - PIN10 (input floating).
+ * PI11 - PIN11 (input floating).
+ * PI12 - PIN12 (input floating).
+ * PI13 - PIN13 (input floating).
+ * PI14 - PIN14 (input floating).
+ * PI15 - PIN15 (input floating).
+ */
+#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \
+ PIN_MODE_INPUT(GPIOI_PIN1) | \
+ PIN_MODE_INPUT(GPIOI_PIN2) | \
+ PIN_MODE_INPUT(GPIOI_PIN3) | \
+ PIN_MODE_INPUT(GPIOI_PIN4) | \
+ PIN_MODE_INPUT(GPIOI_PIN5) | \
+ PIN_MODE_INPUT(GPIOI_PIN6) | \
+ PIN_MODE_INPUT(GPIOI_PIN7) | \
+ PIN_MODE_INPUT(GPIOI_PIN8) | \
+ PIN_MODE_INPUT(GPIOI_PIN9) | \
+ PIN_MODE_INPUT(GPIOI_PIN10) | \
+ PIN_MODE_INPUT(GPIOI_PIN11) | \
+ PIN_MODE_INPUT(GPIOI_PIN12) | \
+ PIN_MODE_INPUT(GPIOI_PIN13) | \
+ PIN_MODE_INPUT(GPIOI_PIN14) | \
+ PIN_MODE_INPUT(GPIOI_PIN15))
+#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
+#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_100M(GPIOI_PIN0) | \
+ PIN_OSPEED_100M(GPIOI_PIN1) | \
+ PIN_OSPEED_100M(GPIOI_PIN2) | \
+ PIN_OSPEED_100M(GPIOI_PIN3) | \
+ PIN_OSPEED_100M(GPIOI_PIN4) | \
+ PIN_OSPEED_100M(GPIOI_PIN5) | \
+ PIN_OSPEED_100M(GPIOI_PIN6) | \
+ PIN_OSPEED_100M(GPIOI_PIN7) | \
+ PIN_OSPEED_100M(GPIOI_PIN8) | \
+ PIN_OSPEED_100M(GPIOI_PIN9) | \
+ PIN_OSPEED_100M(GPIOI_PIN10) | \
+ PIN_OSPEED_100M(GPIOI_PIN11) | \
+ PIN_OSPEED_100M(GPIOI_PIN12) | \
+ PIN_OSPEED_100M(GPIOI_PIN13) | \
+ PIN_OSPEED_100M(GPIOI_PIN14) | \
+ PIN_OSPEED_100M(GPIOI_PIN15))
+#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOI_PIN15))
+#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \
+ PIN_ODR_HIGH(GPIOI_PIN1) | \
+ PIN_ODR_HIGH(GPIOI_PIN2) | \
+ PIN_ODR_HIGH(GPIOI_PIN3) | \
+ PIN_ODR_HIGH(GPIOI_PIN4) | \
+ PIN_ODR_HIGH(GPIOI_PIN5) | \
+ PIN_ODR_HIGH(GPIOI_PIN6) | \
+ PIN_ODR_HIGH(GPIOI_PIN7) | \
+ PIN_ODR_HIGH(GPIOI_PIN8) | \
+ PIN_ODR_HIGH(GPIOI_PIN9) | \
+ PIN_ODR_HIGH(GPIOI_PIN10) | \
+ PIN_ODR_HIGH(GPIOI_PIN11) | \
+ PIN_ODR_HIGH(GPIOI_PIN12) | \
+ PIN_ODR_HIGH(GPIOI_PIN13) | \
+ PIN_ODR_HIGH(GPIOI_PIN14) | \
+ PIN_ODR_HIGH(GPIOI_PIN15))
+#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN7, 0))
+#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOI_PIN15, 0))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.mk b/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.mk
index c9f62196..dba2e483 100644
--- a/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.mk
+++ b/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.mk
@@ -1,6 +1,6 @@
-# Required include directories
-BOARDINC = $(GFXLIB)/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board
-
-# List of all the board related files.
-BOARDSRC = $(BOARDINC)/board.c \
+# Required include directories
+BOARDINC = $(GFXLIB)/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board
+
+# List of all the board related files.
+BOARDSRC = $(BOARDINC)/board.c \
$(BOARDINC)/flash_memory.c
\ No newline at end of file
diff --git a/boards/base/Olimex-STM32-LCD/chibios_board/board.c b/boards/base/Olimex-STM32-LCD/chibios_board/board.c
index 397ed99b..33cbada4 100644
--- a/boards/base/Olimex-STM32-LCD/chibios_board/board.c
+++ b/boards/base/Olimex-STM32-LCD/chibios_board/board.c
@@ -1,88 +1,88 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#include "ch.h"
-#include "hal.h"
-
-/**
- * @brief PAL setup.
- * @details Digital I/O ports static configuration as defined in @p board.h.
- * This variable is used by the HAL when initializing the PAL driver.
- */
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-const PALConfig pal_default_config =
-{
- {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
- {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
- {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
- {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
- {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
- {VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH},
- {VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH},
-};
-#endif
-
-/*
- * Early initialization code.
- * This initialization must be performed just after stack setup and before
- * any other initialization.
- */
-void __early_init(void) {
- stm32_clock_init();
-}
-
-#if HAL_USE_SDC || defined(__DOXYGEN__)
-/**
- * @brief SDC card detection.
- */
-bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
- (void)sdcp;
-
- return TRUE;
-}
-
-/**
- * @brief SDC card write protection detection.
- */
-bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
- (void)sdcp;
-
- return FALSE;
-}
-#endif /* HAL_USE_SDC */
-
-#if HAL_USE_MMC_SPI
-/* Board-related functions related to the MMC_SPI driver.*/
-bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
- (void)mmcp;
-
- return TRUE;
-}
-
-bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
- (void)mmcp;
-
- return FALSE;
-}
-#endif
-
-/*
- * Board-specific initialization code.
- */
-void boardInit(void) {
-
-}
-
+/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+ {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+ {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+ {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+ {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
+ {VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH},
+ {VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH},
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+ (void)sdcp;
+
+ return TRUE;
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
+ (void)sdcp;
+
+ return FALSE;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI
+/* Board-related functions related to the MMC_SPI driver.*/
+bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+ (void)mmcp;
+
+ return TRUE;
+}
+
+bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+ (void)mmcp;
+
+ return FALSE;
+}
+#endif
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+
+}
+
diff --git a/boards/base/Olimex-STM32-LCD/chibios_board/board.h b/boards/base/Olimex-STM32-LCD/chibios_board/board.h
index 0d510aba..b3f7e246 100644
--- a/boards/base/Olimex-STM32-LCD/chibios_board/board.h
+++ b/boards/base/Olimex-STM32-LCD/chibios_board/board.h
@@ -1,196 +1,196 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/*
- * Setup for the Olimex STM32-LCD proto board.
- */
-
-/*
- * Board identifier.
- */
-#define BOARD_OLIMEX_STM32_LCD
-#define BOARD_NAME "Olimex STM32-LCD"
-
-/*
- * Board frequencies.
- */
-#define STM32_LSECLK 32768
-#define STM32_HSECLK 8000000
-
-/*
- * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
- */
-#define STM32F10X_HD
-
-/*
- * IO pins assignments.
- */
-#define GPIOA_SPI1NSS 4
-
-#define GPIOB_SPI2NSS 12
-
-#define GPIOA_USB_P 0
-#define GPIOD_USB_DISC 2
-
-#define GPIOE_TFT_RST 2
-#define GPIOD_TFT_LIGHT 13
-#define GPIOC_TFT_YD 0
-#define GPIOC_TFT_YU 1
-#define GPIOC_TFT_XL 2
-#define GPIOC_TFT_XR 3
-
-/*
- * I/O ports initial setup, this configuration is established soon after reset
- * in the initialization code.
- *
- * The digits have the following meaning:
- * 0 - Analog input.
- * 1 - Push Pull output 10MHz.
- * 2 - Push Pull output 2MHz.
- * 3 - Push Pull output 50MHz.
- * 4 - Digital input.
- * 5 - Open Drain output 10MHz.
- * 6 - Open Drain output 2MHz.
- * 7 - Open Drain output 50MHz.
- * 8 - Digital input with PullUp or PullDown resistor depending on ODR.
- * 9 - Alternate Push Pull output 10MHz.
- * A - Alternate Push Pull output 2MHz.
- * B - Alternate Push Pull output 50MHz.
- * C - Reserved.
- * D - Alternate Open Drain output 10MHz.
- * E - Alternate Open Drain output 2MHz.
- * F - Alternate Open Drain output 50MHz.
- * Please refer to the STM32 Reference Manual for details.
- */
-
-/*
- * Port A setup.
- * Everything input with pull-up except:
- * PA0 - Normal input (USB P).
- * PA2 - Alternate output (USART2 TX).
- * PA3 - Normal input (USART2 RX).
- * PA11 - Normal input (USB DM).
- * PA12 - Normal input (USB DP).
- */
-#define VAL_GPIOACRL 0x88884B84 /* PA7...PA0 */
-#define VAL_GPIOACRH 0x88844888 /* PA15...PA8 */
-#define VAL_GPIOAODR 0xFFFFFFFF
-
-/*
- * Port B setup.
- * Everything input with pull-up except:
- */
-#define VAL_GPIOBCRL 0x88888888 /* PB7...PB0 */
-#define VAL_GPIOBCRH 0x88888888 /* PB15...PB8 */
-#define VAL_GPIOBODR 0xFFFFFFFF
-
-/*
- * Port C setup.
- * Everything input with pull-up except:
- * PC0 - Analog Input (TP_YD).
- * PC1 - Analog Input (TP_YU).
- * PC2 - Analog Input (TP_XL).
- * PC3 - Analog Input (TP_XR).
- * PC8 - Alternate PP 50M (SD_D0).
- * PC9 - Alternate PP 50M (SD_D1).
- * PC10 - Alternate PP 50M (SD_D2).
- * PC11 - Alternate PP 50M (SD_D3).
- * PC12 - Alternate PP 50M (SD_CLK).
- * PC14 - Normal input (XTAL).
- * PC15 - Normal input (XTAL).
- */
-#define VAL_GPIOCCRL 0x88880000 /* PC7...PC0 */
-#define VAL_GPIOCCRH 0x448BBBBB /* PC15...PC8 */
-#define VAL_GPIOCODR 0xFFFFFFFF
-
-/*
- * Port D setup.
- * Everything input with pull-up except:
- * PD2 - Alternate PP 50M (SD_CMD)
- * PD0 - Alternate PP 50M (FSMC_D2)
- * PD1 - Alternate PP 50M (FSMC_D3)
- * PD4 - Alternate PP 50M (TFT_RD)
- * PD5 - Alternate PP 50M (TFT_WR)
- * PD7 - Alternate PP 50M (TFT_CS)
- * PD8 - Alternate PP 50M (FSMC_D13)
- * PD9 - Alternate PP 50M (FSMC_D14)
- * PD10 - Alternate PP 50M (FSMC_D15)
- * PD14 - Alternate PP 50M (FSMC_D0)
- * PD15 - Alternate PP 50M (FSMC_D1)
- */
-#define VAL_GPIODCRL 0xBBBB8BBB /* PD7...PD0 */
-#define VAL_GPIODCRH 0xBB388BBB /* PD15...PD8 */
-#define VAL_GPIODODR 0xFFFFFFFF
-
-/*
- * Port E setup.
- * Everything input with pull-up except:
- * PE2 - Digital Output (TFT_RST)
- * PE3 - Alternate PP 50M (TFT_RS)
- * PE7 - Alternate PP 50M (FSMC_D4)
- * PE8 - Alternate PP 50M (FSMC_D5)
- * PE9 - Alternate PP 50M (FSMC_D6)
- * PE10 - Alternate PP 50M (FSMC_D7)
- * PE11 - Alternate PP 50M (FSMC_D8)
- * PE12 - Alternate PP 50M (FSMC_D9)
- * PE13 - Alternate PP 50M (FSMC_D10)
- * PE14 - Alternate PP 50M (FSMC_D11)
- * PE15 - Alternate PP 50M (FSMC_D12)
- */
-#define VAL_GPIOECRL 0xB888B388 /* PE7...PE0 */
-#define VAL_GPIOECRH 0xBBBBBBBB /* PE15...PE8 */
-#define VAL_GPIOEODR 0xFFFFFFFF
-
-/*
- * Port F setup.
- * Everything input with pull-up expect:
- */
-#define VAL_GPIOFCRL 0x88888888 /* PF7...PF0 */
-#define VAL_GPIOFCRH 0x88888888 /* PF15...PF8 */
-#define VAL_GPIOFODR 0xFFFFFFFF
-
-/*
- * Port G setup.
- * Everything input with pull-up expect:
- */
-#define VAL_GPIOGCRL 0x88888888 /* PG7...PG0 */
-#define VAL_GPIOGCRH 0x88888888 /* PG15...PG8 */
-#define VAL_GPIOGODR 0xFFFFFFFF
-
-/*
- * USB bus activation macro, required by the USB driver.
- */
-#define usb_lld_connect_bus(usbp) palClearPad(GPIOD, GPIOD_USB_DISC)
-
-/*
- * USB bus de-activation macro, required by the USB driver.
- */
-#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOD, GPIOD_USB_DISC)
-
-#if !defined(_FROM_ASM_)
-#ifdef __cplusplus
-extern "C" {
-#endif
- void boardInit(void);
-#ifdef __cplusplus
-}
-#endif
-#endif /* _FROM_ASM_ */
-
-#endif /* _BOARD_H_ */
+/*
+ ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the Olimex STM32-LCD proto board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_STM32_LCD
+#define BOARD_NAME "Olimex STM32-LCD"
+
+/*
+ * Board frequencies.
+ */
+#define STM32_LSECLK 32768
+#define STM32_HSECLK 8000000
+
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define STM32F10X_HD
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_SPI1NSS 4
+
+#define GPIOB_SPI2NSS 12
+
+#define GPIOA_USB_P 0
+#define GPIOD_USB_DISC 2
+
+#define GPIOE_TFT_RST 2
+#define GPIOD_TFT_LIGHT 13
+#define GPIOC_TFT_YD 0
+#define GPIOC_TFT_YU 1
+#define GPIOC_TFT_XL 2
+#define GPIOC_TFT_XR 3
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ *
+ * The digits have the following meaning:
+ * 0 - Analog input.
+ * 1 - Push Pull output 10MHz.
+ * 2 - Push Pull output 2MHz.
+ * 3 - Push Pull output 50MHz.
+ * 4 - Digital input.
+ * 5 - Open Drain output 10MHz.
+ * 6 - Open Drain output 2MHz.
+ * 7 - Open Drain output 50MHz.
+ * 8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ * 9 - Alternate Push Pull output 10MHz.
+ * A - Alternate Push Pull output 2MHz.
+ * B - Alternate Push Pull output 50MHz.
+ * C - Reserved.
+ * D - Alternate Open Drain output 10MHz.
+ * E - Alternate Open Drain output 2MHz.
+ * F - Alternate Open Drain output 50MHz.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+
+/*
+ * Port A setup.
+ * Everything input with pull-up except:
+ * PA0 - Normal input (USB P).
+ * PA2 - Alternate output (USART2 TX).
+ * PA3 - Normal input (USART2 RX).
+ * PA11 - Normal input (USB DM).
+ * PA12 - Normal input (USB DP).
+ */
+#define VAL_GPIOACRL 0x88884B84 /* PA7...PA0 */
+#define VAL_GPIOACRH 0x88844888 /* PA15...PA8 */
+#define VAL_GPIOAODR 0xFFFFFFFF
+
+/*
+ * Port B setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOBCRL 0x88888888 /* PB7...PB0 */
+#define VAL_GPIOBCRH 0x88888888 /* PB15...PB8 */
+#define VAL_GPIOBODR 0xFFFFFFFF
+
+/*
+ * Port C setup.
+ * Everything input with pull-up except:
+ * PC0 - Analog Input (TP_YD).
+ * PC1 - Analog Input (TP_YU).
+ * PC2 - Analog Input (TP_XL).
+ * PC3 - Analog Input (TP_XR).
+ * PC8 - Alternate PP 50M (SD_D0).
+ * PC9 - Alternate PP 50M (SD_D1).
+ * PC10 - Alternate PP 50M (SD_D2).
+ * PC11 - Alternate PP 50M (SD_D3).
+ * PC12 - Alternate PP 50M (SD_CLK).
+ * PC14 - Normal input (XTAL).
+ * PC15 - Normal input (XTAL).
+ */
+#define VAL_GPIOCCRL 0x88880000 /* PC7...PC0 */
+#define VAL_GPIOCCRH 0x448BBBBB /* PC15...PC8 */
+#define VAL_GPIOCODR 0xFFFFFFFF
+
+/*
+ * Port D setup.
+ * Everything input with pull-up except:
+ * PD2 - Alternate PP 50M (SD_CMD)
+ * PD0 - Alternate PP 50M (FSMC_D2)
+ * PD1 - Alternate PP 50M (FSMC_D3)
+ * PD4 - Alternate PP 50M (TFT_RD)
+ * PD5 - Alternate PP 50M (TFT_WR)
+ * PD7 - Alternate PP 50M (TFT_CS)
+ * PD8 - Alternate PP 50M (FSMC_D13)
+ * PD9 - Alternate PP 50M (FSMC_D14)
+ * PD10 - Alternate PP 50M (FSMC_D15)
+ * PD14 - Alternate PP 50M (FSMC_D0)
+ * PD15 - Alternate PP 50M (FSMC_D1)
+ */
+#define VAL_GPIODCRL 0xBBBB8BBB /* PD7...PD0 */
+#define VAL_GPIODCRH 0xBB388BBB /* PD15...PD8 */
+#define VAL_GPIODODR 0xFFFFFFFF
+
+/*
+ * Port E setup.
+ * Everything input with pull-up except:
+ * PE2 - Digital Output (TFT_RST)
+ * PE3 - Alternate PP 50M (TFT_RS)
+ * PE7 - Alternate PP 50M (FSMC_D4)
+ * PE8 - Alternate PP 50M (FSMC_D5)
+ * PE9 - Alternate PP 50M (FSMC_D6)
+ * PE10 - Alternate PP 50M (FSMC_D7)
+ * PE11 - Alternate PP 50M (FSMC_D8)
+ * PE12 - Alternate PP 50M (FSMC_D9)
+ * PE13 - Alternate PP 50M (FSMC_D10)
+ * PE14 - Alternate PP 50M (FSMC_D11)
+ * PE15 - Alternate PP 50M (FSMC_D12)
+ */
+#define VAL_GPIOECRL 0xB888B388 /* PE7...PE0 */
+#define VAL_GPIOECRH 0xBBBBBBBB /* PE15...PE8 */
+#define VAL_GPIOEODR 0xFFFFFFFF
+
+/*
+ * Port F setup.
+ * Everything input with pull-up expect:
+ */
+#define VAL_GPIOFCRL 0x88888888 /* PF7...PF0 */
+#define VAL_GPIOFCRH 0x88888888 /* PF15...PF8 */
+#define VAL_GPIOFODR 0xFFFFFFFF
+
+/*
+ * Port G setup.
+ * Everything input with pull-up expect:
+ */
+#define VAL_GPIOGCRL 0x88888888 /* PG7...PG0 */
+#define VAL_GPIOGCRH 0x88888888 /* PG15...PG8 */
+#define VAL_GPIOGODR 0xFFFFFFFF
+
+/*
+ * USB bus activation macro, required by the USB driver.
+ */
+#define usb_lld_connect_bus(usbp) palClearPad(GPIOD, GPIOD_USB_DISC)
+
+/*
+ * USB bus de-activation macro, required by the USB driver.
+ */
+#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOD, GPIOD_USB_DISC)
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/base/Olimex-STM32-LCD/chibios_board/board.mk b/boards/base/Olimex-STM32-LCD/chibios_board/board.mk
index 397afe3e..97c293db 100644
--- a/boards/base/Olimex-STM32-LCD/chibios_board/board.mk
+++ b/boards/base/Olimex-STM32-LCD/chibios_board/board.mk
@@ -1,3 +1,3 @@
-BOARDINC = $(GFXLIB)/boards/base/Olimex-STM32-LCD/chibios_board
-BOARDSRC = $(BOARDINC)/board.c \
-
+BOARDINC = $(GFXLIB)/boards/base/Olimex-STM32-LCD/chibios_board
+BOARDSRC = $(BOARDINC)/board.c \
+
diff --git a/boards/base/STM32F429i-Discovery/chibios/board.mk b/boards/base/STM32F429i-Discovery/chibios/board.mk
index 730bb083..e690d83c 100644
--- a/boards/base/STM32F429i-Discovery/chibios/board.mk
+++ b/boards/base/STM32F429i-Discovery/chibios/board.mk
@@ -1,7 +1,7 @@
-GFXINC += $(GFXLIB)/boards/base/STM32F429i-Discovery/chibios
-GFXSRC += $(GFXLIB)/boards/base/STM32F429i-Discovery/chibios/stm32f429i_discovery_sdram.c \
- $(GFXLIB)/boards/base/STM32F429i-Discovery/chibios/stm32f4xx_fmc.c
-
-GFXDEFS += -DGFX_USE_OS_CHIBIOS=GFXON
-include $(GFXLIB)/drivers/gdisp/STM32LTDC/driver.mk
-include $(GFXLIB)/drivers/ginput/touch/STMPE811/driver.mk
+GFXINC += $(GFXLIB)/boards/base/STM32F429i-Discovery/chibios
+GFXSRC += $(GFXLIB)/boards/base/STM32F429i-Discovery/chibios/stm32f429i_discovery_sdram.c \
+ $(GFXLIB)/boards/base/STM32F429i-Discovery/chibios/stm32f4xx_fmc.c
+
+GFXDEFS += -DGFX_USE_OS_CHIBIOS=GFXON
+include $(GFXLIB)/drivers/gdisp/STM32LTDC/driver.mk
+include $(GFXLIB)/drivers/ginput/touch/STMPE811/driver.mk
diff --git a/boards/base/STM32F429i-Discovery/chibios/board_STM32LTDC.h b/boards/base/STM32F429i-Discovery/chibios/board_STM32LTDC.h
index cdcb69f9..a44d25c7 100644
--- a/boards/base/STM32F429i-Discovery/chibios/board_STM32LTDC.h
+++ b/boards/base/STM32F429i-Discovery/chibios/board_STM32LTDC.h
@@ -1,212 +1,212 @@
-/*
- * This file is subject to the terms of the GFX License. If a copy of
- * the license was not distributed with this file, you can obtain one at:
- *
- * http://ugfx.io/license.html
- */
-
-#ifndef _GDISP_LLD_BOARD_H
-#define _GDISP_LLD_BOARD_H
-
-#include "stm32f4xx_fmc.h"
-#include "stm32f429i_discovery_sdram.h"
-#include
-
-#define SPI_PORT &SPID5
-#define DC_PORT GPIOD
-#define DC_PIN GPIOD_LCD_WRX
-
-static const SPIConfig spi_cfg = {
- NULL,
- GPIOC,
- GPIOC_SPI5_LCD_CS,
- ((1 << 3) & SPI_CR1_BR) | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR
-};
-
-static const ltdcConfig driverCfg = {
- 240, 320,
- 10, 2,
- 20, 2,
- 10, 4,
- 0,
- 0x000000,
- {
- (LLDCOLOR_TYPE *)SDRAM_BANK_ADDR, // frame
- 240, 320, // width, height
- 240 * LTDC_PIXELBYTES, // pitch
- LTDC_PIXELFORMAT, // fmt
- 0, 0, // x, y
- 240, 320, // cx, cy
- 0x00000000, // defcolor
- 0x000000, // keycolor
- LTDC_BLEND_FIX1_FIX2, // blending
- 0, // palette
- 0, // palettelen
- 0xFF, // alpha
- LTDC_LEF_ENABLE // flags
- },
-#if STM32LTDC_USE_LAYER2 || STM32LTDC_USE_DOUBLEBUFFERING
- { // Foreground layer config (if turned on)
- (LLDCOLOR_TYPE *)(SDRAM_BANK_ADDR+(240 * 320 * LTDC_PIXELBYTES)), // Frame buffer address
- 240, 320, // width, height
- 240 * LTDC_PIXELBYTES, // pitch
- LTDC_PIXELFORMAT, // fmt
- 0, 0, // x, y
- 240, 320, // cx, cy
- 0x00000000, // Default color (ARGB8888)
- 0x000000, // Color key (RGB888)
- LTDC_BLEND_MOD1_MOD2, // Blending factors
- 0, // Palette (RGB888, can be NULL)
- 0, // Palette length
- 0xFF, // Constant alpha factor
- LTDC_LEF_ENABLE // Layer configuration flags
- }
-#else
- LTDC_UNUSED_LAYER_CONFIG
-#endif
-};
-
-#include "ili9341.h"
-
-static void acquire_bus(GDisplay *g) {
- (void) g;
-
- spiSelect(SPI_PORT);
-}
-
-static void release_bus(GDisplay *g) {
- (void) g;
-
- spiUnselect(SPI_PORT);
-}
-
-static void write_index(GDisplay *g, gU8 index) {
- static gU8 sindex;
- (void) g;
-
- palClearPad(DC_PORT, DC_PIN);
- sindex = index;
- spiSend(SPI_PORT, 1, &sindex);
-}
-
-static void write_data(GDisplay *g, gU8 data) {
- static gU8 sdata;
- (void) g;
-
- palSetPad(DC_PORT, DC_PIN);
- sdata = data;
- spiSend(SPI_PORT, 1, &sdata);
-}
-
-static void Init9341(GDisplay *g) {
- #define REG_TYPEMASK 0xFF00
- #define REG_DATAMASK 0x00FF
-
- #define REG_DATA 0x0000
- #define REG_COMMAND 0x0100
- #define REG_DELAY 0x0200
-
- static const gU16 initdata[] = {
- REG_COMMAND | ILI9341_CMD_RESET,
- REG_DELAY | 5,
- REG_COMMAND | ILI9341_CMD_DISPLAY_OFF,
- REG_COMMAND | ILI9341_SET_FRAME_CTL_NORMAL, 0x00, 0x1B,
- REG_COMMAND | ILI9341_SET_FUNCTION_CTL, 0x0A, 0xA2,
- REG_COMMAND | ILI9341_SET_POWER_CTL_1, 0x10,
- REG_COMMAND | ILI9341_SET_POWER_CTL_2, 0x10,
- #if 1
- REG_COMMAND | ILI9341_SET_VCOM_CTL_1, 0x45, 0x15,
- REG_COMMAND | ILI9341_SET_VCOM_CTL_2, 0x90,
- #else
- REG_COMMAND | ILI9341_SET_VCOM_CTL_1, 0x35, 0x3E,
- REG_COMMAND | ILI9341_SET_VCOM_CTL_2, 0xBE,
- #endif
- REG_COMMAND | ILI9341_SET_MEM_ACS_CTL, 0xC8,
- REG_COMMAND | ILI9341_SET_RGB_IF_SIG_CTL, 0xC2,
- REG_COMMAND | ILI9341_SET_FUNCTION_CTL, 0x0A, 0xA7, 0x27, 0x04,
- REG_COMMAND | ILI9341_SET_COL_ADDR, 0x00, 0x00, 0x00, 0xEF,
- REG_COMMAND | ILI9341_SET_PAGE_ADDR, 0x00, 0x00, 0x01, 0x3F,
- REG_COMMAND | ILI9341_SET_IF_CTL, 0x01, 0x00, 0x06,
- REG_COMMAND | ILI9341_SET_GAMMA, 0x01,
- REG_COMMAND | ILI9341_SET_PGAMMA,
- #if 1
- 0x0F, 0x29, 0x24, 0x0C, 0x0E, 0x09, 0x4E, 0x78,
- 0x3C, 0x09, 0x13, 0x05, 0x17, 0x11, 0x00,
- #else
- 0x1F, 0x1a, 0x18, 0x0a, 0x0f, 0x06, 0x45, 0x87,
- 0x32, 0x0a, 0x07, 0x02, 0x07, 0x05, 0x00,
- #endif
- REG_COMMAND | ILI9341_SET_NGAMMA,
- #if 1
- 0x00, 0x16, 0x1B, 0x04, 0x11, 0x07, 0x31, 0x33,
- 0x42, 0x05, 0x0C, 0x0A, 0x28, 0x2F, 0x0F,
- #else
- 0x00, 0x25, 0x27, 0x05, 0x10, 0x09, 0x3a, 0x78,
- 0x4d, 0x05, 0x18, 0x0d, 0x38, 0x3a, 0x1f,
- #endif
- REG_COMMAND | ILI9341_CMD_SLEEP_OFF,
- REG_DELAY | 10,
- REG_COMMAND | ILI9341_CMD_DISPLAY_ON,
- REG_COMMAND | ILI9341_SET_MEM
- };
-
- const gU16 *p;
-
- acquire_bus(g);
- for(p = initdata; p < &initdata[sizeof(initdata)/sizeof(initdata[0])]; p++) {
- switch(*p & REG_TYPEMASK) {
- case REG_DATA: write_data(g, *p); break;
- case REG_COMMAND: write_index(g, *p); break;
- case REG_DELAY: gfxSleepMilliseconds(*p & 0xFF); break;
- }
- }
- release_bus(g);
-}
-
-static void init_board(GDisplay *g) {
- (void) g;
-
- palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); // UART_TX
- palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7)); // UART_RX
- palSetPadMode(GPIOF, GPIOF_LCD_DCX, PAL_MODE_ALTERNATE(5));
- palSetPadMode(GPIOF, GPIOF_LCD_DE, PAL_MODE_ALTERNATE(14));
-
- #define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */
- #define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */
- #define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */
- #define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */
- #define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */
- #define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */
-
- #define STM32_PLLSAIN_VALUE 192
- #define STM32_PLLSAIQ_VALUE 7
- #define STM32_PLLSAIR_VALUE 4
- #define STM32_PLLSAIR_POST STM32_SAIR_DIV4
-
- /* PLLSAI activation.*/
- RCC->PLLSAICFGR = (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24);
- RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST;
- RCC->CR |= RCC_CR_PLLSAION;
- while(!(RCC->CR & RCC_CR_PLLSAIRDY)); // wait for PLLSAI to lock
-
- // Initialise the SDRAM
- SDRAM_Init();
-
- // Clear the SDRAM
- memset((void *)SDRAM_BANK_ADDR, 0, 0x400000);
-
- spiStart(SPI_PORT, &spi_cfg);
-
- Init9341(g);
-}
-
-static GFXINLINE void post_init_board(GDisplay *g) {
- (void) g;
-}
-
-static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
- (void) g;
- (void) percent;
-}
-
-#endif /* _GDISP_LLD_BOARD_H */
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ * http://ugfx.io/license.html
+ */
+
+#ifndef _GDISP_LLD_BOARD_H
+#define _GDISP_LLD_BOARD_H
+
+#include "stm32f4xx_fmc.h"
+#include "stm32f429i_discovery_sdram.h"
+#include
+
+#define SPI_PORT &SPID5
+#define DC_PORT GPIOD
+#define DC_PIN GPIOD_LCD_WRX
+
+static const SPIConfig spi_cfg = {
+ NULL,
+ GPIOC,
+ GPIOC_SPI5_LCD_CS,
+ ((1 << 3) & SPI_CR1_BR) | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR
+};
+
+static const ltdcConfig driverCfg = {
+ 240, 320,
+ 10, 2,
+ 20, 2,
+ 10, 4,
+ 0,
+ 0x000000,
+ {
+ (LLDCOLOR_TYPE *)SDRAM_BANK_ADDR, // frame
+ 240, 320, // width, height
+ 240 * LTDC_PIXELBYTES, // pitch
+ LTDC_PIXELFORMAT, // fmt
+ 0, 0, // x, y
+ 240, 320, // cx, cy
+ 0x00000000, // defcolor
+ 0x000000, // keycolor
+ LTDC_BLEND_FIX1_FIX2, // blending
+ 0, // palette
+ 0, // palettelen
+ 0xFF, // alpha
+ LTDC_LEF_ENABLE // flags
+ },
+#if STM32LTDC_USE_LAYER2 || STM32LTDC_USE_DOUBLEBUFFERING
+ { // Foreground layer config (if turned on)
+ (LLDCOLOR_TYPE *)(SDRAM_BANK_ADDR+(240 * 320 * LTDC_PIXELBYTES)), // Frame buffer address
+ 240, 320, // width, height
+ 240 * LTDC_PIXELBYTES, // pitch
+ LTDC_PIXELFORMAT, // fmt
+ 0, 0, // x, y
+ 240, 320, // cx, cy
+ 0x00000000, // Default color (ARGB8888)
+ 0x000000, // Color key (RGB888)
+ LTDC_BLEND_MOD1_MOD2, // Blending factors
+ 0, // Palette (RGB888, can be NULL)
+ 0, // Palette length
+ 0xFF, // Constant alpha factor
+ LTDC_LEF_ENABLE // Layer configuration flags
+ }
+#else
+ LTDC_UNUSED_LAYER_CONFIG
+#endif
+};
+
+#include "ili9341.h"
+
+static void acquire_bus(GDisplay *g) {
+ (void) g;
+
+ spiSelect(SPI_PORT);
+}
+
+static void release_bus(GDisplay *g) {
+ (void) g;
+
+ spiUnselect(SPI_PORT);
+}
+
+static void write_index(GDisplay *g, gU8 index) {
+ static gU8 sindex;
+ (void) g;
+
+ palClearPad(DC_PORT, DC_PIN);
+ sindex = index;
+ spiSend(SPI_PORT, 1, &sindex);
+}
+
+static void write_data(GDisplay *g, gU8 data) {
+ static gU8 sdata;
+ (void) g;
+
+ palSetPad(DC_PORT, DC_PIN);
+ sdata = data;
+ spiSend(SPI_PORT, 1, &sdata);
+}
+
+static void Init9341(GDisplay *g) {
+ #define REG_TYPEMASK 0xFF00
+ #define REG_DATAMASK 0x00FF
+
+ #define REG_DATA 0x0000
+ #define REG_COMMAND 0x0100
+ #define REG_DELAY 0x0200
+
+ static const gU16 initdata[] = {
+ REG_COMMAND | ILI9341_CMD_RESET,
+ REG_DELAY | 5,
+ REG_COMMAND | ILI9341_CMD_DISPLAY_OFF,
+ REG_COMMAND | ILI9341_SET_FRAME_CTL_NORMAL, 0x00, 0x1B,
+ REG_COMMAND | ILI9341_SET_FUNCTION_CTL, 0x0A, 0xA2,
+ REG_COMMAND | ILI9341_SET_POWER_CTL_1, 0x10,
+ REG_COMMAND | ILI9341_SET_POWER_CTL_2, 0x10,
+ #if 1
+ REG_COMMAND | ILI9341_SET_VCOM_CTL_1, 0x45, 0x15,
+ REG_COMMAND | ILI9341_SET_VCOM_CTL_2, 0x90,
+ #else
+ REG_COMMAND | ILI9341_SET_VCOM_CTL_1, 0x35, 0x3E,
+ REG_COMMAND | ILI9341_SET_VCOM_CTL_2, 0xBE,
+ #endif
+ REG_COMMAND | ILI9341_SET_MEM_ACS_CTL, 0xC8,
+ REG_COMMAND | ILI9341_SET_RGB_IF_SIG_CTL, 0xC2,
+ REG_COMMAND | ILI9341_SET_FUNCTION_CTL, 0x0A, 0xA7, 0x27, 0x04,
+ REG_COMMAND | ILI9341_SET_COL_ADDR, 0x00, 0x00, 0x00, 0xEF,
+ REG_COMMAND | ILI9341_SET_PAGE_ADDR, 0x00, 0x00, 0x01, 0x3F,
+ REG_COMMAND | ILI9341_SET_IF_CTL, 0x01, 0x00, 0x06,
+ REG_COMMAND | ILI9341_SET_GAMMA, 0x01,
+ REG_COMMAND | ILI9341_SET_PGAMMA,
+ #if 1
+ 0x0F, 0x29, 0x24, 0x0C, 0x0E, 0x09, 0x4E, 0x78,
+ 0x3C, 0x09, 0x13, 0x05, 0x17, 0x11, 0x00,
+ #else
+ 0x1F, 0x1a, 0x18, 0x0a, 0x0f, 0x06, 0x45, 0x87,
+ 0x32, 0x0a, 0x07, 0x02, 0x07, 0x05, 0x00,
+ #endif
+ REG_COMMAND | ILI9341_SET_NGAMMA,
+ #if 1
+ 0x00, 0x16, 0x1B, 0x04, 0x11, 0x07, 0x31, 0x33,
+ 0x42, 0x05, 0x0C, 0x0A, 0x28, 0x2F, 0x0F,
+ #else
+ 0x00, 0x25, 0x27, 0x05, 0x10, 0x09, 0x3a, 0x78,
+ 0x4d, 0x05, 0x18, 0x0d, 0x38, 0x3a, 0x1f,
+ #endif
+ REG_COMMAND | ILI9341_CMD_SLEEP_OFF,
+ REG_DELAY | 10,
+ REG_COMMAND | ILI9341_CMD_DISPLAY_ON,
+ REG_COMMAND | ILI9341_SET_MEM
+ };
+
+ const gU16 *p;
+
+ acquire_bus(g);
+ for(p = initdata; p < &initdata[sizeof(initdata)/sizeof(initdata[0])]; p++) {
+ switch(*p & REG_TYPEMASK) {
+ case REG_DATA: write_data(g, *p); break;
+ case REG_COMMAND: write_index(g, *p); break;
+ case REG_DELAY: gfxSleepMilliseconds(*p & 0xFF); break;
+ }
+ }
+ release_bus(g);
+}
+
+static void init_board(GDisplay *g) {
+ (void) g;
+
+ palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); // UART_TX
+ palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7)); // UART_RX
+ palSetPadMode(GPIOF, GPIOF_LCD_DCX, PAL_MODE_ALTERNATE(5));
+ palSetPadMode(GPIOF, GPIOF_LCD_DE, PAL_MODE_ALTERNATE(14));
+
+ #define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */
+ #define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */
+ #define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */
+ #define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */
+ #define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */
+ #define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */
+
+ #define STM32_PLLSAIN_VALUE 192
+ #define STM32_PLLSAIQ_VALUE 7
+ #define STM32_PLLSAIR_VALUE 4
+ #define STM32_PLLSAIR_POST STM32_SAIR_DIV4
+
+ /* PLLSAI activation.*/
+ RCC->PLLSAICFGR = (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24);
+ RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST;
+ RCC->CR |= RCC_CR_PLLSAION;
+ while(!(RCC->CR & RCC_CR_PLLSAIRDY)); // wait for PLLSAI to lock
+
+ // Initialise the SDRAM
+ SDRAM_Init();
+
+ // Clear the SDRAM
+ memset((void *)SDRAM_BANK_ADDR, 0, 0x400000);
+
+ spiStart(SPI_PORT, &spi_cfg);
+
+ Init9341(g);
+}
+
+static GFXINLINE void post_init_board(GDisplay *g) {
+ (void) g;
+}
+
+static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
+ (void) g;
+ (void) percent;
+}
+
+#endif /* _GDISP_LLD_BOARD_H */
diff --git a/boards/base/STM32F429i-Discovery/chibios/gmouse_lld_STMPE811_board.h b/boards/base/STM32F429i-Discovery/chibios/gmouse_lld_STMPE811_board.h
index 47b5d1ba..667c8937 100644
--- a/boards/base/STM32F429i-Discovery/chibios/gmouse_lld_STMPE811_board.h
+++ b/boards/base/STM32F429i-Discovery/chibios/gmouse_lld_STMPE811_board.h
@@ -1,126 +1,126 @@
-/*
- * This file is subject to the terms of the GFX License. If a copy of
- * the license was not distributed with this file, you can obtain one at:
- *
- * http://ugfx.io/license.html
- */
-
-#ifndef _GINPUT_LLD_MOUSE_BOARD_H
-#define _GINPUT_LLD_MOUSE_BOARD_H
-
-// Resolution and Accuracy Settings
-#define GMOUSE_STMPE811_PEN_CALIBRATE_ERROR 8
-#define GMOUSE_STMPE811_PEN_CLICK_ERROR 6
-#define GMOUSE_STMPE811_PEN_MOVE_ERROR 4
-#define GMOUSE_STMPE811_FINGER_CALIBRATE_ERROR 14
-#define GMOUSE_STMPE811_FINGER_CLICK_ERROR 18
-#define GMOUSE_STMPE811_FINGER_MOVE_ERROR 14
-
-// How much extra data to allocate at the end of the GMouse structure for the board's use
-#define GMOUSE_STMPE811_BOARD_DATA_SIZE 0
-
-// Options - Leave these commented to make it user configurable in the gfxconf.h
-//#define GMOUSE_STMPE811_READ_PRESSURE GFXOFF
-//#define GMOUSE_STMPE811_SELF_CALIBRATE GFXOFF
-//#define GMOUSE_STMPE811_TEST_MODE GFXOFF
-
-// Set to GFXOFF because it does not work properly on this board even though the pin exists.
-#define GMOUSE_STMPE811_GPIO_IRQPIN GFXOFF
-
-// If GFXON this is a really slow CPU and we should always clear the FIFO between reads.
-#define GMOUSE_STMPE811_SLOW_CPU GFXOFF
-
-// Slave address
-#define STMPE811_ADDR 0x41
-
-// Maximum timeout
-#define STMPE811_TIMEOUT 0x3000
-
-static const I2CConfig i2ccfg = {
- OPMODE_I2C,
- 400000,
- FAST_DUTY_CYCLE_2,
-};
-
-static gBool init_board(GMouse* m, unsigned driverinstance) {
- (void) m;
-
- // This board only supports one touch panel
- if (driverinstance)
- return gFalse;
-
- // Set pin modes
- #if CH_KERNEL_MAJOR == 2
- palSetPadMode(GPIOA, 15, PAL_MODE_INPUT | PAL_STM32_PUDR_FLOATING); /* TP IRQ */
- palSetPadMode(GPIOA, 8, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN); /* SCL */
- palSetPadMode(GPIOC, 9, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN); /* SDA */
- #else
- palSetPadMode(GPIOA, 15, PAL_MODE_INPUT | PAL_STM32_PUPDR_FLOATING); /* TP IRQ */
- palSetPadMode(GPIOA, 8, PAL_MODE_ALTERNATE(4) | PAL_STM32_PUPDR_FLOATING); /* SCL */
- palSetPadMode(GPIOC, 9, PAL_MODE_ALTERNATE(4) | PAL_STM32_PUPDR_FLOATING); /* SDA */
- #endif
-
- // Start the I2C
- i2cStart(&I2CD3, &i2ccfg);
-
- return gTrue;
-}
-
-#if GMOUSE_STMPE811_GPIO_IRQPIN
- static gBool getpin_irq(GMouse* m) {
- (void) m;
-
- return !palReadPad(GPIOA, 15);
- }
-#endif
-
-static GFXINLINE void aquire_bus(GMouse* m) {
- (void) m;
-
-}
-
-static GFXINLINE void release_bus(GMouse* m) {
- (void) m;
-
-}
-
-static void write_reg(GMouse* m, gU8 reg, gU8 val) {
- gU8 txbuf[2];
- (void) m;
-
- txbuf[0] = reg;
- txbuf[1] = val;
-
- i2cAcquireBus(&I2CD3);
- i2cMasterTransmitTimeout(&I2CD3, STMPE811_ADDR, txbuf, 2, 0, 0, MS2ST(STMPE811_TIMEOUT));
- i2cReleaseBus(&I2CD3);
-}
-
-static gU8 read_byte(GMouse* m, gU8 reg) {
- gU8 rxbuf[1];
- (void) m;
-
- rxbuf[0] = 0;
-
- i2cAcquireBus(&I2CD3);
- i2cMasterTransmitTimeout(&I2CD3, STMPE811_ADDR, ®, 1, rxbuf, 1, MS2ST(STMPE811_TIMEOUT));
- i2cReleaseBus(&I2CD3);
-
- return rxbuf[0];
-}
-
-static gU16 read_word(GMouse* m, gU8 reg) {
- gU8 rxbuf[2];
- (void) m;
-
- rxbuf[0] = 0;
- rxbuf[1] = 0;
-
- i2cAcquireBus(&I2CD3);
- i2cMasterTransmitTimeout(&I2CD3, STMPE811_ADDR, ®, 1, rxbuf, 2, MS2ST(STMPE811_TIMEOUT));
- i2cReleaseBus(&I2CD3);
-
- return (((gU16)rxbuf[0]) << 8) | rxbuf[1];
-}
-
-#endif /* _GINPUT_LLD_MOUSE_BOARD_H */
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ * http://ugfx.io/license.html
+ */
+
+#ifndef _GINPUT_LLD_MOUSE_BOARD_H
+#define _GINPUT_LLD_MOUSE_BOARD_H
+
+// Resolution and Accuracy Settings
+#define GMOUSE_STMPE811_PEN_CALIBRATE_ERROR 8
+#define GMOUSE_STMPE811_PEN_CLICK_ERROR 6
+#define GMOUSE_STMPE811_PEN_MOVE_ERROR 4
+#define GMOUSE_STMPE811_FINGER_CALIBRATE_ERROR 14
+#define GMOUSE_STMPE811_FINGER_CLICK_ERROR 18
+#define GMOUSE_STMPE811_FINGER_MOVE_ERROR 14
+
+// How much extra data to allocate at the end of the GMouse structure for the board's use
+#define GMOUSE_STMPE811_BOARD_DATA_SIZE 0
+
+// Options - Leave these commented to make it user configurable in the gfxconf.h
+//#define GMOUSE_STMPE811_READ_PRESSURE GFXOFF
+//#define GMOUSE_STMPE811_SELF_CALIBRATE GFXOFF
+//#define GMOUSE_STMPE811_TEST_MODE GFXOFF
+
+// Set to GFXOFF because it does not work properly on this board even though the pin exists.
+#define GMOUSE_STMPE811_GPIO_IRQPIN GFXOFF
+
+// If GFXON this is a really slow CPU and we should always clear the FIFO between reads.
+#define GMOUSE_STMPE811_SLOW_CPU GFXOFF
+
+// Slave address
+#define STMPE811_ADDR 0x41
+
+// Maximum timeout
+#define STMPE811_TIMEOUT 0x3000
+
+static const I2CConfig i2ccfg = {
+ OPMODE_I2C,
+ 400000,
+ FAST_DUTY_CYCLE_2,
+};
+
+static gBool init_board(GMouse* m, unsigned driverinstance) {
+ (void) m;
+
+ // This board only supports one touch panel
+ if (driverinstance)
+ return gFalse;
+
+ // Set pin modes
+ #if CH_KERNEL_MAJOR == 2
+ palSetPadMode(GPIOA, 15, PAL_MODE_INPUT | PAL_STM32_PUDR_FLOATING); /* TP IRQ */
+ palSetPadMode(GPIOA, 8, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN); /* SCL */
+ palSetPadMode(GPIOC, 9, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN); /* SDA */
+ #else
+ palSetPadMode(GPIOA, 15, PAL_MODE_INPUT | PAL_STM32_PUPDR_FLOATING); /* TP IRQ */
+ palSetPadMode(GPIOA, 8, PAL_MODE_ALTERNATE(4) | PAL_STM32_PUPDR_FLOATING); /* SCL */
+ palSetPadMode(GPIOC, 9, PAL_MODE_ALTERNATE(4) | PAL_STM32_PUPDR_FLOATING); /* SDA */
+ #endif
+
+ // Start the I2C
+ i2cStart(&I2CD3, &i2ccfg);
+
+ return gTrue;
+}
+
+#if GMOUSE_STMPE811_GPIO_IRQPIN
+ static gBool getpin_irq(GMouse* m) {
+ (void) m;
+
+ return !palReadPad(GPIOA, 15);
+ }
+#endif
+
+static GFXINLINE void aquire_bus(GMouse* m) {
+ (void) m;
+
+}
+
+static GFXINLINE void release_bus(GMouse* m) {
+ (void) m;
+
+}
+
+static void write_reg(GMouse* m, gU8 reg, gU8 val) {
+ gU8 txbuf[2];
+ (void) m;
+
+ txbuf[0] = reg;
+ txbuf[1] = val;
+
+ i2cAcquireBus(&I2CD3);
+ i2cMasterTransmitTimeout(&I2CD3, STMPE811_ADDR, txbuf, 2, 0, 0, MS2ST(STMPE811_TIMEOUT));
+ i2cReleaseBus(&I2CD3);
+}
+
+static gU8 read_byte(GMouse* m, gU8 reg) {
+ gU8 rxbuf[1];
+ (void) m;
+
+ rxbuf[0] = 0;
+
+ i2cAcquireBus(&I2CD3);
+ i2cMasterTransmitTimeout(&I2CD3, STMPE811_ADDR, ®, 1, rxbuf, 1, MS2ST(STMPE811_TIMEOUT));
+ i2cReleaseBus(&I2CD3);
+
+ return rxbuf[0];
+}
+
+static gU16 read_word(GMouse* m, gU8 reg) {
+ gU8 rxbuf[2];
+ (void) m;
+
+ rxbuf[0] = 0;
+ rxbuf[1] = 0;
+
+ i2cAcquireBus(&I2CD3);
+ i2cMasterTransmitTimeout(&I2CD3, STMPE811_ADDR, ®, 1, rxbuf, 2, MS2ST(STMPE811_TIMEOUT));
+ i2cReleaseBus(&I2CD3);
+
+ return (((gU16)rxbuf[0]) << 8) | rxbuf[1];
+}
+
+#endif /* _GINPUT_LLD_MOUSE_BOARD_H */
diff --git a/boards/base/STM32F429i-Discovery/chibios/stm32f4xx_fmc.c b/boards/base/STM32F429i-Discovery/chibios/stm32f4xx_fmc.c
index 010d6d51..d6a35813 100644
--- a/boards/base/STM32F429i-Discovery/chibios/stm32f4xx_fmc.c
+++ b/boards/base/STM32F429i-Discovery/chibios/stm32f4xx_fmc.c
@@ -1,1380 +1,1380 @@
-/**
- ******************************************************************************
- * @file stm32f4xx_fmc.c
- * @author MCD Application Team
- * @version V1.2.1
- * @date 19-September-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the FMC peripheral:
- * + Interface with SRAM, PSRAM, NOR and OneNAND memories
- * + Interface with NAND memories
- * + Interface with 16-bit PC Card compatible memories
- * + Interface with SDRAM memories
- * + Interrupts and flags management
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2013 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "ch.h"
-#include "stm32f4xx_fmc.h"
-//#include "stm32f4xx_rcc.h"
-
-#if CH_KERNEL_MAJOR == 2
- #define assert_param(expr) chDbgAssert(expr,"STPeriph FMC","")
-#else
- #define assert_param(expr) chDbgAssert(expr,"STPeriph FMC")
-#endif
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup FMC
- * @brief FMC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* --------------------- FMC registers bit mask ---------------------------- */
-/* FMC BCRx Mask */
-#define BCR_MBKEN_SET ((gU32)0x00000001)
-#define BCR_MBKEN_RESET ((gU32)0x000FFFFE)
-#define BCR_FACCEN_SET ((gU32)0x00000040)
-
-/* FMC PCRx Mask */
-#define PCR_PBKEN_SET ((gU32)0x00000004)
-#define PCR_PBKEN_RESET ((gU32)0x000FFFFB)
-#define PCR_ECCEN_SET ((gU32)0x00000040)
-#define PCR_ECCEN_RESET ((gU32)0x000FFFBF)
-#define PCR_MEMORYTYPE_NAND ((gU32)0x00000008)
-
-/* FMC SDCRx write protection Mask*/
-#define SDCR_WriteProtection_RESET ((gU32)0x00007DFF)
-
-/* FMC SDCMR Mask*/
-#define SDCMR_CTB1_RESET ((gU32)0x003FFFEF)
-#define SDCMR_CTB2_RESET ((gU32)0x003FFFF7)
-#define SDCMR_CTB1_2_RESET ((gU32)0x003FFFE7)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup FMC_Private_Functions
- * @{
- */
-
-/** @defgroup FMC_Group1 NOR/SRAM Controller functions
- * @brief NOR/SRAM Controller functions
- *
-@verbatim
- ===============================================================================
- ##### NOR and SRAM Controller functions #####
- ===============================================================================
-
- [..] The following sequence should be followed to configure the FMC to interface
- with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank:
-
- (#) Enable the clock for the FMC and associated GPIOs using the following functions:
- RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
-
- (#) FMC pins configuration
- (++) Connect the involved FMC pins to AF12 using the following function
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC);
- (++) Configure these FMC pins in alternate function mode by calling the function
- GPIO_Init();
-
- (#) Declare a FMC_NORSRAMInitTypeDef structure, for example:
- FMC_NORSRAMInitTypeDef FMC_NORSRAMInitStructure;
- and fill the FMC_NORSRAMInitStructure variable with the allowed values of
- the structure member.
-
- (#) Initialize the NOR/SRAM Controller by calling the function
- FMC_NORSRAMInit(&FMC_NORSRAMInitStructure);
-
- (#) Then enable the NOR/SRAM Bank, for example:
- FMC_NORSRAMCmd(FMC_Bank1_NORSRAM2, ENABLE);
-
- (#) At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initializes the FMC NOR/SRAM Banks registers to their default
- * reset values.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank1_NORSRAM1: FMC Bank1 NOR/SRAM1
- * @arg FMC_Bank1_NORSRAM2: FMC Bank1 NOR/SRAM2
- * @arg FMC_Bank1_NORSRAM3: FMC Bank1 NOR/SRAM3
- * @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4
- * @retval None
- */
-void FMC_NORSRAMDeInit(gU32 FMC_Bank)
-{
- /* Check the parameter */
- assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank));
-
- /* FMC_Bank1_NORSRAM1 */
- if(FMC_Bank == FMC_Bank1_NORSRAM1)
- {
- FMC_Bank1->BTCR[FMC_Bank] = 0x000030DB;
- }
- /* FMC_Bank1_NORSRAM2, FMC_Bank1_NORSRAM3 or FMC_Bank1_NORSRAM4 */
- else
- {
- FMC_Bank1->BTCR[FMC_Bank] = 0x000030D2;
- }
- FMC_Bank1->BTCR[FMC_Bank + 1] = 0x0FFFFFFF;
- FMC_Bank1E->BWTR[FMC_Bank] = 0x0FFFFFFF;
-}
-
-/**
- * @brief Initializes the FMC NOR/SRAM Banks according to the specified
- * parameters in the FMC_NORSRAMInitStruct.
- * @param FMC_NORSRAMInitStruct : pointer to a FMC_NORSRAMInitTypeDef structure
- * that contains the configuration information for the FMC NOR/SRAM
- * specified Banks.
- * @retval None
- */
-void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
-{
- gU32 tmpr = 0;
-
- /* Check the parameters */
- assert_param(IS_FMC_NORSRAM_BANK(FMC_NORSRAMInitStruct->FMC_Bank));
- assert_param(IS_FMC_MUX(FMC_NORSRAMInitStruct->FMC_DataAddressMux));
- assert_param(IS_FMC_MEMORY(FMC_NORSRAMInitStruct->FMC_MemoryType));
- assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(FMC_NORSRAMInitStruct->FMC_MemoryDataWidth));
- assert_param(IS_FMC_BURSTMODE(FMC_NORSRAMInitStruct->FMC_BurstAccessMode));
- assert_param(IS_FMC_WAIT_POLARITY(FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity));
- assert_param(IS_FMC_WRAP_MODE(FMC_NORSRAMInitStruct->FMC_WrapMode));
- assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(FMC_NORSRAMInitStruct->FMC_WaitSignalActive));
- assert_param(IS_FMC_WRITE_OPERATION(FMC_NORSRAMInitStruct->FMC_WriteOperation));
- assert_param(IS_FMC_WAITE_SIGNAL(FMC_NORSRAMInitStruct->FMC_WaitSignal));
- assert_param(IS_FMC_EXTENDED_MODE(FMC_NORSRAMInitStruct->FMC_ExtendedMode));
- assert_param(IS_FMC_ASYNWAIT(FMC_NORSRAMInitStruct->FMC_AsynchronousWait));
- assert_param(IS_FMC_WRITE_BURST(FMC_NORSRAMInitStruct->FMC_WriteBurst));
- assert_param(IS_FMC_CONTINOUS_CLOCK(FMC_NORSRAMInitStruct->FMC_ContinousClock));
- assert_param(IS_FMC_ADDRESS_SETUP_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime));
- assert_param(IS_FMC_ADDRESS_HOLD_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime));
- assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime));
- assert_param(IS_FMC_TURNAROUND_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration));
- assert_param(IS_FMC_CLK_DIV(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision));
- assert_param(IS_FMC_DATA_LATENCY(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency));
- assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode));
-
- /* NOR/SRAM Bank control register configuration */
- FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] =
- (gU32)FMC_NORSRAMInitStruct->FMC_DataAddressMux |
- FMC_NORSRAMInitStruct->FMC_MemoryType |
- FMC_NORSRAMInitStruct->FMC_MemoryDataWidth |
- FMC_NORSRAMInitStruct->FMC_BurstAccessMode |
- FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity |
- FMC_NORSRAMInitStruct->FMC_WrapMode |
- FMC_NORSRAMInitStruct->FMC_WaitSignalActive |
- FMC_NORSRAMInitStruct->FMC_WriteOperation |
- FMC_NORSRAMInitStruct->FMC_WaitSignal |
- FMC_NORSRAMInitStruct->FMC_ExtendedMode |
- FMC_NORSRAMInitStruct->FMC_AsynchronousWait |
- FMC_NORSRAMInitStruct->FMC_WriteBurst |
- FMC_NORSRAMInitStruct->FMC_ContinousClock;
-
-
- if(FMC_NORSRAMInitStruct->FMC_MemoryType == FMC_MemoryType_NOR)
- {
- FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] |= (gU32)BCR_FACCEN_SET;
- }
-
- /* Configure Continuous clock feature when bank2..4 is used */
- if((FMC_NORSRAMInitStruct->FMC_ContinousClock == FMC_CClock_SyncAsync) && (FMC_NORSRAMInitStruct->FMC_Bank != FMC_Bank1_NORSRAM1))
- {
- tmpr = (gU32)((FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1]) & ~(((gU32)0x0F) << 20));
-
- FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1] |= FMC_NORSRAMInitStruct->FMC_ContinousClock;
- FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1] |= FMC_BurstAccessMode_Enable;
- FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1] = (gU32)(tmpr | (((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision)-1) << 20));
- }
-
- /* NOR/SRAM Bank timing register configuration */
- FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank+1] =
- (gU32)FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime |
- (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime << 4) |
- (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime << 8) |
- (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration << 16) |
- ((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision) << 20) |
- ((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency) << 24) |
- FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode;
-
- /* NOR/SRAM Bank timing register for write configuration, if extended mode is used */
- if(FMC_NORSRAMInitStruct->FMC_ExtendedMode == FMC_ExtendedMode_Enable)
- {
- assert_param(IS_FMC_ADDRESS_SETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime));
- assert_param(IS_FMC_ADDRESS_HOLD_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime));
- assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime));
- assert_param(IS_FMC_CLK_DIV(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision));
- assert_param(IS_FMC_DATA_LATENCY(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency));
- assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode));
-
- FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] =
- (gU32)FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime |
- (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime << 4 )|
- (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime << 8) |
- ((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision) << 20) |
- ((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency) << 24) |
- FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode;
- }
- else
- {
- FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] = 0x0FFFFFFF;
- }
-
-}
-
-/**
- * @brief Fills each FMC_NORSRAMInitStruct member with its default value.
- * @param FMC_NORSRAMInitStruct: pointer to a FMC_NORSRAMInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
-{
- /* Reset NOR/SRAM Init structure parameters values */
- FMC_NORSRAMInitStruct->FMC_Bank = FMC_Bank1_NORSRAM1;
- FMC_NORSRAMInitStruct->FMC_DataAddressMux = FMC_DataAddressMux_Enable;
- FMC_NORSRAMInitStruct->FMC_MemoryType = FMC_MemoryType_SRAM;
- FMC_NORSRAMInitStruct->FMC_MemoryDataWidth = FMC_NORSRAM_MemoryDataWidth_16b;
- FMC_NORSRAMInitStruct->FMC_BurstAccessMode = FMC_BurstAccessMode_Disable;
- FMC_NORSRAMInitStruct->FMC_AsynchronousWait = FMC_AsynchronousWait_Disable;
- FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low;
- FMC_NORSRAMInitStruct->FMC_WrapMode = FMC_WrapMode_Disable;
- FMC_NORSRAMInitStruct->FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState;
- FMC_NORSRAMInitStruct->FMC_WriteOperation = FMC_WriteOperation_Enable;
- FMC_NORSRAMInitStruct->FMC_WaitSignal = FMC_WaitSignal_Enable;
- FMC_NORSRAMInitStruct->FMC_ExtendedMode = FMC_ExtendedMode_Disable;
- FMC_NORSRAMInitStruct->FMC_WriteBurst = FMC_WriteBurst_Disable;
- FMC_NORSRAMInitStruct->FMC_ContinousClock = FMC_CClock_SyncOnly;
-
- FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime = 15;
- FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime = 15;
- FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime = 255;
- FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration = 15;
- FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision = 15;
- FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency = 15;
- FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode = FMC_AccessMode_A;
- FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime = 15;
- FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime = 15;
- FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime = 255;
- FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_BusTurnAroundDuration = 15;
- FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision = 15;
- FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency = 15;
- FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode = FMC_AccessMode_A;
-}
-
-/**
- * @brief Enables or disables the specified NOR/SRAM Memory Bank.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank1_NORSRAM1: FMC Bank1 NOR/SRAM1
- * @arg FMC_Bank1_NORSRAM2: FMC Bank1 NOR/SRAM2
- * @arg FMC_Bank1_NORSRAM3: FMC Bank1 NOR/SRAM3
- * @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4
- * @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMC_NORSRAMCmd(gU32 FMC_Bank, FunctionalState NewState)
-{
- assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
- FMC_Bank1->BTCR[FMC_Bank] |= BCR_MBKEN_SET;
- }
- else
- {
- /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
- FMC_Bank1->BTCR[FMC_Bank] &= BCR_MBKEN_RESET;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup FMC_Group2 NAND Controller functions
- * @brief NAND Controller functions
- *
-@verbatim
- ===============================================================================
- ##### NAND Controller functions #####
- ===============================================================================
-
- [..] The following sequence should be followed to configure the FMC to interface
- with 8-bit or 16-bit NAND memory connected to the NAND Bank:
-
- (#) Enable the clock for the FMC and associated GPIOs using the following functions:
- (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);
- (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
-
- (#) FMC pins configuration
- (++) Connect the involved FMC pins to AF12 using the following function
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC);
- (++) Configure these FMC pins in alternate function mode by calling the function
- GPIO_Init();
-
- (#) Declare a FMC_NANDInitTypeDef structure, for example:
- FMC_NANDInitTypeDef FMC_NANDInitStructure;
- and fill the FMC_NANDInitStructure variable with the allowed values of
- the structure member.
-
- (#) Initialize the NAND Controller by calling the function
- FMC_NANDInit(&FMC_NANDInitStructure);
-
- (#) Then enable the NAND Bank, for example:
- FMC_NANDCmd(FMC_Bank3_NAND, ENABLE);
-
- (#) At this stage you can read/write from/to the memory connected to the NAND Bank.
-
- [..]
- (@) To enable the Error Correction Code (ECC), you have to use the function
- FMC_NANDECCCmd(FMC_Bank3_NAND, ENABLE);
- [..]
- (@) and to get the current ECC value you have to use the function
- ECCval = FMC_GetECC(FMC_Bank3_NAND);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initializes the FMC NAND Banks registers to their default reset values.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank2_NAND: FMC Bank2 NAND
- * @arg FMC_Bank3_NAND: FMC Bank3 NAND
- * @retval None
- */
-void FMC_NANDDeInit(gU32 FMC_Bank)
-{
- /* Check the parameter */
- assert_param(IS_FMC_NAND_BANK(FMC_Bank));
-
- if(FMC_Bank == FMC_Bank2_NAND)
- {
- /* Set the FMC_Bank2 registers to their reset values */
- FMC_Bank2->PCR2 = 0x00000018;
- FMC_Bank2->SR2 = 0x00000040;
- FMC_Bank2->PMEM2 = 0xFCFCFCFC;
- FMC_Bank2->PATT2 = 0xFCFCFCFC;
- }
- /* FMC_Bank3_NAND */
- else
- {
- /* Set the FMC_Bank3 registers to their reset values */
- FMC_Bank3->PCR3 = 0x00000018;
- FMC_Bank3->SR3 = 0x00000040;
- FMC_Bank3->PMEM3 = 0xFCFCFCFC;
- FMC_Bank3->PATT3 = 0xFCFCFCFC;
- }
-}
-
-/**
- * @brief Initializes the FMC NAND Banks according to the specified parameters
- * in the FMC_NANDInitStruct.
- * @param FMC_NANDInitStruct : pointer to a FMC_NANDInitTypeDef structure that
- * contains the configuration information for the FMC NAND specified Banks.
- * @retval None
- */
-void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct)
-{
- gU32 tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
-
- /* Check the parameters */
- assert_param(IS_FMC_NAND_BANK(FMC_NANDInitStruct->FMC_Bank));
- assert_param(IS_FMC_WAIT_FEATURE(FMC_NANDInitStruct->FMC_Waitfeature));
- assert_param(IS_FMC_NAND_MEMORY_WIDTH(FMC_NANDInitStruct->FMC_MemoryDataWidth));
- assert_param(IS_FMC_ECC_STATE(FMC_NANDInitStruct->FMC_ECC));
- assert_param(IS_FMC_ECCPAGE_SIZE(FMC_NANDInitStruct->FMC_ECCPageSize));
- assert_param(IS_FMC_TCLR_TIME(FMC_NANDInitStruct->FMC_TCLRSetupTime));
- assert_param(IS_FMC_TAR_TIME(FMC_NANDInitStruct->FMC_TARSetupTime));
- assert_param(IS_FMC_SETUP_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime));
- assert_param(IS_FMC_WAIT_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime));
- assert_param(IS_FMC_HOLD_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime));
- assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime));
- assert_param(IS_FMC_SETUP_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime));
- assert_param(IS_FMC_WAIT_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime));
- assert_param(IS_FMC_HOLD_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime));
- assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime));
-
- /* Set the tmppcr value according to FMC_NANDInitStruct parameters */
- tmppcr = (gU32)FMC_NANDInitStruct->FMC_Waitfeature |
- PCR_MEMORYTYPE_NAND |
- FMC_NANDInitStruct->FMC_MemoryDataWidth |
- FMC_NANDInitStruct->FMC_ECC |
- FMC_NANDInitStruct->FMC_ECCPageSize |
- (FMC_NANDInitStruct->FMC_TCLRSetupTime << 9 )|
- (FMC_NANDInitStruct->FMC_TARSetupTime << 13);
-
- /* Set tmppmem value according to FMC_CommonSpaceTimingStructure parameters */
- tmppmem = (gU32)FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime |
- (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) |
- (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)|
- (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24);
-
- /* Set tmppatt value according to FMC_AttributeSpaceTimingStructure parameters */
- tmppatt = (gU32)FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime |
- (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) |
- (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)|
- (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24);
-
- if(FMC_NANDInitStruct->FMC_Bank == FMC_Bank2_NAND)
- {
- /* FMC_Bank2_NAND registers configuration */
- FMC_Bank2->PCR2 = tmppcr;
- FMC_Bank2->PMEM2 = tmppmem;
- FMC_Bank2->PATT2 = tmppatt;
- }
- else
- {
- /* FMC_Bank3_NAND registers configuration */
- FMC_Bank3->PCR3 = tmppcr;
- FMC_Bank3->PMEM3 = tmppmem;
- FMC_Bank3->PATT3 = tmppatt;
- }
-}
-
-
-/**
- * @brief Fills each FMC_NANDInitStruct member with its default value.
- * @param FMC_NANDInitStruct: pointer to a FMC_NANDInitTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct)
-{
- /* Reset NAND Init structure parameters values */
- FMC_NANDInitStruct->FMC_Bank = FMC_Bank2_NAND;
- FMC_NANDInitStruct->FMC_Waitfeature = FMC_Waitfeature_Disable;
- FMC_NANDInitStruct->FMC_MemoryDataWidth = FMC_NAND_MemoryDataWidth_16b;
- FMC_NANDInitStruct->FMC_ECC = FMC_ECC_Disable;
- FMC_NANDInitStruct->FMC_ECCPageSize = FMC_ECCPageSize_256Bytes;
- FMC_NANDInitStruct->FMC_TCLRSetupTime = 0x0;
- FMC_NANDInitStruct->FMC_TARSetupTime = 0x0;
- FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime = 252;
- FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime = 252;
- FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime = 252;
- FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime = 252;
- FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime = 252;
- FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime = 252;
- FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime = 252;
- FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime = 252;
-}
-
-/**
- * @brief Enables or disables the specified NAND Memory Bank.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank2_NAND: FMC Bank2 NAND
- * @arg FMC_Bank3_NAND: FMC Bank3 NAND
- * @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMC_NANDCmd(gU32 FMC_Bank, FunctionalState NewState)
-{
- assert_param(IS_FMC_NAND_BANK(FMC_Bank));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
- if(FMC_Bank == FMC_Bank2_NAND)
- {
- FMC_Bank2->PCR2 |= PCR_PBKEN_SET;
- }
- else
- {
- FMC_Bank3->PCR3 |= PCR_PBKEN_SET;
- }
- }
- else
- {
- /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
- if(FMC_Bank == FMC_Bank2_NAND)
- {
- FMC_Bank2->PCR2 &= PCR_PBKEN_RESET;
- }
- else
- {
- FMC_Bank3->PCR3 &= PCR_PBKEN_RESET;
- }
- }
-}
-/**
- * @brief Enables or disables the FMC NAND ECC feature.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank2_NAND: FMC Bank2 NAND
- * @arg FMC_Bank3_NAND: FMC Bank3 NAND
- * @param NewState: new state of the FMC NAND ECC feature.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMC_NANDECCCmd(gU32 FMC_Bank, FunctionalState NewState)
-{
- assert_param(IS_FMC_NAND_BANK(FMC_Bank));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
- if(FMC_Bank == FMC_Bank2_NAND)
- {
- FMC_Bank2->PCR2 |= PCR_ECCEN_SET;
- }
- else
- {
- FMC_Bank3->PCR3 |= PCR_ECCEN_SET;
- }
- }
- else
- {
- /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
- if(FMC_Bank == FMC_Bank2_NAND)
- {
- FMC_Bank2->PCR2 &= PCR_ECCEN_RESET;
- }
- else
- {
- FMC_Bank3->PCR3 &= PCR_ECCEN_RESET;
- }
- }
-}
-
-/**
- * @brief Returns the error correction code register value.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank2_NAND: FMC Bank2 NAND
- * @arg FMC_Bank3_NAND: FMC Bank3 NAND
- * @retval The Error Correction Code (ECC) value.
- */
-gU32 FMC_GetECC(gU32 FMC_Bank)
-{
- gU32 eccval = 0x00000000;
-
- if(FMC_Bank == FMC_Bank2_NAND)
- {
- /* Get the ECCR2 register value */
- eccval = FMC_Bank2->ECCR2;
- }
- else
- {
- /* Get the ECCR3 register value */
- eccval = FMC_Bank3->ECCR3;
- }
- /* Return the error correction code value */
- return(eccval);
-}
-/**
- * @}
- */
-
-/** @defgroup FMC_Group3 PCCARD Controller functions
- * @brief PCCARD Controller functions
- *
-@verbatim
- ===============================================================================
- ##### PCCARD Controller functions #####
- ===============================================================================
-
- [..] he following sequence should be followed to configure the FMC to interface
- with 16-bit PC Card compatible memory connected to the PCCARD Bank:
-
- (#) Enable the clock for the FMC and associated GPIOs using the following functions:
- (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);
- (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
-
- (#) FMC pins configuration
- (++) Connect the involved FMC pins to AF12 using the following function
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC);
- (++) Configure these FMC pins in alternate function mode by calling the function
- GPIO_Init();
-
- (#) Declare a FMC_PCCARDInitTypeDef structure, for example:
- FMC_PCCARDInitTypeDef FMC_PCCARDInitStructure;
- and fill the FMC_PCCARDInitStructure variable with the allowed values of
- the structure member.
-
- (#) Initialize the PCCARD Controller by calling the function
- FMC_PCCARDInit(&FMC_PCCARDInitStructure);
-
- (#) Then enable the PCCARD Bank:
- FMC_PCCARDCmd(ENABLE);
-
- (#) At this stage you can read/write from/to the memory connected to the PCCARD Bank.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initializes the FMC PCCARD Bank registers to their default reset values.
- * @param None
- * @retval None
- */
-void FMC_PCCARDDeInit(void)
-{
- /* Set the FMC_Bank4 registers to their reset values */
- FMC_Bank4->PCR4 = 0x00000018;
- FMC_Bank4->SR4 = 0x00000000;
- FMC_Bank4->PMEM4 = 0xFCFCFCFC;
- FMC_Bank4->PATT4 = 0xFCFCFCFC;
- FMC_Bank4->PIO4 = 0xFCFCFCFC;
-}
-
-/**
- * @brief Initializes the FMC PCCARD Bank according to the specified parameters
- * in the FMC_PCCARDInitStruct.
- * @param FMC_PCCARDInitStruct : pointer to a FMC_PCCARDInitTypeDef structure
- * that contains the configuration information for the FMC PCCARD Bank.
- * @retval None
- */
-void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_FMC_WAIT_FEATURE(FMC_PCCARDInitStruct->FMC_Waitfeature));
- assert_param(IS_FMC_TCLR_TIME(FMC_PCCARDInitStruct->FMC_TCLRSetupTime));
- assert_param(IS_FMC_TAR_TIME(FMC_PCCARDInitStruct->FMC_TARSetupTime));
-
- assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime));
- assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime));
- assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime));
- assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime));
-
- assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime));
- assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime));
- assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime));
- assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime));
- assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime));
- assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime));
- assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime));
- assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime));
-
- /* Set the PCR4 register value according to FMC_PCCARDInitStruct parameters */
- FMC_Bank4->PCR4 = (gU32)FMC_PCCARDInitStruct->FMC_Waitfeature |
- FMC_NAND_MemoryDataWidth_16b |
- (FMC_PCCARDInitStruct->FMC_TCLRSetupTime << 9) |
- (FMC_PCCARDInitStruct->FMC_TARSetupTime << 13);
-
- /* Set PMEM4 register value according to FMC_CommonSpaceTimingStructure parameters */
- FMC_Bank4->PMEM4 = (gU32)FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime |
- (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) |
- (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)|
- (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24);
-
- /* Set PATT4 register value according to FMC_AttributeSpaceTimingStructure parameters */
- FMC_Bank4->PATT4 = (gU32)FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime |
- (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) |
- (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)|
- (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24);
-
- /* Set PIO4 register value according to FMC_IOSpaceTimingStructure parameters */
- FMC_Bank4->PIO4 = (gU32)FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime |
- (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime << 8) |
- (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime << 16)|
- (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime << 24);
-}
-
-/**
- * @brief Fills each FMC_PCCARDInitStruct member with its default value.
- * @param FMC_PCCARDInitStruct: pointer to a FMC_PCCARDInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct)
-{
- /* Reset PCCARD Init structure parameters values */
- FMC_PCCARDInitStruct->FMC_Waitfeature = FMC_Waitfeature_Disable;
- FMC_PCCARDInitStruct->FMC_TCLRSetupTime = 0;
- FMC_PCCARDInitStruct->FMC_TARSetupTime = 0;
- FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime = 252;
- FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime = 252;
- FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime = 252;
- FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime = 252;
- FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime = 252;
- FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime = 252;
- FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime = 252;
- FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime = 252;
- FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime = 252;
- FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime = 252;
- FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime = 252;
- FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime = 252;
-}
-
-/**
- * @brief Enables or disables the PCCARD Memory Bank.
- * @param NewState: new state of the PCCARD Memory Bank.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMC_PCCARDCmd(FunctionalState NewState)
-{
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
- FMC_Bank4->PCR4 |= PCR_PBKEN_SET;
- }
- else
- {
- /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
- FMC_Bank4->PCR4 &= PCR_PBKEN_RESET;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Group4 SDRAM Controller functions
- * @brief SDRAM Controller functions
- *
-@verbatim
- ===============================================================================
- ##### SDRAM Controller functions #####
- ===============================================================================
-
- [..] The following sequence should be followed to configure the FMC to interface
- with SDRAM memory connected to the SDRAM Bank 1 or SDRAM bank 2:
-
- (#) Enable the clock for the FMC and associated GPIOs using the following functions:
- (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);
- (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
-
- (#) FMC pins configuration
- (++) Connect the involved FMC pins to AF12 using the following function
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC);
- (++) Configure these FMC pins in alternate function mode by calling the function
- GPIO_Init();
-
- (#) Declare a FMC_SDRAMInitTypeDef structure, for example:
- FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure;
- and fill the FMC_SDRAMInitStructure variable with the allowed values of
- the structure member.
-
- (#) Initialize the SDRAM Controller by calling the function
- FMC_SDRAMInit(&FMC_SDRAMInitStructure);
-
- (#) Declare a FMC_SDRAMCommandTypeDef structure, for example:
- FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
- and fill the FMC_SDRAMCommandStructure variable with the allowed values of
- the structure member.
-
- (#) Configure the SDCMR register with the desired command parameters by calling
- the function FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
-
- (#) At this stage, the SDRAM memory is ready for any valid command.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initializes the FMC SDRAM Banks registers to their default
- * reset values.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
- * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
- * @retval None
- */
-void FMC_SDRAMDeInit(gU32 FMC_Bank)
-{
- /* Check the parameter */
- assert_param(IS_FMC_SDRAM_BANK(FMC_Bank));
-
- FMC_Bank5_6->SDCR[FMC_Bank] = 0x000002D0;
- FMC_Bank5_6->SDTR[FMC_Bank] = 0x0FFFFFFF;
- FMC_Bank5_6->SDCMR = 0x00000000;
- FMC_Bank5_6->SDRTR = 0x00000000;
- FMC_Bank5_6->SDSR = 0x00000000;
-}
-
-/**
- * @brief Initializes the FMC SDRAM Banks according to the specified
- * parameters in the FMC_SDRAMInitStruct.
- * @param FMC_SDRAMInitStruct : pointer to a FMC_SDRAMInitTypeDef structure
- * that contains the configuration information for the FMC SDRAM
- * specified Banks.
- * @retval None
- */
-void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
-{
- /* temporary registers */
- gU32 tmpr1 = 0;
- gU32 tmpr2 = 0;
- gU32 tmpr3 = 0;
- gU32 tmpr4 = 0;
-
- /* Check the parameters */
-
- /* Control parameters */
- assert_param(IS_FMC_SDRAM_BANK(FMC_SDRAMInitStruct->FMC_Bank));
- assert_param(IS_FMC_COLUMNBITS_NUMBER(FMC_SDRAMInitStruct->FMC_ColumnBitsNumber));
- assert_param(IS_FMC_ROWBITS_NUMBER(FMC_SDRAMInitStruct->FMC_RowBitsNumber));
- assert_param(IS_FMC_SDMEMORY_WIDTH(FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth));
- assert_param(IS_FMC_INTERNALBANK_NUMBER(FMC_SDRAMInitStruct->FMC_InternalBankNumber));
- assert_param(IS_FMC_CAS_LATENCY(FMC_SDRAMInitStruct->FMC_CASLatency));
- assert_param(IS_FMC_WRITE_PROTECTION(FMC_SDRAMInitStruct->FMC_WriteProtection));
- assert_param(IS_FMC_SDCLOCK_PERIOD(FMC_SDRAMInitStruct->FMC_SDClockPeriod));
- assert_param(IS_FMC_READ_BURST(FMC_SDRAMInitStruct->FMC_ReadBurst));
- assert_param(IS_FMC_READPIPE_DELAY(FMC_SDRAMInitStruct->FMC_ReadPipeDelay));
-
- /* Timing parameters */
- assert_param(IS_FMC_LOADTOACTIVE_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay));
- assert_param(IS_FMC_EXITSELFREFRESH_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay));
- assert_param(IS_FMC_SELFREFRESH_TIME(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime));
- assert_param(IS_FMC_ROWCYCLE_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay));
- assert_param(IS_FMC_WRITE_RECOVERY_TIME(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime));
- assert_param(IS_FMC_RP_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay));
- assert_param(IS_FMC_RCD_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay));
-
- /* SDRAM bank control register configuration */
- tmpr1 = (gU32)FMC_SDRAMInitStruct->FMC_ColumnBitsNumber |
- FMC_SDRAMInitStruct->FMC_RowBitsNumber |
- FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth |
- FMC_SDRAMInitStruct->FMC_InternalBankNumber |
- FMC_SDRAMInitStruct->FMC_CASLatency |
- FMC_SDRAMInitStruct->FMC_WriteProtection |
- FMC_SDRAMInitStruct->FMC_SDClockPeriod |
- FMC_SDRAMInitStruct->FMC_ReadBurst |
- FMC_SDRAMInitStruct->FMC_ReadPipeDelay;
-
- if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM )
- {
- FMC_Bank5_6->SDCR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr1;
- }
- else /* SDCR2 "don't care" bits configuration */
- {
- tmpr3 = (gU32)FMC_SDRAMInitStruct->FMC_SDClockPeriod |
- FMC_SDRAMInitStruct->FMC_ReadBurst |
- FMC_SDRAMInitStruct->FMC_ReadPipeDelay;
-
- FMC_Bank5_6->SDCR[FMC_Bank1_SDRAM] = tmpr3;
- FMC_Bank5_6->SDCR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr1;
- }
- /* SDRAM bank timing register configuration */
- if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM )
- {
- tmpr2 = (gU32)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay)-1) << 24);
-
- FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2;
- }
- else /* SDTR "don't care bits configuration */
- {
- tmpr2 = (gU32)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16);
-
- tmpr4 = (gU32)(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20);
-
- FMC_Bank5_6->SDTR[FMC_Bank1_SDRAM] = tmpr4;
- FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2;
- }
-
-}
-
-/**
- * @brief Fills each FMC_SDRAMInitStruct member with its default value.
- * @param FMC_SDRAMInitStruct: pointer to a FMC_SDRAMInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void FMC_SDRAMStructInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
-{
- /* Reset SDRAM Init structure parameters values */
- FMC_SDRAMInitStruct->FMC_Bank = FMC_Bank1_SDRAM;
- FMC_SDRAMInitStruct->FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
- FMC_SDRAMInitStruct->FMC_RowBitsNumber = FMC_RowBits_Number_11b;
- FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b;
- FMC_SDRAMInitStruct->FMC_InternalBankNumber = FMC_InternalBank_Number_4;
- FMC_SDRAMInitStruct->FMC_CASLatency = FMC_CAS_Latency_1;
- FMC_SDRAMInitStruct->FMC_WriteProtection = FMC_Write_Protection_Enable;
- FMC_SDRAMInitStruct->FMC_SDClockPeriod = FMC_SDClock_Disable;
- FMC_SDRAMInitStruct->FMC_ReadBurst = FMC_Read_Burst_Disable;
- FMC_SDRAMInitStruct->FMC_ReadPipeDelay = FMC_ReadPipe_Delay_0;
-
- FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay = 16;
- FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay = 16;
- FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime = 16;
- FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay = 16;
- FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime = 16;
- FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay = 16;
- FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay = 16;
-
-}
-
-/**
- * @brief Configures the SDRAM memory command issued when the device is accessed.
- * @param FMC_SDRAMCommandStruct: pointer to a FMC_SDRAMCommandTypeDef structure
- * which will be configured.
- * @retval None
- */
-void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct)
-{
- gU32 tmpr = 0x0;
-
- /* check parameters */
- assert_param(IS_FMC_COMMAND_MODE(FMC_SDRAMCommandStruct->FMC_CommandMode));
- assert_param(IS_FMC_COMMAND_TARGET(FMC_SDRAMCommandStruct->FMC_CommandTarget));
- assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber));
- assert_param(IS_FMC_MODE_REGISTER(FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition));
-
- tmpr = (gU32)(FMC_SDRAMCommandStruct->FMC_CommandMode |
- FMC_SDRAMCommandStruct->FMC_CommandTarget |
- (((FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber)-1)<<5) |
- ((FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition)<<9));
-
- FMC_Bank5_6->SDCMR = tmpr;
-
-}
-
-
-/**
- * @brief Returns the indicated FMC SDRAM bank mode status.
- * @param SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be
- * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
- * @retval The FMC SDRAM bank mode status
- */
-gU32 FMC_GetModeStatus(gU32 SDRAM_Bank)
-{
- gU32 tmpreg = 0;
-
- /* Check the parameter */
- assert_param(IS_FMC_SDRAM_BANK(SDRAM_Bank));
-
- /* Get the busy flag status */
- if(SDRAM_Bank == FMC_Bank1_SDRAM)
- {
- tmpreg = (gU32)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES1);
- }
- else
- {
- tmpreg = ((gU32)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES2) >> 2);
- }
-
- /* Return the mode status */
- return tmpreg;
-}
-
-/**
- * @brief defines the SDRAM Memory Refresh rate.
- * @param FMC_Count: specifies the Refresh timer count.
- * @retval None
- */
-void FMC_SetRefreshCount(gU32 FMC_Count)
-{
- /* check the parameters */
- assert_param(IS_FMC_REFRESH_COUNT(FMC_Count));
-
- FMC_Bank5_6->SDRTR |= (FMC_Count<<1);
-
-}
-
-/**
- * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
- * @param FMC_Number: specifies the auto Refresh number.
- * @retval None
- */
-void FMC_SetAutoRefresh_Number(gU32 FMC_Number)
-{
- /* check the parameters */
- assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_Number));
-
- FMC_Bank5_6->SDCMR |= (FMC_Number << 5);
-}
-
-/**
- * @brief Enables or disables write protection to the specified FMC SDRAM Bank.
- * @param SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be
- * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
- * @param NewState: new state of the write protection flag.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMC_SDRAMWriteProtectionConfig(gU32 SDRAM_Bank, FunctionalState NewState)
-{
- /* Check the parameter */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_FMC_SDRAM_BANK(SDRAM_Bank));
-
- if (NewState != DISABLE)
- {
- FMC_Bank5_6->SDCR[SDRAM_Bank] |= FMC_Write_Protection_Enable;
- }
- else
- {
- FMC_Bank5_6->SDCR[SDRAM_Bank] &= SDCR_WriteProtection_RESET;
- }
-
-}
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Group5 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified FMC interrupts.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank2_NAND: FMC Bank2 NAND
- * @arg FMC_Bank3_NAND: FMC Bank3 NAND
- * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
- * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
- * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
- * @param FMC_IT: specifies the FMC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg FMC_IT_RisingEdge: Rising edge detection interrupt.
- * @arg FMC_IT_Level: Level edge detection interrupt.
- * @arg FMC_IT_FallingEdge: Falling edge detection interrupt.
- * @arg FMC_IT_Refresh: Refresh error detection interrupt.
- * @param NewState: new state of the specified FMC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMC_ITConfig(gU32 FMC_Bank, gU32 FMC_IT, FunctionalState NewState)
-{
- assert_param(IS_FMC_IT_BANK(FMC_Bank));
- assert_param(IS_FMC_IT(FMC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected FMC_Bank2 interrupts */
- if(FMC_Bank == FMC_Bank2_NAND)
- {
- FMC_Bank2->SR2 |= FMC_IT;
- }
- /* Enable the selected FMC_Bank3 interrupts */
- else if (FMC_Bank == FMC_Bank3_NAND)
- {
- FMC_Bank3->SR3 |= FMC_IT;
- }
- /* Enable the selected FMC_Bank4 interrupts */
- else if (FMC_Bank == FMC_Bank4_PCCARD)
- {
- FMC_Bank4->SR4 |= FMC_IT;
- }
- /* Enable the selected FMC_Bank5_6 interrupt */
- else
- {
- /* Enables the interrupt if the refresh error flag is set */
- FMC_Bank5_6->SDRTR |= FMC_IT;
- }
- }
- else
- {
- /* Disable the selected FMC_Bank2 interrupts */
- if(FMC_Bank == FMC_Bank2_NAND)
- {
-
- FMC_Bank2->SR2 &= (gU32)~FMC_IT;
- }
- /* Disable the selected FMC_Bank3 interrupts */
- else if (FMC_Bank == FMC_Bank3_NAND)
- {
- FMC_Bank3->SR3 &= (gU32)~FMC_IT;
- }
- /* Disable the selected FMC_Bank4 interrupts */
- else if(FMC_Bank == FMC_Bank4_PCCARD)
- {
- FMC_Bank4->SR4 &= (gU32)~FMC_IT;
- }
- /* Disable the selected FMC_Bank5_6 interrupt */
- else
- {
- /* Disables the interrupt if the refresh error flag is not set */
- FMC_Bank5_6->SDRTR &= (gU32)~FMC_IT;
- }
- }
-}
-
-/**
- * @brief Checks whether the specified FMC flag is set or not.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank2_NAND: FMC Bank2 NAND
- * @arg FMC_Bank3_NAND: FMC Bank3 NAND
- * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
- * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
- * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
- * @arg FMC_Bank1_SDRAM | FMC_Bank2_SDRAM: FMC Bank1 or Bank2 SDRAM
- * @param FMC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg FMC_FLAG_RisingEdge: Rising edge detection Flag.
- * @arg FMC_FLAG_Level: Level detection Flag.
- * @arg FMC_FLAG_FallingEdge: Falling edge detection Flag.
- * @arg FMC_FLAG_FEMPT: Fifo empty Flag.
- * @arg FMC_FLAG_Refresh: Refresh error Flag.
- * @arg FMC_FLAG_Busy: Busy status Flag.
- * @retval The new state of FMC_FLAG (SET or RESET).
- */
-FlagStatus FMC_GetFlagStatus(gU32 FMC_Bank, gU32 FMC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- gU32 tmpsr = 0x00000000;
-
- /* Check the parameters */
- assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank));
- assert_param(IS_FMC_GET_FLAG(FMC_FLAG));
-
- if(FMC_Bank == FMC_Bank2_NAND)
- {
- tmpsr = FMC_Bank2->SR2;
- }
- else if(FMC_Bank == FMC_Bank3_NAND)
- {
- tmpsr = FMC_Bank3->SR3;
- }
- else if(FMC_Bank == FMC_Bank4_PCCARD)
- {
- tmpsr = FMC_Bank4->SR4;
- }
- else
- {
- tmpsr = FMC_Bank5_6->SDSR;
- }
-
- /* Get the flag status */
- if ((tmpsr & FMC_FLAG) != FMC_FLAG )
- {
- bitstatus = RESET;
- }
- else
- {
- bitstatus = SET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the FMC's pending flags.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank2_NAND: FMC Bank2 NAND
- * @arg FMC_Bank3_NAND: FMC Bank3 NAND
- * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
- * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
- * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
- * @param FMC_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg FMC_FLAG_RisingEdge: Rising edge detection Flag.
- * @arg FMC_FLAG_Level: Level detection Flag.
- * @arg FMC_FLAG_FallingEdge: Falling edge detection Flag.
- * @arg FMC_FLAG_Refresh: Refresh error Flag.
- * @retval None
- */
-void FMC_ClearFlag(gU32 FMC_Bank, gU32 FMC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank));
- assert_param(IS_FMC_CLEAR_FLAG(FMC_FLAG)) ;
-
- if(FMC_Bank == FMC_Bank2_NAND)
- {
- FMC_Bank2->SR2 &= (~FMC_FLAG);
- }
- else if(FMC_Bank == FMC_Bank3_NAND)
- {
- FMC_Bank3->SR3 &= (~FMC_FLAG);
- }
- else if(FMC_Bank == FMC_Bank4_PCCARD)
- {
- FMC_Bank4->SR4 &= (~FMC_FLAG);
- }
- /* FMC_Bank5_6 SDRAM*/
- else
- {
- FMC_Bank5_6->SDRTR &= (~FMC_FLAG);
- }
-
-}
-
-/**
- * @brief Checks whether the specified FMC interrupt has occurred or not.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank2_NAND: FMC Bank2 NAND
- * @arg FMC_Bank3_NAND: FMC Bank3 NAND
- * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
- * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
- * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
- * @param FMC_IT: specifies the FMC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg FMC_IT_RisingEdge: Rising edge detection interrupt.
- * @arg FMC_IT_Level: Level edge detection interrupt.
- * @arg FMC_IT_FallingEdge: Falling edge detection interrupt.
- * @arg FMC_IT_Refresh: Refresh error detection interrupt.
- * @retval The new state of FMC_IT (SET or RESET).
- */
-ITStatus FMC_GetITStatus(gU32 FMC_Bank, gU32 FMC_IT)
-{
- ITStatus bitstatus = RESET;
- gU32 tmpsr = 0x0;
- gU32 tmpsr2 = 0x0;
- gU32 itstatus = 0x0;
- gU32 itenable = 0x0;
-
- /* Check the parameters */
- assert_param(IS_FMC_IT_BANK(FMC_Bank));
- assert_param(IS_FMC_GET_IT(FMC_IT));
-
- if(FMC_Bank == FMC_Bank2_NAND)
- {
- tmpsr = FMC_Bank2->SR2;
- }
- else if(FMC_Bank == FMC_Bank3_NAND)
- {
- tmpsr = FMC_Bank3->SR3;
- }
- else if(FMC_Bank == FMC_Bank4_PCCARD)
- {
- tmpsr = FMC_Bank4->SR4;
- }
- /* FMC_Bank5_6 SDRAM*/
- else
- {
- tmpsr = FMC_Bank5_6->SDRTR;
- tmpsr2 = FMC_Bank5_6->SDSR;
- }
-
- /* get the IT enable bit status*/
- itenable = tmpsr & FMC_IT;
-
- /* get the corresponding IT Flag status*/
- if((FMC_Bank == FMC_Bank1_SDRAM) || (FMC_Bank == FMC_Bank2_SDRAM))
- {
- itstatus = tmpsr2 & FMC_SDSR_RE;
- }
- else
- {
- itstatus = tmpsr & (FMC_IT >> 3);
- }
-
- if ((itstatus != (gU32)RESET) && (itenable != (gU32)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the FMC's interrupt pending bits.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank2_NAND: FMC Bank2 NAND
- * @arg FMC_Bank3_NAND: FMC Bank3 NAND
- * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
- * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
- * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
- * @param FMC_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg FMC_IT_RisingEdge: Rising edge detection interrupt.
- * @arg FMC_IT_Level: Level edge detection interrupt.
- * @arg FMC_IT_FallingEdge: Falling edge detection interrupt.
- * @arg FMC_IT_Refresh: Refresh error detection interrupt.
- * @retval None
- */
-void FMC_ClearITPendingBit(gU32 FMC_Bank, gU32 FMC_IT)
-{
- /* Check the parameters */
- assert_param(IS_FMC_IT_BANK(FMC_Bank));
- assert_param(IS_FMC_IT(FMC_IT));
-
- if(FMC_Bank == FMC_Bank2_NAND)
- {
- FMC_Bank2->SR2 &= ~(FMC_IT >> 3);
- }
- else if(FMC_Bank == FMC_Bank3_NAND)
- {
- FMC_Bank3->SR3 &= ~(FMC_IT >> 3);
- }
- else if(FMC_Bank == FMC_Bank4_PCCARD)
- {
- FMC_Bank4->SR4 &= ~(FMC_IT >> 3);
- }
- /* FMC_Bank5_6 SDRAM*/
- else
- {
- FMC_Bank5_6->SDRTR |= FMC_SDRTR_CRE;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file stm32f4xx_fmc.c
+ * @author MCD Application Team
+ * @version V1.2.1
+ * @date 19-September-2013
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the FMC peripheral:
+ * + Interface with SRAM, PSRAM, NOR and OneNAND memories
+ * + Interface with NAND memories
+ * + Interface with 16-bit PC Card compatible memories
+ * + Interface with SDRAM memories
+ * + Interrupts and flags management
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2013 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "ch.h"
+#include "stm32f4xx_fmc.h"
+//#include "stm32f4xx_rcc.h"
+
+#if CH_KERNEL_MAJOR == 2
+ #define assert_param(expr) chDbgAssert(expr,"STPeriph FMC","")
+#else
+ #define assert_param(expr) chDbgAssert(expr,"STPeriph FMC")
+#endif
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup FMC
+ * @brief FMC driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* --------------------- FMC registers bit mask ---------------------------- */
+/* FMC BCRx Mask */
+#define BCR_MBKEN_SET ((gU32)0x00000001)
+#define BCR_MBKEN_RESET ((gU32)0x000FFFFE)
+#define BCR_FACCEN_SET ((gU32)0x00000040)
+
+/* FMC PCRx Mask */
+#define PCR_PBKEN_SET ((gU32)0x00000004)
+#define PCR_PBKEN_RESET ((gU32)0x000FFFFB)
+#define PCR_ECCEN_SET ((gU32)0x00000040)
+#define PCR_ECCEN_RESET ((gU32)0x000FFFBF)
+#define PCR_MEMORYTYPE_NAND ((gU32)0x00000008)
+
+/* FMC SDCRx write protection Mask*/
+#define SDCR_WriteProtection_RESET ((gU32)0x00007DFF)
+
+/* FMC SDCMR Mask*/
+#define SDCMR_CTB1_RESET ((gU32)0x003FFFEF)
+#define SDCMR_CTB2_RESET ((gU32)0x003FFFF7)
+#define SDCMR_CTB1_2_RESET ((gU32)0x003FFFE7)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup FMC_Private_Functions
+ * @{
+ */
+
+/** @defgroup FMC_Group1 NOR/SRAM Controller functions
+ * @brief NOR/SRAM Controller functions
+ *
+@verbatim
+ ===============================================================================
+ ##### NOR and SRAM Controller functions #####
+ ===============================================================================
+
+ [..] The following sequence should be followed to configure the FMC to interface
+ with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank:
+
+ (#) Enable the clock for the FMC and associated GPIOs using the following functions:
+ RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);
+ RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
+
+ (#) FMC pins configuration
+ (++) Connect the involved FMC pins to AF12 using the following function
+ GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC);
+ (++) Configure these FMC pins in alternate function mode by calling the function
+ GPIO_Init();
+
+ (#) Declare a FMC_NORSRAMInitTypeDef structure, for example:
+ FMC_NORSRAMInitTypeDef FMC_NORSRAMInitStructure;
+ and fill the FMC_NORSRAMInitStructure variable with the allowed values of
+ the structure member.
+
+ (#) Initialize the NOR/SRAM Controller by calling the function
+ FMC_NORSRAMInit(&FMC_NORSRAMInitStructure);
+
+ (#) Then enable the NOR/SRAM Bank, for example:
+ FMC_NORSRAMCmd(FMC_Bank1_NORSRAM2, ENABLE);
+
+ (#) At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief De-initializes the FMC NOR/SRAM Banks registers to their default
+ * reset values.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank1_NORSRAM1: FMC Bank1 NOR/SRAM1
+ * @arg FMC_Bank1_NORSRAM2: FMC Bank1 NOR/SRAM2
+ * @arg FMC_Bank1_NORSRAM3: FMC Bank1 NOR/SRAM3
+ * @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4
+ * @retval None
+ */
+void FMC_NORSRAMDeInit(gU32 FMC_Bank)
+{
+ /* Check the parameter */
+ assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank));
+
+ /* FMC_Bank1_NORSRAM1 */
+ if(FMC_Bank == FMC_Bank1_NORSRAM1)
+ {
+ FMC_Bank1->BTCR[FMC_Bank] = 0x000030DB;
+ }
+ /* FMC_Bank1_NORSRAM2, FMC_Bank1_NORSRAM3 or FMC_Bank1_NORSRAM4 */
+ else
+ {
+ FMC_Bank1->BTCR[FMC_Bank] = 0x000030D2;
+ }
+ FMC_Bank1->BTCR[FMC_Bank + 1] = 0x0FFFFFFF;
+ FMC_Bank1E->BWTR[FMC_Bank] = 0x0FFFFFFF;
+}
+
+/**
+ * @brief Initializes the FMC NOR/SRAM Banks according to the specified
+ * parameters in the FMC_NORSRAMInitStruct.
+ * @param FMC_NORSRAMInitStruct : pointer to a FMC_NORSRAMInitTypeDef structure
+ * that contains the configuration information for the FMC NOR/SRAM
+ * specified Banks.
+ * @retval None
+ */
+void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
+{
+ gU32 tmpr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NORSRAM_BANK(FMC_NORSRAMInitStruct->FMC_Bank));
+ assert_param(IS_FMC_MUX(FMC_NORSRAMInitStruct->FMC_DataAddressMux));
+ assert_param(IS_FMC_MEMORY(FMC_NORSRAMInitStruct->FMC_MemoryType));
+ assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(FMC_NORSRAMInitStruct->FMC_MemoryDataWidth));
+ assert_param(IS_FMC_BURSTMODE(FMC_NORSRAMInitStruct->FMC_BurstAccessMode));
+ assert_param(IS_FMC_WAIT_POLARITY(FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity));
+ assert_param(IS_FMC_WRAP_MODE(FMC_NORSRAMInitStruct->FMC_WrapMode));
+ assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(FMC_NORSRAMInitStruct->FMC_WaitSignalActive));
+ assert_param(IS_FMC_WRITE_OPERATION(FMC_NORSRAMInitStruct->FMC_WriteOperation));
+ assert_param(IS_FMC_WAITE_SIGNAL(FMC_NORSRAMInitStruct->FMC_WaitSignal));
+ assert_param(IS_FMC_EXTENDED_MODE(FMC_NORSRAMInitStruct->FMC_ExtendedMode));
+ assert_param(IS_FMC_ASYNWAIT(FMC_NORSRAMInitStruct->FMC_AsynchronousWait));
+ assert_param(IS_FMC_WRITE_BURST(FMC_NORSRAMInitStruct->FMC_WriteBurst));
+ assert_param(IS_FMC_CONTINOUS_CLOCK(FMC_NORSRAMInitStruct->FMC_ContinousClock));
+ assert_param(IS_FMC_ADDRESS_SETUP_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime));
+ assert_param(IS_FMC_ADDRESS_HOLD_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime));
+ assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime));
+ assert_param(IS_FMC_TURNAROUND_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration));
+ assert_param(IS_FMC_CLK_DIV(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision));
+ assert_param(IS_FMC_DATA_LATENCY(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency));
+ assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode));
+
+ /* NOR/SRAM Bank control register configuration */
+ FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] =
+ (gU32)FMC_NORSRAMInitStruct->FMC_DataAddressMux |
+ FMC_NORSRAMInitStruct->FMC_MemoryType |
+ FMC_NORSRAMInitStruct->FMC_MemoryDataWidth |
+ FMC_NORSRAMInitStruct->FMC_BurstAccessMode |
+ FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity |
+ FMC_NORSRAMInitStruct->FMC_WrapMode |
+ FMC_NORSRAMInitStruct->FMC_WaitSignalActive |
+ FMC_NORSRAMInitStruct->FMC_WriteOperation |
+ FMC_NORSRAMInitStruct->FMC_WaitSignal |
+ FMC_NORSRAMInitStruct->FMC_ExtendedMode |
+ FMC_NORSRAMInitStruct->FMC_AsynchronousWait |
+ FMC_NORSRAMInitStruct->FMC_WriteBurst |
+ FMC_NORSRAMInitStruct->FMC_ContinousClock;
+
+
+ if(FMC_NORSRAMInitStruct->FMC_MemoryType == FMC_MemoryType_NOR)
+ {
+ FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] |= (gU32)BCR_FACCEN_SET;
+ }
+
+ /* Configure Continuous clock feature when bank2..4 is used */
+ if((FMC_NORSRAMInitStruct->FMC_ContinousClock == FMC_CClock_SyncAsync) && (FMC_NORSRAMInitStruct->FMC_Bank != FMC_Bank1_NORSRAM1))
+ {
+ tmpr = (gU32)((FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1]) & ~(((gU32)0x0F) << 20));
+
+ FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1] |= FMC_NORSRAMInitStruct->FMC_ContinousClock;
+ FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1] |= FMC_BurstAccessMode_Enable;
+ FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1] = (gU32)(tmpr | (((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision)-1) << 20));
+ }
+
+ /* NOR/SRAM Bank timing register configuration */
+ FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank+1] =
+ (gU32)FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime |
+ (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime << 4) |
+ (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime << 8) |
+ (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration << 16) |
+ ((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision) << 20) |
+ ((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency) << 24) |
+ FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode;
+
+ /* NOR/SRAM Bank timing register for write configuration, if extended mode is used */
+ if(FMC_NORSRAMInitStruct->FMC_ExtendedMode == FMC_ExtendedMode_Enable)
+ {
+ assert_param(IS_FMC_ADDRESS_SETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime));
+ assert_param(IS_FMC_ADDRESS_HOLD_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime));
+ assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime));
+ assert_param(IS_FMC_CLK_DIV(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision));
+ assert_param(IS_FMC_DATA_LATENCY(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency));
+ assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode));
+
+ FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] =
+ (gU32)FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime |
+ (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime << 4 )|
+ (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime << 8) |
+ ((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision) << 20) |
+ ((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency) << 24) |
+ FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode;
+ }
+ else
+ {
+ FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] = 0x0FFFFFFF;
+ }
+
+}
+
+/**
+ * @brief Fills each FMC_NORSRAMInitStruct member with its default value.
+ * @param FMC_NORSRAMInitStruct: pointer to a FMC_NORSRAMInitTypeDef structure
+ * which will be initialized.
+ * @retval None
+ */
+void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
+{
+ /* Reset NOR/SRAM Init structure parameters values */
+ FMC_NORSRAMInitStruct->FMC_Bank = FMC_Bank1_NORSRAM1;
+ FMC_NORSRAMInitStruct->FMC_DataAddressMux = FMC_DataAddressMux_Enable;
+ FMC_NORSRAMInitStruct->FMC_MemoryType = FMC_MemoryType_SRAM;
+ FMC_NORSRAMInitStruct->FMC_MemoryDataWidth = FMC_NORSRAM_MemoryDataWidth_16b;
+ FMC_NORSRAMInitStruct->FMC_BurstAccessMode = FMC_BurstAccessMode_Disable;
+ FMC_NORSRAMInitStruct->FMC_AsynchronousWait = FMC_AsynchronousWait_Disable;
+ FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low;
+ FMC_NORSRAMInitStruct->FMC_WrapMode = FMC_WrapMode_Disable;
+ FMC_NORSRAMInitStruct->FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState;
+ FMC_NORSRAMInitStruct->FMC_WriteOperation = FMC_WriteOperation_Enable;
+ FMC_NORSRAMInitStruct->FMC_WaitSignal = FMC_WaitSignal_Enable;
+ FMC_NORSRAMInitStruct->FMC_ExtendedMode = FMC_ExtendedMode_Disable;
+ FMC_NORSRAMInitStruct->FMC_WriteBurst = FMC_WriteBurst_Disable;
+ FMC_NORSRAMInitStruct->FMC_ContinousClock = FMC_CClock_SyncOnly;
+
+ FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime = 15;
+ FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime = 15;
+ FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime = 255;
+ FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration = 15;
+ FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision = 15;
+ FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency = 15;
+ FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode = FMC_AccessMode_A;
+ FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime = 15;
+ FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime = 15;
+ FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime = 255;
+ FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_BusTurnAroundDuration = 15;
+ FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision = 15;
+ FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency = 15;
+ FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode = FMC_AccessMode_A;
+}
+
+/**
+ * @brief Enables or disables the specified NOR/SRAM Memory Bank.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank1_NORSRAM1: FMC Bank1 NOR/SRAM1
+ * @arg FMC_Bank1_NORSRAM2: FMC Bank1 NOR/SRAM2
+ * @arg FMC_Bank1_NORSRAM3: FMC Bank1 NOR/SRAM3
+ * @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4
+ * @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FMC_NORSRAMCmd(gU32 FMC_Bank, FunctionalState NewState)
+{
+ assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
+ FMC_Bank1->BTCR[FMC_Bank] |= BCR_MBKEN_SET;
+ }
+ else
+ {
+ /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
+ FMC_Bank1->BTCR[FMC_Bank] &= BCR_MBKEN_RESET;
+ }
+}
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Group2 NAND Controller functions
+ * @brief NAND Controller functions
+ *
+@verbatim
+ ===============================================================================
+ ##### NAND Controller functions #####
+ ===============================================================================
+
+ [..] The following sequence should be followed to configure the FMC to interface
+ with 8-bit or 16-bit NAND memory connected to the NAND Bank:
+
+ (#) Enable the clock for the FMC and associated GPIOs using the following functions:
+ (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);
+ (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
+
+ (#) FMC pins configuration
+ (++) Connect the involved FMC pins to AF12 using the following function
+ GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC);
+ (++) Configure these FMC pins in alternate function mode by calling the function
+ GPIO_Init();
+
+ (#) Declare a FMC_NANDInitTypeDef structure, for example:
+ FMC_NANDInitTypeDef FMC_NANDInitStructure;
+ and fill the FMC_NANDInitStructure variable with the allowed values of
+ the structure member.
+
+ (#) Initialize the NAND Controller by calling the function
+ FMC_NANDInit(&FMC_NANDInitStructure);
+
+ (#) Then enable the NAND Bank, for example:
+ FMC_NANDCmd(FMC_Bank3_NAND, ENABLE);
+
+ (#) At this stage you can read/write from/to the memory connected to the NAND Bank.
+
+ [..]
+ (@) To enable the Error Correction Code (ECC), you have to use the function
+ FMC_NANDECCCmd(FMC_Bank3_NAND, ENABLE);
+ [..]
+ (@) and to get the current ECC value you have to use the function
+ ECCval = FMC_GetECC(FMC_Bank3_NAND);
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief De-initializes the FMC NAND Banks registers to their default reset values.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank2_NAND: FMC Bank2 NAND
+ * @arg FMC_Bank3_NAND: FMC Bank3 NAND
+ * @retval None
+ */
+void FMC_NANDDeInit(gU32 FMC_Bank)
+{
+ /* Check the parameter */
+ assert_param(IS_FMC_NAND_BANK(FMC_Bank));
+
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+ /* Set the FMC_Bank2 registers to their reset values */
+ FMC_Bank2->PCR2 = 0x00000018;
+ FMC_Bank2->SR2 = 0x00000040;
+ FMC_Bank2->PMEM2 = 0xFCFCFCFC;
+ FMC_Bank2->PATT2 = 0xFCFCFCFC;
+ }
+ /* FMC_Bank3_NAND */
+ else
+ {
+ /* Set the FMC_Bank3 registers to their reset values */
+ FMC_Bank3->PCR3 = 0x00000018;
+ FMC_Bank3->SR3 = 0x00000040;
+ FMC_Bank3->PMEM3 = 0xFCFCFCFC;
+ FMC_Bank3->PATT3 = 0xFCFCFCFC;
+ }
+}
+
+/**
+ * @brief Initializes the FMC NAND Banks according to the specified parameters
+ * in the FMC_NANDInitStruct.
+ * @param FMC_NANDInitStruct : pointer to a FMC_NANDInitTypeDef structure that
+ * contains the configuration information for the FMC NAND specified Banks.
+ * @retval None
+ */
+void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct)
+{
+ gU32 tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_NAND_BANK(FMC_NANDInitStruct->FMC_Bank));
+ assert_param(IS_FMC_WAIT_FEATURE(FMC_NANDInitStruct->FMC_Waitfeature));
+ assert_param(IS_FMC_NAND_MEMORY_WIDTH(FMC_NANDInitStruct->FMC_MemoryDataWidth));
+ assert_param(IS_FMC_ECC_STATE(FMC_NANDInitStruct->FMC_ECC));
+ assert_param(IS_FMC_ECCPAGE_SIZE(FMC_NANDInitStruct->FMC_ECCPageSize));
+ assert_param(IS_FMC_TCLR_TIME(FMC_NANDInitStruct->FMC_TCLRSetupTime));
+ assert_param(IS_FMC_TAR_TIME(FMC_NANDInitStruct->FMC_TARSetupTime));
+ assert_param(IS_FMC_SETUP_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime));
+ assert_param(IS_FMC_SETUP_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime));
+
+ /* Set the tmppcr value according to FMC_NANDInitStruct parameters */
+ tmppcr = (gU32)FMC_NANDInitStruct->FMC_Waitfeature |
+ PCR_MEMORYTYPE_NAND |
+ FMC_NANDInitStruct->FMC_MemoryDataWidth |
+ FMC_NANDInitStruct->FMC_ECC |
+ FMC_NANDInitStruct->FMC_ECCPageSize |
+ (FMC_NANDInitStruct->FMC_TCLRSetupTime << 9 )|
+ (FMC_NANDInitStruct->FMC_TARSetupTime << 13);
+
+ /* Set tmppmem value according to FMC_CommonSpaceTimingStructure parameters */
+ tmppmem = (gU32)FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime |
+ (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) |
+ (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)|
+ (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24);
+
+ /* Set tmppatt value according to FMC_AttributeSpaceTimingStructure parameters */
+ tmppatt = (gU32)FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime |
+ (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) |
+ (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)|
+ (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24);
+
+ if(FMC_NANDInitStruct->FMC_Bank == FMC_Bank2_NAND)
+ {
+ /* FMC_Bank2_NAND registers configuration */
+ FMC_Bank2->PCR2 = tmppcr;
+ FMC_Bank2->PMEM2 = tmppmem;
+ FMC_Bank2->PATT2 = tmppatt;
+ }
+ else
+ {
+ /* FMC_Bank3_NAND registers configuration */
+ FMC_Bank3->PCR3 = tmppcr;
+ FMC_Bank3->PMEM3 = tmppmem;
+ FMC_Bank3->PATT3 = tmppatt;
+ }
+}
+
+
+/**
+ * @brief Fills each FMC_NANDInitStruct member with its default value.
+ * @param FMC_NANDInitStruct: pointer to a FMC_NANDInitTypeDef structure which
+ * will be initialized.
+ * @retval None
+ */
+void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct)
+{
+ /* Reset NAND Init structure parameters values */
+ FMC_NANDInitStruct->FMC_Bank = FMC_Bank2_NAND;
+ FMC_NANDInitStruct->FMC_Waitfeature = FMC_Waitfeature_Disable;
+ FMC_NANDInitStruct->FMC_MemoryDataWidth = FMC_NAND_MemoryDataWidth_16b;
+ FMC_NANDInitStruct->FMC_ECC = FMC_ECC_Disable;
+ FMC_NANDInitStruct->FMC_ECCPageSize = FMC_ECCPageSize_256Bytes;
+ FMC_NANDInitStruct->FMC_TCLRSetupTime = 0x0;
+ FMC_NANDInitStruct->FMC_TARSetupTime = 0x0;
+ FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime = 252;
+ FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime = 252;
+ FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime = 252;
+ FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime = 252;
+ FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime = 252;
+ FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime = 252;
+ FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime = 252;
+ FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime = 252;
+}
+
+/**
+ * @brief Enables or disables the specified NAND Memory Bank.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank2_NAND: FMC Bank2 NAND
+ * @arg FMC_Bank3_NAND: FMC Bank3 NAND
+ * @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FMC_NANDCmd(gU32 FMC_Bank, FunctionalState NewState)
+{
+ assert_param(IS_FMC_NAND_BANK(FMC_Bank));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+ FMC_Bank2->PCR2 |= PCR_PBKEN_SET;
+ }
+ else
+ {
+ FMC_Bank3->PCR3 |= PCR_PBKEN_SET;
+ }
+ }
+ else
+ {
+ /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+ FMC_Bank2->PCR2 &= PCR_PBKEN_RESET;
+ }
+ else
+ {
+ FMC_Bank3->PCR3 &= PCR_PBKEN_RESET;
+ }
+ }
+}
+/**
+ * @brief Enables or disables the FMC NAND ECC feature.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank2_NAND: FMC Bank2 NAND
+ * @arg FMC_Bank3_NAND: FMC Bank3 NAND
+ * @param NewState: new state of the FMC NAND ECC feature.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FMC_NANDECCCmd(gU32 FMC_Bank, FunctionalState NewState)
+{
+ assert_param(IS_FMC_NAND_BANK(FMC_Bank));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+ FMC_Bank2->PCR2 |= PCR_ECCEN_SET;
+ }
+ else
+ {
+ FMC_Bank3->PCR3 |= PCR_ECCEN_SET;
+ }
+ }
+ else
+ {
+ /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+ FMC_Bank2->PCR2 &= PCR_ECCEN_RESET;
+ }
+ else
+ {
+ FMC_Bank3->PCR3 &= PCR_ECCEN_RESET;
+ }
+ }
+}
+
+/**
+ * @brief Returns the error correction code register value.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank2_NAND: FMC Bank2 NAND
+ * @arg FMC_Bank3_NAND: FMC Bank3 NAND
+ * @retval The Error Correction Code (ECC) value.
+ */
+gU32 FMC_GetECC(gU32 FMC_Bank)
+{
+ gU32 eccval = 0x00000000;
+
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+ /* Get the ECCR2 register value */
+ eccval = FMC_Bank2->ECCR2;
+ }
+ else
+ {
+ /* Get the ECCR3 register value */
+ eccval = FMC_Bank3->ECCR3;
+ }
+ /* Return the error correction code value */
+ return(eccval);
+}
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Group3 PCCARD Controller functions
+ * @brief PCCARD Controller functions
+ *
+@verbatim
+ ===============================================================================
+ ##### PCCARD Controller functions #####
+ ===============================================================================
+
+ [..] he following sequence should be followed to configure the FMC to interface
+ with 16-bit PC Card compatible memory connected to the PCCARD Bank:
+
+ (#) Enable the clock for the FMC and associated GPIOs using the following functions:
+ (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);
+ (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
+
+ (#) FMC pins configuration
+ (++) Connect the involved FMC pins to AF12 using the following function
+ GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC);
+ (++) Configure these FMC pins in alternate function mode by calling the function
+ GPIO_Init();
+
+ (#) Declare a FMC_PCCARDInitTypeDef structure, for example:
+ FMC_PCCARDInitTypeDef FMC_PCCARDInitStructure;
+ and fill the FMC_PCCARDInitStructure variable with the allowed values of
+ the structure member.
+
+ (#) Initialize the PCCARD Controller by calling the function
+ FMC_PCCARDInit(&FMC_PCCARDInitStructure);
+
+ (#) Then enable the PCCARD Bank:
+ FMC_PCCARDCmd(ENABLE);
+
+ (#) At this stage you can read/write from/to the memory connected to the PCCARD Bank.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief De-initializes the FMC PCCARD Bank registers to their default reset values.
+ * @param None
+ * @retval None
+ */
+void FMC_PCCARDDeInit(void)
+{
+ /* Set the FMC_Bank4 registers to their reset values */
+ FMC_Bank4->PCR4 = 0x00000018;
+ FMC_Bank4->SR4 = 0x00000000;
+ FMC_Bank4->PMEM4 = 0xFCFCFCFC;
+ FMC_Bank4->PATT4 = 0xFCFCFCFC;
+ FMC_Bank4->PIO4 = 0xFCFCFCFC;
+}
+
+/**
+ * @brief Initializes the FMC PCCARD Bank according to the specified parameters
+ * in the FMC_PCCARDInitStruct.
+ * @param FMC_PCCARDInitStruct : pointer to a FMC_PCCARDInitTypeDef structure
+ * that contains the configuration information for the FMC PCCARD Bank.
+ * @retval None
+ */
+void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_WAIT_FEATURE(FMC_PCCARDInitStruct->FMC_Waitfeature));
+ assert_param(IS_FMC_TCLR_TIME(FMC_PCCARDInitStruct->FMC_TCLRSetupTime));
+ assert_param(IS_FMC_TAR_TIME(FMC_PCCARDInitStruct->FMC_TARSetupTime));
+
+ assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime));
+
+ assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime));
+ assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime));
+ assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime));
+ assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime));
+ assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime));
+
+ /* Set the PCR4 register value according to FMC_PCCARDInitStruct parameters */
+ FMC_Bank4->PCR4 = (gU32)FMC_PCCARDInitStruct->FMC_Waitfeature |
+ FMC_NAND_MemoryDataWidth_16b |
+ (FMC_PCCARDInitStruct->FMC_TCLRSetupTime << 9) |
+ (FMC_PCCARDInitStruct->FMC_TARSetupTime << 13);
+
+ /* Set PMEM4 register value according to FMC_CommonSpaceTimingStructure parameters */
+ FMC_Bank4->PMEM4 = (gU32)FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime |
+ (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) |
+ (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)|
+ (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24);
+
+ /* Set PATT4 register value according to FMC_AttributeSpaceTimingStructure parameters */
+ FMC_Bank4->PATT4 = (gU32)FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime |
+ (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) |
+ (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)|
+ (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24);
+
+ /* Set PIO4 register value according to FMC_IOSpaceTimingStructure parameters */
+ FMC_Bank4->PIO4 = (gU32)FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime |
+ (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime << 8) |
+ (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime << 16)|
+ (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime << 24);
+}
+
+/**
+ * @brief Fills each FMC_PCCARDInitStruct member with its default value.
+ * @param FMC_PCCARDInitStruct: pointer to a FMC_PCCARDInitTypeDef structure
+ * which will be initialized.
+ * @retval None
+ */
+void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct)
+{
+ /* Reset PCCARD Init structure parameters values */
+ FMC_PCCARDInitStruct->FMC_Waitfeature = FMC_Waitfeature_Disable;
+ FMC_PCCARDInitStruct->FMC_TCLRSetupTime = 0;
+ FMC_PCCARDInitStruct->FMC_TARSetupTime = 0;
+ FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime = 252;
+ FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime = 252;
+ FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime = 252;
+ FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime = 252;
+ FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime = 252;
+ FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime = 252;
+ FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime = 252;
+ FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime = 252;
+ FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime = 252;
+ FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime = 252;
+ FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime = 252;
+ FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime = 252;
+}
+
+/**
+ * @brief Enables or disables the PCCARD Memory Bank.
+ * @param NewState: new state of the PCCARD Memory Bank.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FMC_PCCARDCmd(FunctionalState NewState)
+{
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
+ FMC_Bank4->PCR4 |= PCR_PBKEN_SET;
+ }
+ else
+ {
+ /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
+ FMC_Bank4->PCR4 &= PCR_PBKEN_RESET;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Group4 SDRAM Controller functions
+ * @brief SDRAM Controller functions
+ *
+@verbatim
+ ===============================================================================
+ ##### SDRAM Controller functions #####
+ ===============================================================================
+
+ [..] The following sequence should be followed to configure the FMC to interface
+ with SDRAM memory connected to the SDRAM Bank 1 or SDRAM bank 2:
+
+ (#) Enable the clock for the FMC and associated GPIOs using the following functions:
+ (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);
+ (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
+
+ (#) FMC pins configuration
+ (++) Connect the involved FMC pins to AF12 using the following function
+ GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC);
+ (++) Configure these FMC pins in alternate function mode by calling the function
+ GPIO_Init();
+
+ (#) Declare a FMC_SDRAMInitTypeDef structure, for example:
+ FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure;
+ and fill the FMC_SDRAMInitStructure variable with the allowed values of
+ the structure member.
+
+ (#) Initialize the SDRAM Controller by calling the function
+ FMC_SDRAMInit(&FMC_SDRAMInitStructure);
+
+ (#) Declare a FMC_SDRAMCommandTypeDef structure, for example:
+ FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
+ and fill the FMC_SDRAMCommandStructure variable with the allowed values of
+ the structure member.
+
+ (#) Configure the SDCMR register with the desired command parameters by calling
+ the function FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
+
+ (#) At this stage, the SDRAM memory is ready for any valid command.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief De-initializes the FMC SDRAM Banks registers to their default
+ * reset values.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
+ * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
+ * @retval None
+ */
+void FMC_SDRAMDeInit(gU32 FMC_Bank)
+{
+ /* Check the parameter */
+ assert_param(IS_FMC_SDRAM_BANK(FMC_Bank));
+
+ FMC_Bank5_6->SDCR[FMC_Bank] = 0x000002D0;
+ FMC_Bank5_6->SDTR[FMC_Bank] = 0x0FFFFFFF;
+ FMC_Bank5_6->SDCMR = 0x00000000;
+ FMC_Bank5_6->SDRTR = 0x00000000;
+ FMC_Bank5_6->SDSR = 0x00000000;
+}
+
+/**
+ * @brief Initializes the FMC SDRAM Banks according to the specified
+ * parameters in the FMC_SDRAMInitStruct.
+ * @param FMC_SDRAMInitStruct : pointer to a FMC_SDRAMInitTypeDef structure
+ * that contains the configuration information for the FMC SDRAM
+ * specified Banks.
+ * @retval None
+ */
+void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
+{
+ /* temporary registers */
+ gU32 tmpr1 = 0;
+ gU32 tmpr2 = 0;
+ gU32 tmpr3 = 0;
+ gU32 tmpr4 = 0;
+
+ /* Check the parameters */
+
+ /* Control parameters */
+ assert_param(IS_FMC_SDRAM_BANK(FMC_SDRAMInitStruct->FMC_Bank));
+ assert_param(IS_FMC_COLUMNBITS_NUMBER(FMC_SDRAMInitStruct->FMC_ColumnBitsNumber));
+ assert_param(IS_FMC_ROWBITS_NUMBER(FMC_SDRAMInitStruct->FMC_RowBitsNumber));
+ assert_param(IS_FMC_SDMEMORY_WIDTH(FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth));
+ assert_param(IS_FMC_INTERNALBANK_NUMBER(FMC_SDRAMInitStruct->FMC_InternalBankNumber));
+ assert_param(IS_FMC_CAS_LATENCY(FMC_SDRAMInitStruct->FMC_CASLatency));
+ assert_param(IS_FMC_WRITE_PROTECTION(FMC_SDRAMInitStruct->FMC_WriteProtection));
+ assert_param(IS_FMC_SDCLOCK_PERIOD(FMC_SDRAMInitStruct->FMC_SDClockPeriod));
+ assert_param(IS_FMC_READ_BURST(FMC_SDRAMInitStruct->FMC_ReadBurst));
+ assert_param(IS_FMC_READPIPE_DELAY(FMC_SDRAMInitStruct->FMC_ReadPipeDelay));
+
+ /* Timing parameters */
+ assert_param(IS_FMC_LOADTOACTIVE_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay));
+ assert_param(IS_FMC_EXITSELFREFRESH_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay));
+ assert_param(IS_FMC_SELFREFRESH_TIME(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime));
+ assert_param(IS_FMC_ROWCYCLE_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay));
+ assert_param(IS_FMC_WRITE_RECOVERY_TIME(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime));
+ assert_param(IS_FMC_RP_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay));
+ assert_param(IS_FMC_RCD_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay));
+
+ /* SDRAM bank control register configuration */
+ tmpr1 = (gU32)FMC_SDRAMInitStruct->FMC_ColumnBitsNumber |
+ FMC_SDRAMInitStruct->FMC_RowBitsNumber |
+ FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth |
+ FMC_SDRAMInitStruct->FMC_InternalBankNumber |
+ FMC_SDRAMInitStruct->FMC_CASLatency |
+ FMC_SDRAMInitStruct->FMC_WriteProtection |
+ FMC_SDRAMInitStruct->FMC_SDClockPeriod |
+ FMC_SDRAMInitStruct->FMC_ReadBurst |
+ FMC_SDRAMInitStruct->FMC_ReadPipeDelay;
+
+ if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM )
+ {
+ FMC_Bank5_6->SDCR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr1;
+ }
+ else /* SDCR2 "don't care" bits configuration */
+ {
+ tmpr3 = (gU32)FMC_SDRAMInitStruct->FMC_SDClockPeriod |
+ FMC_SDRAMInitStruct->FMC_ReadBurst |
+ FMC_SDRAMInitStruct->FMC_ReadPipeDelay;
+
+ FMC_Bank5_6->SDCR[FMC_Bank1_SDRAM] = tmpr3;
+ FMC_Bank5_6->SDCR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr1;
+ }
+ /* SDRAM bank timing register configuration */
+ if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM )
+ {
+ tmpr2 = (gU32)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay)-1) << 24);
+
+ FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2;
+ }
+ else /* SDTR "don't care bits configuration */
+ {
+ tmpr2 = (gU32)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16);
+
+ tmpr4 = (gU32)(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20);
+
+ FMC_Bank5_6->SDTR[FMC_Bank1_SDRAM] = tmpr4;
+ FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2;
+ }
+
+}
+
+/**
+ * @brief Fills each FMC_SDRAMInitStruct member with its default value.
+ * @param FMC_SDRAMInitStruct: pointer to a FMC_SDRAMInitTypeDef structure
+ * which will be initialized.
+ * @retval None
+ */
+void FMC_SDRAMStructInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
+{
+ /* Reset SDRAM Init structure parameters values */
+ FMC_SDRAMInitStruct->FMC_Bank = FMC_Bank1_SDRAM;
+ FMC_SDRAMInitStruct->FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
+ FMC_SDRAMInitStruct->FMC_RowBitsNumber = FMC_RowBits_Number_11b;
+ FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b;
+ FMC_SDRAMInitStruct->FMC_InternalBankNumber = FMC_InternalBank_Number_4;
+ FMC_SDRAMInitStruct->FMC_CASLatency = FMC_CAS_Latency_1;
+ FMC_SDRAMInitStruct->FMC_WriteProtection = FMC_Write_Protection_Enable;
+ FMC_SDRAMInitStruct->FMC_SDClockPeriod = FMC_SDClock_Disable;
+ FMC_SDRAMInitStruct->FMC_ReadBurst = FMC_Read_Burst_Disable;
+ FMC_SDRAMInitStruct->FMC_ReadPipeDelay = FMC_ReadPipe_Delay_0;
+
+ FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay = 16;
+ FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay = 16;
+ FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime = 16;
+ FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay = 16;
+ FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime = 16;
+ FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay = 16;
+ FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay = 16;
+
+}
+
+/**
+ * @brief Configures the SDRAM memory command issued when the device is accessed.
+ * @param FMC_SDRAMCommandStruct: pointer to a FMC_SDRAMCommandTypeDef structure
+ * which will be configured.
+ * @retval None
+ */
+void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct)
+{
+ gU32 tmpr = 0x0;
+
+ /* check parameters */
+ assert_param(IS_FMC_COMMAND_MODE(FMC_SDRAMCommandStruct->FMC_CommandMode));
+ assert_param(IS_FMC_COMMAND_TARGET(FMC_SDRAMCommandStruct->FMC_CommandTarget));
+ assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber));
+ assert_param(IS_FMC_MODE_REGISTER(FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition));
+
+ tmpr = (gU32)(FMC_SDRAMCommandStruct->FMC_CommandMode |
+ FMC_SDRAMCommandStruct->FMC_CommandTarget |
+ (((FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber)-1)<<5) |
+ ((FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition)<<9));
+
+ FMC_Bank5_6->SDCMR = tmpr;
+
+}
+
+
+/**
+ * @brief Returns the indicated FMC SDRAM bank mode status.
+ * @param SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be
+ * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
+ * @retval The FMC SDRAM bank mode status
+ */
+gU32 FMC_GetModeStatus(gU32 SDRAM_Bank)
+{
+ gU32 tmpreg = 0;
+
+ /* Check the parameter */
+ assert_param(IS_FMC_SDRAM_BANK(SDRAM_Bank));
+
+ /* Get the busy flag status */
+ if(SDRAM_Bank == FMC_Bank1_SDRAM)
+ {
+ tmpreg = (gU32)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES1);
+ }
+ else
+ {
+ tmpreg = ((gU32)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES2) >> 2);
+ }
+
+ /* Return the mode status */
+ return tmpreg;
+}
+
+/**
+ * @brief defines the SDRAM Memory Refresh rate.
+ * @param FMC_Count: specifies the Refresh timer count.
+ * @retval None
+ */
+void FMC_SetRefreshCount(gU32 FMC_Count)
+{
+ /* check the parameters */
+ assert_param(IS_FMC_REFRESH_COUNT(FMC_Count));
+
+ FMC_Bank5_6->SDRTR |= (FMC_Count<<1);
+
+}
+
+/**
+ * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
+ * @param FMC_Number: specifies the auto Refresh number.
+ * @retval None
+ */
+void FMC_SetAutoRefresh_Number(gU32 FMC_Number)
+{
+ /* check the parameters */
+ assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_Number));
+
+ FMC_Bank5_6->SDCMR |= (FMC_Number << 5);
+}
+
+/**
+ * @brief Enables or disables write protection to the specified FMC SDRAM Bank.
+ * @param SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be
+ * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
+ * @param NewState: new state of the write protection flag.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FMC_SDRAMWriteProtectionConfig(gU32 SDRAM_Bank, FunctionalState NewState)
+{
+ /* Check the parameter */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_FMC_SDRAM_BANK(SDRAM_Bank));
+
+ if (NewState != DISABLE)
+ {
+ FMC_Bank5_6->SDCR[SDRAM_Bank] |= FMC_Write_Protection_Enable;
+ }
+ else
+ {
+ FMC_Bank5_6->SDCR[SDRAM_Bank] &= SDCR_WriteProtection_RESET;
+ }
+
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FMC_Group5 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified FMC interrupts.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank2_NAND: FMC Bank2 NAND
+ * @arg FMC_Bank3_NAND: FMC Bank3 NAND
+ * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
+ * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
+ * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
+ * @param FMC_IT: specifies the FMC interrupt sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RisingEdge: Rising edge detection interrupt.
+ * @arg FMC_IT_Level: Level edge detection interrupt.
+ * @arg FMC_IT_FallingEdge: Falling edge detection interrupt.
+ * @arg FMC_IT_Refresh: Refresh error detection interrupt.
+ * @param NewState: new state of the specified FMC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FMC_ITConfig(gU32 FMC_Bank, gU32 FMC_IT, FunctionalState NewState)
+{
+ assert_param(IS_FMC_IT_BANK(FMC_Bank));
+ assert_param(IS_FMC_IT(FMC_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected FMC_Bank2 interrupts */
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+ FMC_Bank2->SR2 |= FMC_IT;
+ }
+ /* Enable the selected FMC_Bank3 interrupts */
+ else if (FMC_Bank == FMC_Bank3_NAND)
+ {
+ FMC_Bank3->SR3 |= FMC_IT;
+ }
+ /* Enable the selected FMC_Bank4 interrupts */
+ else if (FMC_Bank == FMC_Bank4_PCCARD)
+ {
+ FMC_Bank4->SR4 |= FMC_IT;
+ }
+ /* Enable the selected FMC_Bank5_6 interrupt */
+ else
+ {
+ /* Enables the interrupt if the refresh error flag is set */
+ FMC_Bank5_6->SDRTR |= FMC_IT;
+ }
+ }
+ else
+ {
+ /* Disable the selected FMC_Bank2 interrupts */
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+
+ FMC_Bank2->SR2 &= (gU32)~FMC_IT;
+ }
+ /* Disable the selected FMC_Bank3 interrupts */
+ else if (FMC_Bank == FMC_Bank3_NAND)
+ {
+ FMC_Bank3->SR3 &= (gU32)~FMC_IT;
+ }
+ /* Disable the selected FMC_Bank4 interrupts */
+ else if(FMC_Bank == FMC_Bank4_PCCARD)
+ {
+ FMC_Bank4->SR4 &= (gU32)~FMC_IT;
+ }
+ /* Disable the selected FMC_Bank5_6 interrupt */
+ else
+ {
+ /* Disables the interrupt if the refresh error flag is not set */
+ FMC_Bank5_6->SDRTR &= (gU32)~FMC_IT;
+ }
+ }
+}
+
+/**
+ * @brief Checks whether the specified FMC flag is set or not.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank2_NAND: FMC Bank2 NAND
+ * @arg FMC_Bank3_NAND: FMC Bank3 NAND
+ * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
+ * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
+ * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
+ * @arg FMC_Bank1_SDRAM | FMC_Bank2_SDRAM: FMC Bank1 or Bank2 SDRAM
+ * @param FMC_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg FMC_FLAG_RisingEdge: Rising edge detection Flag.
+ * @arg FMC_FLAG_Level: Level detection Flag.
+ * @arg FMC_FLAG_FallingEdge: Falling edge detection Flag.
+ * @arg FMC_FLAG_FEMPT: Fifo empty Flag.
+ * @arg FMC_FLAG_Refresh: Refresh error Flag.
+ * @arg FMC_FLAG_Busy: Busy status Flag.
+ * @retval The new state of FMC_FLAG (SET or RESET).
+ */
+FlagStatus FMC_GetFlagStatus(gU32 FMC_Bank, gU32 FMC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ gU32 tmpsr = 0x00000000;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank));
+ assert_param(IS_FMC_GET_FLAG(FMC_FLAG));
+
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+ tmpsr = FMC_Bank2->SR2;
+ }
+ else if(FMC_Bank == FMC_Bank3_NAND)
+ {
+ tmpsr = FMC_Bank3->SR3;
+ }
+ else if(FMC_Bank == FMC_Bank4_PCCARD)
+ {
+ tmpsr = FMC_Bank4->SR4;
+ }
+ else
+ {
+ tmpsr = FMC_Bank5_6->SDSR;
+ }
+
+ /* Get the flag status */
+ if ((tmpsr & FMC_FLAG) != FMC_FLAG )
+ {
+ bitstatus = RESET;
+ }
+ else
+ {
+ bitstatus = SET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the FMC's pending flags.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank2_NAND: FMC Bank2 NAND
+ * @arg FMC_Bank3_NAND: FMC Bank3 NAND
+ * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
+ * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
+ * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
+ * @param FMC_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FMC_FLAG_RisingEdge: Rising edge detection Flag.
+ * @arg FMC_FLAG_Level: Level detection Flag.
+ * @arg FMC_FLAG_FallingEdge: Falling edge detection Flag.
+ * @arg FMC_FLAG_Refresh: Refresh error Flag.
+ * @retval None
+ */
+void FMC_ClearFlag(gU32 FMC_Bank, gU32 FMC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank));
+ assert_param(IS_FMC_CLEAR_FLAG(FMC_FLAG)) ;
+
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+ FMC_Bank2->SR2 &= (~FMC_FLAG);
+ }
+ else if(FMC_Bank == FMC_Bank3_NAND)
+ {
+ FMC_Bank3->SR3 &= (~FMC_FLAG);
+ }
+ else if(FMC_Bank == FMC_Bank4_PCCARD)
+ {
+ FMC_Bank4->SR4 &= (~FMC_FLAG);
+ }
+ /* FMC_Bank5_6 SDRAM*/
+ else
+ {
+ FMC_Bank5_6->SDRTR &= (~FMC_FLAG);
+ }
+
+}
+
+/**
+ * @brief Checks whether the specified FMC interrupt has occurred or not.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank2_NAND: FMC Bank2 NAND
+ * @arg FMC_Bank3_NAND: FMC Bank3 NAND
+ * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
+ * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
+ * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
+ * @param FMC_IT: specifies the FMC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg FMC_IT_RisingEdge: Rising edge detection interrupt.
+ * @arg FMC_IT_Level: Level edge detection interrupt.
+ * @arg FMC_IT_FallingEdge: Falling edge detection interrupt.
+ * @arg FMC_IT_Refresh: Refresh error detection interrupt.
+ * @retval The new state of FMC_IT (SET or RESET).
+ */
+ITStatus FMC_GetITStatus(gU32 FMC_Bank, gU32 FMC_IT)
+{
+ ITStatus bitstatus = RESET;
+ gU32 tmpsr = 0x0;
+ gU32 tmpsr2 = 0x0;
+ gU32 itstatus = 0x0;
+ gU32 itenable = 0x0;
+
+ /* Check the parameters */
+ assert_param(IS_FMC_IT_BANK(FMC_Bank));
+ assert_param(IS_FMC_GET_IT(FMC_IT));
+
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+ tmpsr = FMC_Bank2->SR2;
+ }
+ else if(FMC_Bank == FMC_Bank3_NAND)
+ {
+ tmpsr = FMC_Bank3->SR3;
+ }
+ else if(FMC_Bank == FMC_Bank4_PCCARD)
+ {
+ tmpsr = FMC_Bank4->SR4;
+ }
+ /* FMC_Bank5_6 SDRAM*/
+ else
+ {
+ tmpsr = FMC_Bank5_6->SDRTR;
+ tmpsr2 = FMC_Bank5_6->SDSR;
+ }
+
+ /* get the IT enable bit status*/
+ itenable = tmpsr & FMC_IT;
+
+ /* get the corresponding IT Flag status*/
+ if((FMC_Bank == FMC_Bank1_SDRAM) || (FMC_Bank == FMC_Bank2_SDRAM))
+ {
+ itstatus = tmpsr2 & FMC_SDSR_RE;
+ }
+ else
+ {
+ itstatus = tmpsr & (FMC_IT >> 3);
+ }
+
+ if ((itstatus != (gU32)RESET) && (itenable != (gU32)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the FMC's interrupt pending bits.
+ * @param FMC_Bank: specifies the FMC Bank to be used
+ * This parameter can be one of the following values:
+ * @arg FMC_Bank2_NAND: FMC Bank2 NAND
+ * @arg FMC_Bank3_NAND: FMC Bank3 NAND
+ * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
+ * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
+ * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
+ * @param FMC_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FMC_IT_RisingEdge: Rising edge detection interrupt.
+ * @arg FMC_IT_Level: Level edge detection interrupt.
+ * @arg FMC_IT_FallingEdge: Falling edge detection interrupt.
+ * @arg FMC_IT_Refresh: Refresh error detection interrupt.
+ * @retval None
+ */
+void FMC_ClearITPendingBit(gU32 FMC_Bank, gU32 FMC_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_FMC_IT_BANK(FMC_Bank));
+ assert_param(IS_FMC_IT(FMC_IT));
+
+ if(FMC_Bank == FMC_Bank2_NAND)
+ {
+ FMC_Bank2->SR2 &= ~(FMC_IT >> 3);
+ }
+ else if(FMC_Bank == FMC_Bank3_NAND)
+ {
+ FMC_Bank3->SR3 &= ~(FMC_IT >> 3);
+ }
+ else if(FMC_Bank == FMC_Bank4_PCCARD)
+ {
+ FMC_Bank4->SR4 &= ~(FMC_IT >> 3);
+ }
+ /* FMC_Bank5_6 SDRAM*/
+ else
+ {
+ FMC_Bank5_6->SDRTR |= FMC_SDRTR_CRE;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/boards/base/STM32F469i-Discovery/CubeHAL/gmouse_lld_FT6x06_board.h b/boards/base/STM32F469i-Discovery/CubeHAL/gmouse_lld_FT6x06_board.h
index d185f3ad..935c8862 100644
--- a/boards/base/STM32F469i-Discovery/CubeHAL/gmouse_lld_FT6x06_board.h
+++ b/boards/base/STM32F469i-Discovery/CubeHAL/gmouse_lld_FT6x06_board.h
@@ -1,110 +1,110 @@
-/*
- * This file is subject to the terms of the GFX License. If a copy of
- * the license was not distributed with this file, you can obtain one at:
- *
- * http://ugfx.io/license.html
- */
-
-#ifndef _GINPUT_LLD_MOUSE_BOARD_H
-#define _GINPUT_LLD_MOUSE_BOARD_H
-
-#include "ft6x06.h"
-#include "stm32f4xx.h"
-#include "stm32f4xx_hal.h"
-
-// Resolution and Accuracy Settings
-#define GMOUSE_FT6x06_PEN_CALIBRATE_ERROR 40
-#define GMOUSE_FT6x06_PEN_CLICK_ERROR 16
-#define GMOUSE_FT6x06_PEN_MOVE_ERROR 14
-#define GMOUSE_FT6x06_FINGER_CALIBRATE_ERROR 50
-#define GMOUSE_FT6x06_FINGER_CLICK_ERROR 28
-#define GMOUSE_FT6x06_FINGER_MOVE_ERROR 24
-
-// How much extra data to allocate at the end of the GMouse structure for the board's use
-#define GMOUSE_FT6x06_BOARD_DATA_SIZE 0
-
-/* The FT6x06 I2C slave address */
-#define FT6x06_SLAVE_ADDR 0x54
-
-I2C_HandleTypeDef i2cHandle;
-/* Maximum speed (400kHz) */
-#define CLOCKSPEED 400000;
-
-static gBool init_board(GMouse* m, unsigned instance) {
- (void)m;
- (void)instance;
-
- GPIO_InitTypeDef gpioInit;
- /* I2C1_SCL PB8 */
- __HAL_RCC_GPIOB_CLK_ENABLE(); // Enable GPIOB clock
- gpioInit.Pin = GPIO_PIN_8;
- gpioInit.Mode = GPIO_MODE_AF_OD; // I2C -> Open-drain
- gpioInit.Pull = GPIO_NOPULL; // Open-drain -> no pull
- gpioInit.Speed = GPIO_SPEED_FREQ_HIGH; // High speed
- gpioInit.Alternate = GPIO_AF4_I2C1; // Alternate function 4
- HAL_GPIO_Init(GPIOB, &gpioInit);
-
- /* I2C1_SDA PB9 */
- gpioInit.Pin = GPIO_PIN_9;
- HAL_GPIO_Init(GPIOB, &gpioInit);
-
- /* LCD_INT PJ5 */
- __HAL_RCC_GPIOJ_CLK_ENABLE();
- gpioInit.Pin = GPIO_PIN_5;
- gpioInit.Mode = GPIO_MODE_INPUT; // Input mode
- gpioInit.Pull = GPIO_PULLUP; // Pull-up
- HAL_GPIO_Init(GPIOJ, &gpioInit);
-
- /* I2C1 intialization */
- i2cHandle.Instance = I2C1;
- i2cHandle.Init.ClockSpeed = CLOCKSPEED;
- i2cHandle.Init.DutyCycle = I2C_DUTYCYCLE_2; // Normal duty cycle
- i2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; // No dual adressing needed
- i2cHandle.Init.OwnAddress1 = 0x00;
- i2cHandle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
- i2cHandle.Init.OwnAddress2 = 0x00;
- i2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; // All not needed so disabled
- i2cHandle.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
-
- __HAL_RCC_I2C1_CLK_ENABLE();
-
- if(HAL_I2C_Init(&i2cHandle) == HAL_OK)
- return gTrue;
-
- return gFalse;
-}
-
-static GFXINLINE void aquire_bus(GMouse* m) {
- (void)m;
-}
-
-static GFXINLINE void release_bus(GMouse* m) {
- (void)m;
-}
-
-static void write_reg(GMouse* m, gU8 reg, gU8 val) {
- (void)m;
-
- HAL_I2C_Mem_Write(&i2cHandle, FT6x06_SLAVE_ADDR, (gU16)reg, I2C_MEMADD_SIZE_8BIT, &val, 1, 1000);
-}
-
-static gU8 read_byte(GMouse* m, gU8 reg) {
- (void)m;
- gU8 result;
-
- HAL_I2C_Mem_Read(&i2cHandle, FT6x06_SLAVE_ADDR, (gU16)reg, I2C_MEMADD_SIZE_8BIT, &result, 1, 1000);
-
- return result;
-}
-
-static gU16 read_word(GMouse* m, gU8 reg) {
- (void)m;
- gU8 result[2];
-
- HAL_I2C_Mem_Read(&i2cHandle, FT6x06_SLAVE_ADDR, (gU16)reg, I2C_MEMADD_SIZE_8BIT, result, 2, 1000);
-
- return (result[0]<<8 | result[1]);
-
-}
-
-#endif /* _GINPUT_LLD_MOUSE_BOARD_H */
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ * http://ugfx.io/license.html
+ */
+
+#ifndef _GINPUT_LLD_MOUSE_BOARD_H
+#define _GINPUT_LLD_MOUSE_BOARD_H
+
+#include "ft6x06.h"
+#include "stm32f4xx.h"
+#include "stm32f4xx_hal.h"
+
+// Resolution and Accuracy Settings
+#define GMOUSE_FT6x06_PEN_CALIBRATE_ERROR 40
+#define GMOUSE_FT6x06_PEN_CLICK_ERROR 16
+#define GMOUSE_FT6x06_PEN_MOVE_ERROR 14
+#define GMOUSE_FT6x06_FINGER_CALIBRATE_ERROR 50
+#define GMOUSE_FT6x06_FINGER_CLICK_ERROR 28
+#define GMOUSE_FT6x06_FINGER_MOVE_ERROR 24
+
+// How much extra data to allocate at the end of the GMouse structure for the board's use
+#define GMOUSE_FT6x06_BOARD_DATA_SIZE 0
+
+/* The FT6x06 I2C slave address */
+#define FT6x06_SLAVE_ADDR 0x54
+
+I2C_HandleTypeDef i2cHandle;
+/* Maximum speed (400kHz) */
+#define CLOCKSPEED 400000;
+
+static gBool init_board(GMouse* m, unsigned instance) {
+ (void)m;
+ (void)instance;
+
+ GPIO_InitTypeDef gpioInit;
+ /* I2C1_SCL PB8 */
+ __HAL_RCC_GPIOB_CLK_ENABLE(); // Enable GPIOB clock
+ gpioInit.Pin = GPIO_PIN_8;
+ gpioInit.Mode = GPIO_MODE_AF_OD; // I2C -> Open-drain
+ gpioInit.Pull = GPIO_NOPULL; // Open-drain -> no pull
+ gpioInit.Speed = GPIO_SPEED_FREQ_HIGH; // High speed
+ gpioInit.Alternate = GPIO_AF4_I2C1; // Alternate function 4
+ HAL_GPIO_Init(GPIOB, &gpioInit);
+
+ /* I2C1_SDA PB9 */
+ gpioInit.Pin = GPIO_PIN_9;
+ HAL_GPIO_Init(GPIOB, &gpioInit);
+
+ /* LCD_INT PJ5 */
+ __HAL_RCC_GPIOJ_CLK_ENABLE();
+ gpioInit.Pin = GPIO_PIN_5;
+ gpioInit.Mode = GPIO_MODE_INPUT; // Input mode
+ gpioInit.Pull = GPIO_PULLUP; // Pull-up
+ HAL_GPIO_Init(GPIOJ, &gpioInit);
+
+ /* I2C1 intialization */
+ i2cHandle.Instance = I2C1;
+ i2cHandle.Init.ClockSpeed = CLOCKSPEED;
+ i2cHandle.Init.DutyCycle = I2C_DUTYCYCLE_2; // Normal duty cycle
+ i2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; // No dual adressing needed
+ i2cHandle.Init.OwnAddress1 = 0x00;
+ i2cHandle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
+ i2cHandle.Init.OwnAddress2 = 0x00;
+ i2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; // All not needed so disabled
+ i2cHandle.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
+
+ __HAL_RCC_I2C1_CLK_ENABLE();
+
+ if(HAL_I2C_Init(&i2cHandle) == HAL_OK)
+ return gTrue;
+
+ return gFalse;
+}
+
+static GFXINLINE void aquire_bus(GMouse* m) {
+ (void)m;
+}
+
+static GFXINLINE void release_bus(GMouse* m) {
+ (void)m;
+}
+
+static void write_reg(GMouse* m, gU8 reg, gU8 val) {
+ (void)m;
+
+ HAL_I2C_Mem_Write(&i2cHandle, FT6x06_SLAVE_ADDR, (gU16)reg, I2C_MEMADD_SIZE_8BIT, &val, 1, 1000);
+}
+
+static gU8 read_byte(GMouse* m, gU8 reg) {
+ (void)m;
+ gU8 result;
+
+ HAL_I2C_Mem_Read(&i2cHandle, FT6x06_SLAVE_ADDR, (gU16)reg, I2C_MEMADD_SIZE_8BIT, &result, 1, 1000);
+
+ return result;
+}
+
+static gU16 read_word(GMouse* m, gU8 reg) {
+ (void)m;
+ gU8 result[2];
+
+ HAL_I2C_Mem_Read(&i2cHandle, FT6x06_SLAVE_ADDR, (gU16)reg, I2C_MEMADD_SIZE_8BIT, result, 2, 1000);
+
+ return (result[0]<<8 | result[1]);
+
+}
+
+#endif /* _GINPUT_LLD_MOUSE_BOARD_H */
diff --git a/boards/base/STM32F469i-Discovery/otm8009a.c b/boards/base/STM32F469i-Discovery/otm8009a.c
index e830d53a..d7737fd0 100644
--- a/boards/base/STM32F469i-Discovery/otm8009a.c
+++ b/boards/base/STM32F469i-Discovery/otm8009a.c
@@ -1,454 +1,454 @@
-/**
- ******************************************************************************
- * @file otm8009a.c
- * @author MCD Application Team
- * @version V1.0.2
- * @date 27-January-2017
- * @brief This file provides the LCD Driver for KoD KM-040TMP-02-0621 (WVGA)
- * DSI LCD Display OTM8009A.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "otm8009a.h"
-
-/** @addtogroup BSP
- * @{
- */
-
-/** @addtogroup Components
- * @{
- */
-
-/** @defgroup OTM8009A OTM8009A
- * @brief This file provides a set of functions needed to drive the
- * otm8009a IC display driver.
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup OTM8009A_Private_Constants OTM8009A Private Constants
- * @{
- */
-
-/*
- * @brief Constant tables of register settings used to transmit DSI
- * command packets as power up initialization sequence of the KoD LCD (OTM8009A LCD Driver)
- */
-const gU8 lcdRegData1[] = {0x80,0x09,0x01,0xFF};
-const gU8 lcdRegData2[] = {0x80,0x09,0xFF};
-const gU8 lcdRegData3[] = {0x00,0x09,0x0F,0x0E,0x07,0x10,0x0B,0x0A,0x04,0x07,0x0B,0x08,0x0F,0x10,0x0A,0x01,0xE1};
-const gU8 lcdRegData4[] = {0x00,0x09,0x0F,0x0E,0x07,0x10,0x0B,0x0A,0x04,0x07,0x0B,0x08,0x0F,0x10,0x0A,0x01,0xE2};
-const gU8 lcdRegData5[] = {0x79,0x79,0xD8};
-const gU8 lcdRegData6[] = {0x00,0x01,0xB3};
-const gU8 lcdRegData7[] = {0x85,0x01,0x00,0x84,0x01,0x00,0xCE};
-const gU8 lcdRegData8[] = {0x18,0x04,0x03,0x39,0x00,0x00,0x00,0x18,0x03,0x03,0x3A,0x00,0x00,0x00,0xCE};
-const gU8 lcdRegData9[] = {0x18,0x02,0x03,0x3B,0x00,0x00,0x00,0x18,0x01,0x03,0x3C,0x00,0x00,0x00,0xCE};
-const gU8 lcdRegData10[] = {0x01,0x01,0x20,0x20,0x00,0x00,0x01,0x02,0x00,0x00,0xCF};
-const gU8 lcdRegData11[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
-const gU8 lcdRegData12[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
-const gU8 lcdRegData13[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
-const gU8 lcdRegData14[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
-const gU8 lcdRegData15[] = {0x00,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
-const gU8 lcdRegData16[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00,0xCB};
-const gU8 lcdRegData17[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
-const gU8 lcdRegData18[] = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xCB};
-const gU8 lcdRegData19[] = {0x00,0x26,0x09,0x0B,0x01,0x25,0x00,0x00,0x00,0x00,0xCC};
-const gU8 lcdRegData20[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x26,0x0A,0x0C,0x02,0xCC};
-const gU8 lcdRegData21[] = {0x25,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCC};
-const gU8 lcdRegData22[] = {0x00,0x25,0x0C,0x0A,0x02,0x26,0x00,0x00,0x00,0x00,0xCC};
-const gU8 lcdRegData23[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x25,0x0B,0x09,0x01,0xCC};
-const gU8 lcdRegData24[] = {0x26,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCC};
-const gU8 lcdRegData25[] = {0xFF,0xFF,0xFF,0xFF};
-/*
- * CASET value (Column Address Set) : X direction LCD GRAM boundaries
- * depending on LCD orientation mode and PASET value (Page Address Set) : Y direction
- * LCD GRAM boundaries depending on LCD orientation mode
- * XS[15:0] = 0x000 = 0, XE[15:0] = 0x31F = 799 for landscape mode : apply to CASET
- * YS[15:0] = 0x000 = 0, YE[15:0] = 0x31F = 799 for portrait mode : : apply to PASET
- */
-const gU8 lcdRegData27[] = {0x00, 0x00, 0x03, 0x1F, OTM8009A_CMD_CASET};
-/*
- * XS[15:0] = 0x000 = 0, XE[15:0] = 0x1DF = 479 for portrait mode : apply to CASET
- * YS[15:0] = 0x000 = 0, YE[15:0] = 0x1DF = 479 for landscape mode : apply to PASET
- */
-const gU8 lcdRegData28[] = {0x00, 0x00, 0x01, 0xDF, OTM8009A_CMD_PASET};
-
-
-const gU8 ShortRegData1[] = {OTM8009A_CMD_NOP, 0x00};
-const gU8 ShortRegData2[] = {OTM8009A_CMD_NOP, 0x80};
-const gU8 ShortRegData3[] = {0xC4, 0x30};
-const gU8 ShortRegData4[] = {OTM8009A_CMD_NOP, 0x8A};
-const gU8 ShortRegData5[] = {0xC4, 0x40};
-const gU8 ShortRegData6[] = {OTM8009A_CMD_NOP, 0xB1};
-const gU8 ShortRegData7[] = {0xC5, 0xA9};
-const gU8 ShortRegData8[] = {OTM8009A_CMD_NOP, 0x91};
-const gU8 ShortRegData9[] = {0xC5, 0x34};
-const gU8 ShortRegData10[] = {OTM8009A_CMD_NOP, 0xB4};
-const gU8 ShortRegData11[] = {0xC0, 0x50};
-const gU8 ShortRegData12[] = {0xD9, 0x4E};
-const gU8 ShortRegData13[] = {OTM8009A_CMD_NOP, 0x81};
-const gU8 ShortRegData14[] = {0xC1, 0x66};
-const gU8 ShortRegData15[] = {OTM8009A_CMD_NOP, 0xA1};
-const gU8 ShortRegData16[] = {0xC1, 0x08};
-const gU8 ShortRegData17[] = {OTM8009A_CMD_NOP, 0x92};
-const gU8 ShortRegData18[] = {0xC5, 0x01};
-const gU8 ShortRegData19[] = {OTM8009A_CMD_NOP, 0x95};
-const gU8 ShortRegData20[] = {OTM8009A_CMD_NOP, 0x94};
-const gU8 ShortRegData21[] = {0xC5, 0x33};
-const gU8 ShortRegData22[] = {OTM8009A_CMD_NOP, 0xA3};
-const gU8 ShortRegData23[] = {0xC0, 0x1B};
-const gU8 ShortRegData24[] = {OTM8009A_CMD_NOP, 0x82};
-const gU8 ShortRegData25[] = {0xC5, 0x83};
-const gU8 ShortRegData26[] = {0xC4, 0x83};
-const gU8 ShortRegData27[] = {0xC1, 0x0E};
-const gU8 ShortRegData28[] = {OTM8009A_CMD_NOP, 0xA6};
-const gU8 ShortRegData29[] = {OTM8009A_CMD_NOP, 0xA0};
-const gU8 ShortRegData30[] = {OTM8009A_CMD_NOP, 0xB0};
-const gU8 ShortRegData31[] = {OTM8009A_CMD_NOP, 0xC0};
-const gU8 ShortRegData32[] = {OTM8009A_CMD_NOP, 0xD0};
-const gU8 ShortRegData33[] = {OTM8009A_CMD_NOP, 0x90};
-const gU8 ShortRegData34[] = {OTM8009A_CMD_NOP, 0xE0};
-const gU8 ShortRegData35[] = {OTM8009A_CMD_NOP, 0xF0};
-const gU8 ShortRegData36[] = {OTM8009A_CMD_SLPOUT, 0x00};
-const gU8 ShortRegData37[] = {OTM8009A_CMD_COLMOD, OTM8009A_COLMOD_RGB565};
-const gU8 ShortRegData38[] = {OTM8009A_CMD_COLMOD, OTM8009A_COLMOD_RGB888};
-const gU8 ShortRegData39[] = {OTM8009A_CMD_MADCTR, OTM8009A_MADCTR_MODE_LANDSCAPE};
-const gU8 ShortRegData40[] = {OTM8009A_CMD_WRDISBV, 0x7F};
-const gU8 ShortRegData41[] = {OTM8009A_CMD_WRCTRLD, 0x2C};
-const gU8 ShortRegData42[] = {OTM8009A_CMD_WRCABC, 0x02};
-const gU8 ShortRegData43[] = {OTM8009A_CMD_WRCABCMB, 0xFF};
-const gU8 ShortRegData44[] = {OTM8009A_CMD_DISPON, 0x00};
-const gU8 ShortRegData45[] = {OTM8009A_CMD_RAMWR, 0x00};
-const gU8 ShortRegData46[] = {0xCF, 0x00};
-const gU8 ShortRegData47[] = {0xC5, 0x66};
-const gU8 ShortRegData48[] = {OTM8009A_CMD_NOP, 0xB6};
-const gU8 ShortRegData49[] = {0xF5, 0x06};
-const gU8 ShortRegData50[] = {OTM8009A_CMD_NOP, 0xB1};
-const gU8 ShortRegData51[] = {0xC6, 0x06};
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup OTM8009A_Exported_Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup OTM8009A_Exported_Functions OTM8009A Exported Functions
- * @{
- */
-
-/**
- * @brief DSI IO write short/long command.
- * @note : Can be surcharged by application code implementation of the function.
- */
-__weak void DSI_IO_WriteCmd(gU32 NbrParams, gU8 *pParams)
-{
- /* NOTE : This function Should not be modified, when it is needed,
- the DSI_IO_WriteCmd could be implemented in the user file
- */
-}
-
-/**
- * @brief Initializes the LCD KoD display part by communication in DSI mode in Video Mode
- * with IC Display Driver OTM8009A (see IC Driver specification for more information).
- * @param hdsi_eval : pointer on DSI configuration structure
- * @param hdsivideo_handle : pointer on DSI video mode configuration structure
- * @retval Status
- */
-gU8 OTM8009A_Init(gU32 ColorCoding, gU32 orientation)
-{
- /* Enable CMD2 to access vendor specific commands */
- /* Enter in command 2 mode and set EXTC to enable address shift function (0x00) */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
- DSI_IO_WriteCmd( 3, (gU8 *)lcdRegData1);
-
- /* Enter ORISE Command 2 */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2); /* Shift address to 0x80 */
- DSI_IO_WriteCmd( 2, (gU8 *)lcdRegData2);
-
- /////////////////////////////////////////////////////////////////////
- /* SD_PCH_CTRL - 0xC480h - 129th parameter - Default 0x00 */
- /* Set SD_PT */
- /* -> Source output level during porch and non-display area to GND */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData3);
- OTM8009A_IO_Delay(10);
- /* Not documented */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData4);
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData5);
- OTM8009A_IO_Delay(10);
- /////////////////////////////////////////////////////////////////////
-
- /* PWR_CTRL4 - 0xC4B0h - 178th parameter - Default 0xA8 */
- /* Set gvdd_en_test */
- /* -> enable GVDD test mode !!! */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData6);
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData7);
-
- /* PWR_CTRL2 - 0xC590h - 146th parameter - Default 0x79 */
- /* Set pump 4 vgh voltage */
- /* -> from 15.0v down to 13.0v */
- /* Set pump 5 vgh voltage */
- /* -> from -12.0v downto -9.0v */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData8);
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData9);
-
- /* P_DRV_M - 0xC0B4h - 181th parameter - Default 0x00 */
- /* -> Column inversion */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData10);
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData11);
-
- /* VCOMDC - 0xD900h - 1st parameter - Default 0x39h */
- /* VCOM Voltage settings */
- /* -> from -1.0000v downto -1.2625v */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData12);
-
- /* Oscillator adjustment for Idle/Normal mode (LPDT only) set to 65Hz (default is 60Hz) */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData13);
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData14);
-
- /* Video mode internal */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData15);
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData16);
-
- /* PWR_CTRL2 - 0xC590h - 147h parameter - Default 0x00 */
- /* Set pump 4&5 x6 */
- /* -> ONLY VALID when PUMP4_EN_ASDM_HV = "0" */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData17);
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData18);
-
- /* PWR_CTRL2 - 0xC590h - 150th parameter - Default 0x33h */
- /* Change pump4 clock ratio */
- /* -> from 1 line to 1/2 line */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData19);
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData9);
-
- /* GVDD/NGVDD settings */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
- DSI_IO_WriteCmd( 2, (gU8 *)lcdRegData5);
-
- /* PWR_CTRL2 - 0xC590h - 149th parameter - Default 0x33h */
- /* Rewrite the default value ! */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData20);
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData21);
-
- /* Panel display timing Setting 3 */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData22);
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData23);
-
- /* Power control 1 */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData24);
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData25);
-
- /* Source driver precharge */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData13);
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData26);
-
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData15);
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData27);
-
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData28);
- DSI_IO_WriteCmd( 2, (gU8 *)lcdRegData6);
-
- /* GOAVST */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
- DSI_IO_WriteCmd( 6, (gU8 *)lcdRegData7);
-
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData29);
- DSI_IO_WriteCmd( 14, (gU8 *)lcdRegData8);
-
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData30);
- DSI_IO_WriteCmd( 14, (gU8 *)lcdRegData9);
-
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData31);
- DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData10);
-
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData32);
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData46);
-
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
- DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData11);
-
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData33);
- DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData12);
-
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData29);
- DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData13);
-
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData30);
- DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData14);
-
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData31);
- DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData15);
-
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData32);
- DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData16);
-
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData34);
- DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData17);
-
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData35);
- DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData18);
-
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
- DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData19);
-
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData33);
- DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData20);
-
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData29);
- DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData21);
-
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData30);
- DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData22);
-
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData31);
- DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData23);
-
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData32);
- DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData24);
-
- /////////////////////////////////////////////////////////////////////////////
- /* PWR_CTRL1 - 0xc580h - 130th parameter - default 0x00 */
- /* Pump 1 min and max DM */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData13);
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData47);
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData48);
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData49);
- /////////////////////////////////////////////////////////////////////////////
-
- /* CABC LEDPWM frequency adjusted to 19,5kHz */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData50);
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData51);
-
- /* Exit CMD2 mode */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
- DSI_IO_WriteCmd( 3, (gU8 *)lcdRegData25);
-
- /*************************************************************************** */
- /* Standard DCS Initialization TO KEEP CAN BE DONE IN HSDT */
- /*************************************************************************** */
-
- /* NOP - goes back to DCS std command ? */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
-
- /* Gamma correction 2.2+ table (HSDT possible) */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
- DSI_IO_WriteCmd( 16, (gU8 *)lcdRegData3);
-
- /* Gamma correction 2.2- table (HSDT possible) */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
- DSI_IO_WriteCmd( 16, (gU8 *)lcdRegData4);
-
- /* Send Sleep Out command to display : no parameter */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData36);
-
- /* Wait for sleep out exit */
- OTM8009A_IO_Delay(120);
-
- switch(ColorCoding)
- {
- case OTM8009A_FORMAT_RBG565 :
- /* Set Pixel color format to RGB565 */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData37);
- break;
- case OTM8009A_FORMAT_RGB888 :
- /* Set Pixel color format to RGB888 */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData38);
- break;
- default :
- break;
- }
-
- /* Send command to configure display in landscape orientation mode. By default
- the orientation mode is portrait */
- if(orientation == OTM8009A_ORIENTATION_LANDSCAPE)
- {
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData39);
- DSI_IO_WriteCmd( 4, (gU8 *)lcdRegData27);
- DSI_IO_WriteCmd( 4, (gU8 *)lcdRegData28);
- }
-
- /** CABC : Content Adaptive Backlight Control section start >> */
- /* Note : defaut is 0 (lowest Brightness), 0xFF is highest Brightness, try 0x7F : intermediate value */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData40);
-
- /* defaut is 0, try 0x2C - Brightness Control Block, Display Dimming & BackLight on */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData41);
-
- /* defaut is 0, try 0x02 - image Content based Adaptive Brightness [Still Picture] */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData42);
-
- /* defaut is 0 (lowest Brightness), 0xFF is highest Brightness */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData43);
-
- /** CABC : Content Adaptive Backlight Control section end << */
-
- /* Send Command Display On */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData44);
-
- /* NOP command */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
-
- /* Send Command GRAM memory write (no parameters) : this initiates frame write via other DSI commands sent by */
- /* DSI host from LTDC incoming pixels in video mode */
- DSI_IO_WriteCmd(0, (gU8 *)ShortRegData45);
-
- return 0;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file otm8009a.c
+ * @author MCD Application Team
+ * @version V1.0.2
+ * @date 27-January-2017
+ * @brief This file provides the LCD Driver for KoD KM-040TMP-02-0621 (WVGA)
+ * DSI LCD Display OTM8009A.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2017 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "otm8009a.h"
+
+/** @addtogroup BSP
+ * @{
+ */
+
+/** @addtogroup Components
+ * @{
+ */
+
+/** @defgroup OTM8009A OTM8009A
+ * @brief This file provides a set of functions needed to drive the
+ * otm8009a IC display driver.
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup OTM8009A_Private_Constants OTM8009A Private Constants
+ * @{
+ */
+
+/*
+ * @brief Constant tables of register settings used to transmit DSI
+ * command packets as power up initialization sequence of the KoD LCD (OTM8009A LCD Driver)
+ */
+const gU8 lcdRegData1[] = {0x80,0x09,0x01,0xFF};
+const gU8 lcdRegData2[] = {0x80,0x09,0xFF};
+const gU8 lcdRegData3[] = {0x00,0x09,0x0F,0x0E,0x07,0x10,0x0B,0x0A,0x04,0x07,0x0B,0x08,0x0F,0x10,0x0A,0x01,0xE1};
+const gU8 lcdRegData4[] = {0x00,0x09,0x0F,0x0E,0x07,0x10,0x0B,0x0A,0x04,0x07,0x0B,0x08,0x0F,0x10,0x0A,0x01,0xE2};
+const gU8 lcdRegData5[] = {0x79,0x79,0xD8};
+const gU8 lcdRegData6[] = {0x00,0x01,0xB3};
+const gU8 lcdRegData7[] = {0x85,0x01,0x00,0x84,0x01,0x00,0xCE};
+const gU8 lcdRegData8[] = {0x18,0x04,0x03,0x39,0x00,0x00,0x00,0x18,0x03,0x03,0x3A,0x00,0x00,0x00,0xCE};
+const gU8 lcdRegData9[] = {0x18,0x02,0x03,0x3B,0x00,0x00,0x00,0x18,0x01,0x03,0x3C,0x00,0x00,0x00,0xCE};
+const gU8 lcdRegData10[] = {0x01,0x01,0x20,0x20,0x00,0x00,0x01,0x02,0x00,0x00,0xCF};
+const gU8 lcdRegData11[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
+const gU8 lcdRegData12[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
+const gU8 lcdRegData13[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
+const gU8 lcdRegData14[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
+const gU8 lcdRegData15[] = {0x00,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
+const gU8 lcdRegData16[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00,0xCB};
+const gU8 lcdRegData17[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
+const gU8 lcdRegData18[] = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xCB};
+const gU8 lcdRegData19[] = {0x00,0x26,0x09,0x0B,0x01,0x25,0x00,0x00,0x00,0x00,0xCC};
+const gU8 lcdRegData20[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x26,0x0A,0x0C,0x02,0xCC};
+const gU8 lcdRegData21[] = {0x25,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCC};
+const gU8 lcdRegData22[] = {0x00,0x25,0x0C,0x0A,0x02,0x26,0x00,0x00,0x00,0x00,0xCC};
+const gU8 lcdRegData23[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x25,0x0B,0x09,0x01,0xCC};
+const gU8 lcdRegData24[] = {0x26,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCC};
+const gU8 lcdRegData25[] = {0xFF,0xFF,0xFF,0xFF};
+/*
+ * CASET value (Column Address Set) : X direction LCD GRAM boundaries
+ * depending on LCD orientation mode and PASET value (Page Address Set) : Y direction
+ * LCD GRAM boundaries depending on LCD orientation mode
+ * XS[15:0] = 0x000 = 0, XE[15:0] = 0x31F = 799 for landscape mode : apply to CASET
+ * YS[15:0] = 0x000 = 0, YE[15:0] = 0x31F = 799 for portrait mode : : apply to PASET
+ */
+const gU8 lcdRegData27[] = {0x00, 0x00, 0x03, 0x1F, OTM8009A_CMD_CASET};
+/*
+ * XS[15:0] = 0x000 = 0, XE[15:0] = 0x1DF = 479 for portrait mode : apply to CASET
+ * YS[15:0] = 0x000 = 0, YE[15:0] = 0x1DF = 479 for landscape mode : apply to PASET
+ */
+const gU8 lcdRegData28[] = {0x00, 0x00, 0x01, 0xDF, OTM8009A_CMD_PASET};
+
+
+const gU8 ShortRegData1[] = {OTM8009A_CMD_NOP, 0x00};
+const gU8 ShortRegData2[] = {OTM8009A_CMD_NOP, 0x80};
+const gU8 ShortRegData3[] = {0xC4, 0x30};
+const gU8 ShortRegData4[] = {OTM8009A_CMD_NOP, 0x8A};
+const gU8 ShortRegData5[] = {0xC4, 0x40};
+const gU8 ShortRegData6[] = {OTM8009A_CMD_NOP, 0xB1};
+const gU8 ShortRegData7[] = {0xC5, 0xA9};
+const gU8 ShortRegData8[] = {OTM8009A_CMD_NOP, 0x91};
+const gU8 ShortRegData9[] = {0xC5, 0x34};
+const gU8 ShortRegData10[] = {OTM8009A_CMD_NOP, 0xB4};
+const gU8 ShortRegData11[] = {0xC0, 0x50};
+const gU8 ShortRegData12[] = {0xD9, 0x4E};
+const gU8 ShortRegData13[] = {OTM8009A_CMD_NOP, 0x81};
+const gU8 ShortRegData14[] = {0xC1, 0x66};
+const gU8 ShortRegData15[] = {OTM8009A_CMD_NOP, 0xA1};
+const gU8 ShortRegData16[] = {0xC1, 0x08};
+const gU8 ShortRegData17[] = {OTM8009A_CMD_NOP, 0x92};
+const gU8 ShortRegData18[] = {0xC5, 0x01};
+const gU8 ShortRegData19[] = {OTM8009A_CMD_NOP, 0x95};
+const gU8 ShortRegData20[] = {OTM8009A_CMD_NOP, 0x94};
+const gU8 ShortRegData21[] = {0xC5, 0x33};
+const gU8 ShortRegData22[] = {OTM8009A_CMD_NOP, 0xA3};
+const gU8 ShortRegData23[] = {0xC0, 0x1B};
+const gU8 ShortRegData24[] = {OTM8009A_CMD_NOP, 0x82};
+const gU8 ShortRegData25[] = {0xC5, 0x83};
+const gU8 ShortRegData26[] = {0xC4, 0x83};
+const gU8 ShortRegData27[] = {0xC1, 0x0E};
+const gU8 ShortRegData28[] = {OTM8009A_CMD_NOP, 0xA6};
+const gU8 ShortRegData29[] = {OTM8009A_CMD_NOP, 0xA0};
+const gU8 ShortRegData30[] = {OTM8009A_CMD_NOP, 0xB0};
+const gU8 ShortRegData31[] = {OTM8009A_CMD_NOP, 0xC0};
+const gU8 ShortRegData32[] = {OTM8009A_CMD_NOP, 0xD0};
+const gU8 ShortRegData33[] = {OTM8009A_CMD_NOP, 0x90};
+const gU8 ShortRegData34[] = {OTM8009A_CMD_NOP, 0xE0};
+const gU8 ShortRegData35[] = {OTM8009A_CMD_NOP, 0xF0};
+const gU8 ShortRegData36[] = {OTM8009A_CMD_SLPOUT, 0x00};
+const gU8 ShortRegData37[] = {OTM8009A_CMD_COLMOD, OTM8009A_COLMOD_RGB565};
+const gU8 ShortRegData38[] = {OTM8009A_CMD_COLMOD, OTM8009A_COLMOD_RGB888};
+const gU8 ShortRegData39[] = {OTM8009A_CMD_MADCTR, OTM8009A_MADCTR_MODE_LANDSCAPE};
+const gU8 ShortRegData40[] = {OTM8009A_CMD_WRDISBV, 0x7F};
+const gU8 ShortRegData41[] = {OTM8009A_CMD_WRCTRLD, 0x2C};
+const gU8 ShortRegData42[] = {OTM8009A_CMD_WRCABC, 0x02};
+const gU8 ShortRegData43[] = {OTM8009A_CMD_WRCABCMB, 0xFF};
+const gU8 ShortRegData44[] = {OTM8009A_CMD_DISPON, 0x00};
+const gU8 ShortRegData45[] = {OTM8009A_CMD_RAMWR, 0x00};
+const gU8 ShortRegData46[] = {0xCF, 0x00};
+const gU8 ShortRegData47[] = {0xC5, 0x66};
+const gU8 ShortRegData48[] = {OTM8009A_CMD_NOP, 0xB6};
+const gU8 ShortRegData49[] = {0xF5, 0x06};
+const gU8 ShortRegData50[] = {OTM8009A_CMD_NOP, 0xB1};
+const gU8 ShortRegData51[] = {0xC6, 0x06};
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup OTM8009A_Exported_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup OTM8009A_Exported_Functions OTM8009A Exported Functions
+ * @{
+ */
+
+/**
+ * @brief DSI IO write short/long command.
+ * @note : Can be surcharged by application code implementation of the function.
+ */
+__weak void DSI_IO_WriteCmd(gU32 NbrParams, gU8 *pParams)
+{
+ /* NOTE : This function Should not be modified, when it is needed,
+ the DSI_IO_WriteCmd could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Initializes the LCD KoD display part by communication in DSI mode in Video Mode
+ * with IC Display Driver OTM8009A (see IC Driver specification for more information).
+ * @param hdsi_eval : pointer on DSI configuration structure
+ * @param hdsivideo_handle : pointer on DSI video mode configuration structure
+ * @retval Status
+ */
+gU8 OTM8009A_Init(gU32 ColorCoding, gU32 orientation)
+{
+ /* Enable CMD2 to access vendor specific commands */
+ /* Enter in command 2 mode and set EXTC to enable address shift function (0x00) */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
+ DSI_IO_WriteCmd( 3, (gU8 *)lcdRegData1);
+
+ /* Enter ORISE Command 2 */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2); /* Shift address to 0x80 */
+ DSI_IO_WriteCmd( 2, (gU8 *)lcdRegData2);
+
+ /////////////////////////////////////////////////////////////////////
+ /* SD_PCH_CTRL - 0xC480h - 129th parameter - Default 0x00 */
+ /* Set SD_PT */
+ /* -> Source output level during porch and non-display area to GND */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData3);
+ OTM8009A_IO_Delay(10);
+ /* Not documented */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData4);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData5);
+ OTM8009A_IO_Delay(10);
+ /////////////////////////////////////////////////////////////////////
+
+ /* PWR_CTRL4 - 0xC4B0h - 178th parameter - Default 0xA8 */
+ /* Set gvdd_en_test */
+ /* -> enable GVDD test mode !!! */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData6);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData7);
+
+ /* PWR_CTRL2 - 0xC590h - 146th parameter - Default 0x79 */
+ /* Set pump 4 vgh voltage */
+ /* -> from 15.0v down to 13.0v */
+ /* Set pump 5 vgh voltage */
+ /* -> from -12.0v downto -9.0v */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData8);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData9);
+
+ /* P_DRV_M - 0xC0B4h - 181th parameter - Default 0x00 */
+ /* -> Column inversion */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData10);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData11);
+
+ /* VCOMDC - 0xD900h - 1st parameter - Default 0x39h */
+ /* VCOM Voltage settings */
+ /* -> from -1.0000v downto -1.2625v */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData12);
+
+ /* Oscillator adjustment for Idle/Normal mode (LPDT only) set to 65Hz (default is 60Hz) */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData13);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData14);
+
+ /* Video mode internal */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData15);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData16);
+
+ /* PWR_CTRL2 - 0xC590h - 147h parameter - Default 0x00 */
+ /* Set pump 4&5 x6 */
+ /* -> ONLY VALID when PUMP4_EN_ASDM_HV = "0" */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData17);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData18);
+
+ /* PWR_CTRL2 - 0xC590h - 150th parameter - Default 0x33h */
+ /* Change pump4 clock ratio */
+ /* -> from 1 line to 1/2 line */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData19);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData9);
+
+ /* GVDD/NGVDD settings */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
+ DSI_IO_WriteCmd( 2, (gU8 *)lcdRegData5);
+
+ /* PWR_CTRL2 - 0xC590h - 149th parameter - Default 0x33h */
+ /* Rewrite the default value ! */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData20);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData21);
+
+ /* Panel display timing Setting 3 */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData22);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData23);
+
+ /* Power control 1 */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData24);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData25);
+
+ /* Source driver precharge */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData13);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData26);
+
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData15);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData27);
+
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData28);
+ DSI_IO_WriteCmd( 2, (gU8 *)lcdRegData6);
+
+ /* GOAVST */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
+ DSI_IO_WriteCmd( 6, (gU8 *)lcdRegData7);
+
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData29);
+ DSI_IO_WriteCmd( 14, (gU8 *)lcdRegData8);
+
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData30);
+ DSI_IO_WriteCmd( 14, (gU8 *)lcdRegData9);
+
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData31);
+ DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData10);
+
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData32);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData46);
+
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
+ DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData11);
+
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData33);
+ DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData12);
+
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData29);
+ DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData13);
+
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData30);
+ DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData14);
+
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData31);
+ DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData15);
+
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData32);
+ DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData16);
+
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData34);
+ DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData17);
+
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData35);
+ DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData18);
+
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
+ DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData19);
+
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData33);
+ DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData20);
+
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData29);
+ DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData21);
+
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData30);
+ DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData22);
+
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData31);
+ DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData23);
+
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData32);
+ DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData24);
+
+ /////////////////////////////////////////////////////////////////////////////
+ /* PWR_CTRL1 - 0xc580h - 130th parameter - default 0x00 */
+ /* Pump 1 min and max DM */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData13);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData47);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData48);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData49);
+ /////////////////////////////////////////////////////////////////////////////
+
+ /* CABC LEDPWM frequency adjusted to 19,5kHz */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData50);
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData51);
+
+ /* Exit CMD2 mode */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
+ DSI_IO_WriteCmd( 3, (gU8 *)lcdRegData25);
+
+ /*************************************************************************** */
+ /* Standard DCS Initialization TO KEEP CAN BE DONE IN HSDT */
+ /*************************************************************************** */
+
+ /* NOP - goes back to DCS std command ? */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
+
+ /* Gamma correction 2.2+ table (HSDT possible) */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
+ DSI_IO_WriteCmd( 16, (gU8 *)lcdRegData3);
+
+ /* Gamma correction 2.2- table (HSDT possible) */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
+ DSI_IO_WriteCmd( 16, (gU8 *)lcdRegData4);
+
+ /* Send Sleep Out command to display : no parameter */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData36);
+
+ /* Wait for sleep out exit */
+ OTM8009A_IO_Delay(120);
+
+ switch(ColorCoding)
+ {
+ case OTM8009A_FORMAT_RBG565 :
+ /* Set Pixel color format to RGB565 */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData37);
+ break;
+ case OTM8009A_FORMAT_RGB888 :
+ /* Set Pixel color format to RGB888 */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData38);
+ break;
+ default :
+ break;
+ }
+
+ /* Send command to configure display in landscape orientation mode. By default
+ the orientation mode is portrait */
+ if(orientation == OTM8009A_ORIENTATION_LANDSCAPE)
+ {
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData39);
+ DSI_IO_WriteCmd( 4, (gU8 *)lcdRegData27);
+ DSI_IO_WriteCmd( 4, (gU8 *)lcdRegData28);
+ }
+
+ /** CABC : Content Adaptive Backlight Control section start >> */
+ /* Note : defaut is 0 (lowest Brightness), 0xFF is highest Brightness, try 0x7F : intermediate value */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData40);
+
+ /* defaut is 0, try 0x2C - Brightness Control Block, Display Dimming & BackLight on */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData41);
+
+ /* defaut is 0, try 0x02 - image Content based Adaptive Brightness [Still Picture] */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData42);
+
+ /* defaut is 0 (lowest Brightness), 0xFF is highest Brightness */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData43);
+
+ /** CABC : Content Adaptive Backlight Control section end << */
+
+ /* Send Command Display On */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData44);
+
+ /* NOP command */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
+
+ /* Send Command GRAM memory write (no parameters) : this initiates frame write via other DSI commands sent by */
+ /* DSI host from LTDC incoming pixels in video mode */
+ DSI_IO_WriteCmd(0, (gU8 *)ShortRegData45);
+
+ return 0;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/boards/base/STM32F469i-Discovery/otm8009a.h b/boards/base/STM32F469i-Discovery/otm8009a.h
index 52fc107c..9e5ea951 100644
--- a/boards/base/STM32F469i-Discovery/otm8009a.h
+++ b/boards/base/STM32F469i-Discovery/otm8009a.h
@@ -1,224 +1,224 @@
-/**
- ******************************************************************************
- * @file otm8009a.h
- * @author MCD Application Team
- * @version V1.0.2
- * @date 27-January-2017
- * @brief This file contains all the constants parameters for the OTM8009A
- * which is the LCD Driver for KoD KM-040TMP-02-0621 (WVGA)
- * DSI LCD Display.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __OTM8009A_H
-#define __OTM8009A_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include
-/** @addtogroup BSP
- * @{
- */
-
-/** @addtogroup Components
- * @{
- */
-
-/** @addtogroup otm8009a
- * @{
- */
-
-/** @addtogroup OTM8009A_Exported_Variables
- * @{
- */
-
-#if defined ( __GNUC__ )
-#ifndef __weak
-#define __weak __attribute__((weak))
-#endif /* __weak */
-#endif /* __GNUC__ */
-
-/**
- * @brief LCD_OrientationTypeDef
- * Possible values of Display Orientation
- */
-#define OTM8009A_ORIENTATION_PORTRAIT ((gU32)0x00) /* Portrait orientation choice of LCD screen */
-#define OTM8009A_ORIENTATION_LANDSCAPE ((gU32)0x01) /* Landscape orientation choice of LCD screen */
-
-/**
- * @brief Possible values of
- * pixel data format (ie color coding) transmitted on DSI Data lane in DSI packets
- */
-#define OTM8009A_FORMAT_RGB888 ((gU32)0x00) /* Pixel format chosen is RGB888 : 24 bpp */
-#define OTM8009A_FORMAT_RBG565 ((gU32)0x02) /* Pixel format chosen is RGB565 : 16 bpp */
-
-/**
- * @brief otm8009a_480x800 Size
- */
-
-/* Width and Height in Portrait mode */
-#define OTM8009A_480X800_WIDTH ((gU16)480) /* LCD PIXEL WIDTH */
-#define OTM8009A_480X800_HEIGHT ((gU16)800) /* LCD PIXEL HEIGHT */
-
-/* Width and Height in Landscape mode */
-#define OTM8009A_800X480_WIDTH ((gU16)800) /* LCD PIXEL WIDTH */
-#define OTM8009A_800X480_HEIGHT ((gU16)480) /* LCD PIXEL HEIGHT */
-
-/**
- * @brief OTM8009A_480X800 Timing parameters for Portrait orientation mode
- */
-#define OTM8009A_480X800_HSYNC ((gU16)2) /* Horizontal synchronization */
-#define OTM8009A_480X800_HBP ((gU16)34) /* Horizontal back porch */
-#define OTM8009A_480X800_HFP ((gU16)34) /* Horizontal front porch */
-#define OTM8009A_480X800_VSYNC ((gU16)1) /* Vertical synchronization */
-#define OTM8009A_480X800_VBP ((gU16)15) /* Vertical back porch */
-#define OTM8009A_480X800_VFP ((gU16)16) /* Vertical front porch */
-
-/**
- * @brief OTM8009A_800X480 Timing parameters for Landscape orientation mode
- * Same values as for Portrait mode in fact.
- */
-#define OTM8009A_800X480_HSYNC OTM8009A_480X800_VSYNC /* Horizontal synchronization */
-#define OTM8009A_800X480_HBP OTM8009A_480X800_VBP /* Horizontal back porch */
-#define OTM8009A_800X480_HFP OTM8009A_480X800_VFP /* Horizontal front porch */
-#define OTM8009A_800X480_VSYNC OTM8009A_480X800_HSYNC /* Vertical synchronization */
-#define OTM8009A_800X480_VBP OTM8009A_480X800_HBP /* Vertical back porch */
-#define OTM8009A_800X480_VFP OTM8009A_480X800_HFP /* Vertical front porch */
-
-
-/* List of OTM8009A used commands */
-/* Detailed in OTM8009A Data Sheet 'DATA_SHEET_OTM8009A_V0 92.pdf' */
-/* Version of 14 June 2012 */
-#define OTM8009A_CMD_NOP 0x00 /* NOP command */
-#define OTM8009A_CMD_SWRESET 0x01 /* Sw reset command */
-#define OTM8009A_CMD_RDDMADCTL 0x0B /* Read Display MADCTR command : read memory display access ctrl */
-#define OTM8009A_CMD_RDDCOLMOD 0x0C /* Read Display pixel format */
-#define OTM8009A_CMD_SLPIN 0x10 /* Sleep In command */
-#define OTM8009A_CMD_SLPOUT 0x11 /* Sleep Out command */
-#define OTM8009A_CMD_PTLON 0x12 /* Partial mode On command */
-
-#define OTM8009A_CMD_DISPOFF 0x28 /* Display Off command */
-#define OTM8009A_CMD_DISPON 0x29 /* Display On command */
-
-#define OTM8009A_CMD_CASET 0x2A /* Column address set command */
-#define OTM8009A_CMD_PASET 0x2B /* Page address set command */
-
-#define OTM8009A_CMD_RAMWR 0x2C /* Memory (GRAM) write command */
-#define OTM8009A_CMD_RAMRD 0x2E /* Memory (GRAM) read command */
-
-#define OTM8009A_CMD_PLTAR 0x30 /* Partial area command (4 parameters) */
-
-#define OTM8009A_CMD_TEOFF 0x34 /* Tearing Effect Line Off command : command with no parameter */
-
-#define OTM8009A_CMD_TEEON 0x35 /* Tearing Effect Line On command : command with 1 parameter 'TELOM' */
-
-/* Parameter TELOM : Tearing Effect Line Output Mode : possible values */
-#define OTM8009A_TEEON_TELOM_VBLANKING_INFO_ONLY 0x00
-#define OTM8009A_TEEON_TELOM_VBLANKING_AND_HBLANKING_INFO 0x01
-
-#define OTM8009A_CMD_MADCTR 0x36 /* Memory Access write control command */
-
-/* Possible used values of MADCTR */
-#define OTM8009A_MADCTR_MODE_PORTRAIT 0x00
-#define OTM8009A_MADCTR_MODE_LANDSCAPE 0x60 /* MY = 0, MX = 1, MV = 1, ML = 0, RGB = 0 */
-
-#define OTM8009A_CMD_IDMOFF 0x38 /* Idle mode Off command */
-#define OTM8009A_CMD_IDMON 0x39 /* Idle mode On command */
-
-#define OTM8009A_CMD_COLMOD 0x3A /* Interface Pixel format command */
-
-/* Possible values of COLMOD parameter corresponding to used pixel formats */
-#define OTM8009A_COLMOD_RGB565 0x55
-#define OTM8009A_COLMOD_RGB888 0x77
-
-#define OTM8009A_CMD_RAMWRC 0x3C /* Memory write continue command */
-#define OTM8009A_CMD_RAMRDC 0x3E /* Memory read continue command */
-
-#define OTM8009A_CMD_WRTESCN 0x44 /* Write Tearing Effect Scan line command */
-#define OTM8009A_CMD_RDSCNL 0x45 /* Read Tearing Effect Scan line command */
-
-/* CABC Management : ie : Content Adaptive Back light Control in IC OTM8009a */
-#define OTM8009A_CMD_WRDISBV 0x51 /* Write Display Brightness command */
-#define OTM8009A_CMD_WRCTRLD 0x53 /* Write CTRL Display command */
-#define OTM8009A_CMD_WRCABC 0x55 /* Write Content Adaptive Brightness command */
-#define OTM8009A_CMD_WRCABCMB 0x5E /* Write CABC Minimum Brightness command */
-
-/**
- * @brief OTM8009A_480X800 frequency divider
- */
-#define OTM8009A_480X800_FREQUENCY_DIVIDER 2 /* LCD Frequency divider */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup OTM8009A_Exported_Macros OTM8009A Exported Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup OTM8009A_Exported_Functions
- * @{
- */
-void DSI_IO_WriteCmd(gU32 NbrParams, gU8 *pParams);
-gU8 OTM8009A_Init(gU32 ColorCoding, gU32 orientation);
-void OTM8009A_IO_Delay(gU32 Delay);
-/**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __OTM8009A_480X800_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file otm8009a.h
+ * @author MCD Application Team
+ * @version V1.0.2
+ * @date 27-January-2017
+ * @brief This file contains all the constants parameters for the OTM8009A
+ * which is the LCD Driver for KoD KM-040TMP-02-0621 (WVGA)
+ * DSI LCD Display.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2017 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __OTM8009A_H
+#define __OTM8009A_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include
+/** @addtogroup BSP
+ * @{
+ */
+
+/** @addtogroup Components
+ * @{
+ */
+
+/** @addtogroup otm8009a
+ * @{
+ */
+
+/** @addtogroup OTM8009A_Exported_Variables
+ * @{
+ */
+
+#if defined ( __GNUC__ )
+#ifndef __weak
+#define __weak __attribute__((weak))
+#endif /* __weak */
+#endif /* __GNUC__ */
+
+/**
+ * @brief LCD_OrientationTypeDef
+ * Possible values of Display Orientation
+ */
+#define OTM8009A_ORIENTATION_PORTRAIT ((gU32)0x00) /* Portrait orientation choice of LCD screen */
+#define OTM8009A_ORIENTATION_LANDSCAPE ((gU32)0x01) /* Landscape orientation choice of LCD screen */
+
+/**
+ * @brief Possible values of
+ * pixel data format (ie color coding) transmitted on DSI Data lane in DSI packets
+ */
+#define OTM8009A_FORMAT_RGB888 ((gU32)0x00) /* Pixel format chosen is RGB888 : 24 bpp */
+#define OTM8009A_FORMAT_RBG565 ((gU32)0x02) /* Pixel format chosen is RGB565 : 16 bpp */
+
+/**
+ * @brief otm8009a_480x800 Size
+ */
+
+/* Width and Height in Portrait mode */
+#define OTM8009A_480X800_WIDTH ((gU16)480) /* LCD PIXEL WIDTH */
+#define OTM8009A_480X800_HEIGHT ((gU16)800) /* LCD PIXEL HEIGHT */
+
+/* Width and Height in Landscape mode */
+#define OTM8009A_800X480_WIDTH ((gU16)800) /* LCD PIXEL WIDTH */
+#define OTM8009A_800X480_HEIGHT ((gU16)480) /* LCD PIXEL HEIGHT */
+
+/**
+ * @brief OTM8009A_480X800 Timing parameters for Portrait orientation mode
+ */
+#define OTM8009A_480X800_HSYNC ((gU16)2) /* Horizontal synchronization */
+#define OTM8009A_480X800_HBP ((gU16)34) /* Horizontal back porch */
+#define OTM8009A_480X800_HFP ((gU16)34) /* Horizontal front porch */
+#define OTM8009A_480X800_VSYNC ((gU16)1) /* Vertical synchronization */
+#define OTM8009A_480X800_VBP ((gU16)15) /* Vertical back porch */
+#define OTM8009A_480X800_VFP ((gU16)16) /* Vertical front porch */
+
+/**
+ * @brief OTM8009A_800X480 Timing parameters for Landscape orientation mode
+ * Same values as for Portrait mode in fact.
+ */
+#define OTM8009A_800X480_HSYNC OTM8009A_480X800_VSYNC /* Horizontal synchronization */
+#define OTM8009A_800X480_HBP OTM8009A_480X800_VBP /* Horizontal back porch */
+#define OTM8009A_800X480_HFP OTM8009A_480X800_VFP /* Horizontal front porch */
+#define OTM8009A_800X480_VSYNC OTM8009A_480X800_HSYNC /* Vertical synchronization */
+#define OTM8009A_800X480_VBP OTM8009A_480X800_HBP /* Vertical back porch */
+#define OTM8009A_800X480_VFP OTM8009A_480X800_HFP /* Vertical front porch */
+
+
+/* List of OTM8009A used commands */
+/* Detailed in OTM8009A Data Sheet 'DATA_SHEET_OTM8009A_V0 92.pdf' */
+/* Version of 14 June 2012 */
+#define OTM8009A_CMD_NOP 0x00 /* NOP command */
+#define OTM8009A_CMD_SWRESET 0x01 /* Sw reset command */
+#define OTM8009A_CMD_RDDMADCTL 0x0B /* Read Display MADCTR command : read memory display access ctrl */
+#define OTM8009A_CMD_RDDCOLMOD 0x0C /* Read Display pixel format */
+#define OTM8009A_CMD_SLPIN 0x10 /* Sleep In command */
+#define OTM8009A_CMD_SLPOUT 0x11 /* Sleep Out command */
+#define OTM8009A_CMD_PTLON 0x12 /* Partial mode On command */
+
+#define OTM8009A_CMD_DISPOFF 0x28 /* Display Off command */
+#define OTM8009A_CMD_DISPON 0x29 /* Display On command */
+
+#define OTM8009A_CMD_CASET 0x2A /* Column address set command */
+#define OTM8009A_CMD_PASET 0x2B /* Page address set command */
+
+#define OTM8009A_CMD_RAMWR 0x2C /* Memory (GRAM) write command */
+#define OTM8009A_CMD_RAMRD 0x2E /* Memory (GRAM) read command */
+
+#define OTM8009A_CMD_PLTAR 0x30 /* Partial area command (4 parameters) */
+
+#define OTM8009A_CMD_TEOFF 0x34 /* Tearing Effect Line Off command : command with no parameter */
+
+#define OTM8009A_CMD_TEEON 0x35 /* Tearing Effect Line On command : command with 1 parameter 'TELOM' */
+
+/* Parameter TELOM : Tearing Effect Line Output Mode : possible values */
+#define OTM8009A_TEEON_TELOM_VBLANKING_INFO_ONLY 0x00
+#define OTM8009A_TEEON_TELOM_VBLANKING_AND_HBLANKING_INFO 0x01
+
+#define OTM8009A_CMD_MADCTR 0x36 /* Memory Access write control command */
+
+/* Possible used values of MADCTR */
+#define OTM8009A_MADCTR_MODE_PORTRAIT 0x00
+#define OTM8009A_MADCTR_MODE_LANDSCAPE 0x60 /* MY = 0, MX = 1, MV = 1, ML = 0, RGB = 0 */
+
+#define OTM8009A_CMD_IDMOFF 0x38 /* Idle mode Off command */
+#define OTM8009A_CMD_IDMON 0x39 /* Idle mode On command */
+
+#define OTM8009A_CMD_COLMOD 0x3A /* Interface Pixel format command */
+
+/* Possible values of COLMOD parameter corresponding to used pixel formats */
+#define OTM8009A_COLMOD_RGB565 0x55
+#define OTM8009A_COLMOD_RGB888 0x77
+
+#define OTM8009A_CMD_RAMWRC 0x3C /* Memory write continue command */
+#define OTM8009A_CMD_RAMRDC 0x3E /* Memory read continue command */
+
+#define OTM8009A_CMD_WRTESCN 0x44 /* Write Tearing Effect Scan line command */
+#define OTM8009A_CMD_RDSCNL 0x45 /* Read Tearing Effect Scan line command */
+
+/* CABC Management : ie : Content Adaptive Back light Control in IC OTM8009a */
+#define OTM8009A_CMD_WRDISBV 0x51 /* Write Display Brightness command */
+#define OTM8009A_CMD_WRCTRLD 0x53 /* Write CTRL Display command */
+#define OTM8009A_CMD_WRCABC 0x55 /* Write Content Adaptive Brightness command */
+#define OTM8009A_CMD_WRCABCMB 0x5E /* Write CABC Minimum Brightness command */
+
+/**
+ * @brief OTM8009A_480X800 frequency divider
+ */
+#define OTM8009A_480X800_FREQUENCY_DIVIDER 2 /* LCD Frequency divider */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup OTM8009A_Exported_Macros OTM8009A Exported Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup OTM8009A_Exported_Functions
+ * @{
+ */
+void DSI_IO_WriteCmd(gU32 NbrParams, gU8 *pParams);
+gU8 OTM8009A_Init(gU32 ColorCoding, gU32 orientation);
+void OTM8009A_IO_Delay(gU32 Delay);
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __OTM8009A_480X800_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/boards/base/STM32F469i-Discovery/startup_stm32f469xx.s b/boards/base/STM32F469i-Discovery/startup_stm32f469xx.s
index 8dded6a0..8d266a77 100644
--- a/boards/base/STM32F469i-Discovery/startup_stm32f469xx.s
+++ b/boards/base/STM32F469i-Discovery/startup_stm32f469xx.s
@@ -1,589 +1,589 @@
-/**
- ******************************************************************************
- * @file startup_stm32f469xx.s
- * @author MCD Application Team
- * @version V1.1.0
- * @date 17-February-2017
- * @brief STM32F469xx Devices vector table for GCC based toolchains.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M4 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m4
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
-
-/**
- * @brief This is the code that gets called when the processor first
- * starts execution following a reset event. Only the absolutely
- * necessary set is performed, after which the application
- * supplied main() routine is called.
- * @param None
- * @retval : None
-*/
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr sp, =_estack /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
- bl SystemInit
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application's entry point.*/
- bl main
- bx lr
-
-.global WeakCInit
-WeakCInit:
- mov pc, lr
-
- .weak _init
- .thumb_set _init,WeakCInit
-
-.global WeakCExit
-WeakCExit:
- b WeakCExit
-
- .weak exit
- .thumb_set exit,WeakCExit
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- * @param None
- * @retval None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-*******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
- g_pfnVectors:
- .word _estack
- .word Reset_Handler
-
- .word NMI_Handler
- .word HardFault_Handler
- .word MemManage_Handler
- .word BusFault_Handler
- .word UsageFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word DebugMon_Handler
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
-
- /* External Interrupts */
- .word WWDG_IRQHandler /* Window WatchDog */
- .word PVD_IRQHandler /* PVD through EXTI Line detection */
- .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
- .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
- .word FLASH_IRQHandler /* FLASH */
- .word RCC_IRQHandler /* RCC */
- .word EXTI0_IRQHandler /* EXTI Line0 */
- .word EXTI1_IRQHandler /* EXTI Line1 */
- .word EXTI2_IRQHandler /* EXTI Line2 */
- .word EXTI3_IRQHandler /* EXTI Line3 */
- .word EXTI4_IRQHandler /* EXTI Line4 */
- .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
- .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
- .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
- .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
- .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
- .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
- .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
- .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
- .word CAN1_TX_IRQHandler /* CAN1 TX */
- .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
- .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
- .word CAN1_SCE_IRQHandler /* CAN1 SCE */
- .word EXTI9_5_IRQHandler /* External Line[9:5]s */
- .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
- .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
- .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
- .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .word TIM2_IRQHandler /* TIM2 */
- .word TIM3_IRQHandler /* TIM3 */
- .word TIM4_IRQHandler /* TIM4 */
- .word I2C1_EV_IRQHandler /* I2C1 Event */
- .word I2C1_ER_IRQHandler /* I2C1 Error */
- .word I2C2_EV_IRQHandler /* I2C2 Event */
- .word I2C2_ER_IRQHandler /* I2C2 Error */
- .word SPI1_IRQHandler /* SPI1 */
- .word SPI2_IRQHandler /* SPI2 */
- .word USART1_IRQHandler /* USART1 */
- .word USART2_IRQHandler /* USART2 */
- .word USART3_IRQHandler /* USART3 */
- .word EXTI15_10_IRQHandler /* External Line[15:10]s */
- .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
- .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
- .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
- .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
- .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
- .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
- .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
- .word FMC_IRQHandler /* FMC */
- .word SDIO_IRQHandler /* SDIO */
- .word TIM5_IRQHandler /* TIM5 */
- .word SPI3_IRQHandler /* SPI3 */
- .word UART4_IRQHandler /* UART4 */
- .word UART5_IRQHandler /* UART5 */
- .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
- .word TIM7_IRQHandler /* TIM7 */
- .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
- .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
- .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
- .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
- .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
- .word ETH_IRQHandler /* Ethernet */
- .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
- .word CAN2_TX_IRQHandler /* CAN2 TX */
- .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
- .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
- .word CAN2_SCE_IRQHandler /* CAN2 SCE */
- .word OTG_FS_IRQHandler /* USB OTG FS */
- .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
- .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
- .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
- .word USART6_IRQHandler /* USART6 */
- .word I2C3_EV_IRQHandler /* I2C3 event */
- .word I2C3_ER_IRQHandler /* I2C3 error */
- .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
- .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
- .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
- .word OTG_HS_IRQHandler /* USB OTG HS */
- .word DCMI_IRQHandler /* DCMI */
- .word 0 /* Reserved */
- .word HASH_RNG_IRQHandler /* Hash and Rng */
- .word FPU_IRQHandler /* FPU */
- .word UART7_IRQHandler /* UART7 */
- .word UART8_IRQHandler /* UART8 */
- .word SPI4_IRQHandler /* SPI4 */
- .word SPI5_IRQHandler /* SPI5 */
- .word SPI6_IRQHandler /* SPI6 */
- .word SAI1_IRQHandler /* SAI1 */
- .word LTDC_IRQHandler /* LTDC */
- .word LTDC_ER_IRQHandler /* LTDC error */
- .word DMA2D_IRQHandler /* DMA2D */
- .word QUADSPI_IRQHandler /* QUADSPI */
- .word DSI_IRQHandler /* DSI */
-
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak MemManage_Handler
- .thumb_set MemManage_Handler,Default_Handler
-
- .weak BusFault_Handler
- .thumb_set BusFault_Handler,Default_Handler
-
- .weak UsageFault_Handler
- .thumb_set UsageFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak DebugMon_Handler
- .thumb_set DebugMon_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_IRQHandler
- .thumb_set PVD_IRQHandler,Default_Handler
-
- .weak TAMP_STAMP_IRQHandler
- .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
-
- .weak RTC_WKUP_IRQHandler
- .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_IRQHandler
- .thumb_set EXTI0_IRQHandler,Default_Handler
-
- .weak EXTI1_IRQHandler
- .thumb_set EXTI1_IRQHandler,Default_Handler
-
- .weak EXTI2_IRQHandler
- .thumb_set EXTI2_IRQHandler,Default_Handler
-
- .weak EXTI3_IRQHandler
- .thumb_set EXTI3_IRQHandler,Default_Handler
-
- .weak EXTI4_IRQHandler
- .thumb_set EXTI4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream0_IRQHandler
- .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
-
- .weak DMA1_Stream1_IRQHandler
- .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
-
- .weak DMA1_Stream2_IRQHandler
- .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
-
- .weak DMA1_Stream3_IRQHandler
- .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
-
- .weak DMA1_Stream4_IRQHandler
- .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream5_IRQHandler
- .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
-
- .weak DMA1_Stream6_IRQHandler
- .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
-
- .weak ADC_IRQHandler
- .thumb_set ADC_IRQHandler,Default_Handler
-
- .weak CAN1_TX_IRQHandler
- .thumb_set CAN1_TX_IRQHandler,Default_Handler
-
- .weak CAN1_RX0_IRQHandler
- .thumb_set CAN1_RX0_IRQHandler,Default_Handler
-
- .weak CAN1_RX1_IRQHandler
- .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
- .weak CAN1_SCE_IRQHandler
- .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
- .weak EXTI9_5_IRQHandler
- .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_TIM9_IRQHandler
- .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
-
- .weak TIM1_UP_TIM10_IRQHandler
- .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
-
- .weak TIM1_TRG_COM_TIM11_IRQHandler
- .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM4_IRQHandler
- .thumb_set TIM4_IRQHandler,Default_Handler
-
- .weak I2C1_EV_IRQHandler
- .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
- .weak I2C1_ER_IRQHandler
- .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
- .weak I2C2_EV_IRQHandler
- .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
- .weak I2C2_ER_IRQHandler
- .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak USART3_IRQHandler
- .thumb_set USART3_IRQHandler,Default_Handler
-
- .weak EXTI15_10_IRQHandler
- .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
- .weak RTC_Alarm_IRQHandler
- .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
- .weak OTG_FS_WKUP_IRQHandler
- .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
-
- .weak TIM8_BRK_TIM12_IRQHandler
- .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
-
- .weak TIM8_UP_TIM13_IRQHandler
- .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
-
- .weak TIM8_TRG_COM_TIM14_IRQHandler
- .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
-
- .weak TIM8_CC_IRQHandler
- .thumb_set TIM8_CC_IRQHandler,Default_Handler
-
- .weak DMA1_Stream7_IRQHandler
- .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
-
- .weak FMC_IRQHandler
- .thumb_set FMC_IRQHandler,Default_Handler
-
- .weak SDIO_IRQHandler
- .thumb_set SDIO_IRQHandler,Default_Handler
-
- .weak TIM5_IRQHandler
- .thumb_set TIM5_IRQHandler,Default_Handler
-
- .weak SPI3_IRQHandler
- .thumb_set SPI3_IRQHandler,Default_Handler
-
- .weak UART4_IRQHandler
- .thumb_set UART4_IRQHandler,Default_Handler
-
- .weak UART5_IRQHandler
- .thumb_set UART5_IRQHandler,Default_Handler
-
- .weak TIM6_DAC_IRQHandler
- .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
- .weak TIM7_IRQHandler
- .thumb_set TIM7_IRQHandler,Default_Handler
-
- .weak DMA2_Stream0_IRQHandler
- .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
-
- .weak DMA2_Stream1_IRQHandler
- .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
-
- .weak DMA2_Stream2_IRQHandler
- .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
-
- .weak DMA2_Stream3_IRQHandler
- .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
-
- .weak DMA2_Stream4_IRQHandler
- .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
-
- .weak ETH_IRQHandler
- .thumb_set ETH_IRQHandler,Default_Handler
-
- .weak ETH_WKUP_IRQHandler
- .thumb_set ETH_WKUP_IRQHandler,Default_Handler
-
- .weak CAN2_TX_IRQHandler
- .thumb_set CAN2_TX_IRQHandler,Default_Handler
-
- .weak CAN2_RX0_IRQHandler
- .thumb_set CAN2_RX0_IRQHandler,Default_Handler
-
- .weak CAN2_RX1_IRQHandler
- .thumb_set CAN2_RX1_IRQHandler,Default_Handler
-
- .weak CAN2_SCE_IRQHandler
- .thumb_set CAN2_SCE_IRQHandler,Default_Handler
-
- .weak OTG_FS_IRQHandler
- .thumb_set OTG_FS_IRQHandler,Default_Handler
-
- .weak DMA2_Stream5_IRQHandler
- .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
-
- .weak DMA2_Stream6_IRQHandler
- .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
-
- .weak DMA2_Stream7_IRQHandler
- .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
-
- .weak USART6_IRQHandler
- .thumb_set USART6_IRQHandler,Default_Handler
-
- .weak I2C3_EV_IRQHandler
- .thumb_set I2C3_EV_IRQHandler,Default_Handler
-
- .weak I2C3_ER_IRQHandler
- .thumb_set I2C3_ER_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_OUT_IRQHandler
- .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
-
- .weak OTG_HS_EP1_IN_IRQHandler
- .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
-
- .weak OTG_HS_WKUP_IRQHandler
- .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
-
- .weak OTG_HS_IRQHandler
- .thumb_set OTG_HS_IRQHandler,Default_Handler
-
- .weak DCMI_IRQHandler
- .thumb_set DCMI_IRQHandler,Default_Handler
-
- .weak HASH_RNG_IRQHandler
- .thumb_set HASH_RNG_IRQHandler,Default_Handler
-
- .weak FPU_IRQHandler
- .thumb_set FPU_IRQHandler,Default_Handler
-
- .weak UART7_IRQHandler
- .thumb_set UART7_IRQHandler,Default_Handler
-
- .weak UART8_IRQHandler
- .thumb_set UART8_IRQHandler,Default_Handler
-
- .weak SPI4_IRQHandler
- .thumb_set SPI4_IRQHandler,Default_Handler
-
- .weak SPI5_IRQHandler
- .thumb_set SPI5_IRQHandler,Default_Handler
-
- .weak SPI6_IRQHandler
- .thumb_set SPI6_IRQHandler,Default_Handler
-
- .weak SAI1_IRQHandler
- .thumb_set SAI1_IRQHandler,Default_Handler
-
- .weak LTDC_IRQHandler
- .thumb_set LTDC_IRQHandler,Default_Handler
-
- .weak LTDC_ER_IRQHandler
- .thumb_set LTDC_ER_IRQHandler,Default_Handler
-
- .weak DMA2D_IRQHandler
- .thumb_set DMA2D_IRQHandler,Default_Handler
-
- .weak QUADSPI_IRQHandler
- .thumb_set QUADSPI_IRQHandler,Default_Handler
-
- .weak DSI_IRQHandler
- .thumb_set DSI_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
-
-
-
-
-
-
+/**
+ ******************************************************************************
+ * @file startup_stm32f469xx.s
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 17-February-2017
+ * @brief STM32F469xx Devices vector table for GCC based toolchains.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2017 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+
+.global WeakCInit
+WeakCInit:
+ mov pc, lr
+
+ .weak _init
+ .thumb_set _init,WeakCInit
+
+.global WeakCExit
+WeakCExit:
+ b WeakCExit
+
+ .weak exit
+ .thumb_set exit,WeakCExit
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+ g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_IRQHandler /* PVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word CAN1_TX_IRQHandler /* CAN1 TX */
+ .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
+ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
+ .word CAN1_SCE_IRQHandler /* CAN1 SCE */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
+ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
+ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDIO_IRQHandler /* SDIO */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word ETH_IRQHandler /* Ethernet */
+ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .word CAN2_TX_IRQHandler /* CAN2 TX */
+ .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
+ .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
+ .word CAN2_SCE_IRQHandler /* CAN2 SCE */
+ .word OTG_FS_IRQHandler /* USB OTG FS */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_IRQHandler /* DCMI */
+ .word 0 /* Reserved */
+ .word HASH_RNG_IRQHandler /* Hash and Rng */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word LTDC_IRQHandler /* LTDC */
+ .word LTDC_ER_IRQHandler /* LTDC error */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word QUADSPI_IRQHandler /* QUADSPI */
+ .word DSI_IRQHandler /* DSI */
+
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak CAN1_TX_IRQHandler
+ .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+ .weak CAN1_RX0_IRQHandler
+ .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM9_IRQHandler
+ .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM10_IRQHandler
+ .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM11_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak OTG_FS_WKUP_IRQHandler
+ .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDIO_IRQHandler
+ .thumb_set SDIO_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak ETH_IRQHandler
+ .thumb_set ETH_IRQHandler,Default_Handler
+
+ .weak ETH_WKUP_IRQHandler
+ .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+
+ .weak CAN2_TX_IRQHandler
+ .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+ .weak CAN2_RX0_IRQHandler
+ .thumb_set CAN2_RX0_IRQHandler,Default_Handler
+
+ .weak CAN2_RX1_IRQHandler
+ .thumb_set CAN2_RX1_IRQHandler,Default_Handler
+
+ .weak CAN2_SCE_IRQHandler
+ .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+ .weak OTG_FS_IRQHandler
+ .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_IRQHandler
+ .thumb_set DCMI_IRQHandler,Default_Handler
+
+ .weak HASH_RNG_IRQHandler
+ .thumb_set HASH_RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak QUADSPI_IRQHandler
+ .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+ .weak DSI_IRQHandler
+ .thumb_set DSI_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
+
+
+
+
diff --git a/boards/base/STM32F469i-Discovery/stm32f469i_discovery_sdram.c b/boards/base/STM32F469i-Discovery/stm32f469i_discovery_sdram.c
index eeda4fdd..b571d99f 100644
--- a/boards/base/STM32F469i-Discovery/stm32f469i_discovery_sdram.c
+++ b/boards/base/STM32F469i-Discovery/stm32f469i_discovery_sdram.c
@@ -1,529 +1,529 @@
-/**
- ******************************************************************************
- * @file stm32469i_discovery_sdram.c
- * @author MCD Application Team
- * @version V2.0.0
- * @date 27-January-2017
- * @brief This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory
- * device mounted on STM32469I-Discovery board.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* File Info : -----------------------------------------------------------------
- User NOTES
-1. How To use this driver:
---------------------------
- - This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted
- on STM32469I-Discovery board.
- - This driver does not need a specific component driver for the SDRAM device
- to be included with.
-
-2. Driver description:
----------------------
- + Initialization steps:
- o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This
- function includes the MSP layer hardware resources initialization and the
- FMC controller configuration to interface with the external SDRAM memory.
- o It contains the SDRAM initialization sequence to program the SDRAM external
- device using the function BSP_SDRAM_Initialization_sequence(). Note that this
- sequence is standard for all SDRAM devices, but can include some differences
- from a device to another. If it is the case, the right sequence should be
- implemented separately.
-
- + SDRAM read/write operations
- o SDRAM external memory can be accessed with read/write operations once it is
- initialized.
- Read/write operation can be performed with AHB access using the functions
- BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions
- BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA().
- o The AHB access is performed with 32-bit width transaction, the DMA transfer
- configuration is fixed at single (no burst) word transfer (see the
- BSP_SDRAM_MspInit() weak function).
- o User can implement his own functions for read/write access with his desired
- configurations.
- o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler()
- is called in IRQ handler file, to serve the generated interrupt once the DMA
- transfer is complete.
- o You can send a command to the SDRAM device in runtime using the function
- BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between
- the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure.
-
-------------------------------------------------------------------------------*/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f469i_discovery_sdram.h"
-
-/** @addtogroup BSP
- * @{
- */
-
-/** @addtogroup STM32469I_Discovery
- * @{
- */
-
-/** @defgroup STM32469I-Discovery_SDRAM STM32469I Discovery SDRAM
- * @{
- */
-
-/** @defgroup STM32469I-Discovery_SDRAM_Private_Types_Definitions STM32469I Discovery SDRAM Private TypesDef
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup STM32469I-Discovery_SDRAM_Private_Defines STM32469I Discovery SDRAM Private Defines
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup STM32469I-Discovery_SDRAM_Private_Macros STM32469I Discovery SDRAM Private Macros
- * @{
- */
-/**
- * @}
- */
-
-/** @defgroup STM32469I-Discovery_SDRAM_Private_Variables STM32469I Discovery SDRAM Private Variables
- * @{
- */
-static SDRAM_HandleTypeDef sdramHandle;
-static FMC_SDRAM_TimingTypeDef Timing;
-static FMC_SDRAM_CommandTypeDef Command;
-/**
- * @}
- */
-
-/** @defgroup STM32469I-Discovery_SDRAM_Private_Function_Prototypes STM32469I Discovery SDRAM Private Prototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup STM32469I-Discovery_SDRAM_Private_Functions STM32469I Discovery SDRAM Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @defgroup STM32469I_Discovery_SDRAM_Exported_Functions STM32469I Discovery SDRAM Exported Functions
- * @{
- */
-
-/**
- * @brief Initializes the SDRAM device.
- * @retval SDRAM status
- */
-gU8 BSP_SDRAM_Init(void)
-{
- static gU8 sdramstatus = SDRAM_ERROR;
-
- /* SDRAM device configuration */
- sdramHandle.Instance = FMC_SDRAM_DEVICE;
-
- /* Timing configuration for 90 MHz as SD clock frequency (System clock is up to 180 MHz) */
- Timing.LoadToActiveDelay = 2;
- Timing.ExitSelfRefreshDelay = 7;
- Timing.SelfRefreshTime = 4;
- Timing.RowCycleDelay = 7;
- Timing.WriteRecoveryTime = 2;
- Timing.RPDelay = 2;
- Timing.RCDDelay = 2;
-
- sdramHandle.Init.SDBank = FMC_SDRAM_BANK1;
- sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
- sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
- sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
- sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
- sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
- sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
- sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD;
- sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
- sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
-
- /* SDRAM controller initialization */
- /* __weak function can be surcharged by the application code */
- BSP_SDRAM_MspInit(&sdramHandle, (void *)NULL);
- if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)
- {
- sdramstatus = SDRAM_ERROR;
- }
- else
- {
- sdramstatus = SDRAM_OK;
- }
-
- /* SDRAM initialization sequence */
- BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
-
- return sdramstatus;
-}
-
-/**
- * @brief DeInitializes the SDRAM device.
- * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
- */
-gU8 BSP_SDRAM_DeInit(void)
-{
- static gU8 sdramstatus = SDRAM_ERROR;
-
- /* SDRAM device configuration */
- sdramHandle.Instance = FMC_SDRAM_DEVICE;
-
- if(HAL_SDRAM_DeInit(&sdramHandle) == HAL_OK)
- {
- sdramstatus = SDRAM_OK;
-
- /* SDRAM controller De-initialization */
- BSP_SDRAM_MspDeInit(&sdramHandle, (void *)NULL);
- }
-
- return sdramstatus;
-}
-
-
-/**
- * @brief Programs the SDRAM device.
- * @param RefreshCount: SDRAM refresh counter value
- */
-void BSP_SDRAM_Initialization_sequence(gU32 RefreshCount)
-{
- __IO gU32 tmpmrd = 0;
-
- /* Step 1: Configure a clock configuration enable command */
- Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
- Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
- Command.AutoRefreshNumber = 1;
- Command.ModeRegisterDefinition = 0;
-
- /* Send the command */
- HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
-
- /* Step 2: Insert 100 us minimum delay */
- /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
- HAL_Delay(1);
-
- /* Step 3: Configure a PALL (precharge all) command */
- Command.CommandMode = FMC_SDRAM_CMD_PALL;
- Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
- Command.AutoRefreshNumber = 1;
- Command.ModeRegisterDefinition = 0;
-
- /* Send the command */
- HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
-
- /* Step 4: Configure an Auto Refresh command */
- Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
- Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
- Command.AutoRefreshNumber = 8;
- Command.ModeRegisterDefinition = 0;
-
- /* Send the command */
- HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
-
- /* Step 5: Program the external memory mode register */
- tmpmrd = (gU32)SDRAM_MODEREG_BURST_LENGTH_1 |\
- SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
- SDRAM_MODEREG_CAS_LATENCY_3 |\
- SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
- SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
-
- Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
- Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
- Command.AutoRefreshNumber = 1;
- Command.ModeRegisterDefinition = tmpmrd;
-
- /* Send the command */
- HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
-
- /* Step 6: Set the refresh rate counter */
- /* Set the device refresh rate */
- HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount);
-}
-
-/**
- * @brief Reads an mount of data from the SDRAM memory in polling mode.
- * @param uwStartAddress: Read start address
- * @param pData: Pointer to data to be read
- * @param uwDataSize: Size of read data from the memory
- * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
- */
-gU8 BSP_SDRAM_ReadData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
-{
- if(HAL_SDRAM_Read_32b(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
- {
- return SDRAM_ERROR;
- }
- else
- {
- return SDRAM_OK;
- }
-}
-
-/**
- * @brief Reads an mount of data from the SDRAM memory in DMA mode.
- * @param uwStartAddress: Read start address
- * @param pData: Pointer to data to be read
- * @param uwDataSize: Size of read data from the memory
- * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
- */
-gU8 BSP_SDRAM_ReadData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
-{
- if(HAL_SDRAM_Read_DMA(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
- {
- return SDRAM_ERROR;
- }
- else
- {
- return SDRAM_OK;
- }
-}
-
-/**
- * @brief Writes an mount of data to the SDRAM memory in polling mode.
- * @param uwStartAddress: Write start address
- * @param pData: Pointer to data to be written
- * @param uwDataSize: Size of written data from the memory
- * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
- */
-gU8 BSP_SDRAM_WriteData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
-{
- if(HAL_SDRAM_Write_32b(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
- {
- return SDRAM_ERROR;
- }
- else
- {
- return SDRAM_OK;
- }
-}
-
-/**
- * @brief Writes an mount of data to the SDRAM memory in DMA mode.
- * @param uwStartAddress: Write start address
- * @param pData: Pointer to data to be written
- * @param uwDataSize: Size of written data from the memory
- * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
- */
-gU8 BSP_SDRAM_WriteData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
-{
- if(HAL_SDRAM_Write_DMA(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
- {
- return SDRAM_ERROR;
- }
- else
- {
- return SDRAM_OK;
- }
-}
-
-/**
- * @brief Sends command to the SDRAM bank.
- * @param SdramCmd: Pointer to SDRAM command structure
- * @retval HAL status : SDRAM_OK or SDRAM_ERROR.
- */
-gU8 BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
-{
- if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK)
- {
- return SDRAM_ERROR;
- }
- else
- {
- return SDRAM_OK;
- }
-}
-
-/**
- * @brief Handles SDRAM DMA transfer interrupt request.
- */
-void BSP_SDRAM_DMA_IRQHandler(void)
-{
- HAL_DMA_IRQHandler(sdramHandle.hdma);
-}
-
-/**
- * @brief Initializes SDRAM MSP.
- * @note This function can be surcharged by application code.
- * @param hsdram: pointer on SDRAM handle
- * @param Params: pointer on additional configuration parameters, can be NULL.
- */
-__weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params)
-{
- static DMA_HandleTypeDef dma_handle;
- GPIO_InitTypeDef gpio_init_structure;
-
- if(hsdram != (SDRAM_HandleTypeDef *)NULL)
- {
- /* Enable FMC clock */
- __HAL_RCC_FMC_CLK_ENABLE();
-
- /* Enable chosen DMAx clock */
- __DMAx_CLK_ENABLE();
-
- /* Enable GPIOs clock */
- __HAL_RCC_GPIOC_CLK_ENABLE();
- __HAL_RCC_GPIOD_CLK_ENABLE();
- __HAL_RCC_GPIOE_CLK_ENABLE();
- __HAL_RCC_GPIOF_CLK_ENABLE();
- __HAL_RCC_GPIOG_CLK_ENABLE();
- __HAL_RCC_GPIOH_CLK_ENABLE();
- __HAL_RCC_GPIOI_CLK_ENABLE();
-
- /* Common GPIO configuration */
- gpio_init_structure.Mode = GPIO_MODE_AF_PP;
- gpio_init_structure.Pull = GPIO_PULLUP;
- gpio_init_structure.Speed = GPIO_SPEED_FAST;
- gpio_init_structure.Alternate = GPIO_AF12_FMC;
-
- /* GPIOC configuration : PC0 is SDNWE */
- gpio_init_structure.Pin = GPIO_PIN_0;
- HAL_GPIO_Init(GPIOC, &gpio_init_structure);
-
- /* GPIOD configuration */
- gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8| GPIO_PIN_9 | GPIO_PIN_10 |\
- GPIO_PIN_14 | GPIO_PIN_15;
-
-
- HAL_GPIO_Init(GPIOD, &gpio_init_structure);
-
- /* GPIOE configuration */
- gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
- GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
- GPIO_PIN_15;
-
- HAL_GPIO_Init(GPIOE, &gpio_init_structure);
-
- /* GPIOF configuration */
- gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
- GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
- GPIO_PIN_15;
-
- HAL_GPIO_Init(GPIOF, &gpio_init_structure);
-
- /* GPIOG configuration */
- gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\
- GPIO_PIN_15;
- HAL_GPIO_Init(GPIOG, &gpio_init_structure);
-
- /* GPIOH configuration */
- gpio_init_structure.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_8 | GPIO_PIN_9 |\
- GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
- GPIO_PIN_15;
- HAL_GPIO_Init(GPIOH, &gpio_init_structure);
-
- /* GPIOI configuration */
- gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 |\
- GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_9 | GPIO_PIN_10;
- HAL_GPIO_Init(GPIOI, &gpio_init_structure);
-
- /* Configure common DMA parameters */
- dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL;
- dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY;
- dma_handle.Init.PeriphInc = DMA_PINC_ENABLE;
- dma_handle.Init.MemInc = DMA_MINC_ENABLE;
- dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
- dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
- dma_handle.Init.Mode = DMA_NORMAL;
- dma_handle.Init.Priority = DMA_PRIORITY_HIGH;
- dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
- dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
- dma_handle.Init.MemBurst = DMA_MBURST_SINGLE;
- dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE;
-
- dma_handle.Instance = SDRAM_DMAx_STREAM;
-
- /* Associate the DMA handle */
- __HAL_LINKDMA(hsdram, hdma, dma_handle);
-
- /* Deinitialize the stream for new transfer */
- HAL_DMA_DeInit(&dma_handle);
-
- /* Configure the DMA stream */
- HAL_DMA_Init(&dma_handle);
-
- /* NVIC configuration for DMA transfer complete interrupt */
- HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0);
- HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
-
- } /* of if(hsdram != (SDRAM_HandleTypeDef *)NULL) */
-}
-
-/**
- * @brief DeInitializes SDRAM MSP.
- * @note This function can be surcharged by application code.
- * @param hsdram: pointer on SDRAM handle
- * @param Params: pointer on additional configuration parameters, can be NULL.
- */
-__weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params)
-{
- static DMA_HandleTypeDef dma_handle;
-
- if(hsdram != (SDRAM_HandleTypeDef *)NULL)
- {
- /* Disable NVIC configuration for DMA interrupt */
- HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn);
-
- /* Deinitialize the stream for new transfer */
- dma_handle.Instance = SDRAM_DMAx_STREAM;
- HAL_DMA_DeInit(&dma_handle);
-
- /* DeInit GPIO pins can be done in the application
- (by surcharging this __weak function) */
-
- /* GPIO pins clock, FMC clock and DMA clock can be shut down in the application
- by surcharging this __weak function */
-
- } /* of if(hsdram != (SDRAM_HandleTypeDef *)NULL) */
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file stm32469i_discovery_sdram.c
+ * @author MCD Application Team
+ * @version V2.0.0
+ * @date 27-January-2017
+ * @brief This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory
+ * device mounted on STM32469I-Discovery board.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2017 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* File Info : -----------------------------------------------------------------
+ User NOTES
+1. How To use this driver:
+--------------------------
+ - This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted
+ on STM32469I-Discovery board.
+ - This driver does not need a specific component driver for the SDRAM device
+ to be included with.
+
+2. Driver description:
+---------------------
+ + Initialization steps:
+ o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This
+ function includes the MSP layer hardware resources initialization and the
+ FMC controller configuration to interface with the external SDRAM memory.
+ o It contains the SDRAM initialization sequence to program the SDRAM external
+ device using the function BSP_SDRAM_Initialization_sequence(). Note that this
+ sequence is standard for all SDRAM devices, but can include some differences
+ from a device to another. If it is the case, the right sequence should be
+ implemented separately.
+
+ + SDRAM read/write operations
+ o SDRAM external memory can be accessed with read/write operations once it is
+ initialized.
+ Read/write operation can be performed with AHB access using the functions
+ BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions
+ BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA().
+ o The AHB access is performed with 32-bit width transaction, the DMA transfer
+ configuration is fixed at single (no burst) word transfer (see the
+ BSP_SDRAM_MspInit() weak function).
+ o User can implement his own functions for read/write access with his desired
+ configurations.
+ o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler()
+ is called in IRQ handler file, to serve the generated interrupt once the DMA
+ transfer is complete.
+ o You can send a command to the SDRAM device in runtime using the function
+ BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between
+ the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure.
+
+------------------------------------------------------------------------------*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f469i_discovery_sdram.h"
+
+/** @addtogroup BSP
+ * @{
+ */
+
+/** @addtogroup STM32469I_Discovery
+ * @{
+ */
+
+/** @defgroup STM32469I-Discovery_SDRAM STM32469I Discovery SDRAM
+ * @{
+ */
+
+/** @defgroup STM32469I-Discovery_SDRAM_Private_Types_Definitions STM32469I Discovery SDRAM Private TypesDef
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup STM32469I-Discovery_SDRAM_Private_Defines STM32469I Discovery SDRAM Private Defines
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup STM32469I-Discovery_SDRAM_Private_Macros STM32469I Discovery SDRAM Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @defgroup STM32469I-Discovery_SDRAM_Private_Variables STM32469I Discovery SDRAM Private Variables
+ * @{
+ */
+static SDRAM_HandleTypeDef sdramHandle;
+static FMC_SDRAM_TimingTypeDef Timing;
+static FMC_SDRAM_CommandTypeDef Command;
+/**
+ * @}
+ */
+
+/** @defgroup STM32469I-Discovery_SDRAM_Private_Function_Prototypes STM32469I Discovery SDRAM Private Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup STM32469I-Discovery_SDRAM_Private_Functions STM32469I Discovery SDRAM Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup STM32469I_Discovery_SDRAM_Exported_Functions STM32469I Discovery SDRAM Exported Functions
+ * @{
+ */
+
+/**
+ * @brief Initializes the SDRAM device.
+ * @retval SDRAM status
+ */
+gU8 BSP_SDRAM_Init(void)
+{
+ static gU8 sdramstatus = SDRAM_ERROR;
+
+ /* SDRAM device configuration */
+ sdramHandle.Instance = FMC_SDRAM_DEVICE;
+
+ /* Timing configuration for 90 MHz as SD clock frequency (System clock is up to 180 MHz) */
+ Timing.LoadToActiveDelay = 2;
+ Timing.ExitSelfRefreshDelay = 7;
+ Timing.SelfRefreshTime = 4;
+ Timing.RowCycleDelay = 7;
+ Timing.WriteRecoveryTime = 2;
+ Timing.RPDelay = 2;
+ Timing.RCDDelay = 2;
+
+ sdramHandle.Init.SDBank = FMC_SDRAM_BANK1;
+ sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
+ sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
+ sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
+ sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
+ sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
+ sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
+ sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD;
+ sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
+ sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
+
+ /* SDRAM controller initialization */
+ /* __weak function can be surcharged by the application code */
+ BSP_SDRAM_MspInit(&sdramHandle, (void *)NULL);
+ if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)
+ {
+ sdramstatus = SDRAM_ERROR;
+ }
+ else
+ {
+ sdramstatus = SDRAM_OK;
+ }
+
+ /* SDRAM initialization sequence */
+ BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
+
+ return sdramstatus;
+}
+
+/**
+ * @brief DeInitializes the SDRAM device.
+ * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
+ */
+gU8 BSP_SDRAM_DeInit(void)
+{
+ static gU8 sdramstatus = SDRAM_ERROR;
+
+ /* SDRAM device configuration */
+ sdramHandle.Instance = FMC_SDRAM_DEVICE;
+
+ if(HAL_SDRAM_DeInit(&sdramHandle) == HAL_OK)
+ {
+ sdramstatus = SDRAM_OK;
+
+ /* SDRAM controller De-initialization */
+ BSP_SDRAM_MspDeInit(&sdramHandle, (void *)NULL);
+ }
+
+ return sdramstatus;
+}
+
+
+/**
+ * @brief Programs the SDRAM device.
+ * @param RefreshCount: SDRAM refresh counter value
+ */
+void BSP_SDRAM_Initialization_sequence(gU32 RefreshCount)
+{
+ __IO gU32 tmpmrd = 0;
+
+ /* Step 1: Configure a clock configuration enable command */
+ Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
+ Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
+ Command.AutoRefreshNumber = 1;
+ Command.ModeRegisterDefinition = 0;
+
+ /* Send the command */
+ HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
+
+ /* Step 2: Insert 100 us minimum delay */
+ /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
+ HAL_Delay(1);
+
+ /* Step 3: Configure a PALL (precharge all) command */
+ Command.CommandMode = FMC_SDRAM_CMD_PALL;
+ Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
+ Command.AutoRefreshNumber = 1;
+ Command.ModeRegisterDefinition = 0;
+
+ /* Send the command */
+ HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
+
+ /* Step 4: Configure an Auto Refresh command */
+ Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
+ Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
+ Command.AutoRefreshNumber = 8;
+ Command.ModeRegisterDefinition = 0;
+
+ /* Send the command */
+ HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
+
+ /* Step 5: Program the external memory mode register */
+ tmpmrd = (gU32)SDRAM_MODEREG_BURST_LENGTH_1 |\
+ SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
+ SDRAM_MODEREG_CAS_LATENCY_3 |\
+ SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
+ SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
+
+ Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
+ Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
+ Command.AutoRefreshNumber = 1;
+ Command.ModeRegisterDefinition = tmpmrd;
+
+ /* Send the command */
+ HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
+
+ /* Step 6: Set the refresh rate counter */
+ /* Set the device refresh rate */
+ HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount);
+}
+
+/**
+ * @brief Reads an mount of data from the SDRAM memory in polling mode.
+ * @param uwStartAddress: Read start address
+ * @param pData: Pointer to data to be read
+ * @param uwDataSize: Size of read data from the memory
+ * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
+ */
+gU8 BSP_SDRAM_ReadData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
+{
+ if(HAL_SDRAM_Read_32b(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
+ {
+ return SDRAM_ERROR;
+ }
+ else
+ {
+ return SDRAM_OK;
+ }
+}
+
+/**
+ * @brief Reads an mount of data from the SDRAM memory in DMA mode.
+ * @param uwStartAddress: Read start address
+ * @param pData: Pointer to data to be read
+ * @param uwDataSize: Size of read data from the memory
+ * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
+ */
+gU8 BSP_SDRAM_ReadData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
+{
+ if(HAL_SDRAM_Read_DMA(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
+ {
+ return SDRAM_ERROR;
+ }
+ else
+ {
+ return SDRAM_OK;
+ }
+}
+
+/**
+ * @brief Writes an mount of data to the SDRAM memory in polling mode.
+ * @param uwStartAddress: Write start address
+ * @param pData: Pointer to data to be written
+ * @param uwDataSize: Size of written data from the memory
+ * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
+ */
+gU8 BSP_SDRAM_WriteData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
+{
+ if(HAL_SDRAM_Write_32b(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
+ {
+ return SDRAM_ERROR;
+ }
+ else
+ {
+ return SDRAM_OK;
+ }
+}
+
+/**
+ * @brief Writes an mount of data to the SDRAM memory in DMA mode.
+ * @param uwStartAddress: Write start address
+ * @param pData: Pointer to data to be written
+ * @param uwDataSize: Size of written data from the memory
+ * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
+ */
+gU8 BSP_SDRAM_WriteData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
+{
+ if(HAL_SDRAM_Write_DMA(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
+ {
+ return SDRAM_ERROR;
+ }
+ else
+ {
+ return SDRAM_OK;
+ }
+}
+
+/**
+ * @brief Sends command to the SDRAM bank.
+ * @param SdramCmd: Pointer to SDRAM command structure
+ * @retval HAL status : SDRAM_OK or SDRAM_ERROR.
+ */
+gU8 BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
+{
+ if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK)
+ {
+ return SDRAM_ERROR;
+ }
+ else
+ {
+ return SDRAM_OK;
+ }
+}
+
+/**
+ * @brief Handles SDRAM DMA transfer interrupt request.
+ */
+void BSP_SDRAM_DMA_IRQHandler(void)
+{
+ HAL_DMA_IRQHandler(sdramHandle.hdma);
+}
+
+/**
+ * @brief Initializes SDRAM MSP.
+ * @note This function can be surcharged by application code.
+ * @param hsdram: pointer on SDRAM handle
+ * @param Params: pointer on additional configuration parameters, can be NULL.
+ */
+__weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params)
+{
+ static DMA_HandleTypeDef dma_handle;
+ GPIO_InitTypeDef gpio_init_structure;
+
+ if(hsdram != (SDRAM_HandleTypeDef *)NULL)
+ {
+ /* Enable FMC clock */
+ __HAL_RCC_FMC_CLK_ENABLE();
+
+ /* Enable chosen DMAx clock */
+ __DMAx_CLK_ENABLE();
+
+ /* Enable GPIOs clock */
+ __HAL_RCC_GPIOC_CLK_ENABLE();
+ __HAL_RCC_GPIOD_CLK_ENABLE();
+ __HAL_RCC_GPIOE_CLK_ENABLE();
+ __HAL_RCC_GPIOF_CLK_ENABLE();
+ __HAL_RCC_GPIOG_CLK_ENABLE();
+ __HAL_RCC_GPIOH_CLK_ENABLE();
+ __HAL_RCC_GPIOI_CLK_ENABLE();
+
+ /* Common GPIO configuration */
+ gpio_init_structure.Mode = GPIO_MODE_AF_PP;
+ gpio_init_structure.Pull = GPIO_PULLUP;
+ gpio_init_structure.Speed = GPIO_SPEED_FAST;
+ gpio_init_structure.Alternate = GPIO_AF12_FMC;
+
+ /* GPIOC configuration : PC0 is SDNWE */
+ gpio_init_structure.Pin = GPIO_PIN_0;
+ HAL_GPIO_Init(GPIOC, &gpio_init_structure);
+
+ /* GPIOD configuration */
+ gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8| GPIO_PIN_9 | GPIO_PIN_10 |\
+ GPIO_PIN_14 | GPIO_PIN_15;
+
+
+ HAL_GPIO_Init(GPIOD, &gpio_init_structure);
+
+ /* GPIOE configuration */
+ gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
+ GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
+ GPIO_PIN_15;
+
+ HAL_GPIO_Init(GPIOE, &gpio_init_structure);
+
+ /* GPIOF configuration */
+ gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
+ GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
+ GPIO_PIN_15;
+
+ HAL_GPIO_Init(GPIOF, &gpio_init_structure);
+
+ /* GPIOG configuration */
+ gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\
+ GPIO_PIN_15;
+ HAL_GPIO_Init(GPIOG, &gpio_init_structure);
+
+ /* GPIOH configuration */
+ gpio_init_structure.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_8 | GPIO_PIN_9 |\
+ GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
+ GPIO_PIN_15;
+ HAL_GPIO_Init(GPIOH, &gpio_init_structure);
+
+ /* GPIOI configuration */
+ gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 |\
+ GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_9 | GPIO_PIN_10;
+ HAL_GPIO_Init(GPIOI, &gpio_init_structure);
+
+ /* Configure common DMA parameters */
+ dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL;
+ dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY;
+ dma_handle.Init.PeriphInc = DMA_PINC_ENABLE;
+ dma_handle.Init.MemInc = DMA_MINC_ENABLE;
+ dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
+ dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
+ dma_handle.Init.Mode = DMA_NORMAL;
+ dma_handle.Init.Priority = DMA_PRIORITY_HIGH;
+ dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+ dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
+ dma_handle.Init.MemBurst = DMA_MBURST_SINGLE;
+ dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE;
+
+ dma_handle.Instance = SDRAM_DMAx_STREAM;
+
+ /* Associate the DMA handle */
+ __HAL_LINKDMA(hsdram, hdma, dma_handle);
+
+ /* Deinitialize the stream for new transfer */
+ HAL_DMA_DeInit(&dma_handle);
+
+ /* Configure the DMA stream */
+ HAL_DMA_Init(&dma_handle);
+
+ /* NVIC configuration for DMA transfer complete interrupt */
+ HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0);
+ HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
+
+ } /* of if(hsdram != (SDRAM_HandleTypeDef *)NULL) */
+}
+
+/**
+ * @brief DeInitializes SDRAM MSP.
+ * @note This function can be surcharged by application code.
+ * @param hsdram: pointer on SDRAM handle
+ * @param Params: pointer on additional configuration parameters, can be NULL.
+ */
+__weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params)
+{
+ static DMA_HandleTypeDef dma_handle;
+
+ if(hsdram != (SDRAM_HandleTypeDef *)NULL)
+ {
+ /* Disable NVIC configuration for DMA interrupt */
+ HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn);
+
+ /* Deinitialize the stream for new transfer */
+ dma_handle.Instance = SDRAM_DMAx_STREAM;
+ HAL_DMA_DeInit(&dma_handle);
+
+ /* DeInit GPIO pins can be done in the application
+ (by surcharging this __weak function) */
+
+ /* GPIO pins clock, FMC clock and DMA clock can be shut down in the application
+ by surcharging this __weak function */
+
+ } /* of if(hsdram != (SDRAM_HandleTypeDef *)NULL) */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/boards/base/STM32F469i-Discovery/stm32f469i_discovery_sdram.h b/boards/base/STM32F469i-Discovery/stm32f469i_discovery_sdram.h
index de731a2d..ef3ef7e7 100644
--- a/boards/base/STM32F469i-Discovery/stm32f469i_discovery_sdram.h
+++ b/boards/base/STM32F469i-Discovery/stm32f469i_discovery_sdram.h
@@ -1,169 +1,169 @@
-/**
- ******************************************************************************
- * @file stm32469i_discovery_sdram.h
- * @author MCD Application Team
- * @version V2.0.0
- * @date 27-January-2017
- * @brief This file contains the common defines and functions prototypes for
- * the stm32469i_discovery_sdram.c driver.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32469I_DISCOVERY_SDRAM_H
-#define __STM32469I_DISCOVERY_SDRAM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup BSP
- * @{
- */
-
-/** @addtogroup STM32469I_Discovery
- * @{
- */
-
-/** @addtogroup STM32469I-Discovery_SDRAM
- * @{
- */
-
-/** @defgroup STM32469I-Discovery_SDRAM_Exported_Types STM32469I Discovery SDRAM Exported Types
- * @{
- */
-
-/**
- * @brief SDRAM status structure definition
- */
-#define SDRAM_OK ((gU8)0x00)
-#define SDRAM_ERROR ((gU8)0x01)
-
-/**
- * @}
- */
-
-/** @defgroup STM32469I-Discovery_SDRAM_Exported_Constants STM32469I Discovery SDRAM Exported Constants
- * @{
- */
-#define SDRAM_DEVICE_ADDR ((gU32)0xC0000000)
-
- /* SDRAM device size in Bytes */
- #define SDRAM_DEVICE_SIZE ((gU32)0x1000000)
-
-#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_32
-#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2
-
-/* SDRAM refresh counter (90 MHz SD clock) */
-#define REFRESH_COUNT ((gU32)0x0569)
-#define SDRAM_TIMEOUT ((gU32)0xFFFF)
-
-/* DMA definitions for SDRAM DMA transfer */
-#define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
-#define __DMAx_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
-#define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0
-#define SDRAM_DMAx_STREAM DMA2_Stream0
-#define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn
-#define SDRAM_DMAx_IRQHandler DMA2_Stream0_IRQHandler
-
-
-/**
- * @brief FMC SDRAM Mode definition register defines
- */
-#define SDRAM_MODEREG_BURST_LENGTH_1 ((gU16)0x0000)
-#define SDRAM_MODEREG_BURST_LENGTH_2 ((gU16)0x0001)
-#define SDRAM_MODEREG_BURST_LENGTH_4 ((gU16)0x0002)
-#define SDRAM_MODEREG_BURST_LENGTH_8 ((gU16)0x0004)
-#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((gU16)0x0000)
-#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((gU16)0x0008)
-#define SDRAM_MODEREG_CAS_LATENCY_2 ((gU16)0x0020)
-#define SDRAM_MODEREG_CAS_LATENCY_3 ((gU16)0x0030)
-#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((gU16)0x0000)
-#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((gU16)0x0000)
-#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((gU16)0x0200)
-/**
- * @}
- */
-
-/** @defgroup STM32469I-Discovery_SDRAM_Exported_Macro STM32469I Discovery SDRAM Exported Macro
- * @{
- */
-/**
- * @}
- */
-
-/** @addtogroup STM32469I_Discovery_SDRAM_Exported_Functions
- * @{
- */
-gU8 BSP_SDRAM_Init(void);
-gU8 BSP_SDRAM_DeInit(void);
-void BSP_SDRAM_Initialization_sequence(gU32 RefreshCount);
-gU8 BSP_SDRAM_ReadData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
-gU8 BSP_SDRAM_ReadData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
-gU8 BSP_SDRAM_WriteData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
-gU8 BSP_SDRAM_WriteData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
-gU8 BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
-void BSP_SDRAM_DMA_IRQHandler(void);
-
-/* These function can be modified in case the current settings (e.g. DMA stream)
- need to be changed for specific application needs */
-void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params);
-void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32469I_DISCOVERY_SDRAM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file stm32469i_discovery_sdram.h
+ * @author MCD Application Team
+ * @version V2.0.0
+ * @date 27-January-2017
+ * @brief This file contains the common defines and functions prototypes for
+ * the stm32469i_discovery_sdram.c driver.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2017 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32469I_DISCOVERY_SDRAM_H
+#define __STM32469I_DISCOVERY_SDRAM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup BSP
+ * @{
+ */
+
+/** @addtogroup STM32469I_Discovery
+ * @{
+ */
+
+/** @addtogroup STM32469I-Discovery_SDRAM
+ * @{
+ */
+
+/** @defgroup STM32469I-Discovery_SDRAM_Exported_Types STM32469I Discovery SDRAM Exported Types
+ * @{
+ */
+
+/**
+ * @brief SDRAM status structure definition
+ */
+#define SDRAM_OK ((gU8)0x00)
+#define SDRAM_ERROR ((gU8)0x01)
+
+/**
+ * @}
+ */
+
+/** @defgroup STM32469I-Discovery_SDRAM_Exported_Constants STM32469I Discovery SDRAM Exported Constants
+ * @{
+ */
+#define SDRAM_DEVICE_ADDR ((gU32)0xC0000000)
+
+ /* SDRAM device size in Bytes */
+ #define SDRAM_DEVICE_SIZE ((gU32)0x1000000)
+
+#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_32
+#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2
+
+/* SDRAM refresh counter (90 MHz SD clock) */
+#define REFRESH_COUNT ((gU32)0x0569)
+#define SDRAM_TIMEOUT ((gU32)0xFFFF)
+
+/* DMA definitions for SDRAM DMA transfer */
+#define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMAx_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0
+#define SDRAM_DMAx_STREAM DMA2_Stream0
+#define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn
+#define SDRAM_DMAx_IRQHandler DMA2_Stream0_IRQHandler
+
+
+/**
+ * @brief FMC SDRAM Mode definition register defines
+ */
+#define SDRAM_MODEREG_BURST_LENGTH_1 ((gU16)0x0000)
+#define SDRAM_MODEREG_BURST_LENGTH_2 ((gU16)0x0001)
+#define SDRAM_MODEREG_BURST_LENGTH_4 ((gU16)0x0002)
+#define SDRAM_MODEREG_BURST_LENGTH_8 ((gU16)0x0004)
+#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((gU16)0x0000)
+#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((gU16)0x0008)
+#define SDRAM_MODEREG_CAS_LATENCY_2 ((gU16)0x0020)
+#define SDRAM_MODEREG_CAS_LATENCY_3 ((gU16)0x0030)
+#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((gU16)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((gU16)0x0000)
+#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((gU16)0x0200)
+/**
+ * @}
+ */
+
+/** @defgroup STM32469I-Discovery_SDRAM_Exported_Macro STM32469I Discovery SDRAM Exported Macro
+ * @{
+ */
+/**
+ * @}
+ */
+
+/** @addtogroup STM32469I_Discovery_SDRAM_Exported_Functions
+ * @{
+ */
+gU8 BSP_SDRAM_Init(void);
+gU8 BSP_SDRAM_DeInit(void);
+void BSP_SDRAM_Initialization_sequence(gU32 RefreshCount);
+gU8 BSP_SDRAM_ReadData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
+gU8 BSP_SDRAM_ReadData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
+gU8 BSP_SDRAM_WriteData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
+gU8 BSP_SDRAM_WriteData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
+gU8 BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
+void BSP_SDRAM_DMA_IRQHandler(void);
+
+/* These function can be modified in case the current settings (e.g. DMA stream)
+ need to be changed for specific application needs */
+void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params);
+void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32469I_DISCOVERY_SDRAM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/boards/base/STM32F469i-Discovery/stm32f469i_raw32_it.c b/boards/base/STM32F469i-Discovery/stm32f469i_raw32_it.c
index 0b6fdf84..df2f41f1 100644
--- a/boards/base/STM32F469i-Discovery/stm32f469i_raw32_it.c
+++ b/boards/base/STM32F469i-Discovery/stm32f469i_raw32_it.c
@@ -1,176 +1,176 @@
-/**
- ******************************************************************************
- * @file Templates_LL/Src/stm32f4xx_it.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 17-February-2017
- * @brief Main Interrupt Service Routines.
- * This file provides template for all exceptions handler and
- * peripherals interrupt service routine.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f469i_raw32_it.h"
-
-/** @addtogroup STM32F4xx_LL_Examples
- * @{
- */
-
-/** @addtogroup Templates_LL
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/* Cortex-M4 Processor Exceptions Handlers */
-/******************************************************************************/
-
-/**
- * @brief This function handles NMI exception.
- * @param None
- * @retval None
- */
-void NMI_Handler(void)
-{
-}
-
-/**
- * @brief This function handles Hard Fault exception.
- * @param None
- * @retval None
- */
-void HardFault_Handler(void)
-{
- /* Go to infinite loop when Hard Fault exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles Memory Manage exception.
- * @param None
- * @retval None
- */
-void MemManage_Handler(void)
-{
- /* Go to infinite loop when Memory Manage exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles Bus Fault exception.
- * @param None
- * @retval None
- */
-void BusFault_Handler(void)
-{
- /* Go to infinite loop when Bus Fault exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles Usage Fault exception.
- * @param None
- * @retval None
- */
-void UsageFault_Handler(void)
-{
- /* Go to infinite loop when Usage Fault exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles SVCall exception.
- * @param None
- * @retval None
- */
-void SVC_Handler(void)
-{
-}
-
-/**
- * @brief This function handles Debug Monitor exception.
- * @param None
- * @retval None
- */
-void DebugMon_Handler(void)
-{
-}
-
-/**
- * @brief This function handles PendSVC exception.
- * @param None
- * @retval None
- */
-void PendSV_Handler(void)
-{
-}
-
-/**
- * @brief This function handles SysTick Handler.
- * @param None
- * @retval None
- */
-void SysTick_Handler(void)
-{
- HAL_IncTick();
-}
-
-/******************************************************************************/
-/* STM32F4xx Peripherals Interrupt Handlers */
-/* Add here the Interrupt Handler for the used peripheral(s) (GPIO), for the */
-/* available peripheral interrupt handler's name please refer to the startup */
-/* file (startup_stm32f4xx.s). */
-/******************************************************************************/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file Templates_LL/Src/stm32f4xx_it.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 17-February-2017
+ * @brief Main Interrupt Service Routines.
+ * This file provides template for all exceptions handler and
+ * peripherals interrupt service routine.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2017 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f469i_raw32_it.h"
+
+/** @addtogroup STM32F4xx_LL_Examples
+ * @{
+ */
+
+/** @addtogroup Templates_LL
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/* Cortex-M4 Processor Exceptions Handlers */
+/******************************************************************************/
+
+/**
+ * @brief This function handles NMI exception.
+ * @param None
+ * @retval None
+ */
+void NMI_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles Hard Fault exception.
+ * @param None
+ * @retval None
+ */
+void HardFault_Handler(void)
+{
+ /* Go to infinite loop when Hard Fault exception occurs */
+ while (1)
+ {
+ }
+}
+
+/**
+ * @brief This function handles Memory Manage exception.
+ * @param None
+ * @retval None
+ */
+void MemManage_Handler(void)
+{
+ /* Go to infinite loop when Memory Manage exception occurs */
+ while (1)
+ {
+ }
+}
+
+/**
+ * @brief This function handles Bus Fault exception.
+ * @param None
+ * @retval None
+ */
+void BusFault_Handler(void)
+{
+ /* Go to infinite loop when Bus Fault exception occurs */
+ while (1)
+ {
+ }
+}
+
+/**
+ * @brief This function handles Usage Fault exception.
+ * @param None
+ * @retval None
+ */
+void UsageFault_Handler(void)
+{
+ /* Go to infinite loop when Usage Fault exception occurs */
+ while (1)
+ {
+ }
+}
+
+/**
+ * @brief This function handles SVCall exception.
+ * @param None
+ * @retval None
+ */
+void SVC_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles Debug Monitor exception.
+ * @param None
+ * @retval None
+ */
+void DebugMon_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles PendSVC exception.
+ * @param None
+ * @retval None
+ */
+void PendSV_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles SysTick Handler.
+ * @param None
+ * @retval None
+ */
+void SysTick_Handler(void)
+{
+ HAL_IncTick();
+}
+
+/******************************************************************************/
+/* STM32F4xx Peripherals Interrupt Handlers */
+/* Add here the Interrupt Handler for the used peripheral(s) (GPIO), for the */
+/* available peripheral interrupt handler's name please refer to the startup */
+/* file (startup_stm32f4xx.s). */
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/boards/base/STM32F469i-Discovery/stm32f469i_raw32_it.h b/boards/base/STM32F469i-Discovery/stm32f469i_raw32_it.h
index 4ff24ba1..d92e79fd 100644
--- a/boards/base/STM32F469i-Discovery/stm32f469i_raw32_it.h
+++ b/boards/base/STM32F469i-Discovery/stm32f469i_raw32_it.h
@@ -1,69 +1,69 @@
-/**
- ******************************************************************************
- * @file Templates_LL/Inc/stm32f4xx_it.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 17-February-2017
- * @brief This file contains the headers of the interrupt handlers.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_IT_H
-#define __STM32F4xx_IT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_IT_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file Templates_LL/Inc/stm32f4xx_it.h
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 17-February-2017
+ * @brief This file contains the headers of the interrupt handlers.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2017 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_IT_H
+#define __STM32F4xx_IT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/boards/base/STM32F469i-Discovery/stm32f469i_raw32_system.c b/boards/base/STM32F469i-Discovery/stm32f469i_raw32_system.c
index d6f02d94..63e6b3c5 100644
--- a/boards/base/STM32F469i-Discovery/stm32f469i_raw32_system.c
+++ b/boards/base/STM32F469i-Discovery/stm32f469i_raw32_system.c
@@ -1,450 +1,450 @@
-/**
- ******************************************************************************
- * @file system_stm32f4xx.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 17-February-2017
- * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
- *
- * This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f4xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f4xx_system
- * @{
- */
-
-/** @addtogroup STM32F4xx_System_Private_Includes
- * @{
- */
-
-
-#include "stm32f4xx.h"
-
-#if !defined (HSE_VALUE)
-#if defined(USE_STM32469I_DISCO_REVA)
- #define HSE_VALUE ((gU32)25000000) /*!< Default value of the External oscillator in Hz */
-#else
- #define HSE_VALUE ((gU32)8000000) /*!< Default value of the External oscillator in Hz */
-#endif /* USE_STM32469I_DISCO_REVA */
-#endif /* HSE_VALUE */
-
-#if !defined (HSI_VALUE)
- #define HSI_VALUE ((gU32)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_Defines
- * @{
- */
-
-/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to use external SDRAM mounted
- on DK as data memory */
-/* #define DATA_IN_ExtSDRAM */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
-/******************************************************************************/
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_Variables
- * @{
- */
- /* This variable is updated in three ways:
- 1) by calling CMSIS function SystemCoreClockUpdate()
- 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
- Note: If you use this function to configure the system clock; then there
- is no need to call the 2 first functions listed above, since SystemCoreClock
- variable is updated automatically.
- */
-gU32 SystemCoreClock = 16000000;
-const gU8 AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const gU8 APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
- * @{
- */
-
-#if defined (DATA_IN_ExtSDRAM)
- static void SystemInit_ExtMemCtl(void);
-#endif /* DATA_IN_ExtSDRAM */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system
- * Initialize the FPU setting, vector table location and External memory
- * configuration.
- * @param None
- * @retval None
- */
-void SystemInit(void)
-{
- /* FPU settings ------------------------------------------------------------*/
- #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
- #endif
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= (gU32)0x00000001;
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (gU32)0xFEF6FFFF;
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x24003010;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (gU32)0xFFFBFFFF;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-
-#if defined (DATA_IN_ExtSDRAM)
- SystemInit_ExtMemCtl();
-#endif /* DATA_IN_ExtSDRAM */
-
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
- * 16 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
- * depends on the application requirements), user has to ensure that HSE_VALUE
- * is same as the real frequency of the crystal used. Otherwise, this function
- * may have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate(void)
-{
- gU32 tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock source */
- SystemCoreClock = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock source */
- SystemCoreClock = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock source */
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
- SYSCLK = PLL_VCO / PLL_P
- */
- pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-
- if (pllsource != 0)
- {
- /* HSE used as PLL clock source */
- pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
- else
- {
- /* HSI used as PLL clock source */
- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
-
- pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
- SystemCoreClock = pllvco/pllp;
- break;
- default:
- SystemCoreClock = HSI_VALUE;
- break;
- }
- /* Compute HCLK frequency --------------------------------------------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK frequency */
- SystemCoreClock >>= tmp;
-}
-
-#if defined (DATA_IN_ExtSDRAM)
-/**
- * @brief Setup the external memory controller.
- * Called in startup_stm32f4xx.s before jump to main.
- * This function configures the external memories (SRAM/SDRAM)
- * This SRAM/SDRAM will be used as program data memory (including heap and stack).
- * @param None
- * @retval None
- */
-void SystemInit_ExtMemCtl(void)
-{
- register gU32 tmpreg = 0, timeout = 0xFFFF;
- register __IO gU32 index;
-
- /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH, and GPIOI interface
- clock */
- RCC->AHB1ENR |= 0x000001FC;
-
- /* Connect PCx pins to FMC Alternate function */
- GPIOC->AFR[0] = 0x0000000C;
- GPIOC->AFR[1] = 0x00000000;
- /* Configure PCx pins in Alternate function mode */
- GPIOC->MODER = 0x00000002;
- /* Configure PCx pins speed to 100 MHz */
- GPIOC->OSPEEDR = 0x00000003;
- /* Configure PCx pins Output type to push-pull */
- GPIOC->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PCx pins */
- GPIOC->PUPDR = 0x00000000;
-
- /* Connect PDx pins to FMC Alternate function */
- GPIOD->AFR[0] = 0x000000CC;
- GPIOD->AFR[1] = 0xCC000CCC;
- /* Configure PDx pins in Alternate function mode */
- GPIOD->MODER = 0xA02A000A;
- /* Configure PDx pins speed to 100 MHz */
- GPIOD->OSPEEDR = 0xF03F000F;
- /* Configure PDx pins Output type to push-pull */
- GPIOD->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PDx pins */
- GPIOD->PUPDR = 0x00000000;
-
- /* Connect PEx pins to FMC Alternate function */
- GPIOE->AFR[0] = 0xC00000CC;
- GPIOE->AFR[1] = 0xCCCCCCCC;
- /* Configure PEx pins in Alternate function mode */
- GPIOE->MODER = 0xAAAA800A;
- /* Configure PEx pins speed to 100 MHz */
- GPIOE->OSPEEDR = 0xFFFFC00F;
- /* Configure PEx pins Output type to push-pull */
- GPIOE->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PEx pins */
- GPIOE->PUPDR = 0x00000000;
-
- /* Connect PFx pins to FMC Alternate function */
- GPIOF->AFR[0] = 0x00CCCCCC;
- GPIOF->AFR[1] = 0xCCCCC000;
- /* Configure PFx pins in Alternate function mode */
- GPIOF->MODER = 0xAA800AAA;
- /* Configure PFx pins speed to 100 MHz */
- GPIOF->OSPEEDR = 0xFFC00FFF;
- /* Configure PFx pins Output type to push-pull */
- GPIOF->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PFx pins */
- GPIOF->PUPDR = 0x00000000;
-
- /* Connect PGx pins to FMC Alternate function */
- GPIOG->AFR[0] = 0x00CC00CC;
- GPIOG->AFR[1] = 0xC000000C;
- /* Configure PGx pins in Alternate function mode */
- GPIOG->MODER = 0x80020A0A;
- /* Configure PGx pins speed to 100 MHz */
- GPIOG->OSPEEDR = 0xC0030F0F;
- /* Configure PGx pins Output type to push-pull */
- GPIOG->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PGx pins */
- GPIOG->PUPDR = 0x00000000;
-
- /* Connect PHx pins to FMC Alternate function */
- GPIOH->AFR[0] = 0x0000CC00;
- GPIOH->AFR[1] = 0xCCCCCCCC;
- /* Configure PHx pins in Alternate function mode */
- GPIOH->MODER = 0xAAAA00A0;
- /* Configure PHx pins speed to 100 MHz */
- GPIOH->OSPEEDR = 0xFFFF00F0;
- /* Configure PHx pins Output type to push-pull */
- GPIOH->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PHx pins */
- GPIOH->PUPDR = 0x00000000;
-
- /* Connect PIx pins to FMC Alternate function */
- GPIOI->AFR[0] = 0xCCCCCCCC;
- GPIOI->AFR[1] = 0x00000CC0;
- /* Configure PIx pins in Alternate function mode */
- GPIOI->MODER = 0x0028AAAA;
- /* Configure PIx pins speed to 100 MHz */
- GPIOI->OSPEEDR = 0x003CFFFF;
- /* Configure PIx pins Output type to push-pull */
- GPIOI->OTYPER = 0x00000000;
- /* No pull-up, pull-down for PIx pins */
- GPIOI->PUPDR = 0x00000000;
-
- /* FMC Configuration */
- /* Enable the FMC interface clock */
- RCC->AHB3ENR |= 0x00000001;
-
- /* Configure and enable SDRAM bank2 */
- FMC_Bank5_6->SDCR[0] = 0x000019E4;
- FMC_Bank5_6->SDTR[0] = 0x01115351;
-
- /* SDRAM initialization sequence */
- /* Clock enable command */
- FMC_Bank5_6->SDCMR = 0x00000011;
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- while((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* Delay */
- for (index = 0; index<1000; index++);
-
- /* PALL command */
- FMC_Bank5_6->SDCMR = 0x00000012;
- timeout = 0xFFFF;
- while((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* Auto refresh command */
- FMC_Bank5_6->SDCMR = 0x000000F3;
- timeout = 0xFFFF;
- while((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* MRD register program */
- FMC_Bank5_6->SDCMR = 0x00046014;
- timeout = 0xFFFF;
- while((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
- }
-
- /* Set refresh count */
- tmpreg = FMC_Bank5_6->SDRTR;
- FMC_Bank5_6->SDRTR = (tmpreg | (0x0000056A<<1));
-
- /* Disable write protection */
- tmpreg = FMC_Bank5_6->SDCR[0];
- FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
-}
-#endif /* DATA_IN_ExtSDRAM */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.c
+ * @author MCD Application Team
+ * @version V1.0.0
+ * @date 17-February-2017
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f4xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2017 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Includes
+ * @{
+ */
+
+
+#include "stm32f4xx.h"
+
+#if !defined (HSE_VALUE)
+#if defined(USE_STM32469I_DISCO_REVA)
+ #define HSE_VALUE ((gU32)25000000) /*!< Default value of the External oscillator in Hz */
+#else
+ #define HSE_VALUE ((gU32)8000000) /*!< Default value of the External oscillator in Hz */
+#endif /* USE_STM32469I_DISCO_REVA */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((gU32)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Defines
+ * @{
+ */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SDRAM mounted
+ on DK as data memory */
+/* #define DATA_IN_ExtSDRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+gU32 SystemCoreClock = 16000000;
+const gU8 AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const gU8 APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+#if defined (DATA_IN_ExtSDRAM)
+ static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSDRAM */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+ #endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (gU32)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (gU32)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (gU32)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
+ * depends on the application requirements), user has to ensure that HSE_VALUE
+ * is same as the real frequency of the crystal used. Otherwise, this function
+ * may have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+ gU32 tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock source */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock source */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock source */
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+ SYSCLK = PLL_VCO / PLL_P
+ */
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+
+ if (pllsource != 0)
+ {
+ /* HSE used as PLL clock source */
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+
+ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+ SystemCoreClock = pllvco/pllp;
+ break;
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK frequency --------------------------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK frequency */
+ SystemCoreClock >>= tmp;
+}
+
+#if defined (DATA_IN_ExtSDRAM)
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f4xx.s before jump to main.
+ * This function configures the external memories (SRAM/SDRAM)
+ * This SRAM/SDRAM will be used as program data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+ register gU32 tmpreg = 0, timeout = 0xFFFF;
+ register __IO gU32 index;
+
+ /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH, and GPIOI interface
+ clock */
+ RCC->AHB1ENR |= 0x000001FC;
+
+ /* Connect PCx pins to FMC Alternate function */
+ GPIOC->AFR[0] = 0x0000000C;
+ GPIOC->AFR[1] = 0x00000000;
+ /* Configure PCx pins in Alternate function mode */
+ GPIOC->MODER = 0x00000002;
+ /* Configure PCx pins speed to 100 MHz */
+ GPIOC->OSPEEDR = 0x00000003;
+ /* Configure PCx pins Output type to push-pull */
+ GPIOC->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PCx pins */
+ GPIOC->PUPDR = 0x00000000;
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x000000CC;
+ GPIOD->AFR[1] = 0xCC000CCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xA02A000A;
+ /* Configure PDx pins speed to 100 MHz */
+ GPIOD->OSPEEDR = 0xF03F000F;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00000CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAA800A;
+ /* Configure PEx pins speed to 100 MHz */
+ GPIOE->OSPEEDR = 0xFFFFC00F;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0x00CCCCCC;
+ GPIOF->AFR[1] = 0xCCCCC000;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAA800AAA;
+ /* Configure PFx pins speed to 100 MHz */
+ GPIOF->OSPEEDR = 0xFFC00FFF;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0x00CC00CC;
+ GPIOG->AFR[1] = 0xC000000C;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0x80020A0A;
+ /* Configure PGx pins speed to 100 MHz */
+ GPIOG->OSPEEDR = 0xC0030F0F;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+ /* Connect PHx pins to FMC Alternate function */
+ GPIOH->AFR[0] = 0x0000CC00;
+ GPIOH->AFR[1] = 0xCCCCCCCC;
+ /* Configure PHx pins in Alternate function mode */
+ GPIOH->MODER = 0xAAAA00A0;
+ /* Configure PHx pins speed to 100 MHz */
+ GPIOH->OSPEEDR = 0xFFFF00F0;
+ /* Configure PHx pins Output type to push-pull */
+ GPIOH->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PHx pins */
+ GPIOH->PUPDR = 0x00000000;
+
+ /* Connect PIx pins to FMC Alternate function */
+ GPIOI->AFR[0] = 0xCCCCCCCC;
+ GPIOI->AFR[1] = 0x00000CC0;
+ /* Configure PIx pins in Alternate function mode */
+ GPIOI->MODER = 0x0028AAAA;
+ /* Configure PIx pins speed to 100 MHz */
+ GPIOI->OSPEEDR = 0x003CFFFF;
+ /* Configure PIx pins Output type to push-pull */
+ GPIOI->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PIx pins */
+ GPIOI->PUPDR = 0x00000000;
+
+ /* FMC Configuration */
+ /* Enable the FMC interface clock */
+ RCC->AHB3ENR |= 0x00000001;
+
+ /* Configure and enable SDRAM bank2 */
+ FMC_Bank5_6->SDCR[0] = 0x000019E4;
+ FMC_Bank5_6->SDTR[0] = 0x01115351;
+
+ /* SDRAM initialization sequence */
+ /* Clock enable command */
+ FMC_Bank5_6->SDCMR = 0x00000011;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Delay */
+ for (index = 0; index<1000; index++);
+
+ /* PALL command */
+ FMC_Bank5_6->SDCMR = 0x00000012;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Auto refresh command */
+ FMC_Bank5_6->SDCMR = 0x000000F3;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* MRD register program */
+ FMC_Bank5_6->SDCMR = 0x00046014;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Set refresh count */
+ tmpreg = FMC_Bank5_6->SDRTR;
+ FMC_Bank5_6->SDRTR = (tmpreg | (0x0000056A<<1));
+
+ /* Disable write protection */
+ tmpreg = FMC_Bank5_6->SDCR[0];
+ FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+}
+#endif /* DATA_IN_ExtSDRAM */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c b/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c
index 77183b8a..16148f1d 100644
--- a/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c
+++ b/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c
@@ -1,69 +1,69 @@
-#include "../../../gfx.h"
-#if GFX_COMPAT_V2 && GFX_COMPAT_OLDCOLORS
- #undef Red
- #undef Green
- #undef Blue
-#endif
-#include "stm32f7xx_hal.h"
-
-#if GFX_USE_OS_CHIBIOS
- #define HAL_GPIO_Init(port, ptr) palSetGroupMode(port, (ptr)->Pin, 0, (ptr)->Mode|((ptr)->Speed<<3)|((ptr)->Pull<<5)|((ptr)->Alternate<<7))
-#else
- gTicks gfxSystemTicks(void)
- {
- return HAL_GetTick();
- }
-
- gTicks gfxMillisecondsToTicks(gDelay ms)
- {
- return ms;
- }
-#endif
-
-void SystemClock_Config(void)
-{
- RCC_ClkInitTypeDef RCC_ClkInitStruct;
- RCC_OscInitTypeDef RCC_OscInitStruct;
-
- /* Enable HSE Oscillator and activate PLL with HSE as source */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
- RCC_OscInitStruct.HSEState = RCC_HSE_ON;
- RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
- RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
- RCC_OscInitStruct.PLL.PLLM = 25;
- RCC_OscInitStruct.PLL.PLLN = 432;
- RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
- RCC_OscInitStruct.PLL.PLLQ = 9;
- HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
- /* Activate the OverDrive to reach the 216 MHz Frequency */
- HAL_PWREx_EnableOverDrive();
-
- /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
- RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
- RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
- RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
- HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
-}
-
-void Raw32OSInit(void)
-{
- /* Enable the CPU Cache's */
- SCB_EnableICache(); // Enable I-Cache
- SCB_EnableDCache(); // Enable D-Cache
-
-
- /* STM32F7xx HAL library initialization:
- - Configure the Flash ART accelerator on ITCM interface
- - Configure the Systick to generate an interrupt each 1 msec
- - Set NVIC Group Priority to 4
- - Global MSP (MCU Support Package) initialization
- */
- HAL_Init();
-
- /* Configure the system clock to 216 MHz */
- SystemClock_Config();
-}
+#include "../../../gfx.h"
+#if GFX_COMPAT_V2 && GFX_COMPAT_OLDCOLORS
+ #undef Red
+ #undef Green
+ #undef Blue
+#endif
+#include "stm32f7xx_hal.h"
+
+#if GFX_USE_OS_CHIBIOS
+ #define HAL_GPIO_Init(port, ptr) palSetGroupMode(port, (ptr)->Pin, 0, (ptr)->Mode|((ptr)->Speed<<3)|((ptr)->Pull<<5)|((ptr)->Alternate<<7))
+#else
+ gTicks gfxSystemTicks(void)
+ {
+ return HAL_GetTick();
+ }
+
+ gTicks gfxMillisecondsToTicks(gDelay ms)
+ {
+ return ms;
+ }
+#endif
+
+void SystemClock_Config(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /* Enable HSE Oscillator and activate PLL with HSE as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 25;
+ RCC_OscInitStruct.PLL.PLLN = 432;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = 9;
+ HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+ /* Activate the OverDrive to reach the 216 MHz Frequency */
+ HAL_PWREx_EnableOverDrive();
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+ HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
+}
+
+void Raw32OSInit(void)
+{
+ /* Enable the CPU Cache's */
+ SCB_EnableICache(); // Enable I-Cache
+ SCB_EnableDCache(); // Enable D-Cache
+
+
+ /* STM32F7xx HAL library initialization:
+ - Configure the Flash ART accelerator on ITCM interface
+ - Configure the Systick to generate an interrupt each 1 msec
+ - Set NVIC Group Priority to 4
+ - Global MSP (MCU Support Package) initialization
+ */
+ HAL_Init();
+
+ /* Configure the system clock to 216 MHz */
+ SystemClock_Config();
+}
diff --git a/changelog.txt b/changelog.txt
index 9acf6987..9c8c601b 100644
--- a/changelog.txt
+++ b/changelog.txt
@@ -1,516 +1,516 @@
-*****************************************************************************
-*** Releases ***
-*****************************************************************************
-
-*** After Release 2.9 ***
-CHANGE: Added type gImage to replace V2.x gdispImage.
-FIX: Fixed GWIN console widget scroll.
-FIX: A warning and adjustment is made if GDISP_IMAGE_BMP_BLIT_BUFFER_SIZE is less than 40 bytes.
-FIX: Prevent compiler warnings on duplicate const specifiers.
-FEATURE: Added support for ChibiOS 6.x kernel.
-FEATURE: Added support for ChibiOS 7.x kernel.
-CHANGE: STM32LTDC driver: Refactor to outsource clock setup for LTDC & DMA2D peripherals to the board file.
-CHANGE: STM32LTDC driver: Remove obsolete LTDC_NO_CLOCK_INIT macro as this clock setup is now outsourced to the board file.
-CHANGE: STM32LTDC driver: Automatically enable DMA cache flushing on STM32H7 platforms.
-CHANGE: STM32LTDC driver: Rename LTDC_USE_DMA2D to STM32LTDC_USE_DMA2D.
-CHANGE: STM32LTDC driver: Rename ALLOW_2ND_LAYER to STM32LTDC_USE_LAYER2.
-CHANGE: STM32LTDC driver: Rename LTDC_DMA_CACHE_FLUSH to STM32LTDC_DMA_CACHE_FLUSH.
-CHANGE: STM32LTDC driver: Rename GDISP_LTDC_USE_RGB565 to STM32LTDC_USE_RGB565.
-FEATURE: STM32LTDC driver: Support double buffering. This introduces STM32LTDC_USE_DOUBLEBUFFERING.
-FIX: STM32LTDC driver: Fix bug in gdisp_lld_blit_area() which affected blits with source coordinates other than (0, 0).
-FIX: Improve /demos/benchmarks/rectangles.
-FIX: Win32 driver: Fix buffer position calculation in gdisp_lld_blit_area().
-FIX: Win32 driver: Fix memory leak / invalid pointer to free() when re-calculating buffer position in a specific situation.
-FIX: Prevent const qualifier being discarded in vfnprintg().
-FIX: Fix missing return value in gfxQueueFSyncPut().
-FIX: Fix missing return value in gfxQueueFSyncPush().
-FIX: Fix missing return value in gfxQueueFSyncInsert().
-FEATURE: Adding support for FreeBSD.
-FIX: Fix incorrect calls to mmap() and sem_open() in SDL2 driver (lax operating systems such as Linux & MacOS were silently tolerating these).
-FIX: Minor code improvements
-FEATURE: Add cmake support
-
-
-*** Release 2.9 ***
-FEATURE: Added config vars GINPUT_TOUCH_CALIBRATION_FONT1 and GINPUT_TOUCH_CALIBRATION_FONT2
-FEATURE: Added config vars GINPUT_TOUCH_CALIBRATION_TITLE and GINPUT_TOUCH_CALIBRATION_ERROR
-FIX: Fixed ensuring the clock is fully started in STM32LTDC based boards
-FIX: Added support for negative baseline_x in fonts
-FIX: Fixed some word wrapping issues
-FIX: Fixed drawing of 3x3 pixel boxes
-FIX: Fixed issue in RTX5/CMSIS2 port which resulted in hanging delays/threads
-FEATURE: Added GFX_COMPAT_V2 to maintain source compatibility with V2.x programs. It is turned on by default.
-FEATURE: Added GFX_COMPAT_OLDCOLORS to allow V2.x Red, Green, Blue color names. It is turned on by default.
-CHANGE: Added GFX_RED, GFX_BLUE, GFX_GREEN etc to replace V2.x Red, Gree, Blue color names
-CHANGE: Added GFXON/GFXOFF to replace V2.x TRUE/FALSE for configuration options.
-CHANGE: Added types gI8, gU8 .. gI32, gU32 to replace V2.x int8_t etc
-CHANGE: Added type gBool to replace V2.x bool_t, and values gTrue/gFalse to replace TRUE/FALSE
-CHANGE: Added type gDelay to replace V2.x delaytime_t and values gDelayNone/gDelayForever to replace TIME_IMMEDIATE/TIME_INFINITE
-CHANGE: Added type gTicks to replace V2.x systemticks_t
-CHANGE: Added type gThread to replace V2.x gfxThreadHandle and macros GFX_THREAD_FUNCTION/STACK to replace DECLARE_THREAD_FUNCTION & DECLARE_THREAD_STACK
-CHANGE: Added type gThreadreturn to replace V2.x threadreturn_t and pseudo function gfxThreadReturn() to replace THREAD_RETURN()
-CHANGE: Added type gThreadpriority to replace V2.x threadpriority_t and values gThreadpriorityLow/Normal/High to replace LOW_/NORMAL_/HIGH_PRIORITY
-CHANGE: Added type gPoint to replace V2.x point and point_t
-CHANGE: Added type gCoord to replace V2.x coord_t
-CHANGE: Added type gPixel to replace V2.x pixel_t
-CHANGE: Added type gColor to replace V2.x color_t
-CHANGE: Added type gColorformat to replace V2.x colorformat
-CHANGE: Added type gFont to replace V2.x font_t
-CHANGE: Added type gPowermode to replace V2.x powermode_t, and values gPowerXXX replace powerXXX
-CHANGE: Added type gJustify to replace V2.x justify_t, and values gJustifyXXX replace justifyXXX
-CHANGE: Added type gFontmetric to replace V2.x fontmetric_t, and values gFontXXX replace fontXXX
-CHANGE: Added type gOrientation to replace V2.x orientation_t, and values gOrientationX replace GDISP_ROTATE_X
-CHANGE: Added type gSem to replace V2.x gfxSem, and values gSemMaxCount replace MAX_SEMAPHORE_COUNT
-CHANGE: Added type gMutex to replace V2.x gfxMutex
-CHANGE: Added macros JUSTIFYMASK_HORIZONTAL, JUSTIFYMASK_VERTICAL to replace V2.x macros JUSTIFYMASK_LEFTRIGHT, JUSTIFYMASK_TOPBOTTOM
-FEATURE: Added types gPtr, gPtrDiff and gAny
-FEATURE: Added type gMemSize and config macro GFX_MEM_LT64K
-FEATURE: Added type gFileSize
-FEATURE: Added gI64 and gU64 when the compiler supports it. GFX_TYPE_64 macro is defined as GFXON if it does.
-FEATURE: Fixed headers to ensure size_t, NULL are always defined. size_t is not used as it may be 64bit.
-FIX: Added gfxRealloc() to Qt port
-FIX: Fixed UC1610 driver private area initialisation
-FIX: Fixed ST7735 driver and added kapacuk changes
-FEATURE: Added keyboard support to radio buttons (by Steffan)
-FEATURE: Added internal use only GFX_COMPILESTAGE (used to control compilation)
-FEATURE: Added support for ChibiOS Kernel V5
-FEATURE: Added WS29EPD WaveShare E-Paper display
-FIX: Fixed GQUEUE full synchronous function signatures
-CHANGE: Removed label widget auto-sizing during redraw. It will still auto-size during creation
-FIX: Fixed realloc bug for RAW32 (and derivitives)
-
-
-*** Release 2.8 ***
-FEATURE: Added support for 128x32 SSD1306 based displays
-FIX: Fixed recursion bug in console history
-FIX: Multithreading issue with slow window redraws and large images
-FIX: Ensure valid thread stack sizes on platforms where it matters
-FEATURE: Added support for a GFILE user provided file system
-FEATURE: Added gwinListItemSetText() to replace text in a GWIN list item
-FEATURE: Added GDISP_IMAGE_BMP_BLIT_BUFFER_SIZE configuration option
-FEATURE: Added GDISP_IMAGE_PNG_BLIT_BUFFER_SIZE configuration option
-FEATURE: Added GDISP_IMAGE_PNG_FILE_BUFFER_SIZE configuration option
-FEATURE: Added GDISP_IMAGE_PNG_Z_BUFFER_SIZE configuration option
-FEATURE: Added GDISP_IMAGE_GIF_BLIT_BUFFER_SIZE configuration option
-FIX: Fixed extra dots when drawing anti-aliased fonts with wordwrap
-FEATURE: Increase non-UTF8 font support to 0 to 255 rather than just the true ascii set
-FEATURE: Added Fb24bpp driver for RGB888 and BGR888 packed framebuffer displays
-FEATURE: Added UC8173 driver
-FEATURE: Added complete support for Altera Terasic MAX10 NEEK board
-FEATURE: Significantly improved the FreeRTOS port
-FEATURE: Added support for operating system initialisation in FreeRTOS
-FEATURE: Added GFX_OS_CALL_UGFXMAIN configuration option to allow uGFXMain() to be automatically called
-FEATURE: Added GFX_OS_UGFXMAIN_STACKSIZE configuration option to control uGFXMain() stack size
-FIX: Fixed where a font with more than 255 glyphs could fail to display some glyphs
-FIX: Fixed where a font with a large x baseline could be incorrectly clipped or word-wrapped
-IMPROVE: Significantly decrease the stack usage required for word-wrapping
-FEATURE: Added justifyTop, justifyMiddle & justifyBottom text justification to GDISP
-FEATURE: Added justifyWordWrap, justifyNoWordWrap text justification to GDISP (requires GDISP_NEED_TEXT_WORDWRAP)
-FEATURE: Added justifyPad, justifyNoPad text justification to GDISP
-FEATURE: Added GDISP_NEED_TEXT_BOXPADLR and GDISP_NEED_TEXT_BOXPADTB configuration options
-FIX: Fixed an issue on FreeRTOS where thread stacks were being created too large
-FEATURE: Added UC1601s driver
-FIX: Fixed issues with the STM746-Discovery board with ChibiOS
-FEATURE: Added partial definition for the STM32F469i-Discovery board
-FIX: Fixed issue where the variable type of the syncflags of the STM32LTDC driver was too small
-FEATURE: Added KS0108 driver
-FEATURE: Added RA6963 driver
-FIX: Fixed clipping issue in gdispGDrawString()
-CHANGE: Upgrade GFILE FATFS support from V0.10b to V0.13
-FEATURE: Added UC1610 driver
-FIX: Fixed to allow gwinSetText with static text on a TextEdit control
-FIX: Fixed to ChibiOS realloc on a TextEdit control
-FEATURE: Added support for CMSIS V2.0 operating systems (eg RTX5)
-REMOVED: Removed long deprecated functions gfxSemCounter() and gfxSemCounterI()
-FIX: gwinDetachToggle() is now a visible part of the API
-CHANGE: Update OSX makefiles (allows for 64bit building)
-FIX: Fixed resetting a timer on gwinImage objects when using animated GIFs
-FEATURE: Added gwinTextEditSendKey() and gwinTextEditSendSpecialKey()
-FEATURE: Implemented the JPG image decoder
-FEATURE: Added SSD1322 driver
-FEATURE: Added support for Zephyr operating system
-FEATURE: STM32LTDC driver now supports using both layers as seperate displays. The 2nd display is the foreground layer
-CHANGE: STM32LTDC driver now uses RGB888 pixel format by default
-FEATURE: Added GDISP_LTDC_USE_RGB565 config variable to force STM32LTDC driver to use RGB565 pixel format
-FEATURE: The STM32LTDC 2nd display (the foreground layer) supports alpha.
-FEATURE: The STM32 board files for known boards have been updated to contain support for the 2nd layer.
-FEATURE: Added AHTML2COLOR() and ARGB2COLOR() to support alpha. This is currently only supported for the RGB888 pixel format.
-FEATURE: Added the new color GFXTRANSPARENT - only available for RGB888 pixel format on alpha capable displays.
-NOTE: Alpha support in RGB888 requies an alpha capable display (STM32LTDC 2nd display only currently)
-NOTE: Alpha support in RGB888 is NOT the standard ARGB8888 format. Only use AHTML2COLOR() and ARGB2COLOR() to create alpha colors.
-FEATURE: Added nullpointer checks to GDISP image functions (with new error code GDISP_IMAGE_ERR_NULLPOINTER)
-FIX: Add cache flushing to the ChibiOS FATFS/PETITFS block drivers. Needed for STM32F7 chips. This should really be in the ChibiOS DMA routines.
-FIX: Add cache flushing to enable DMA2D accelerated bitblits in the STM32LTDC driver on the STM32F7 cpu.
-FIX: Improved STM32F469i-Discovery board support.
-FIX: Improved STM32F746G-Discovery board support.
-
-
-*** Release 2.7 ***
-FEATURE: Added EXC7200 driver
-FEATURE: Added STM32F439i-EVAL board files
-FIX: Fixed crash when passing NULL to gwinSetStyle()
-FIX: Fixed potential crash when GDISP_NEED_TEXT_WORDWRAP is turned on
-FEATURE: Added SDL driver
-FEATURE: Added ILI9225 driver
-FEATURE: Added ST7735 driver
-FEATURE: Added Linux event input driver
-FIX: Fixed an issue with color formats in Linux-Framebuffer board files
-FIX: Fixed and improving arc rendering functions
-FIX: Preventing possible crash when no valid GWIN default font has been set
-FIX: Updating Windows binaries of the font encoder to improve compatibility
-FIX: Fixed progressbar bounds checking and decrementing
-FEATURE: Added gdispFillDualCircle()
-FIX: Fixed an issue in the filled polygon drawing function which caused irregularities
-FEATURE: Added high-level functions to modify image color palettes
-FIX: Improving gdispDrawThickLine()
-FEATURE: Added gdispAddFont() for adding a dynamic font to the permanent font list
-FEATURE: Added gmiscHittestPoly() for checking whether a point is inside of a polygon
-FIX: Fixed strange multi-thread issues in GEVENT
-FEATURE: Added ILI9488 driver
-FEATURE: Added the ability to display the detected compiler
-FIX: Fixed an illegal instruction in the Cortex M0 task switcher
-FEATURE: Added RAW32 task switching functions which work with ARMCC (the compiler used by Keil) for Cortex M0,M1,M3,M4 and M7
-FEATURE: Added gdispGDrawThickArc()
-FIX: Fixed a memory merging issue with the RAW32 memory allocator
-FIX: Update RAW32 libc threads support for more recent versions of the MinGW compiler
-
-
-*** Release 2.6 ***
-FIX: Fixed bug where the list item count wasn't decremented when an item was removed
-FEATURE: Added options GFILE_FATFS_EXTERNAL_LIB and GFILE_PETITFSFS_EXTERNAL_LIB
-FEATURE: Added FT6x06 driver
-FIX: Fixed issue in STM32F746G-Discovery board file that resulted in bad color reproduction
-FEATURE: Added gwinPrintg()
-FIX: Fixed sprintg and related functions handling of NULL pointers.
-FIX: Fixed width calculation of gdispGDrawString() and gdispGFillString().
-FEATURE: Added QImage display driver.
-FEATURE: Added QWidget touch driver
-FEATURE: Added support for Qt as a GOS platform
-FEATURE: Added ability to set a parent for a win32 ugfx emulator window
-FEATURE: Added ability to inject mouse events for a Win32 ugfx emulator window
-FEATURE: Added ability to turn on and off mouse processing for a win32 ugfx emulator window
-FEATURE: Added ability to capture mouse events on the win32 ugfx emaultor window
-FIX: Fixed issue where children of (nested) containers were not properly handled when callin gwinRaise()
-FEATURE: Automatically close all open files in gfileDeinit()
-FEATURE: Added support for IAR and EDG compilers
-FIX: Fixed crash when loading GIF image without enough memory available
-FEATURE: Added games/minesweeper demo
-FEATURE: Added games/justget10 demo
-
-
-*** Release 2.5 ***
-FEATURE: Added support for numerous compilers
-FIX: Improving STM32LTDC driver
-FEATURE: Added support for NIOS-II platform
-FEATURE: Added Altera-MAX10-NEEK board support
-FIX: Vastly improving keyboard widget default rendering
-FEATURE: Added ILI9342 driver
-FIX: Fixing issues where wrong 'progress' color from widget style palette was used
-FEATURE: Added GWIN_FRAME_KEEPONCLOSE flag to prevent destruction of a frame on close
-FEATURE: Added support for PNG images
-FEATURE: Added new module 'GTRANS' which allows handling application translations
-FEATURE: Added SSD1848 driver
-
-
-*** Release 2.4 ***
-FIX: Add missing stm32m3 cpu makefile option. Update doc to match.
-FEATURE: Added ability to compile ugfx as a single file. Simply compile src/gfx_mk.c
-FEATURE: Added GFXSINGLEMAKE=yes|no to the ugfx makefile to compile ugfx as a single file.
-FEATURE: New board STM32F746G-Discovery
-FEATURE: New gdisp driver STM32LTDC
-FEATURE: Better support for Raw32 platforms
-FEATURE: Renaming GFX_NO_OS_INIT to GFX_OS_NO_INIT
-FEATURE: New demo applications/combo
-FEATURE: Adding more font metrics (BaselineX and BaselineY)
-FEATURE: Adding gdispGetStringWidthCount()
-FEATURE: Implementing widget focusing. See gwinSetFocus() and gwinGetFocus()
-FEATURE: Adding TextEdit widget
-FEATURE: Added color to widget style for focused widgets
-FEATURE: Added GWIN_FOCUS_HIGHLIGHT_WIDTH as an option in the configuration file
-FEATURE: Added support for CMSIS RTOS
-FEATURE: Added support for KEIL RTX
-FEATURE: Replace all references to inline with a reference to GFXINLINE
-FEATURE: Added config option GFX_NO_INLINE to run off inlining of ugfx functions.
-FEATURE: Added word-wrapping support for gdispDrawStringBox() and gdispFillStringBox()
-FIX: Fixing issue in touchscreen calibration code
-FEATURE: Added GFX_OS_PRE_INIT_FUNCTION for early hardware initialization
-FEATURE: Added label rendering functions that allow to set text justification
-FIX: Fixing GTIMER for high clock rate devices
-FEATURE: Added GFX_COMPILER_KEIL and GFX_COMPILER_ARMCC macros
-
-
-*** Release 2.3 ***
-FEATURE: Added more events to the slider widget
-FIX: Clean up visibility issues
-FIX: Correct moving of containers
-FIX: Fix GTIMER bug that could cause all timers to stop.
-FIX: Various minor driver fixes
-FEATURE: Add support for STM32 CCM memory with DMA in SSD1289 and SSD2119
-FEATURE: New Tabset GWIN widget
-FEATURE: New keyboard driver interface with drivers for Win32 and X
-FEATURE: Support for keyboard layouts for non-english keyboards
-FEATURE: GDISP now supports pixmaps (in memory drawing)
-FEATURE: Rename files to improve experience in certain brain-dead IDE's
-FEATURE: Add a checkbox "Toggle Button" custom draw
-FEATURE: Add Tetris as a game demo
-FEATURE: Add HY-MiniSTM32V board support
-FEATURE: Add GWIN feature to flash any window/widget
-FIX: Lots of GDISP monochrome drivers fixed
-FEATURE: Added TLS8204 GDISP driver
-FIX: Fixes for the board files for Olimex SAM7EX256
-FEATURE: Add a number of UEXT connector board files for Olimex SAM7EX256
-FIX: Fix for error rounding in gdispFillConvexPoly()
-FEATURE: Vastly improved gwin arrow button drawing
-FIX: GINPUT toggle fixes
-FIX: GFILE_ALLOW_FLOAT compile error fixed
-FIX: GFILE_NEED_STDIO compile and emulation errors fixed
-FEATURE: Added STMPE610 driver by lliypuk
-FIX: Corrected self calibration code for driver STMPE811
-FEATURE: Added Mikromedia Plus STM32-M4 board based on work by lliypuk & inmarket
-FIX: Work to improve the gdisp SSD1963 driver
-FEATURE: Added SSD1351 gdisp driver
-FEATURE: Added SSD1331 gdisp driver
-FEATURE: Added arduino as a GOS supported operating system
-FEATURE: Added additional pixel format's
-FIX: Color components fixed for some strange compilers
-FEATURE: Added GWIN virtual keyboard widget
-FEATURE: Added gwinListSetSelected()
-FEATURE: Added gwinListViewItem()
-FIX: GDISP driver color conversion when GDISP_PIXEL_FORMAT != GDISP_LLD_PIXEL_FORMAT
-
-
-*** Release 2.2 ***
-FEATURE: Added nested containers demo
-FEATURE: Revised GWIN redraw strategy
-FEATURE: Added generic framebuffer driver
-FEATURE: Added Linux-Framebuffer board definition
-FEATURE: Added FatFS support for GFILE
-FEATURE: Added gfileMount() and gfileUnmount()
-FEATURE: Added gfileSync()
-FEATURE: Added gwinDrawThickLine()
-FEATURE: Added support for eCos
-FEATURE: Added PCF8812 gdisp driver
-FEATURE: Added PCD8544 gdisp driver
-FEATURE: Added Raspberry Pi board support
-FEATURE: Added R61505U gdisp driver
-FIX: Fix threading issues in GEvent for callbacks
-FEATURE: Added geventEventComplete()
-FEATURE: Added support for the RawOS real time operating system
-FEATURE: Operating System initialisation is now optional
-FEATURE: Prevent mouse events going to obscured widgets
-FEATURE: Add GFILE support for file lists
-FEATURE: Add GFILE support for C strings as files
-FEATURE: Add GFILE support for PetitFS
-FEATURE: Added SPFD54124B GDISP driver by user shilow
-FEATURE: Added GWIN GL3D window type
-FEATURE: Generalised all GWIN events to use a common prefix structure.
-FIX: Improve memory usage for the GWIN Frame widget.
-FEATURE: Added transparent custom draws for GWIN containers and frame widgets
-FEATURE: Added image custom draws for GWIN containers and frame widgets
-FEATURE: Added GDRIVER infrastructure. Ported GDISP to use it.
-FEATURE: Added gdispDrawArcSectors() and gdispFillArcSectors().
-FEATURE: Ported GINPUT MOUSE to GDRIVER infrastructure.
-FEATURE: Mouse/Touch now support both pen and finger mode.
-DEPRECATE: gwinAttachMouse() is now handled automaticly.
-FEATURE: Added MAX11802 touch driver by user steved
-FEATURE: Added STM32F429i-Discovery board support
-FEATURE: Added DejaVuSans20 and DejaVuSans20_aa built-in fonts
-FEATURE: Added MatrixFloat2D and MatrixFixed2D operations to GMISC
-FEATURE: Added polygon drawing demo (with rotation, scaling and translation)
-
-
-*** Release 2.1 ***
-FIX: Significant improvements to the way the MCU touch driver works.
-FEATURE: Add support for edge to edge touch calibration.
-FEATURE: Added progressbar widget
-FEATURE: Added gdispGDrawThickLine() by user jpa-
-DEPRECATE: TDISP module removed
-FIX: Console does not execute gwinPrintf() anymore if not visible
-FEATURE: Added gwinGetColor() and gwinGetBgColor()
-FEATURE: Console now has an optional backing store buffer (GWIN_CONSOLE_USE_HISTORY)
-FEATURE: Added smooth scrolling to list widget
-FEATURE: Increased performance of gwinListAddItem()
-FEATURE: Added FreeRTOS port
-FEATURE: Added gfxDeinit()
-FEATURE: Allow touch screen calibration in any display orientation
-FEATURE: New GFILE module to abstract File IO.
-FEATURE: Image file handling changed to use new GFILE module.
-DEPRECTATE: Old image opening functions deprecated.
-FEATURE: Restructure and simplify the include path for GFX
-FEATURE: Added LGDP4532 driver by user shilow
-FIX: Updated board files to support api changes in ChibiOS/RT 2.6.4
-FEATURE: Support for ChibiOS/RT 3.x
-FEATURE: Added gwinProgressbarStop() and gwinProgressbarReset()
-FEATURE: Added generic ILI93xx driver by xlh1460
-FEATURE: Added gwinListEnableRender()
-FEATURE: Added gwinLabelSetAttribute()
-FEATURE: Complete restructure of the GAUDIN and GAUDOUT into a common GAUDIO module
-FEATURE: Added a PWM audio play driver
-FEATURE: Update GADC audio recording driver to new GAUDIO format
-FEATURE: Added vs1053 audio play driver
-FEATURE: Added GAUDIO wave-play demo
-FEATURE: Added many GWIN simple demo's and updated the combined widget demo
-FEATURE: Added gwinEnable() and gwinDisable()
-FIX: Progressbar widget bug fix that could gwinProgressbarStop() to crash
-FIX: Imagebox widget bug fix that could cause gwinImageOpenFile() to crash
-FEATURE: GWIN containers such as "container" and "frame" which provides parent/children widget management
-FEATURE: Added gdispContrastColor()
-FEATURE: Added gwinShow() and gwinHide()
-FEATURE: ChibiOS/RT 3.x support and example for the Mikromedia STM32-M4 board.
-
-
-*** Release 2.0 ***
-FEATURE: GDISP Streaming API and demos.
-DEPRECATE: GDISP_NEED_ASYNC is now deprecated.
-DEPRECATE: 3rd party boing demo is now deprecated (replaced by GDISP Streaming demo)
-FIX: Remove GOS definitions from demo conf files so that it can be supplied by a makefile.
-FEATURE: Repair GDISP low level driver interfaces so they can now be included in the doxygen documentation.
-FEATURE: New driver interface for GDISP
-FEATURE: Multiple display support
-FEATURE: Multiple controller support
-FEATURE: Application pixel format no longer has to match the low level driver pixel format.
-FEATURE: Many more pixel formats are now supported.
-FEATURE: Many performance optimisations
-FEATURE: Vertical scrolling is now supported if the low level driver supports read_pixel.
-FEATURE: Add gdispFlush() for those controllers that need it
-FEATURE: Add GDISP_NEED_AUTOFLUSH and GDISP_NEED_TIMERFLUSH to automatically flush when required.
-FEATURE: Add support for generic portrait and landscape orientation modes
-FEATURE: Add macro GDISP_DEFAULT_ORIENTATION so an application can specify a default orientation.
-FEATURE: Driver files renamed to allow compiles when all object files go in the same directory
-FEATURE: New directory structure for board files. Predefined boards have all the hardware definitions predefined.
-FEATURE: Board definotions, example projects and makefiles for Win32.
-FEATURE: Board definitions, example projects and makefiles for X.
-FEATURE: Board definitions, example projects and makefiles for the Olimex SAM7-EX256 board.
-Feature: Board definitions, example projects and makefiles for the Olimex STM32-LCD board.
-FEATURE: Board definitions, example projects and makefiles for the Mikromedia STM32-M4 board.
-FEATURE: Board definitions, example projects and makefiles for the Marlin board.
-FEATURE: New invsqrt() routine added to GMISC
-
-
-*** Release 1.9 ***
-FEATURE: GWIN list boxes.
-FIX: POSIX port removed, now dedicated OS-X and Linux ports
-FIX: Several bugfixes
-FEATURE: mcufont integration
-FEATURE: SSD1306 driver by user goeck
-FEATURE: ST7565 driver by user sam0737
-FEATURE: ED060SC4 driver by user jpa-
-FIX: SSD1289 area filling bug fix by user samofab
-FEATURE: Added gwinListGetSelectedText()
-FEATURE: Added gwinListSetScroll()
-FEATURE: Added gwinLabelSetBorder()
-
-
-*** Release 1.8 ***
-FEATURE: Rename of the project from ChibiOS/GFX to uGFX
-FEATURE: Moved from github.com to bitbucket.org
-FEATURE: New website with a lot more of documentation
-FEATURE: Introduced dedicated discussion forum
-FEATURE: Complete rework of the widget manager (GWIN)
-FEATURE: Added a lot of new widgets
-FEATURE: Added gfxRealloc() to the GOS module
-FIX: gfxHalt() fix for the Win32 port
-FIX: Cleaned up board file mess
-
-
-*** Release 1.7 ***
-FEATURE: Added RA8875 GDISP driver
-FEATURE: Added FT5x06 GINPUT/touch driver
-FIX: Several bugfixes
-
-
-*** Release 1.6 ***
-FEATURE: Added ILI9325 driver - Thanks to Chris van Dongen aka _Sjaak
-FEATURE: Added TDISP module
-FIX: tdispGotoXY() renamed to tdispSetCursor()
-FEATURE: Addition of GADC, GMISC, GAUDIN, GAUDOUT subsystems
-FIX: Removal of the GDISP_LLD() macro
-DEPRECATE: Removal of the GDISP VMT
-FEATURE: Added SSD2119 GDISP driver
-FEATURE: Added GWIN_BUTTON_LAZY_RELEASE macro to disable cancel feature of buttons
-FEATURE: Implemented all four orientation modes for the ILI9320 GDISP driver
-FIX: Renamed every '__inline' macro to 'inline' for compiler compatibilities
-FEATURE: Supporting all standard functions in GDISP Nokia6610GE8 driver
-FEATURE: Added STMPE811 GINPUT driver
-FEATURE: Added gdispDrawPoly() and gdispFillConvexPoly()
-FEATURE: Added arrow button style to GWIN buttons
-FEATURE: Added the ability to specify a custom button drawing routine
-FEATURE: SSD1963 rework by username 'fred'
-FEATURE: Added Picture converter tool
-FEATURE: Added slider widget
-FEATURE: First MIPS32 (PIC32) board files contributed by user 'Dmytro'
-FEATURE: Added gwinDraw() routine
-FEATURE: Added GINPUT Dial support and driver using GADC
-FEATURE: Simplified assigning inputs to buttons and sliders
-FIX: Some fixes for the HD44780 TDISP driver by the user 'Frysk'
-FEATURE: Added ILI9481 by user 'Abhishek'
-FEATURE: Added enable/disable functions for widgets (Buttons)
-FEATURE: Added HX8347D driver by user 'Eddie'
-FEATURE: Added enhanced notepad demo by user 'Abhishek'
-FEATURE: Added GOS module (including sub modules such as GQUEUE)
-FEATURE: Added some functionalities to the TDISP module by user 'Frysk'
-
-
-*** Release 1.5 ***
-FEATURE: GEVENT - for passing event structures from Sources to Listeners
-FEATURE: GTIMER - thread context based once-off and periodic timers.
-FEATURE: GINPUT - extensible, multiple device-type, input sub-system.
-FEATURE: GWIN - full button, console and graph support
-FEATURE: Numerous touch calibration improvements
-FEATURE: Win32 driver - now support gdisp & ginput mouse/touch/toggle
-FEATURE: Win32 driver - full gdisp orientation support
-FEATURE: ILI9320 GDISP driver
-FEATURE: Nokia6610 GDISP driver split in to GE8 and GE12 variants
-FEATURE: Many GDISP drivers changed to use a board interface definition
-FEATURE: GFX source restructure with new gfx.h include file.
-DEPRECATE: console deprecated - replaced with gwin functionality
-DEPRECATE: graph deprecated - replaced with gwin functionality
-DEPRECATE: touchscreen deprecated - replaced with ginput functionality
-FEATURE: Numerous documentation improvements
-FEATURE: Added a number of module demo and test programs
-DEPRECATE: Remove of XPT2046 since full compatibility with ADS7843
-
-
-*** Release 1.4 ***
-FIX: Nokia 6610 fix
-FEATURE: New driver: Win32
-FEATURE: implementation of gdispFillArc()
-FIX: Hardware accelerate Arc routines
-FIX: Fix axis orientation for Arc routines
-FEATURE: new gdisp rounded box routines
-FEATURE: new gdispDrawStringBox()
-FEATURE: GWIN infrastructure
-FEATURE: now we fully support doxygen
-
-
-*** Release 1.3 ***
-FEATURE: added FSMC for SSD1289 / F4
-FEATURE: added calibration storage interface
-FIX: bugfix in filling functions for SSD1289
-FEATURE: added point_t struct in gdisp.h
-FEATURE: added graph module
-
-
-*** Release 1.2 ***
-FIX: orientation macros changed
-FIX: huge internal bugfix in orientation stuff (big thanks to Abhishek)
-FEATURE: added TOUCHPAD_XY_INVERTED macro
-FIX: struct cal renamed to struct cal_t
-FIX: SCREEN_WIDTH and SCREEN_HEIGHT renamed to GDISP_SCREEN_WIDTH and GDISP_SCREEN_HEIGHT
-FIX: struct TOUCHPAD_t renamed to struct TOUCHPADDriver_t
-FIX: struct GConsole renamed to struct GConsole_t
-FIX: lcdConsoleXXX() functions have been renamed to gfxConsoleXXX()
-FEATURE: FSMC for SSD1289 F2/F4
-
-
-*** Release 1.1 ***
-FIX: removed gdisp and touchpad prefix of driver directories
-UPDATE: added SSD1963 driver
-FIX: fixed Validation, VMT driver, console and BitBlit
-FEATURE: added clipping support
-FEATURE: addad gdispDrawArc()
-FEATURE: added SSD1963 DMA support
-FEATURE: added touchpad interface for storing calibration values (#define TOUCHPAD_STORE_CALIBRATION)
-CHANGE: replaced every GDISP_XXX macro with GDISP_XXX
-CHANGE: removed last digit of version number
-
+*****************************************************************************
+*** Releases ***
+*****************************************************************************
+
+*** After Release 2.9 ***
+CHANGE: Added type gImage to replace V2.x gdispImage.
+FIX: Fixed GWIN console widget scroll.
+FIX: A warning and adjustment is made if GDISP_IMAGE_BMP_BLIT_BUFFER_SIZE is less than 40 bytes.
+FIX: Prevent compiler warnings on duplicate const specifiers.
+FEATURE: Added support for ChibiOS 6.x kernel.
+FEATURE: Added support for ChibiOS 7.x kernel.
+CHANGE: STM32LTDC driver: Refactor to outsource clock setup for LTDC & DMA2D peripherals to the board file.
+CHANGE: STM32LTDC driver: Remove obsolete LTDC_NO_CLOCK_INIT macro as this clock setup is now outsourced to the board file.
+CHANGE: STM32LTDC driver: Automatically enable DMA cache flushing on STM32H7 platforms.
+CHANGE: STM32LTDC driver: Rename LTDC_USE_DMA2D to STM32LTDC_USE_DMA2D.
+CHANGE: STM32LTDC driver: Rename ALLOW_2ND_LAYER to STM32LTDC_USE_LAYER2.
+CHANGE: STM32LTDC driver: Rename LTDC_DMA_CACHE_FLUSH to STM32LTDC_DMA_CACHE_FLUSH.
+CHANGE: STM32LTDC driver: Rename GDISP_LTDC_USE_RGB565 to STM32LTDC_USE_RGB565.
+FEATURE: STM32LTDC driver: Support double buffering. This introduces STM32LTDC_USE_DOUBLEBUFFERING.
+FIX: STM32LTDC driver: Fix bug in gdisp_lld_blit_area() which affected blits with source coordinates other than (0, 0).
+FIX: Improve /demos/benchmarks/rectangles.
+FIX: Win32 driver: Fix buffer position calculation in gdisp_lld_blit_area().
+FIX: Win32 driver: Fix memory leak / invalid pointer to free() when re-calculating buffer position in a specific situation.
+FIX: Prevent const qualifier being discarded in vfnprintg().
+FIX: Fix missing return value in gfxQueueFSyncPut().
+FIX: Fix missing return value in gfxQueueFSyncPush().
+FIX: Fix missing return value in gfxQueueFSyncInsert().
+FEATURE: Adding support for FreeBSD.
+FIX: Fix incorrect calls to mmap() and sem_open() in SDL2 driver (lax operating systems such as Linux & MacOS were silently tolerating these).
+FIX: Minor code improvements
+FEATURE: Add cmake support
+
+
+*** Release 2.9 ***
+FEATURE: Added config vars GINPUT_TOUCH_CALIBRATION_FONT1 and GINPUT_TOUCH_CALIBRATION_FONT2
+FEATURE: Added config vars GINPUT_TOUCH_CALIBRATION_TITLE and GINPUT_TOUCH_CALIBRATION_ERROR
+FIX: Fixed ensuring the clock is fully started in STM32LTDC based boards
+FIX: Added support for negative baseline_x in fonts
+FIX: Fixed some word wrapping issues
+FIX: Fixed drawing of 3x3 pixel boxes
+FIX: Fixed issue in RTX5/CMSIS2 port which resulted in hanging delays/threads
+FEATURE: Added GFX_COMPAT_V2 to maintain source compatibility with V2.x programs. It is turned on by default.
+FEATURE: Added GFX_COMPAT_OLDCOLORS to allow V2.x Red, Green, Blue color names. It is turned on by default.
+CHANGE: Added GFX_RED, GFX_BLUE, GFX_GREEN etc to replace V2.x Red, Gree, Blue color names
+CHANGE: Added GFXON/GFXOFF to replace V2.x TRUE/FALSE for configuration options.
+CHANGE: Added types gI8, gU8 .. gI32, gU32 to replace V2.x int8_t etc
+CHANGE: Added type gBool to replace V2.x bool_t, and values gTrue/gFalse to replace TRUE/FALSE
+CHANGE: Added type gDelay to replace V2.x delaytime_t and values gDelayNone/gDelayForever to replace TIME_IMMEDIATE/TIME_INFINITE
+CHANGE: Added type gTicks to replace V2.x systemticks_t
+CHANGE: Added type gThread to replace V2.x gfxThreadHandle and macros GFX_THREAD_FUNCTION/STACK to replace DECLARE_THREAD_FUNCTION & DECLARE_THREAD_STACK
+CHANGE: Added type gThreadreturn to replace V2.x threadreturn_t and pseudo function gfxThreadReturn() to replace THREAD_RETURN()
+CHANGE: Added type gThreadpriority to replace V2.x threadpriority_t and values gThreadpriorityLow/Normal/High to replace LOW_/NORMAL_/HIGH_PRIORITY
+CHANGE: Added type gPoint to replace V2.x point and point_t
+CHANGE: Added type gCoord to replace V2.x coord_t
+CHANGE: Added type gPixel to replace V2.x pixel_t
+CHANGE: Added type gColor to replace V2.x color_t
+CHANGE: Added type gColorformat to replace V2.x colorformat
+CHANGE: Added type gFont to replace V2.x font_t
+CHANGE: Added type gPowermode to replace V2.x powermode_t, and values gPowerXXX replace powerXXX
+CHANGE: Added type gJustify to replace V2.x justify_t, and values gJustifyXXX replace justifyXXX
+CHANGE: Added type gFontmetric to replace V2.x fontmetric_t, and values gFontXXX replace fontXXX
+CHANGE: Added type gOrientation to replace V2.x orientation_t, and values gOrientationX replace GDISP_ROTATE_X
+CHANGE: Added type gSem to replace V2.x gfxSem, and values gSemMaxCount replace MAX_SEMAPHORE_COUNT
+CHANGE: Added type gMutex to replace V2.x gfxMutex
+CHANGE: Added macros JUSTIFYMASK_HORIZONTAL, JUSTIFYMASK_VERTICAL to replace V2.x macros JUSTIFYMASK_LEFTRIGHT, JUSTIFYMASK_TOPBOTTOM
+FEATURE: Added types gPtr, gPtrDiff and gAny
+FEATURE: Added type gMemSize and config macro GFX_MEM_LT64K
+FEATURE: Added type gFileSize
+FEATURE: Added gI64 and gU64 when the compiler supports it. GFX_TYPE_64 macro is defined as GFXON if it does.
+FEATURE: Fixed headers to ensure size_t, NULL are always defined. size_t is not used as it may be 64bit.
+FIX: Added gfxRealloc() to Qt port
+FIX: Fixed UC1610 driver private area initialisation
+FIX: Fixed ST7735 driver and added kapacuk changes
+FEATURE: Added keyboard support to radio buttons (by Steffan)
+FEATURE: Added internal use only GFX_COMPILESTAGE (used to control compilation)
+FEATURE: Added support for ChibiOS Kernel V5
+FEATURE: Added WS29EPD WaveShare E-Paper display
+FIX: Fixed GQUEUE full synchronous function signatures
+CHANGE: Removed label widget auto-sizing during redraw. It will still auto-size during creation
+FIX: Fixed realloc bug for RAW32 (and derivitives)
+
+
+*** Release 2.8 ***
+FEATURE: Added support for 128x32 SSD1306 based displays
+FIX: Fixed recursion bug in console history
+FIX: Multithreading issue with slow window redraws and large images
+FIX: Ensure valid thread stack sizes on platforms where it matters
+FEATURE: Added support for a GFILE user provided file system
+FEATURE: Added gwinListItemSetText() to replace text in a GWIN list item
+FEATURE: Added GDISP_IMAGE_BMP_BLIT_BUFFER_SIZE configuration option
+FEATURE: Added GDISP_IMAGE_PNG_BLIT_BUFFER_SIZE configuration option
+FEATURE: Added GDISP_IMAGE_PNG_FILE_BUFFER_SIZE configuration option
+FEATURE: Added GDISP_IMAGE_PNG_Z_BUFFER_SIZE configuration option
+FEATURE: Added GDISP_IMAGE_GIF_BLIT_BUFFER_SIZE configuration option
+FIX: Fixed extra dots when drawing anti-aliased fonts with wordwrap
+FEATURE: Increase non-UTF8 font support to 0 to 255 rather than just the true ascii set
+FEATURE: Added Fb24bpp driver for RGB888 and BGR888 packed framebuffer displays
+FEATURE: Added UC8173 driver
+FEATURE: Added complete support for Altera Terasic MAX10 NEEK board
+FEATURE: Significantly improved the FreeRTOS port
+FEATURE: Added support for operating system initialisation in FreeRTOS
+FEATURE: Added GFX_OS_CALL_UGFXMAIN configuration option to allow uGFXMain() to be automatically called
+FEATURE: Added GFX_OS_UGFXMAIN_STACKSIZE configuration option to control uGFXMain() stack size
+FIX: Fixed where a font with more than 255 glyphs could fail to display some glyphs
+FIX: Fixed where a font with a large x baseline could be incorrectly clipped or word-wrapped
+IMPROVE: Significantly decrease the stack usage required for word-wrapping
+FEATURE: Added justifyTop, justifyMiddle & justifyBottom text justification to GDISP
+FEATURE: Added justifyWordWrap, justifyNoWordWrap text justification to GDISP (requires GDISP_NEED_TEXT_WORDWRAP)
+FEATURE: Added justifyPad, justifyNoPad text justification to GDISP
+FEATURE: Added GDISP_NEED_TEXT_BOXPADLR and GDISP_NEED_TEXT_BOXPADTB configuration options
+FIX: Fixed an issue on FreeRTOS where thread stacks were being created too large
+FEATURE: Added UC1601s driver
+FIX: Fixed issues with the STM746-Discovery board with ChibiOS
+FEATURE: Added partial definition for the STM32F469i-Discovery board
+FIX: Fixed issue where the variable type of the syncflags of the STM32LTDC driver was too small
+FEATURE: Added KS0108 driver
+FEATURE: Added RA6963 driver
+FIX: Fixed clipping issue in gdispGDrawString()
+CHANGE: Upgrade GFILE FATFS support from V0.10b to V0.13
+FEATURE: Added UC1610 driver
+FIX: Fixed to allow gwinSetText with static text on a TextEdit control
+FIX: Fixed to ChibiOS realloc on a TextEdit control
+FEATURE: Added support for CMSIS V2.0 operating systems (eg RTX5)
+REMOVED: Removed long deprecated functions gfxSemCounter() and gfxSemCounterI()
+FIX: gwinDetachToggle() is now a visible part of the API
+CHANGE: Update OSX makefiles (allows for 64bit building)
+FIX: Fixed resetting a timer on gwinImage objects when using animated GIFs
+FEATURE: Added gwinTextEditSendKey() and gwinTextEditSendSpecialKey()
+FEATURE: Implemented the JPG image decoder
+FEATURE: Added SSD1322 driver
+FEATURE: Added support for Zephyr operating system
+FEATURE: STM32LTDC driver now supports using both layers as seperate displays. The 2nd display is the foreground layer
+CHANGE: STM32LTDC driver now uses RGB888 pixel format by default
+FEATURE: Added GDISP_LTDC_USE_RGB565 config variable to force STM32LTDC driver to use RGB565 pixel format
+FEATURE: The STM32LTDC 2nd display (the foreground layer) supports alpha.
+FEATURE: The STM32 board files for known boards have been updated to contain support for the 2nd layer.
+FEATURE: Added AHTML2COLOR() and ARGB2COLOR() to support alpha. This is currently only supported for the RGB888 pixel format.
+FEATURE: Added the new color GFXTRANSPARENT - only available for RGB888 pixel format on alpha capable displays.
+NOTE: Alpha support in RGB888 requies an alpha capable display (STM32LTDC 2nd display only currently)
+NOTE: Alpha support in RGB888 is NOT the standard ARGB8888 format. Only use AHTML2COLOR() and ARGB2COLOR() to create alpha colors.
+FEATURE: Added nullpointer checks to GDISP image functions (with new error code GDISP_IMAGE_ERR_NULLPOINTER)
+FIX: Add cache flushing to the ChibiOS FATFS/PETITFS block drivers. Needed for STM32F7 chips. This should really be in the ChibiOS DMA routines.
+FIX: Add cache flushing to enable DMA2D accelerated bitblits in the STM32LTDC driver on the STM32F7 cpu.
+FIX: Improved STM32F469i-Discovery board support.
+FIX: Improved STM32F746G-Discovery board support.
+
+
+*** Release 2.7 ***
+FEATURE: Added EXC7200 driver
+FEATURE: Added STM32F439i-EVAL board files
+FIX: Fixed crash when passing NULL to gwinSetStyle()
+FIX: Fixed potential crash when GDISP_NEED_TEXT_WORDWRAP is turned on
+FEATURE: Added SDL driver
+FEATURE: Added ILI9225 driver
+FEATURE: Added ST7735 driver
+FEATURE: Added Linux event input driver
+FIX: Fixed an issue with color formats in Linux-Framebuffer board files
+FIX: Fixed and improving arc rendering functions
+FIX: Preventing possible crash when no valid GWIN default font has been set
+FIX: Updating Windows binaries of the font encoder to improve compatibility
+FIX: Fixed progressbar bounds checking and decrementing
+FEATURE: Added gdispFillDualCircle()
+FIX: Fixed an issue in the filled polygon drawing function which caused irregularities
+FEATURE: Added high-level functions to modify image color palettes
+FIX: Improving gdispDrawThickLine()
+FEATURE: Added gdispAddFont() for adding a dynamic font to the permanent font list
+FEATURE: Added gmiscHittestPoly() for checking whether a point is inside of a polygon
+FIX: Fixed strange multi-thread issues in GEVENT
+FEATURE: Added ILI9488 driver
+FEATURE: Added the ability to display the detected compiler
+FIX: Fixed an illegal instruction in the Cortex M0 task switcher
+FEATURE: Added RAW32 task switching functions which work with ARMCC (the compiler used by Keil) for Cortex M0,M1,M3,M4 and M7
+FEATURE: Added gdispGDrawThickArc()
+FIX: Fixed a memory merging issue with the RAW32 memory allocator
+FIX: Update RAW32 libc threads support for more recent versions of the MinGW compiler
+
+
+*** Release 2.6 ***
+FIX: Fixed bug where the list item count wasn't decremented when an item was removed
+FEATURE: Added options GFILE_FATFS_EXTERNAL_LIB and GFILE_PETITFSFS_EXTERNAL_LIB
+FEATURE: Added FT6x06 driver
+FIX: Fixed issue in STM32F746G-Discovery board file that resulted in bad color reproduction
+FEATURE: Added gwinPrintg()
+FIX: Fixed sprintg and related functions handling of NULL pointers.
+FIX: Fixed width calculation of gdispGDrawString() and gdispGFillString().
+FEATURE: Added QImage display driver.
+FEATURE: Added QWidget touch driver
+FEATURE: Added support for Qt as a GOS platform
+FEATURE: Added ability to set a parent for a win32 ugfx emulator window
+FEATURE: Added ability to inject mouse events for a Win32 ugfx emulator window
+FEATURE: Added ability to turn on and off mouse processing for a win32 ugfx emulator window
+FEATURE: Added ability to capture mouse events on the win32 ugfx emaultor window
+FIX: Fixed issue where children of (nested) containers were not properly handled when callin gwinRaise()
+FEATURE: Automatically close all open files in gfileDeinit()
+FEATURE: Added support for IAR and EDG compilers
+FIX: Fixed crash when loading GIF image without enough memory available
+FEATURE: Added games/minesweeper demo
+FEATURE: Added games/justget10 demo
+
+
+*** Release 2.5 ***
+FEATURE: Added support for numerous compilers
+FIX: Improving STM32LTDC driver
+FEATURE: Added support for NIOS-II platform
+FEATURE: Added Altera-MAX10-NEEK board support
+FIX: Vastly improving keyboard widget default rendering
+FEATURE: Added ILI9342 driver
+FIX: Fixing issues where wrong 'progress' color from widget style palette was used
+FEATURE: Added GWIN_FRAME_KEEPONCLOSE flag to prevent destruction of a frame on close
+FEATURE: Added support for PNG images
+FEATURE: Added new module 'GTRANS' which allows handling application translations
+FEATURE: Added SSD1848 driver
+
+
+*** Release 2.4 ***
+FIX: Add missing stm32m3 cpu makefile option. Update doc to match.
+FEATURE: Added ability to compile ugfx as a single file. Simply compile src/gfx_mk.c
+FEATURE: Added GFXSINGLEMAKE=yes|no to the ugfx makefile to compile ugfx as a single file.
+FEATURE: New board STM32F746G-Discovery
+FEATURE: New gdisp driver STM32LTDC
+FEATURE: Better support for Raw32 platforms
+FEATURE: Renaming GFX_NO_OS_INIT to GFX_OS_NO_INIT
+FEATURE: New demo applications/combo
+FEATURE: Adding more font metrics (BaselineX and BaselineY)
+FEATURE: Adding gdispGetStringWidthCount()
+FEATURE: Implementing widget focusing. See gwinSetFocus() and gwinGetFocus()
+FEATURE: Adding TextEdit widget
+FEATURE: Added color to widget style for focused widgets
+FEATURE: Added GWIN_FOCUS_HIGHLIGHT_WIDTH as an option in the configuration file
+FEATURE: Added support for CMSIS RTOS
+FEATURE: Added support for KEIL RTX
+FEATURE: Replace all references to inline with a reference to GFXINLINE
+FEATURE: Added config option GFX_NO_INLINE to run off inlining of ugfx functions.
+FEATURE: Added word-wrapping support for gdispDrawStringBox() and gdispFillStringBox()
+FIX: Fixing issue in touchscreen calibration code
+FEATURE: Added GFX_OS_PRE_INIT_FUNCTION for early hardware initialization
+FEATURE: Added label rendering functions that allow to set text justification
+FIX: Fixing GTIMER for high clock rate devices
+FEATURE: Added GFX_COMPILER_KEIL and GFX_COMPILER_ARMCC macros
+
+
+*** Release 2.3 ***
+FEATURE: Added more events to the slider widget
+FIX: Clean up visibility issues
+FIX: Correct moving of containers
+FIX: Fix GTIMER bug that could cause all timers to stop.
+FIX: Various minor driver fixes
+FEATURE: Add support for STM32 CCM memory with DMA in SSD1289 and SSD2119
+FEATURE: New Tabset GWIN widget
+FEATURE: New keyboard driver interface with drivers for Win32 and X
+FEATURE: Support for keyboard layouts for non-english keyboards
+FEATURE: GDISP now supports pixmaps (in memory drawing)
+FEATURE: Rename files to improve experience in certain brain-dead IDE's
+FEATURE: Add a checkbox "Toggle Button" custom draw
+FEATURE: Add Tetris as a game demo
+FEATURE: Add HY-MiniSTM32V board support
+FEATURE: Add GWIN feature to flash any window/widget
+FIX: Lots of GDISP monochrome drivers fixed
+FEATURE: Added TLS8204 GDISP driver
+FIX: Fixes for the board files for Olimex SAM7EX256
+FEATURE: Add a number of UEXT connector board files for Olimex SAM7EX256
+FIX: Fix for error rounding in gdispFillConvexPoly()
+FEATURE: Vastly improved gwin arrow button drawing
+FIX: GINPUT toggle fixes
+FIX: GFILE_ALLOW_FLOAT compile error fixed
+FIX: GFILE_NEED_STDIO compile and emulation errors fixed
+FEATURE: Added STMPE610 driver by lliypuk
+FIX: Corrected self calibration code for driver STMPE811
+FEATURE: Added Mikromedia Plus STM32-M4 board based on work by lliypuk & inmarket
+FIX: Work to improve the gdisp SSD1963 driver
+FEATURE: Added SSD1351 gdisp driver
+FEATURE: Added SSD1331 gdisp driver
+FEATURE: Added arduino as a GOS supported operating system
+FEATURE: Added additional pixel format's
+FIX: Color components fixed for some strange compilers
+FEATURE: Added GWIN virtual keyboard widget
+FEATURE: Added gwinListSetSelected()
+FEATURE: Added gwinListViewItem()
+FIX: GDISP driver color conversion when GDISP_PIXEL_FORMAT != GDISP_LLD_PIXEL_FORMAT
+
+
+*** Release 2.2 ***
+FEATURE: Added nested containers demo
+FEATURE: Revised GWIN redraw strategy
+FEATURE: Added generic framebuffer driver
+FEATURE: Added Linux-Framebuffer board definition
+FEATURE: Added FatFS support for GFILE
+FEATURE: Added gfileMount() and gfileUnmount()
+FEATURE: Added gfileSync()
+FEATURE: Added gwinDrawThickLine()
+FEATURE: Added support for eCos
+FEATURE: Added PCF8812 gdisp driver
+FEATURE: Added PCD8544 gdisp driver
+FEATURE: Added Raspberry Pi board support
+FEATURE: Added R61505U gdisp driver
+FIX: Fix threading issues in GEvent for callbacks
+FEATURE: Added geventEventComplete()
+FEATURE: Added support for the RawOS real time operating system
+FEATURE: Operating System initialisation is now optional
+FEATURE: Prevent mouse events going to obscured widgets
+FEATURE: Add GFILE support for file lists
+FEATURE: Add GFILE support for C strings as files
+FEATURE: Add GFILE support for PetitFS
+FEATURE: Added SPFD54124B GDISP driver by user shilow
+FEATURE: Added GWIN GL3D window type
+FEATURE: Generalised all GWIN events to use a common prefix structure.
+FIX: Improve memory usage for the GWIN Frame widget.
+FEATURE: Added transparent custom draws for GWIN containers and frame widgets
+FEATURE: Added image custom draws for GWIN containers and frame widgets
+FEATURE: Added GDRIVER infrastructure. Ported GDISP to use it.
+FEATURE: Added gdispDrawArcSectors() and gdispFillArcSectors().
+FEATURE: Ported GINPUT MOUSE to GDRIVER infrastructure.
+FEATURE: Mouse/Touch now support both pen and finger mode.
+DEPRECATE: gwinAttachMouse() is now handled automaticly.
+FEATURE: Added MAX11802 touch driver by user steved
+FEATURE: Added STM32F429i-Discovery board support
+FEATURE: Added DejaVuSans20 and DejaVuSans20_aa built-in fonts
+FEATURE: Added MatrixFloat2D and MatrixFixed2D operations to GMISC
+FEATURE: Added polygon drawing demo (with rotation, scaling and translation)
+
+
+*** Release 2.1 ***
+FIX: Significant improvements to the way the MCU touch driver works.
+FEATURE: Add support for edge to edge touch calibration.
+FEATURE: Added progressbar widget
+FEATURE: Added gdispGDrawThickLine() by user jpa-
+DEPRECATE: TDISP module removed
+FIX: Console does not execute gwinPrintf() anymore if not visible
+FEATURE: Added gwinGetColor() and gwinGetBgColor()
+FEATURE: Console now has an optional backing store buffer (GWIN_CONSOLE_USE_HISTORY)
+FEATURE: Added smooth scrolling to list widget
+FEATURE: Increased performance of gwinListAddItem()
+FEATURE: Added FreeRTOS port
+FEATURE: Added gfxDeinit()
+FEATURE: Allow touch screen calibration in any display orientation
+FEATURE: New GFILE module to abstract File IO.
+FEATURE: Image file handling changed to use new GFILE module.
+DEPRECTATE: Old image opening functions deprecated.
+FEATURE: Restructure and simplify the include path for GFX
+FEATURE: Added LGDP4532 driver by user shilow
+FIX: Updated board files to support api changes in ChibiOS/RT 2.6.4
+FEATURE: Support for ChibiOS/RT 3.x
+FEATURE: Added gwinProgressbarStop() and gwinProgressbarReset()
+FEATURE: Added generic ILI93xx driver by xlh1460
+FEATURE: Added gwinListEnableRender()
+FEATURE: Added gwinLabelSetAttribute()
+FEATURE: Complete restructure of the GAUDIN and GAUDOUT into a common GAUDIO module
+FEATURE: Added a PWM audio play driver
+FEATURE: Update GADC audio recording driver to new GAUDIO format
+FEATURE: Added vs1053 audio play driver
+FEATURE: Added GAUDIO wave-play demo
+FEATURE: Added many GWIN simple demo's and updated the combined widget demo
+FEATURE: Added gwinEnable() and gwinDisable()
+FIX: Progressbar widget bug fix that could gwinProgressbarStop() to crash
+FIX: Imagebox widget bug fix that could cause gwinImageOpenFile() to crash
+FEATURE: GWIN containers such as "container" and "frame" which provides parent/children widget management
+FEATURE: Added gdispContrastColor()
+FEATURE: Added gwinShow() and gwinHide()
+FEATURE: ChibiOS/RT 3.x support and example for the Mikromedia STM32-M4 board.
+
+
+*** Release 2.0 ***
+FEATURE: GDISP Streaming API and demos.
+DEPRECATE: GDISP_NEED_ASYNC is now deprecated.
+DEPRECATE: 3rd party boing demo is now deprecated (replaced by GDISP Streaming demo)
+FIX: Remove GOS definitions from demo conf files so that it can be supplied by a makefile.
+FEATURE: Repair GDISP low level driver interfaces so they can now be included in the doxygen documentation.
+FEATURE: New driver interface for GDISP
+FEATURE: Multiple display support
+FEATURE: Multiple controller support
+FEATURE: Application pixel format no longer has to match the low level driver pixel format.
+FEATURE: Many more pixel formats are now supported.
+FEATURE: Many performance optimisations
+FEATURE: Vertical scrolling is now supported if the low level driver supports read_pixel.
+FEATURE: Add gdispFlush() for those controllers that need it
+FEATURE: Add GDISP_NEED_AUTOFLUSH and GDISP_NEED_TIMERFLUSH to automatically flush when required.
+FEATURE: Add support for generic portrait and landscape orientation modes
+FEATURE: Add macro GDISP_DEFAULT_ORIENTATION so an application can specify a default orientation.
+FEATURE: Driver files renamed to allow compiles when all object files go in the same directory
+FEATURE: New directory structure for board files. Predefined boards have all the hardware definitions predefined.
+FEATURE: Board definotions, example projects and makefiles for Win32.
+FEATURE: Board definitions, example projects and makefiles for X.
+FEATURE: Board definitions, example projects and makefiles for the Olimex SAM7-EX256 board.
+Feature: Board definitions, example projects and makefiles for the Olimex STM32-LCD board.
+FEATURE: Board definitions, example projects and makefiles for the Mikromedia STM32-M4 board.
+FEATURE: Board definitions, example projects and makefiles for the Marlin board.
+FEATURE: New invsqrt() routine added to GMISC
+
+
+*** Release 1.9 ***
+FEATURE: GWIN list boxes.
+FIX: POSIX port removed, now dedicated OS-X and Linux ports
+FIX: Several bugfixes
+FEATURE: mcufont integration
+FEATURE: SSD1306 driver by user goeck
+FEATURE: ST7565 driver by user sam0737
+FEATURE: ED060SC4 driver by user jpa-
+FIX: SSD1289 area filling bug fix by user samofab
+FEATURE: Added gwinListGetSelectedText()
+FEATURE: Added gwinListSetScroll()
+FEATURE: Added gwinLabelSetBorder()
+
+
+*** Release 1.8 ***
+FEATURE: Rename of the project from ChibiOS/GFX to uGFX
+FEATURE: Moved from github.com to bitbucket.org
+FEATURE: New website with a lot more of documentation
+FEATURE: Introduced dedicated discussion forum
+FEATURE: Complete rework of the widget manager (GWIN)
+FEATURE: Added a lot of new widgets
+FEATURE: Added gfxRealloc() to the GOS module
+FIX: gfxHalt() fix for the Win32 port
+FIX: Cleaned up board file mess
+
+
+*** Release 1.7 ***
+FEATURE: Added RA8875 GDISP driver
+FEATURE: Added FT5x06 GINPUT/touch driver
+FIX: Several bugfixes
+
+
+*** Release 1.6 ***
+FEATURE: Added ILI9325 driver - Thanks to Chris van Dongen aka _Sjaak
+FEATURE: Added TDISP module
+FIX: tdispGotoXY() renamed to tdispSetCursor()
+FEATURE: Addition of GADC, GMISC, GAUDIN, GAUDOUT subsystems
+FIX: Removal of the GDISP_LLD() macro
+DEPRECATE: Removal of the GDISP VMT
+FEATURE: Added SSD2119 GDISP driver
+FEATURE: Added GWIN_BUTTON_LAZY_RELEASE macro to disable cancel feature of buttons
+FEATURE: Implemented all four orientation modes for the ILI9320 GDISP driver
+FIX: Renamed every '__inline' macro to 'inline' for compiler compatibilities
+FEATURE: Supporting all standard functions in GDISP Nokia6610GE8 driver
+FEATURE: Added STMPE811 GINPUT driver
+FEATURE: Added gdispDrawPoly() and gdispFillConvexPoly()
+FEATURE: Added arrow button style to GWIN buttons
+FEATURE: Added the ability to specify a custom button drawing routine
+FEATURE: SSD1963 rework by username 'fred'
+FEATURE: Added Picture converter tool
+FEATURE: Added slider widget
+FEATURE: First MIPS32 (PIC32) board files contributed by user 'Dmytro'
+FEATURE: Added gwinDraw() routine
+FEATURE: Added GINPUT Dial support and driver using GADC
+FEATURE: Simplified assigning inputs to buttons and sliders
+FIX: Some fixes for the HD44780 TDISP driver by the user 'Frysk'
+FEATURE: Added ILI9481 by user 'Abhishek'
+FEATURE: Added enable/disable functions for widgets (Buttons)
+FEATURE: Added HX8347D driver by user 'Eddie'
+FEATURE: Added enhanced notepad demo by user 'Abhishek'
+FEATURE: Added GOS module (including sub modules such as GQUEUE)
+FEATURE: Added some functionalities to the TDISP module by user 'Frysk'
+
+
+*** Release 1.5 ***
+FEATURE: GEVENT - for passing event structures from Sources to Listeners
+FEATURE: GTIMER - thread context based once-off and periodic timers.
+FEATURE: GINPUT - extensible, multiple device-type, input sub-system.
+FEATURE: GWIN - full button, console and graph support
+FEATURE: Numerous touch calibration improvements
+FEATURE: Win32 driver - now support gdisp & ginput mouse/touch/toggle
+FEATURE: Win32 driver - full gdisp orientation support
+FEATURE: ILI9320 GDISP driver
+FEATURE: Nokia6610 GDISP driver split in to GE8 and GE12 variants
+FEATURE: Many GDISP drivers changed to use a board interface definition
+FEATURE: GFX source restructure with new gfx.h include file.
+DEPRECATE: console deprecated - replaced with gwin functionality
+DEPRECATE: graph deprecated - replaced with gwin functionality
+DEPRECATE: touchscreen deprecated - replaced with ginput functionality
+FEATURE: Numerous documentation improvements
+FEATURE: Added a number of module demo and test programs
+DEPRECATE: Remove of XPT2046 since full compatibility with ADS7843
+
+
+*** Release 1.4 ***
+FIX: Nokia 6610 fix
+FEATURE: New driver: Win32
+FEATURE: implementation of gdispFillArc()
+FIX: Hardware accelerate Arc routines
+FIX: Fix axis orientation for Arc routines
+FEATURE: new gdisp rounded box routines
+FEATURE: new gdispDrawStringBox()
+FEATURE: GWIN infrastructure
+FEATURE: now we fully support doxygen
+
+
+*** Release 1.3 ***
+FEATURE: added FSMC for SSD1289 / F4
+FEATURE: added calibration storage interface
+FIX: bugfix in filling functions for SSD1289
+FEATURE: added point_t struct in gdisp.h
+FEATURE: added graph module
+
+
+*** Release 1.2 ***
+FIX: orientation macros changed
+FIX: huge internal bugfix in orientation stuff (big thanks to Abhishek)
+FEATURE: added TOUCHPAD_XY_INVERTED macro
+FIX: struct cal renamed to struct cal_t
+FIX: SCREEN_WIDTH and SCREEN_HEIGHT renamed to GDISP_SCREEN_WIDTH and GDISP_SCREEN_HEIGHT
+FIX: struct TOUCHPAD_t renamed to struct TOUCHPADDriver_t
+FIX: struct GConsole renamed to struct GConsole_t
+FIX: lcdConsoleXXX() functions have been renamed to gfxConsoleXXX()
+FEATURE: FSMC for SSD1289 F2/F4
+
+
+*** Release 1.1 ***
+FIX: removed gdisp and touchpad prefix of driver directories
+UPDATE: added SSD1963 driver
+FIX: fixed Validation, VMT driver, console and BitBlit
+FEATURE: added clipping support
+FEATURE: addad gdispDrawArc()
+FEATURE: added SSD1963 DMA support
+FEATURE: added touchpad interface for storing calibration values (#define TOUCHPAD_STORE_CALIBRATION)
+CHANGE: replaced every GDISP_XXX macro with GDISP_XXX
+CHANGE: removed last digit of version number
+
diff --git a/demos/applications/mandelbrot/gfxconf.h b/demos/applications/mandelbrot/gfxconf.h
index 17c45142..26f2b89d 100644
--- a/demos/applications/mandelbrot/gfxconf.h
+++ b/demos/applications/mandelbrot/gfxconf.h
@@ -1,45 +1,45 @@
-/*
- * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu
- * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _GFXCONF_H
-#define _GFXCONF_H
-
-/* The operating system to use. One of these must be defined - preferably in your Makefile */
-//#define GFX_USE_OS_CHIBIOS GFXOFF
-//#define GFX_USE_OS_WIN32 GFXOFF
-//#define GFX_USE_OS_LINUX GFXOFF
-//#define GFX_USE_OS_OSX GFXOFF
-
-/* GFX sub-systems to turn on */
-#define GFX_USE_GDISP GFXON
-
-/* Features for the GDISP sub-system. */
-#define GDISP_NEED_VALIDATION GFXON
-
-#endif /* _GFXCONF_H */
+/*
+ * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu
+ * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _GFXCONF_H
+#define _GFXCONF_H
+
+/* The operating system to use. One of these must be defined - preferably in your Makefile */
+//#define GFX_USE_OS_CHIBIOS GFXOFF
+//#define GFX_USE_OS_WIN32 GFXOFF
+//#define GFX_USE_OS_LINUX GFXOFF
+//#define GFX_USE_OS_OSX GFXOFF
+
+/* GFX sub-systems to turn on */
+#define GFX_USE_GDISP GFXON
+
+/* Features for the GDISP sub-system. */
+#define GDISP_NEED_VALIDATION GFXON
+
+#endif /* _GFXCONF_H */
diff --git a/demos/applications/mandelbrot/main.c b/demos/applications/mandelbrot/main.c
index c35ba411..0a33047a 100644
--- a/demos/applications/mandelbrot/main.c
+++ b/demos/applications/mandelbrot/main.c
@@ -1,83 +1,83 @@
-/*
- * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu
- * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "gfx.h"
-
-void mandelbrot(float x1, float y1, float x2, float y2) {
- unsigned int i,j, width, height;
- gU16 iter;
- gColor color;
- float fwidth, fheight;
-
- float sy = y2 - y1;
- float sx = x2 - x1;
- const int MAX = 512;
-
- width = (unsigned int)gdispGetWidth();
- height = (unsigned int)gdispGetHeight();
- fwidth = width;
- fheight = height;
-
- for(i = 0; i < width; i++) {
- for(j = 0; j < height; j++) {
- float cy = j * sy / fheight + y1;
- float cx = i * sx / fwidth + x1;
- float x=0.0f, y=0.0f, xx=0.0f, yy=0.0f;
- for(iter=0; iter <= MAX && xx+yy<4.0f; iter++) {
- xx = x*x;
- yy = y*y;
- y = 2.0f*x*y + cy;
- x = xx - yy + cx;
- }
- //color = ((iter << 8) | (iter&0xFF));
- color = RGB2COLOR(iter<<7, iter<<4, iter);
- gdispDrawPixel(i, j, color);
- }
- }
-}
-
-int main(void) {
- float cx, cy;
- float zoom = 1.0f;
-
- gfxInit();
-
- /* where to zoom in */
- cx = -0.086f;
- cy = 0.85f;
-
- while(1) {
- mandelbrot(-2.0f*zoom+cx, -1.5f*zoom+cy, 2.0f*zoom+cx, 1.5f*zoom+cy);
-
- zoom *= 0.7f;
- if(zoom <= 0.00001f)
- zoom = 1.0f;
- }
-}
-
+/*
+ * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu
+ * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "gfx.h"
+
+void mandelbrot(float x1, float y1, float x2, float y2) {
+ unsigned int i,j, width, height;
+ gU16 iter;
+ gColor color;
+ float fwidth, fheight;
+
+ float sy = y2 - y1;
+ float sx = x2 - x1;
+ const int MAX = 512;
+
+ width = (unsigned int)gdispGetWidth();
+ height = (unsigned int)gdispGetHeight();
+ fwidth = width;
+ fheight = height;
+
+ for(i = 0; i < width; i++) {
+ for(j = 0; j < height; j++) {
+ float cy = j * sy / fheight + y1;
+ float cx = i * sx / fwidth + x1;
+ float x=0.0f, y=0.0f, xx=0.0f, yy=0.0f;
+ for(iter=0; iter <= MAX && xx+yy<4.0f; iter++) {
+ xx = x*x;
+ yy = y*y;
+ y = 2.0f*x*y + cy;
+ x = xx - yy + cx;
+ }
+ //color = ((iter << 8) | (iter&0xFF));
+ color = RGB2COLOR(iter<<7, iter<<4, iter);
+ gdispDrawPixel(i, j, color);
+ }
+ }
+}
+
+int main(void) {
+ float cx, cy;
+ float zoom = 1.0f;
+
+ gfxInit();
+
+ /* where to zoom in */
+ cx = -0.086f;
+ cy = 0.85f;
+
+ while(1) {
+ mandelbrot(-2.0f*zoom+cx, -1.5f*zoom+cy, 2.0f*zoom+cx, 1.5f*zoom+cy);
+
+ zoom *= 0.7f;
+ if(zoom <= 0.00001f)
+ zoom = 1.0f;
+ }
+}
+
diff --git a/demos/applications/notepad/gfxconf.h b/demos/applications/notepad/gfxconf.h
index 9110d6e8..fda08dd9 100644
--- a/demos/applications/notepad/gfxconf.h
+++ b/demos/applications/notepad/gfxconf.h
@@ -1,60 +1,60 @@
-/*
- * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu
- * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _GFXCONF_H
-#define _GFXCONF_H
-
-/* The operating system to use. One of these must be defined - preferably in your Makefile */
-//#define GFX_USE_OS_CHIBIOS GFXOFF
-//#define GFX_USE_OS_WIN32 GFXOFF
-//#define GFX_USE_OS_LINUX GFXOFF
-//#define GFX_USE_OS_OSX GFXOFF
-
-/* GFX sub-systems to turn on */
-#define GFX_USE_GDISP GFXON
-#define GFX_USE_GEVENT GFXON
-#define GFX_USE_GTIMER GFXON
-#define GFX_USE_GINPUT GFXON
-
-/* Features for the GDISP sub-system. */
-#define GDISP_NEED_VALIDATION GFXON
-#define GDISP_NEED_CLIP GFXON
-#define GDISP_NEED_TEXT GFXON
-#define GDISP_NEED_CIRCLE GFXON
-#define GDISP_NEED_MULTITHREAD GFXON
-
-/* Builtin Fonts */
-#define GDISP_INCLUDE_FONT_DEJAVUSANS12_AA GFXON
-#define GDISP_INCLUDE_FONT_DEJAVUSANS24_AA GFXON
-#define GDISP_NEED_ANTIALIAS GFXON
-
-/* Features for the GINPUT sub-system. */
-#define GINPUT_NEED_MOUSE GFXON
-
-#endif /* _GFXCONF_H */
+/*
+ * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu
+ * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _GFXCONF_H
+#define _GFXCONF_H
+
+/* The operating system to use. One of these must be defined - preferably in your Makefile */
+//#define GFX_USE_OS_CHIBIOS GFXOFF
+//#define GFX_USE_OS_WIN32 GFXOFF
+//#define GFX_USE_OS_LINUX GFXOFF
+//#define GFX_USE_OS_OSX GFXOFF
+
+/* GFX sub-systems to turn on */
+#define GFX_USE_GDISP GFXON
+#define GFX_USE_GEVENT GFXON
+#define GFX_USE_GTIMER GFXON
+#define GFX_USE_GINPUT GFXON
+
+/* Features for the GDISP sub-system. */
+#define GDISP_NEED_VALIDATION GFXON
+#define GDISP_NEED_CLIP GFXON
+#define GDISP_NEED_TEXT GFXON
+#define GDISP_NEED_CIRCLE GFXON
+#define GDISP_NEED_MULTITHREAD GFXON
+
+/* Builtin Fonts */
+#define GDISP_INCLUDE_FONT_DEJAVUSANS12_AA GFXON
+#define GDISP_INCLUDE_FONT_DEJAVUSANS24_AA GFXON
+#define GDISP_NEED_ANTIALIAS GFXON
+
+/* Features for the GINPUT sub-system. */
+#define GINPUT_NEED_MOUSE GFXON
+
+#endif /* _GFXCONF_H */
diff --git a/demos/applications/notepad/main.c b/demos/applications/notepad/main.c
index 85d8e0f0..faf5d00b 100644
--- a/demos/applications/notepad/main.c
+++ b/demos/applications/notepad/main.c
@@ -1,116 +1,116 @@
-/*
- * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu
- * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "gfx.h"
-
-#define COLOR_SIZE 20
-#define PEN_SIZE 20
-#define OFFSET 3
-
-#define COLOR_BOX(a) (ev.x >= a && ev.x <= a + COLOR_SIZE)
-#define PEN_BOX(a) (ev.y >= a && ev.y <= a + COLOR_SIZE)
-#define GET_COLOR(a) (COLOR_BOX(a * COLOR_SIZE + OFFSET))
-#define GET_PEN(a) (PEN_BOX(a * 2 * PEN_SIZE + OFFSET))
-#define DRAW_COLOR(a) (a * COLOR_SIZE + OFFSET)
-#define DRAW_PEN(a) (a * 2 * PEN_SIZE + OFFSET)
-#define DRAW_AREA(x, y) (x >= PEN_SIZE + OFFSET + 3 && x <= gdispGetWidth() && \
- y >= COLOR_SIZE + OFFSET + 3 && y <= gdispGetHeight())
-
-void drawScreen(void) {
- char *msg = "uGFX";
- gFont font1, font2;
-
- font1 = gdispOpenFont("DejaVuSans24*");
- font2 = gdispOpenFont("DejaVuSans12*");
-
- gdispClear(GFX_WHITE);
- gdispDrawString(gdispGetWidth()-gdispGetStringWidth(msg, font1)-3, 3, msg, font1, GFX_BLACK);
-
- /* colors */
- gdispFillArea(0 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_BLACK); /* Black */
- gdispFillArea(1 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_RED); /* Red */
- gdispFillArea(2 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_YELLOW); /* Yellow */
- gdispFillArea(3 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_GREEN); /* Green */
- gdispFillArea(4 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_BLUE); /* Blue */
- gdispDrawBox (5 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_WHITE); /* White */
-
- /* pens */
- gdispFillStringBox(OFFSET * 2, DRAW_PEN(1), PEN_SIZE, PEN_SIZE, "1", font2, GFX_WHITE, GFX_BLACK, gJustifyCenter);
- gdispFillStringBox(OFFSET * 2, DRAW_PEN(2), PEN_SIZE, PEN_SIZE, "2", font2, GFX_WHITE, GFX_BLACK, gJustifyCenter);
- gdispFillStringBox(OFFSET * 2, DRAW_PEN(3), PEN_SIZE, PEN_SIZE, "3", font2, GFX_WHITE, GFX_BLACK, gJustifyCenter);
- gdispFillStringBox(OFFSET * 2, DRAW_PEN(4), PEN_SIZE, PEN_SIZE, "4", font2, GFX_WHITE, GFX_BLACK, gJustifyCenter);
- gdispFillStringBox(OFFSET * 2, DRAW_PEN(5), PEN_SIZE, PEN_SIZE, "5", font2, GFX_WHITE, GFX_BLACK, gJustifyCenter);
-
- gdispCloseFont(font1);
- gdispCloseFont(font2);
-}
-
-GEventMouse ev;
-
-int main(void) {
- gColor color = GFX_BLACK;
- gU16 pen = 0;
-
- gfxInit();
- ginputGetMouse(0);
-
- drawScreen();
-
- while (1) {
- ginputGetMouseStatus(0, &ev);
- if (!(ev.buttons & GINPUT_MOUSE_BTN_LEFT))
- continue;
-
- /* inside color box ? */
- if(ev.y >= OFFSET && ev.y <= COLOR_SIZE) {
- if(GET_COLOR(0)) color = GFX_BLACK;
- else if(GET_COLOR(1)) color = GFX_RED;
- else if(GET_COLOR(2)) color = GFX_YELLOW;
- else if(GET_COLOR(3)) color = GFX_GREEN;
- else if(GET_COLOR(4)) color = GFX_BLUE;
- else if(GET_COLOR(5)) color = GFX_WHITE;
-
- /* inside pen box ? */
- } else if(ev.x >= OFFSET && ev.x <= PEN_SIZE) {
- if(GET_PEN(1)) pen = 0;
- else if(GET_PEN(2)) pen = 1;
- else if(GET_PEN(3)) pen = 2;
- else if(GET_PEN(4)) pen = 3;
- else if(GET_PEN(5)) pen = 4;
-
- /* inside drawing area ? */
- } else if(DRAW_AREA(ev.x, ev.y)) {
- if(pen == 0)
- gdispDrawPixel(ev.x, ev.y, color);
- else
- gdispFillCircle(ev.x, ev.y, pen, color);
- }
- }
-}
-
+/*
+ * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu
+ * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "gfx.h"
+
+#define COLOR_SIZE 20
+#define PEN_SIZE 20
+#define OFFSET 3
+
+#define COLOR_BOX(a) (ev.x >= a && ev.x <= a + COLOR_SIZE)
+#define PEN_BOX(a) (ev.y >= a && ev.y <= a + COLOR_SIZE)
+#define GET_COLOR(a) (COLOR_BOX(a * COLOR_SIZE + OFFSET))
+#define GET_PEN(a) (PEN_BOX(a * 2 * PEN_SIZE + OFFSET))
+#define DRAW_COLOR(a) (a * COLOR_SIZE + OFFSET)
+#define DRAW_PEN(a) (a * 2 * PEN_SIZE + OFFSET)
+#define DRAW_AREA(x, y) (x >= PEN_SIZE + OFFSET + 3 && x <= gdispGetWidth() && \
+ y >= COLOR_SIZE + OFFSET + 3 && y <= gdispGetHeight())
+
+void drawScreen(void) {
+ char *msg = "uGFX";
+ gFont font1, font2;
+
+ font1 = gdispOpenFont("DejaVuSans24*");
+ font2 = gdispOpenFont("DejaVuSans12*");
+
+ gdispClear(GFX_WHITE);
+ gdispDrawString(gdispGetWidth()-gdispGetStringWidth(msg, font1)-3, 3, msg, font1, GFX_BLACK);
+
+ /* colors */
+ gdispFillArea(0 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_BLACK); /* Black */
+ gdispFillArea(1 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_RED); /* Red */
+ gdispFillArea(2 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_YELLOW); /* Yellow */
+ gdispFillArea(3 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_GREEN); /* Green */
+ gdispFillArea(4 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_BLUE); /* Blue */
+ gdispDrawBox (5 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_WHITE); /* White */
+
+ /* pens */
+ gdispFillStringBox(OFFSET * 2, DRAW_PEN(1), PEN_SIZE, PEN_SIZE, "1", font2, GFX_WHITE, GFX_BLACK, gJustifyCenter);
+ gdispFillStringBox(OFFSET * 2, DRAW_PEN(2), PEN_SIZE, PEN_SIZE, "2", font2, GFX_WHITE, GFX_BLACK, gJustifyCenter);
+ gdispFillStringBox(OFFSET * 2, DRAW_PEN(3), PEN_SIZE, PEN_SIZE, "3", font2, GFX_WHITE, GFX_BLACK, gJustifyCenter);
+ gdispFillStringBox(OFFSET * 2, DRAW_PEN(4), PEN_SIZE, PEN_SIZE, "4", font2, GFX_WHITE, GFX_BLACK, gJustifyCenter);
+ gdispFillStringBox(OFFSET * 2, DRAW_PEN(5), PEN_SIZE, PEN_SIZE, "5", font2, GFX_WHITE, GFX_BLACK, gJustifyCenter);
+
+ gdispCloseFont(font1);
+ gdispCloseFont(font2);
+}
+
+GEventMouse ev;
+
+int main(void) {
+ gColor color = GFX_BLACK;
+ gU16 pen = 0;
+
+ gfxInit();
+ ginputGetMouse(0);
+
+ drawScreen();
+
+ while (1) {
+ ginputGetMouseStatus(0, &ev);
+ if (!(ev.buttons & GINPUT_MOUSE_BTN_LEFT))
+ continue;
+
+ /* inside color box ? */
+ if(ev.y >= OFFSET && ev.y <= COLOR_SIZE) {
+ if(GET_COLOR(0)) color = GFX_BLACK;
+ else if(GET_COLOR(1)) color = GFX_RED;
+ else if(GET_COLOR(2)) color = GFX_YELLOW;
+ else if(GET_COLOR(3)) color = GFX_GREEN;
+ else if(GET_COLOR(4)) color = GFX_BLUE;
+ else if(GET_COLOR(5)) color = GFX_WHITE;
+
+ /* inside pen box ? */
+ } else if(ev.x >= OFFSET && ev.x <= PEN_SIZE) {
+ if(GET_PEN(1)) pen = 0;
+ else if(GET_PEN(2)) pen = 1;
+ else if(GET_PEN(3)) pen = 2;
+ else if(GET_PEN(4)) pen = 3;
+ else if(GET_PEN(5)) pen = 4;
+
+ /* inside drawing area ? */
+ } else if(DRAW_AREA(ev.x, ev.y)) {
+ if(pen == 0)
+ gdispDrawPixel(ev.x, ev.y, color);
+ else
+ gdispFillCircle(ev.x, ev.y, pen, color);
+ }
+ }
+}
+
diff --git a/demos/modules/gdisp/basics/gfxconf.h b/demos/modules/gdisp/basics/gfxconf.h
index 931f2fe7..ae9f321d 100644
--- a/demos/modules/gdisp/basics/gfxconf.h
+++ b/demos/modules/gdisp/basics/gfxconf.h
@@ -1,47 +1,47 @@
-/*
- * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu
- * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _GFXCONF_H
-#define _GFXCONF_H
-
-/* The operating system to use. One of these must be defined - preferably in your Makefile */
-//#define GFX_USE_OS_CHIBIOS GFXOFF
-//#define GFX_USE_OS_WIN32 GFXOFF
-//#define GFX_USE_OS_LINUX GFXOFF
-//#define GFX_USE_OS_OSX GFXOFF
-
-/* GFX sub-systems to turn on */
-#define GFX_USE_GDISP GFXON
-
-/* Features for the GDISP sub-system. */
-#define GDISP_NEED_VALIDATION GFXON
-#define GDISP_NEED_CLIP GFXON
-
-#endif /* _GFXCONF_H */
-
+/*
+ * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu
+ * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _GFXCONF_H
+#define _GFXCONF_H
+
+/* The operating system to use. One of these must be defined - preferably in your Makefile */
+//#define GFX_USE_OS_CHIBIOS GFXOFF
+//#define GFX_USE_OS_WIN32 GFXOFF
+//#define GFX_USE_OS_LINUX GFXOFF
+//#define GFX_USE_OS_OSX GFXOFF
+
+/* GFX sub-systems to turn on */
+#define GFX_USE_GDISP GFXON
+
+/* Features for the GDISP sub-system. */
+#define GDISP_NEED_VALIDATION GFXON
+#define GDISP_NEED_CLIP GFXON
+
+#endif /* _GFXCONF_H */
+
diff --git a/demos/modules/gdisp/basics/main.c b/demos/modules/gdisp/basics/main.c
index ac7870f1..775cdb71 100644
--- a/demos/modules/gdisp/basics/main.c
+++ b/demos/modules/gdisp/basics/main.c
@@ -1,55 +1,55 @@
-/*
- * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu
- * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "gfx.h"
-
-int main(void) {
- gCoord width, height;
- gCoord i, j;
-
- // Initialize and clear the display
- gfxInit();
-
- // Get the screen size
- width = gdispGetWidth();
- height = gdispGetHeight();
-
- // Code Here
- gdispDrawBox(10, 10, width/2, height/2, GFX_YELLOW);
- gdispFillArea(width/2, height/2, width/2-10, height/2-10, GFX_BLUE);
- gdispDrawLine(5, 30, width-50, height-40, GFX_RED);
-
- for(i = 5, j = 0; i < width && j < height; i += 7, j += i/20)
- gdispDrawPixel(i, j, GFX_WHITE);
-
- while(1) {
- gfxSleepMilliseconds(500);
- }
-}
-
+/*
+ * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu
+ * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "gfx.h"
+
+int main(void) {
+ gCoord width, height;
+ gCoord i, j;
+
+ // Initialize and clear the display
+ gfxInit();
+
+ // Get the screen size
+ width = gdispGetWidth();
+ height = gdispGetHeight();
+
+ // Code Here
+ gdispDrawBox(10, 10, width/2, height/2, GFX_YELLOW);
+ gdispFillArea(width/2, height/2, width/2-10, height/2-10, GFX_BLUE);
+ gdispDrawLine(5, 30, width-50, height-40, GFX_RED);
+
+ for(i = 5, j = 0; i < width && j < height; i += 7, j += i/20)
+ gdispDrawPixel(i, j, GFX_WHITE);
+
+ while(1) {
+ gfxSleepMilliseconds(500);
+ }
+}
+
diff --git a/demos/modules/gdisp/circles/gfxconf.h b/demos/modules/gdisp/circles/gfxconf.h
index a0534700..ef99beec 100644
--- a/demos/modules/gdisp/circles/gfxconf.h
+++ b/demos/modules/gdisp/circles/gfxconf.h
@@ -1,55 +1,55 @@
-/*
- * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu
- * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _GFXCONF_H
-#define _GFXCONF_H
-
-/* The operating system to use. One of these must be defined - preferably in your Makefile */
-//#define GFX_USE_OS_CHIBIOS GFXOFF
-//#define GFX_USE_OS_WIN32 GFXOFF
-//#define GFX_USE_OS_LINUX GFXOFF
-//#define GFX_USE_OS_OSX GFXOFF
-
-/* GFX sub-systems to turn on */
-#define GFX_USE_GDISP GFXON
-#define GFX_USE_GMISC GFXON
-
-/* Features for the GDISP subsystem. */
-#define GDISP_NEED_VALIDATION GFXON
-#define GDISP_NEED_CLIP GFXON
-#define GDISP_NEED_CIRCLE GFXON
-#define GDISP_NEED_ELLIPSE GFXON
-#define GDISP_NEED_ARC GFXON
-
-/* Features for the GMISC subsystem */
-#define GMISC_NEED_FIXEDTRIG GFXON
-#define GMISC_NEED_FASTTRIG GFXON
-
-#endif /* _GFXCONF_H */
-
+/*
+ * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu
+ * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _GFXCONF_H
+#define _GFXCONF_H
+
+/* The operating system to use. One of these must be defined - preferably in your Makefile */
+//#define GFX_USE_OS_CHIBIOS GFXOFF
+//#define GFX_USE_OS_WIN32 GFXOFF
+//#define GFX_USE_OS_LINUX GFXOFF
+//#define GFX_USE_OS_OSX GFXOFF
+
+/* GFX sub-systems to turn on */
+#define GFX_USE_GDISP GFXON
+#define GFX_USE_GMISC GFXON
+
+/* Features for the GDISP subsystem. */
+#define GDISP_NEED_VALIDATION GFXON
+#define GDISP_NEED_CLIP GFXON
+#define GDISP_NEED_CIRCLE GFXON
+#define GDISP_NEED_ELLIPSE GFXON
+#define GDISP_NEED_ARC GFXON
+
+/* Features for the GMISC subsystem */
+#define GMISC_NEED_FIXEDTRIG GFXON
+#define GMISC_NEED_FASTTRIG GFXON
+
+#endif /* _GFXCONF_H */
+
diff --git a/demos/modules/gdisp/circles/main.c b/demos/modules/gdisp/circles/main.c
index bd7d5c2e..d4d8492f 100644
--- a/demos/modules/gdisp/circles/main.c
+++ b/demos/modules/gdisp/circles/main.c
@@ -1,54 +1,54 @@
-/*
- * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu
- * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "gfx.h"
-
-int main(void) {
- gCoord width, height;
-
- // Initialize and clear the display
- gfxInit();
-
- // Get the screen size
- width = gdispGetWidth();
- height = gdispGetHeight();
-
- // Code Here
- gdispFillArc(width/2, height/2, width/4, -10, -45, GFX_WHITE);
- gdispDrawCircle(width/2+width/8, height/2-height/8, 13, GFX_GREEN);
- gdispFillCircle (width/2+width/8, height/2-height/8, 10, GFX_RED);
- gdispDrawArc(width/2+width/8, height/2-height/8, 20, 25, 115, GFX_GRAY);
- gdispFillEllipse (width-width/6, height-height/6, width/8, height/16, GFX_BLUE);
- gdispDrawEllipse (width-width/6, height-height/6, width/16, height/8, GFX_YELLOW);
-
- while(1) {
- gfxSleepMilliseconds(500);
- }
-}
-
+/*
+ * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu
+ * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "gfx.h"
+
+int main(void) {
+ gCoord width, height;
+
+ // Initialize and clear the display
+ gfxInit();
+
+ // Get the screen size
+ width = gdispGetWidth();
+ height = gdispGetHeight();
+
+ // Code Here
+ gdispFillArc(width/2, height/2, width/4, -10, -45, GFX_WHITE);
+ gdispDrawCircle(width/2+width/8, height/2-height/8, 13, GFX_GREEN);
+ gdispFillCircle (width/2+width/8, height/2-height/8, 10, GFX_RED);
+ gdispDrawArc(width/2+width/8, height/2-height/8, 20, 25, 115, GFX_GRAY);
+ gdispFillEllipse (width-width/6, height-height/6, width/8, height/16, GFX_BLUE);
+ gdispDrawEllipse (width-width/6, height-height/6, width/16, height/8, GFX_YELLOW);
+
+ while(1) {
+ gfxSleepMilliseconds(500);
+ }
+}
+
diff --git a/demos/modules/gdisp/fonts_cyrillic/main.c b/demos/modules/gdisp/fonts_cyrillic/main.c
index ac1d8c71..651e8312 100644
--- a/demos/modules/gdisp/fonts_cyrillic/main.c
+++ b/demos/modules/gdisp/fonts_cyrillic/main.c
@@ -1,49 +1,49 @@
-/*
- * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu
- * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "gfx.h"
-
-int main(void) {
- gFont font1;
-
- // Initialize uGFX and the underlying system
- gfxInit();
-
- // Get the fonts we want to use
- font1 = gdispOpenFont("Archangelsk Regular 12");
-
- // Demonstrate our other fonts
- gdispDrawString(10, 10, "привет мир", font1, GFX_YELLOW);
-
- // Wait forever
- while(1) {
- gfxSleepMilliseconds(500);
- }
-}
-
+/*
+ * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu
+ * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "gfx.h"
+
+int main(void) {
+ gFont font1;
+
+ // Initialize uGFX and the underlying system
+ gfxInit();
+
+ // Get the fonts we want to use
+ font1 = gdispOpenFont("Archangelsk Regular 12");
+
+ // Demonstrate our other fonts
+ gdispDrawString(10, 10, "привет мир", font1, GFX_YELLOW);
+
+ // Wait forever
+ while(1) {
+ gfxSleepMilliseconds(500);
+ }
+}
+
diff --git a/demos/modules/gtimer/gfxconf.h b/demos/modules/gtimer/gfxconf.h
index 4a6807e0..16b61902 100644
--- a/demos/modules/gtimer/gfxconf.h
+++ b/demos/modules/gtimer/gfxconf.h
@@ -1,42 +1,42 @@
-/*
- * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu
- * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _GFXCONF_H
-#define _GFXCONF_H
-
-/* The operating system to use. One of these must be defined - preferably in your Makefile */
-//#define GFX_USE_OS_CHIBIOS GFXOFF
-//#define GFX_USE_OS_WIN32 GFXOFF
-//#define GFX_USE_OS_LINUX GFXOFF
-//#define GFX_USE_OS_OSX GFXOFF
-
-/* GFX sub-systems to turn on */
-#define GFX_USE_GTIMER GFXON
-
-#endif /* _GFXCONF_H */
+/*
+ * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu
+ * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _GFXCONF_H
+#define _GFXCONF_H
+
+/* The operating system to use. One of these must be defined - preferably in your Makefile */
+//#define GFX_USE_OS_CHIBIOS GFXOFF
+//#define GFX_USE_OS_WIN32 GFXOFF
+//#define GFX_USE_OS_LINUX GFXOFF
+//#define GFX_USE_OS_OSX GFXOFF
+
+/* GFX sub-systems to turn on */
+#define GFX_USE_GTIMER GFXON
+
+#endif /* _GFXCONF_H */
diff --git a/demos/modules/gtimer/main.c b/demos/modules/gtimer/main.c
index 7612772c..9fd17c0a 100644
--- a/demos/modules/gtimer/main.c
+++ b/demos/modules/gtimer/main.c
@@ -1,65 +1,65 @@
-/*
- * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu
- * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
- *
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "gfx.h"
-
-GTimer GT1, GT2;
-
-void callback1(void* arg) {
- (void)arg;
-
- palTogglePad(GPIOD, GPIOD_LED3);
-}
-
-void callback2(void* arg) {
- (void)arg;
-
- palSetPad(GPIOD, GPIOD_LED4);
-}
-
-int main(void) {
- gfxInit();
-
- /* initialize the timers */
- gtimerInit(>1);
- gtimerInit(>2);
-
- /* continious mode - callback1() called without any argument every 250ms */
- gtimerStart(>1, callback1, 0, gTrue, 250);
-
- /* single shot mode - callback2() called without any argument once after 1s */
- gtimerStart(>2, callback2, 0, gFalse, 1000);
-
- while(1) {
- gfxSleepMilliseconds(500);
- }
-
- return 0;
-}
-
+/*
+ * Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu
+ * Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "gfx.h"
+
+GTimer GT1, GT2;
+
+void callback1(void* arg) {
+ (void)arg;
+
+ palTogglePad(GPIOD, GPIOD_LED3);
+}
+
+void callback2(void* arg) {
+ (void)arg;
+
+ palSetPad(GPIOD, GPIOD_LED4);
+}
+
+int main(void) {
+ gfxInit();
+
+ /* initialize the timers */
+ gtimerInit(>1);
+ gtimerInit(>2);
+
+ /* continious mode - callback1() called without any argument every 250ms */
+ gtimerStart(>1, callback1, 0, gTrue, 250);
+
+ /* single shot mode - callback2() called without any argument once after 1s */
+ gtimerStart(>2, callback2, 0, gFalse, 1000);
+
+ while(1) {
+ gfxSleepMilliseconds(500);
+ }
+
+ return 0;
+}
+
diff --git a/docs/readme.txt b/docs/readme.txt
index a9009fd9..2c759a22 100644
--- a/docs/readme.txt
+++ b/docs/readme.txt
@@ -1,2 +1,2 @@
-If there is no html directory containing the HTML version of the API documentation, you
-can find an online version of the documentation at http://api.ugfx.io
+If there is no html directory containing the HTML version of the API documentation, you
+can find an online version of the documentation at http://api.ugfx.io
diff --git a/drivers/gdisp/HX8347D/HX8347D.h b/drivers/gdisp/HX8347D/HX8347D.h
index 6f69bc73..69d0b5b9 100644
--- a/drivers/gdisp/HX8347D/HX8347D.h
+++ b/drivers/gdisp/HX8347D/HX8347D.h
@@ -1,134 +1,134 @@
-/*
- * This file is subject to the terms of the GFX License. If a copy of
- * the license was not distributed with this file, you can obtain one at:
- *
- * http://ugfx.io/license.html
- */
-
-#ifndef _HX8347D_H
-#define _HX8347D_H
-
-/* HX8347D registers */
-
-/* page 0 registers */
-#define HX8347D_REG_HID 0x00 /* Himax ID */
-#define HX8347D_REG_DMODE 0x01 /* Display mode control */
-#define HX8347D_REG_SCH 0x02 /* Column address start high */
-#define HX8347D_REG_SCL 0x03 /* Column address start low */
-#define HX8347D_REG_ECH 0x04 /* Column address end high */
-#define HX8347D_REG_ECL 0x05 /* Column address end low */
-#define HX8347D_REG_SPH 0x06 /* Row address start high */
-#define HX8347D_REG_SPL 0x07 /* Row address start low */
-#define HX8347D_REG_EPH 0x08 /* Row address end high */
-#define HX8347D_REG_EPL 0x09 /* Row address end low */
-#define HX8347D_REG_PSLH 0x0a /* Partial area start row high */
-#define HX8347D_REG_PSLL 0x0b /* Partial area start row low */
-#define HX8347D_REG_PELH 0x0c /* Partial area end row high */
-#define HX8347D_REG_PELL 0x0d /* Partial area end row low */
-#define HX8347D_REG_TFAH 0x0e /* Vertical scroll top fixed area high */
-#define HX8347D_REG_TFAL 0x0f /* Vertical scroll top fixed area low */
-
-#define HX8347D_REG_VSAH 0x10 /* Vertical scroll height area high */
-#define HX8347D_REG_VSAL 0x11 /* Vertical scroll height area low */
-#define HX8347D_REG_BFAH 0x12 /* Vertical scroll button area high */
-#define HX8347D_REG_BFAL 0x13 /* Vertical scroll button area low */
-#define HX8347D_REG_VSPH 0x14 /* Vertical scroll start address high */
-#define HX8347D_REG_VSPL 0x15 /* Vertical scroll start address low */
-#define HX8347D_REG_MAC 0x16 /* Memory access control */
-#define HX8347D_REG_COLMOD 0x17 /* COLMOD */
-#define HX8347D_REG_OSCCH 0x18 /* OSC control 2 */
-#define HX8347D_REG_OSCCL 0x19 /* OSC control 1 */
-#define HX8347D_REG_PWC1 0x1a /* Power control 1 */
-#define HX8347D_REG_PWC2 0x1b /* Power control 2 */
-#define HX8347D_REG_PWC3 0x1c /* Power control 3 */
-#define HX8347D_REG_PWC4 0x1d /* Power control 4 */
-#define HX8347D_REG_PWC5 0x1e /* Power control 5 */
-#define HX8347D_REG_PWC6 0x1f /* Power control 6 */
-
-#define HX8347D_REG_SRAMWC 0x22 /* SRAM write control */
-#define HX8347D_REG_VMF 0x23 /* VCOM control 1 */
-#define HX8347D_REG_VMH 0x24 /* VCOM control 2 */
-#define HX8347D_REG_VML 0x25 /* VCOM control 3 */
-#define HX8347D_REG_DC1 0x26 /* Display control 1 */
-#define HX8347D_REG_DC2 0x27 /* Display control 2 */
-#define HX8347D_REG_DC3 0x28 /* Display control 3 */
-#define HX8347D_REG_FRC1 0x29 /* Frame rate control 1 */
-#define HX8347D_REG_FRC2 0x2a /* Frame rate control 2 */
-#define HX8347D_REG_FRC3 0x2b /* Frame rate control 3 */
-#define HX8347D_REG_FRC4 0x2c /* Frame rate control 4 */
-#define HX8347D_REG_GDON 0x2d /* Cycle control 1 */
-#define HX8347D_REG_GDOF 0x2e /* Cycle control 2 */
-#define HX8347D_REG_DINV 0x2f /* Display inversion */
-
-#define HX8347D_REG_RGB1 0x31 /* RGB interface control 1 */
-#define HX8347D_REG_RGB2 0x32 /* RGB interface control 2 */
-#define HX8347D_REG_RGB3 0x33 /* RGB interface control 3 */
-#define HX8347D_REG_RGB4 0x34 /* RGB interface control 4 */
-#define HX8347D_REG_PCH 0x36 /* Panel characteristic */
-#define HX8347D_REG_OTP1 0x38 /* OTP control 1 */
-#define HX8347D_REG_OTP2 0x39 /* OTP control 2 */
-#define HX8347D_REG_OTP3 0x3a /* OTP control 3 */
-#define HX8347D_REG_CABC1 0x3c /* CABC control 1 */
-#define HX8347D_REG_CABC2 0x3d /* CABC control 2 */
-#define HX8347D_REG_CABC3 0x3e /* CABC control 3 */
-#define HX8347D_REG_CABC4 0x3f /* CABC control 4 */
-
-#define HX8347D_REG_VRP0 0x40 /* Gamma control 1 */
-#define HX8347D_REG_VRP1 0x41 /* Gamma control 2 */
-#define HX8347D_REG_VRP2 0x42 /* Gamma control 3 */
-#define HX8347D_REG_VRP3 0x43 /* Gamma control 4 */
-#define HX8347D_REG_VRP4 0x44 /* Gamma control 5 */
-#define HX8347D_REG_VRP5 0x45 /* Gamma control 6 */
-#define HX8347D_REG_PRP0 0x46 /* Gamma control 7 */
-#define HX8347D_REG_PRP1 0x47 /* Gamma control 8 */
-#define HX8347D_REG_PKP0 0x48 /* Gamma control 9 */
-#define HX8347D_REG_PKP1 0x49 /* Gamma control 10 */
-#define HX8347D_REG_PKP2 0x4a /* Gamma control 11 */
-#define HX8347D_REG_PKP3 0x4b /* Gamma control 12 */
-#define HX8347D_REG_PKP4 0x4c /* Gamma control 13 */
-
-#define HX8347D_REG_VRN0 0x50 /* Gamma control 14 */
-#define HX8347D_REG_VRN1 0x51 /* Gamma control 15 */
-#define HX8347D_REG_VRN2 0x52 /* Gamma control 16 */
-#define HX8347D_REG_VRN3 0x53 /* Gamma control 17 */
-#define HX8347D_REG_VRN4 0x54 /* Gamma control 18 */
-#define HX8347D_REG_VRN5 0x55 /* Gamma control 19 */
-#define HX8347D_REG_PRN0 0x56 /* Gamma control 20 */
-#define HX8347D_REG_PRN1 0x57 /* Gamma control 21 */
-#define HX8347D_REG_PKN0 0x58 /* Gamma control 22 */
-#define HX8347D_REG_PKN1 0x59 /* Gamma control 23 */
-#define HX8347D_REG_PKN2 0x5a /* Gamma control 24 */
-#define HX8347D_REG_PKN3 0x5b /* Gamma control 25 */
-#define HX8347D_REG_PKN4 0x5c /* Gamma control 26 */
-#define HX8347D_REG_CGM 0x5d /* Gamma control 27 */
-
-#define HX8347D_REG_TEC 0x60 /* TE control */
-
-#define HX8347D_REG_PS1 0xe4 /* Power saving 1 */
-#define HX8347D_REG_PS2 0xe5 /* Power saving 2 */
-#define HX8347D_REG_PS3 0xe6 /* Power saving 3 */
-#define HX8347D_REG_PS4 0xe7 /* Power saving 4 */
-#define HX8347D_REG_OPONN 0xe8 /* Source OP control normal */
-#define HX8347D_REG_OPONI 0xe9 /* Source OP control idle */
-#define HX8347D_REG_STBAH 0xea /* Power control internal use 1 */
-#define HX8347D_REG_STBAL 0xeb /* Power control internal use 2 */
-#define HX8347D_REG_PTBAH 0xec /* Source control internal use 1 */
-#define HX8347D_REG_PTBAL 0xed /* Source control internal use 2 */
-
-/* page 1 registers */
-#define HX8347D_REG_CABC5 0xc3 /* CABC control 5 */
-#define HX8347D_REG_CABC6 0xc5 /* CABC control 6 */
-#define HX8347D_REG_CABC7 0xc7 /* CABC control 7 */
-#define HX8347D_REG_DBG0 0xcb /* Gain select register 0 */
-#define HX8347D_REG_DBG1 0xcc /* Gain select register 1 */
-#define HX8347D_REG_DBG2 0xcd /* Gain select register 2 */
-#define HX8347D_REG_DBG3 0xce /* Gain select register 3 */
-#define HX8347D_REG_DBG4 0xcf /* Gain select register 4 */
-#define HX8347D_REG_DBG5 0xd0 /* Gain select register 5 */
-#define HX8347D_REG_DBG6 0xd1 /* Gain select register 6 */
-#define HX8347D_REG_DBG7 0xd2 /* Gain select register 7 */
-#define HX8347D_REG_DBG8 0xd3 /* Gain select register 8 */
-
-#define HX8347D_REG_PGSEL 0xff /* Page select */
-
-#endif /* _HX8347D_H */
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ * http://ugfx.io/license.html
+ */
+
+#ifndef _HX8347D_H
+#define _HX8347D_H
+
+/* HX8347D registers */
+
+/* page 0 registers */
+#define HX8347D_REG_HID 0x00 /* Himax ID */
+#define HX8347D_REG_DMODE 0x01 /* Display mode control */
+#define HX8347D_REG_SCH 0x02 /* Column address start high */
+#define HX8347D_REG_SCL 0x03 /* Column address start low */
+#define HX8347D_REG_ECH 0x04 /* Column address end high */
+#define HX8347D_REG_ECL 0x05 /* Column address end low */
+#define HX8347D_REG_SPH 0x06 /* Row address start high */
+#define HX8347D_REG_SPL 0x07 /* Row address start low */
+#define HX8347D_REG_EPH 0x08 /* Row address end high */
+#define HX8347D_REG_EPL 0x09 /* Row address end low */
+#define HX8347D_REG_PSLH 0x0a /* Partial area start row high */
+#define HX8347D_REG_PSLL 0x0b /* Partial area start row low */
+#define HX8347D_REG_PELH 0x0c /* Partial area end row high */
+#define HX8347D_REG_PELL 0x0d /* Partial area end row low */
+#define HX8347D_REG_TFAH 0x0e /* Vertical scroll top fixed area high */
+#define HX8347D_REG_TFAL 0x0f /* Vertical scroll top fixed area low */
+
+#define HX8347D_REG_VSAH 0x10 /* Vertical scroll height area high */
+#define HX8347D_REG_VSAL 0x11 /* Vertical scroll height area low */
+#define HX8347D_REG_BFAH 0x12 /* Vertical scroll button area high */
+#define HX8347D_REG_BFAL 0x13 /* Vertical scroll button area low */
+#define HX8347D_REG_VSPH 0x14 /* Vertical scroll start address high */
+#define HX8347D_REG_VSPL 0x15 /* Vertical scroll start address low */
+#define HX8347D_REG_MAC 0x16 /* Memory access control */
+#define HX8347D_REG_COLMOD 0x17 /* COLMOD */
+#define HX8347D_REG_OSCCH 0x18 /* OSC control 2 */
+#define HX8347D_REG_OSCCL 0x19 /* OSC control 1 */
+#define HX8347D_REG_PWC1 0x1a /* Power control 1 */
+#define HX8347D_REG_PWC2 0x1b /* Power control 2 */
+#define HX8347D_REG_PWC3 0x1c /* Power control 3 */
+#define HX8347D_REG_PWC4 0x1d /* Power control 4 */
+#define HX8347D_REG_PWC5 0x1e /* Power control 5 */
+#define HX8347D_REG_PWC6 0x1f /* Power control 6 */
+
+#define HX8347D_REG_SRAMWC 0x22 /* SRAM write control */
+#define HX8347D_REG_VMF 0x23 /* VCOM control 1 */
+#define HX8347D_REG_VMH 0x24 /* VCOM control 2 */
+#define HX8347D_REG_VML 0x25 /* VCOM control 3 */
+#define HX8347D_REG_DC1 0x26 /* Display control 1 */
+#define HX8347D_REG_DC2 0x27 /* Display control 2 */
+#define HX8347D_REG_DC3 0x28 /* Display control 3 */
+#define HX8347D_REG_FRC1 0x29 /* Frame rate control 1 */
+#define HX8347D_REG_FRC2 0x2a /* Frame rate control 2 */
+#define HX8347D_REG_FRC3 0x2b /* Frame rate control 3 */
+#define HX8347D_REG_FRC4 0x2c /* Frame rate control 4 */
+#define HX8347D_REG_GDON 0x2d /* Cycle control 1 */
+#define HX8347D_REG_GDOF 0x2e /* Cycle control 2 */
+#define HX8347D_REG_DINV 0x2f /* Display inversion */
+
+#define HX8347D_REG_RGB1 0x31 /* RGB interface control 1 */
+#define HX8347D_REG_RGB2 0x32 /* RGB interface control 2 */
+#define HX8347D_REG_RGB3 0x33 /* RGB interface control 3 */
+#define HX8347D_REG_RGB4 0x34 /* RGB interface control 4 */
+#define HX8347D_REG_PCH 0x36 /* Panel characteristic */
+#define HX8347D_REG_OTP1 0x38 /* OTP control 1 */
+#define HX8347D_REG_OTP2 0x39 /* OTP control 2 */
+#define HX8347D_REG_OTP3 0x3a /* OTP control 3 */
+#define HX8347D_REG_CABC1 0x3c /* CABC control 1 */
+#define HX8347D_REG_CABC2 0x3d /* CABC control 2 */
+#define HX8347D_REG_CABC3 0x3e /* CABC control 3 */
+#define HX8347D_REG_CABC4 0x3f /* CABC control 4 */
+
+#define HX8347D_REG_VRP0 0x40 /* Gamma control 1 */
+#define HX8347D_REG_VRP1 0x41 /* Gamma control 2 */
+#define HX8347D_REG_VRP2 0x42 /* Gamma control 3 */
+#define HX8347D_REG_VRP3 0x43 /* Gamma control 4 */
+#define HX8347D_REG_VRP4 0x44 /* Gamma control 5 */
+#define HX8347D_REG_VRP5 0x45 /* Gamma control 6 */
+#define HX8347D_REG_PRP0 0x46 /* Gamma control 7 */
+#define HX8347D_REG_PRP1 0x47 /* Gamma control 8 */
+#define HX8347D_REG_PKP0 0x48 /* Gamma control 9 */
+#define HX8347D_REG_PKP1 0x49 /* Gamma control 10 */
+#define HX8347D_REG_PKP2 0x4a /* Gamma control 11 */
+#define HX8347D_REG_PKP3 0x4b /* Gamma control 12 */
+#define HX8347D_REG_PKP4 0x4c /* Gamma control 13 */
+
+#define HX8347D_REG_VRN0 0x50 /* Gamma control 14 */
+#define HX8347D_REG_VRN1 0x51 /* Gamma control 15 */
+#define HX8347D_REG_VRN2 0x52 /* Gamma control 16 */
+#define HX8347D_REG_VRN3 0x53 /* Gamma control 17 */
+#define HX8347D_REG_VRN4 0x54 /* Gamma control 18 */
+#define HX8347D_REG_VRN5 0x55 /* Gamma control 19 */
+#define HX8347D_REG_PRN0 0x56 /* Gamma control 20 */
+#define HX8347D_REG_PRN1 0x57 /* Gamma control 21 */
+#define HX8347D_REG_PKN0 0x58 /* Gamma control 22 */
+#define HX8347D_REG_PKN1 0x59 /* Gamma control 23 */
+#define HX8347D_REG_PKN2 0x5a /* Gamma control 24 */
+#define HX8347D_REG_PKN3 0x5b /* Gamma control 25 */
+#define HX8347D_REG_PKN4 0x5c /* Gamma control 26 */
+#define HX8347D_REG_CGM 0x5d /* Gamma control 27 */
+
+#define HX8347D_REG_TEC 0x60 /* TE control */
+
+#define HX8347D_REG_PS1 0xe4 /* Power saving 1 */
+#define HX8347D_REG_PS2 0xe5 /* Power saving 2 */
+#define HX8347D_REG_PS3 0xe6 /* Power saving 3 */
+#define HX8347D_REG_PS4 0xe7 /* Power saving 4 */
+#define HX8347D_REG_OPONN 0xe8 /* Source OP control normal */
+#define HX8347D_REG_OPONI 0xe9 /* Source OP control idle */
+#define HX8347D_REG_STBAH 0xea /* Power control internal use 1 */
+#define HX8347D_REG_STBAL 0xeb /* Power control internal use 2 */
+#define HX8347D_REG_PTBAH 0xec /* Source control internal use 1 */
+#define HX8347D_REG_PTBAL 0xed /* Source control internal use 2 */
+
+/* page 1 registers */
+#define HX8347D_REG_CABC5 0xc3 /* CABC control 5 */
+#define HX8347D_REG_CABC6 0xc5 /* CABC control 6 */
+#define HX8347D_REG_CABC7 0xc7 /* CABC control 7 */
+#define HX8347D_REG_DBG0 0xcb /* Gain select register 0 */
+#define HX8347D_REG_DBG1 0xcc /* Gain select register 1 */
+#define HX8347D_REG_DBG2 0xcd /* Gain select register 2 */
+#define HX8347D_REG_DBG3 0xce /* Gain select register 3 */
+#define HX8347D_REG_DBG4 0xcf /* Gain select register 4 */
+#define HX8347D_REG_DBG5 0xd0 /* Gain select register 5 */
+#define HX8347D_REG_DBG6 0xd1 /* Gain select register 6 */
+#define HX8347D_REG_DBG7 0xd2 /* Gain select register 7 */
+#define HX8347D_REG_DBG8 0xd3 /* Gain select register 8 */
+
+#define HX8347D_REG_PGSEL 0xff /* Page select */
+
+#endif /* _HX8347D_H */
diff --git a/drivers/gdisp/HX8347D/gdisp_lld_config.h b/drivers/gdisp/HX8347D/gdisp_lld_config.h
index 49a8ae4c..cdfa650f 100644
--- a/drivers/gdisp/HX8347D/gdisp_lld_config.h
+++ b/drivers/gdisp/HX8347D/gdisp_lld_config.h
@@ -1,24 +1,24 @@
-/*
- * This file is subject to the terms of the GFX License. If a copy of
- * the license was not distributed with this file, you can obtain one at:
- *
- * http://ugfx.io/license.html
- */
-
-#ifndef _GDISP_LLD_CONFIG_H
-#define _GDISP_LLD_CONFIG_H
-
-#if GFX_USE_GDISP
-
-/*===========================================================================*/
-/* Driver hardware support. */
-/*===========================================================================*/
-
-#define GDISP_HARDWARE_STREAM_WRITE GFXON
-#define GDISP_HARDWARE_CONTROL GFXON
-
-#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_RGB565
-
-#endif /* GFX_USE_GDISP */
-
-#endif /* _GDISP_LLD_CONFIG_H */
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ * http://ugfx.io/license.html
+ */
+
+#ifndef _GDISP_LLD_CONFIG_H
+#define _GDISP_LLD_CONFIG_H
+
+#if GFX_USE_GDISP
+
+/*===========================================================================*/
+/* Driver hardware support. */
+/*===========================================================================*/
+
+#define GDISP_HARDWARE_STREAM_WRITE GFXON
+#define GDISP_HARDWARE_CONTROL GFXON
+
+#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_RGB565
+
+#endif /* GFX_USE_GDISP */
+
+#endif /* _GDISP_LLD_CONFIG_H */
diff --git a/drivers/gdisp/ILI9325/gdisp_lld_config.h b/drivers/gdisp/ILI9325/gdisp_lld_config.h
index 6ca6e262..4d60ad3a 100644
--- a/drivers/gdisp/ILI9325/gdisp_lld_config.h
+++ b/drivers/gdisp/ILI9325/gdisp_lld_config.h
@@ -4,23 +4,23 @@
*
* http://ugfx.io/license.html
*/
-
-#ifndef GDISP_LLD_CONFIG_H
-#define GDISP_LLD_CONFIG_H
-
-#if GFX_USE_GDISP
-
-/*===========================================================================*/
-/* Driver hardware support. */
-/*===========================================================================*/
-
+
+#ifndef GDISP_LLD_CONFIG_H
+#define GDISP_LLD_CONFIG_H
+
+#if GFX_USE_GDISP
+
+/*===========================================================================*/
+/* Driver hardware support. */
+/*===========================================================================*/
+
#define GDISP_HARDWARE_STREAM_WRITE GFXON
#define GDISP_HARDWARE_STREAM_READ GFXON
#define GDISP_HARDWARE_STREAM_POS GFXON
#define GDISP_HARDWARE_CONTROL GFXON
-
-#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_RGB565
-
-#endif /* GFX_USE_GDISP */
-
-#endif /* _GDISP_LLD_CONFIG_H */
+
+#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_RGB565
+
+#endif /* GFX_USE_GDISP */
+
+#endif /* _GDISP_LLD_CONFIG_H */
diff --git a/drivers/gdisp/Nokia6610GE12/GE12.h b/drivers/gdisp/Nokia6610GE12/GE12.h
index be1cdf25..d83b406a 100644
--- a/drivers/gdisp/Nokia6610GE12/GE12.h
+++ b/drivers/gdisp/Nokia6610GE12/GE12.h
@@ -4,65 +4,65 @@
*
* http://ugfx.io/license.html
*/
-
-#ifndef GE12_H
-#define GE12_H
-
-// *************************************************************************************
-// LCD Include File for Philips PCF8833 STN RGB- 132x132x3 Driver (GE12)
-//
-// Taken from Philips data sheet Feb 14, 2003
-// *************************************************************************************
-
-// Philips PCF8833 LCD controller command codes
-#define NOP 0x00 // nop
-#define SWRESET 0x01 // software reset
-#define BSTROFF 0x02 // booster voltage OFF
-#define BSTRON 0x03 // booster voltage ON
-#define RDDIDIF 0x04 // read display identification
-#define RDDST 0x09 // read display status
-#define SLEEPIN 0x10 // sleep in
-#define SLEEPOUT 0x11 // sleep out
-#define PTLON 0x12 // partial display mode
-#define NORON 0x13 // display normal mode
-#define INVOFF 0x20 // inversion OFF
-#define INVON 0x21 // inversion ON
-#define DALO 0x22 // all pixel OFF
-#define DAL 0x23 // all pixel ON
-#define SETCON 0x25 // write contrast
-#define DISPOFF 0x28 // display OFF
-#define DISPON 0x29 // display ON
-#define CASET 0x2A // column address set
-#define PASET 0x2B // page address set
-#define RAMWR 0x2C // memory write
-#define RGBSET 0x2D // colour set
-#define PTLAR 0x30 // partial area
-#define VSCRDEF 0x33 // vertical scrolling definition
-#define TEOFF 0x34 // test mode
-#define TEON 0x35 // test mode
-#define MADCTL 0x36 // memory access control
-#define SEP 0x37 // vertical scrolling start address
-#define IDMOFF 0x38 // idle mode OFF
-#define IDMON 0x39 // idle mode ON
-#define COLMOD 0x3A // interface pixel format
-#define SETVOP 0xB0 // set Vop
-#define BRS 0xB4 // bottom row swap
-#define TRS 0xB6 // top row swap
-#define DISCTR 0xB9 // display control
-#define DOR 0xBA // data order
-#define TCDFE 0xBD // enable/disable DF temperature compensation
-#define TCVOPE 0xBF // enable/disable Vop temp comp
-#define EC 0xC0 // internal or external oscillator
-#define SETMUL 0xC2 // set multiplication factor
-#define TCVOPAB 0xC3 // set TCVOP slopes A and B
-#define TCVOPCD 0xC4 // set TCVOP slopes c and d
-#define TCDF 0xC5 // set divider frequency
-#define DF8COLOR 0xC6 // set divider frequency 8-color mode
-#define SETBS 0xC7 // set bias system
-#define RDTEMP 0xC8 // temperature read back
-#define NLI 0xC9 // n-line inversion
-#define RDID1 0xDA // read ID1
-#define RDID2 0xDB // read ID2
-#define RDID3 0xDC // read ID3
-
-#endif /* GE12_H */
+
+#ifndef GE12_H
+#define GE12_H
+
+// *************************************************************************************
+// LCD Include File for Philips PCF8833 STN RGB- 132x132x3 Driver (GE12)
+//
+// Taken from Philips data sheet Feb 14, 2003
+// *************************************************************************************
+
+// Philips PCF8833 LCD controller command codes
+#define NOP 0x00 // nop
+#define SWRESET 0x01 // software reset
+#define BSTROFF 0x02 // booster voltage OFF
+#define BSTRON 0x03 // booster voltage ON
+#define RDDIDIF 0x04 // read display identification
+#define RDDST 0x09 // read display status
+#define SLEEPIN 0x10 // sleep in
+#define SLEEPOUT 0x11 // sleep out
+#define PTLON 0x12 // partial display mode
+#define NORON 0x13 // display normal mode
+#define INVOFF 0x20 // inversion OFF
+#define INVON 0x21 // inversion ON
+#define DALO 0x22 // all pixel OFF
+#define DAL 0x23 // all pixel ON
+#define SETCON 0x25 // write contrast
+#define DISPOFF 0x28 // display OFF
+#define DISPON 0x29 // display ON
+#define CASET 0x2A // column address set
+#define PASET 0x2B // page address set
+#define RAMWR 0x2C // memory write
+#define RGBSET 0x2D // colour set
+#define PTLAR 0x30 // partial area
+#define VSCRDEF 0x33 // vertical scrolling definition
+#define TEOFF 0x34 // test mode
+#define TEON 0x35 // test mode
+#define MADCTL 0x36 // memory access control
+#define SEP 0x37 // vertical scrolling start address
+#define IDMOFF 0x38 // idle mode OFF
+#define IDMON 0x39 // idle mode ON
+#define COLMOD 0x3A // interface pixel format
+#define SETVOP 0xB0 // set Vop
+#define BRS 0xB4 // bottom row swap
+#define TRS 0xB6 // top row swap
+#define DISCTR 0xB9 // display control
+#define DOR 0xBA // data order
+#define TCDFE 0xBD // enable/disable DF temperature compensation
+#define TCVOPE 0xBF // enable/disable Vop temp comp
+#define EC 0xC0 // internal or external oscillator
+#define SETMUL 0xC2 // set multiplication factor
+#define TCVOPAB 0xC3 // set TCVOP slopes A and B
+#define TCVOPCD 0xC4 // set TCVOP slopes c and d
+#define TCDF 0xC5 // set divider frequency
+#define DF8COLOR 0xC6 // set divider frequency 8-color mode
+#define SETBS 0xC7 // set bias system
+#define RDTEMP 0xC8 // temperature read back
+#define NLI 0xC9 // n-line inversion
+#define RDID1 0xDA // read ID1
+#define RDID2 0xDB // read ID2
+#define RDID3 0xDC // read ID3
+
+#endif /* GE12_H */
diff --git a/drivers/gdisp/Nokia6610GE12/gdisp_lld_config.h b/drivers/gdisp/Nokia6610GE12/gdisp_lld_config.h
index 606bf612..2d4a5715 100644
--- a/drivers/gdisp/Nokia6610GE12/gdisp_lld_config.h
+++ b/drivers/gdisp/Nokia6610GE12/gdisp_lld_config.h
@@ -4,21 +4,21 @@
*
* http://ugfx.io/license.html
*/
-
-#ifndef _GDISP_LLD_CONFIG_H
-#define _GDISP_LLD_CONFIG_H
-
-#if GFX_USE_GDISP
-
-/*===========================================================================*/
-/* Driver hardware support. */
-/*===========================================================================*/
-
+
+#ifndef _GDISP_LLD_CONFIG_H
+#define _GDISP_LLD_CONFIG_H
+
+#if GFX_USE_GDISP
+
+/*===========================================================================*/
+/* Driver hardware support. */
+/*===========================================================================*/
+
#define GDISP_HARDWARE_CONTROL GFXON
#define GDISP_HARDWARE_STREAM_WRITE GFXON
-
-#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_RGB444
-
-#endif /* GFX_USE_GDISP */
-
-#endif /* _GDISP_LLD_CONFIG_H */
+
+#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_RGB444
+
+#endif /* GFX_USE_GDISP */
+
+#endif /* _GDISP_LLD_CONFIG_H */
diff --git a/drivers/gdisp/RA6963/board_RA6963.h b/drivers/gdisp/RA6963/board_RA6963.h
index bee22c30..b427393a 100755
--- a/drivers/gdisp/RA6963/board_RA6963.h
+++ b/drivers/gdisp/RA6963/board_RA6963.h
@@ -1,320 +1,320 @@
-/*
- * This file is subject to the terms of the GFX License. If a copy of
- * the license was not distributed with this file, you can obtain one at:
- *
- * http://ugfx.io/license.html
- */
-
-/* RA6963 Driver
- * Pinout:
- * Version 1:
- * 1 - Vee Negative Voltage Output
- * 2 - GND GND
- * 3 - +5V
- * 4 - Vo LCD Driver Supply (10-20k Pot between +5V and Vee)
- * 5 - /WR Write (Low active)
- * 6 - /RD Read (Low active)
- * 7 - /CE Chip Enable (Low active)
- * 8 - C/D Command or Data
- * 9 - /RST Reset (Low active)
- * 10..17 - D0..7
- * 18 - FS Font Select
- * 19 - A Backlight Anode (~4.3V)
- * 20 - K Backlight Cathode (GND)
- */
-#ifndef _GDISP_LLD_BOARD_H
-#define _GDISP_LLD_BOARD_H
-
-// My Settings
-#define RA6963_NEED_READ GFXOFF //works, but is very slow!
-#define RA6963_HAS_RESET GFXOFF
-#define RA6963_NEED_FONT_SELECT GFXOFF
-#define RA6963_NEED_BACKLIGHT GFXOFF
-#define RA6963_NEED_PWMBACKLIGHT GFXOFF
-#define GDISP_SCREEN_HEIGHT 64
-#define GDISP_SCREEN_WIDTH 128
-#define GDISP_INITIAL_CONTRAST 50
-#define GDISP_INITIAL_BACKLIGHT 100
-
-#define RA6963_delay(n) {asm("nop");asm("nop");asm("nop");asm("nop");}
-
-#define LINE_WR PAL_LINE(GPIOB, 8U)
-#if RA6963_NEED_READ
-#define LINE_RD PAL_LINE(GPIOB, 9U)
-#endif
-#define LINE_CE PAL_LINE(GPIOB, 10U)
-#define LINE_CD PAL_LINE(GPIOB, 11U)
-#if RA6963_HAS_RESET
-#define LINE_RST PAL_LINE(GPIOB, 12U)
-#endif
-#define LINE_D0 PAL_LINE(GPIOB, 0U)
-#define LINE_D1 PAL_LINE(GPIOB, 1U)
-#define LINE_D2 PAL_LINE(GPIOB, 2U)
-#define LINE_D3 PAL_LINE(GPIOB, 3U)
-#define LINE_D4 PAL_LINE(GPIOB, 4U)
-#define LINE_D5 PAL_LINE(GPIOB, 5U)
-#define LINE_D6 PAL_LINE(GPIOB, 6U)
-#define LINE_D7 PAL_LINE(GPIOB, 7U)
-#if RA6963_NEED_FONT_SELECT
-#define LINE_FS PAL_LINE(GPIOA, 13U)
-#endif
-#if RA6963_NEED_BACKLIGHT
-#define LINE_BL PAL_LINE(GPIOA, 14U)
-#endif
-
-typedef struct {
- ioline_t WR; //Write PIN
-#if RA6963_NEED_READ
- ioline_t RD; //Read PIN (tie to +5V if not needed)
-#endif
- ioline_t CE; //Chip Enable PIN
- ioline_t CD; //Command/Data Select PIN
-#if RA6963_HAS_RESET
- ioline_t RST; //Reset PIN (tie to +5V if not needed)
-#endif
- ioline_t D[8]; //Data PINs
-#if RA6963_NEED_BACKLIGHT
- ioline_t BL; //Backlight PIN
-#endif
-#if RA6963_NEED_FONT_SELECT
- ioline_t FS; //Font Select PIN (tie to GND if not needed)
-#endif
-} lcd_pins_t;
-
-/*===========================================================================*/
-/* Driver local variables. */
-/*===========================================================================*/
-static const lcd_pins_t lcdpins = {
- LINE_WR,
-#if RA6963_NEED_READ
- LINE_RD,
-#endif
- LINE_CE,
- LINE_CD,
-#if RA6963_HAS_RESET
- LINE_RST,
-#endif
- {
- LINE_D0,
- LINE_D1,
- LINE_D2,
- LINE_D3,
- LINE_D4,
- LINE_D5,
- LINE_D6,
- LINE_D7
- },
-#if RA6963_NEED_BACKLIGHT
- LINE_BL,
-#endif
-#if RA6963_NEED_FONT_SELECT
- LINE_FS,
-#endif
-};
-
-static GFXINLINE void init_board(GDisplay* g){
- (void) g;
- g->board = 0;
- int ii;
-//################################DEBUG#######################################
-#define DEB13_ON palClearLine(PAL_LINE(GPIOB, 13U))
-#define DEB13_OFF palSetLine(PAL_LINE(GPIOB, 13U))
-#define DEB14_ON palClearLine(PAL_LINE(GPIOB, 14U))
-#define DEB14_OFF palSetLine(PAL_LINE(GPIOB, 14U))
-
- palSetLineMode(PAL_LINE(GPIOB, 13U), PAL_MODE_OUTPUT_PUSHPULL);
- DEB13_OFF;
- palSetLineMode(PAL_LINE(GPIOB, 14U), PAL_MODE_OUTPUT_PUSHPULL);
- DEB14_OFF;
-
- //################################DEBUG#######################################
-
- palSetLineMode(lcdpins.WR, PAL_MODE_OUTPUT_PUSHPULL);
- palSetLine(lcdpins.WR);
-#if RA6963_NEED_READ
- palSetLineMode(lcdpins.RD, PAL_MODE_OUTPUT_PUSHPULL);
- palSetLine(lcdpins.RD);
-#endif
- palSetLineMode(lcdpins.CE, PAL_MODE_OUTPUT_PUSHPULL);
- palSetLine(lcdpins.CE);
- palSetLineMode(lcdpins.CD, PAL_MODE_OUTPUT_PUSHPULL);
- palSetLine(lcdpins.CD);
-#if RA6963_HAS_RESET
- palSetLine(lcdpins.RST);
- palSetLineMode(lcdpins.RST, PAL_MODE_OUTPUT_PUSHPULL);
-
-#endif
- for(ii = 0; ii < 8; ii++) {
- palSetLineMode(lcdpins.D[ii], PAL_MODE_OUTPUT_PUSHPULL);
- palClearLine(lcdpins.D[ii]);
- }
-#if RA6963_NEED_BACKLIGHT
-#if RA6963_NEED_PWMBACKLIGHT
- palSetLineMode(lcdpins.BL, PAL_MODE_ALTERNATE(1));
-#else
- palSetLineMode(lcdpins.BL, PAL_MODE_OUTPUT_PUSHPULL);
-#endif
-#endif
-#if RA6963_NEED_FONT_SELECT
- palSetLineMode(lcdpins.FS, PAL_MODE_OUTPUT_PUSHPULL);
- palSetLine(lcdpins.FS);
-#endif
-}
-
-static GFXINLINE void post_init_board(GDisplay *g) {
- (void) g;
-}
-
-static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
- (void) g;
-#if RA6963_HAS_RESET //Make Hardware Reset
- if (state)
- palClearLine(lcdpins.RST);
- else
- palSetLine(lcdpins.RST);
-#else
- (void) state;
-#endif
-}
-
-static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
- (void) g;
- (void) percent;
-#if RA6963_NEED_BACKLIGHT
-#if RA6963_NEED_PWMBACKLIGHT
-
-#else
-
-#endif
-#endif
-}
-
-static GFXINLINE void acquire_bus(GDisplay *g) {
- (void) g;
-}
-
-static GFXINLINE void release_bus(GDisplay *g) {
- (void) g;
-}
-
-
-#if RA6963_NEED_READ
-static GFXINLINE gU8 RA6963_busy_wait(gU8 pattern, gBool lh){
-
- gU8 data;
- int ii;
-
- for(ii = 0; ii < 2; ii++) //Only interested in Bit 0 and 1
- palSetLineMode(lcdpins.D[ii], PAL_MODE_INPUT); //Set pads to input
-
- palClearLine(lcdpins.CE);
- palClearLine(lcdpins.RD);
- do{
- data = 0;
-
- for(ii = 0; ii < 2; ii++){
- if (palReadLine(lcdpins.D[ii]) == PAL_HIGH){ //Read output
- data |= (1<board = 0;
+ int ii;
+//################################DEBUG#######################################
+#define DEB13_ON palClearLine(PAL_LINE(GPIOB, 13U))
+#define DEB13_OFF palSetLine(PAL_LINE(GPIOB, 13U))
+#define DEB14_ON palClearLine(PAL_LINE(GPIOB, 14U))
+#define DEB14_OFF palSetLine(PAL_LINE(GPIOB, 14U))
+
+ palSetLineMode(PAL_LINE(GPIOB, 13U), PAL_MODE_OUTPUT_PUSHPULL);
+ DEB13_OFF;
+ palSetLineMode(PAL_LINE(GPIOB, 14U), PAL_MODE_OUTPUT_PUSHPULL);
+ DEB14_OFF;
+
+ //################################DEBUG#######################################
+
+ palSetLineMode(lcdpins.WR, PAL_MODE_OUTPUT_PUSHPULL);
+ palSetLine(lcdpins.WR);
+#if RA6963_NEED_READ
+ palSetLineMode(lcdpins.RD, PAL_MODE_OUTPUT_PUSHPULL);
+ palSetLine(lcdpins.RD);
+#endif
+ palSetLineMode(lcdpins.CE, PAL_MODE_OUTPUT_PUSHPULL);
+ palSetLine(lcdpins.CE);
+ palSetLineMode(lcdpins.CD, PAL_MODE_OUTPUT_PUSHPULL);
+ palSetLine(lcdpins.CD);
+#if RA6963_HAS_RESET
+ palSetLine(lcdpins.RST);
+ palSetLineMode(lcdpins.RST, PAL_MODE_OUTPUT_PUSHPULL);
+
+#endif
+ for(ii = 0; ii < 8; ii++) {
+ palSetLineMode(lcdpins.D[ii], PAL_MODE_OUTPUT_PUSHPULL);
+ palClearLine(lcdpins.D[ii]);
+ }
+#if RA6963_NEED_BACKLIGHT
+#if RA6963_NEED_PWMBACKLIGHT
+ palSetLineMode(lcdpins.BL, PAL_MODE_ALTERNATE(1));
+#else
+ palSetLineMode(lcdpins.BL, PAL_MODE_OUTPUT_PUSHPULL);
+#endif
+#endif
+#if RA6963_NEED_FONT_SELECT
+ palSetLineMode(lcdpins.FS, PAL_MODE_OUTPUT_PUSHPULL);
+ palSetLine(lcdpins.FS);
+#endif
+}
+
+static GFXINLINE void post_init_board(GDisplay *g) {
+ (void) g;
+}
+
+static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
+ (void) g;
+#if RA6963_HAS_RESET //Make Hardware Reset
+ if (state)
+ palClearLine(lcdpins.RST);
+ else
+ palSetLine(lcdpins.RST);
+#else
+ (void) state;
+#endif
+}
+
+static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
+ (void) g;
+ (void) percent;
+#if RA6963_NEED_BACKLIGHT
+#if RA6963_NEED_PWMBACKLIGHT
+
+#else
+
+#endif
+#endif
+}
+
+static GFXINLINE void acquire_bus(GDisplay *g) {
+ (void) g;
+}
+
+static GFXINLINE void release_bus(GDisplay *g) {
+ (void) g;
+}
+
+
+#if RA6963_NEED_READ
+static GFXINLINE gU8 RA6963_busy_wait(gU8 pattern, gBool lh){
+
+ gU8 data;
+ int ii;
+
+ for(ii = 0; ii < 2; ii++) //Only interested in Bit 0 and 1
+ palSetLineMode(lcdpins.D[ii], PAL_MODE_INPUT); //Set pads to input
+
+ palClearLine(lcdpins.CE);
+ palClearLine(lcdpins.RD);
+ do{
+ data = 0;
+
+ for(ii = 0; ii < 2; ii++){
+ if (palReadLine(lcdpins.D[ii]) == PAL_HIGH){ //Read output
+ data |= (1<priv)
- #define POS (((g->p.x) / RA6963_FONT_WIDTH) + ((g->p.y) * RA6963_GRAPHIC_AREA))
-#endif
-#ifndef GDISP_INITIAL_CONTRAST
- #define GDISP_INITIAL_CONTRAST 50
-#endif
-#ifndef GDISP_INITIAL_BACKLIGHT
- #define GDISP_INITIAL_BACKLIGHT 100
-#endif
-
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-#ifndef write_data_repeat
-#define write_data_repeat(g, data, count) { int i; for (i = 0; i < count; ++i) write_data (g, data); }
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-LLDSPEC gBool gdisp_lld_init(GDisplay *g) {
-#if RA6963_NEED_READ
- g->priv = 0;
-#else
- // The private area is the display surface.
- g->priv = gfxAlloc(BUFFSZ);
-#endif
- // Initialise the board interface
- init_board(g);
-
-#if RA6963_HAS_RESET //Make Hardware Reset
- setpin_reset(g, gTrue);
- gfxSleepMilliseconds(100);
- setpin_reset(g, gFalse);
-#endif
- gfxSleepMilliseconds(50);
- //RA6963 needs Data first THEN command!
-
- write_data(g, (gU8)RA6963_GRAPHIC_HOME); //0
- write_data(g, (gU8)(RA6963_GRAPHIC_HOME>>8)); //0
- write_cmd(g, RA6963_SET_GRAPHIC_HOME_ADDRESS); //0x42
-
- write_data(g, (gU8)RA6963_GRAPHIC_AREA); //16
- write_data(g, 0); //0
- write_cmd(g, RA6963_SET_GRAPHIC_AREA); //0x43
-
- write_data(g, (gU8)RA6963_TEXT_HOME); //0x00
- write_data(g, (gU8)(RA6963_TEXT_HOME>>8)); //0x04 = 0x400
- write_cmd(g, RA6963_SET_TEXT_HOME_ADDRESS); //0x40
-
- write_data(g, (gU8)RA6963_TEXT_AREA); //16
- write_data(g, (gU8)(RA6963_TEXT_AREA>>8)); //0
- write_cmd(g, RA6963_SET_TEXT_AREA); //0x41
-
-/* write_data(g, (gU8)RA6963_OFFSET_REGISTER);
- write_data(g, 0);
- write_cmd(g, RA6963_SET_OFFSET_REGISTER);*/
-
- write_data(g, 0x00);
- write_data(g, 0x00);
- write_cmd(g, RA6963_SET_ADDRESS_POINTER);
-
- write_data(g, 0x00);
- write_data(g, 0x00);
- write_cmd(g, RA6963_SET_CURSOR_POINTER);
-
-
- //write_cmd(g, RA6963_CURSOR_PATTERN_SELECT | RA6963_CURSOR_1_LINE);
- write_cmd(g, RA6963_MODE_SET | RA6963_MODE_OR);
- //write_cmd(g, RA6963_DISPLAY_MODE | RA6963_TEXT_DISPLAY_ON | RA6963_GRAPHIC_DISPLAY_ON);
- write_cmd(g, RA6963_DISPLAY_MODE | RA6963_GRAPHIC_DISPLAY_ON);
-
- // Finish Init
- post_init_board(g);
-#if RA6963_NEED_BACKLIGHT
- // Turn on the back-light
- set_backlight(g, GDISP_INITIAL_BACKLIGHT);
-#endif
- // Initialise the GDISP structure
- g->g.Width = GDISP_SCREEN_WIDTH;
- g->g.Height = GDISP_SCREEN_HEIGHT;
- g->g.Orientation = gOrientation0;
- g->g.Powermode = gPowerOn;
- g->g.Backlight = GDISP_INITIAL_BACKLIGHT;
- g->g.Contrast = GDISP_INITIAL_CONTRAST;
-
- return gTrue;
-}
-
-static void set_viewport(GDisplay *g) {
- if ((g->p.x >= GDISP_SCREEN_WIDTH) || (g->p.y >= GDISP_SCREEN_HEIGHT))
- return; // 0 + ( x / 8 ) + ( y * 16 )
- //gU16 addr = (RA6963_GRAPHIC_HOME + ((g->p.x) / RA6963_FONT_WIDTH) + ((g->p.y) * RA6963_GRAPHIC_AREA));
- gU16 addr = (RA6963_GRAPHIC_HOME + ((g->p.x >> 3) + (g->p.y << 4)));
- #if GFX_COMPILER_WARNING_TYPE == GFX_COMPILER_WARNING_DIRECT
- #warning "check function set_viewport about the shift operations if you change the resolution!"
- #elif GFX_COMPILER_WARNING_TYPE == GFX_COMPILER_WARNING_MACRO
- COMPILER_WARNING("check function set_viewport about the shift operations if you change the resolution!")
- #endif
- write_data(g, (gU8)addr);
- write_data(g, (gU8)(addr>>8));
- write_cmd(g, RA6963_SET_ADDRESS_POINTER);
-}
-
-LLDSPEC void gdisp_lld_write_color(GDisplay *g) {
- gU8 temp;
-
-#if RA6963_NEED_READ
- temp = read_data(g);
-#else
- temp = RAM(g)[POS];
-#endif
-
- if (g->p.color != GFX_WHITE) {
- temp |= (1 << (RA6963_FONT_WIDTH - 1 - ((g->p.x) % RA6963_FONT_WIDTH)));
- }
- else {
- temp &= ~(1 << (RA6963_FONT_WIDTH - 1 - ((g->p.x) % RA6963_FONT_WIDTH)));
- }
-
- write_data(g, temp);
-#if !RA6963_NEED_READ
- RAM(g)[POS] = temp;
-#endif
- //write_cmd(g, RA6963_DATA_WRITE_AND_INCREMENT);
- write_cmd(g, RA6963_DATA_WRITE_AND_NONVARIALBE);
-
-}
-
-LLDSPEC void gdisp_lld_draw_pixel(GDisplay *g) {
- set_viewport(g);
- gdisp_lld_write_color(g);
-}
-
-#if GDISP_HARDWARE_STREAM_WRITE
-LLDSPEC void gdisp_lld_write_start(GDisplay *g) {
- //acquire_bus(g);
- set_viewport(g);
-}
-
-LLDSPEC void gdisp_lld_write_stop(GDisplay *g) {
- //release_bus(g);
-}
-#endif
-
-#if GDISP_HARDWARE_STREAM_READ
-LLDSPEC void gdisp_lld_read_start(GDisplay *g) {
- acquire_bus(g);
- set_viewport(g);
- setreadmode(g);
- dummy_read(g);
-}
-
-LLDSPEC gColor gdisp_lld_read_color(GDisplay *g) {
- gU16 data;
-
- data = read_data(g);
- return gdispNative2Color(data);
-}
-
-LLDSPEC void gdisp_lld_read_stop(GDisplay *g) {
- setwritemode(g);
- release_bus(g);
-}
-#endif
-
-#if GDISP_HARDWARE_FILLS
-LLDSPEC void gdisp_lld_fill_area(GDisplay *g) {
- gU8 data, j;
- set_viewport(g);
-
- if (g->p.color != GFX_WHITE) {
- data = 0xFF; // set dot
- }
- else {
- data = 0; // clr dot
- }
- for (j=0; j < (g->p.cy)/8; j++) {
- write_data_repeat(g, data, (g->p.cx));
- (g->p.cy) +=8;
- set_viewport(g);
- }
-
-}
-#endif // GDISP_HARDWARE_FILLS
-
-#if GDISP_NEED_CONTROL && GDISP_HARDWARE_CONTROL
-LLDSPEC void gdisp_lld_control(GDisplay *g) {
- switch(g->p.x) {
- case GDISP_CONTROL_POWER:
- if (g->g.Powermode == (gPowermode)g->p.ptr)
- return;
-
- switch((gPowermode)g->p.ptr) {
- case gPowerOff:
- acquire_bus(g);
- write_index(g, 0x28);
- gfxSleepMilliseconds(10);
- write_index(g, 0x10);
- release_bus(g);
- break;
-
- case gPowerOn:
- acquire_bus(g);
- write_index(g, 0x11);
- gfxSleepMilliseconds(120);
- write_index(g, 0x29);
- release_bus(g);
- if (g->g.Powermode != gPowerSleep)
- gdisp_lld_init(g);
- break;
-
- case gPowerSleep:
- acquire_bus(g);
- write_index(g, 0x28);
- gfxSleepMilliseconds(10);
- write_index(g, 0x10);
- release_bus(g);
- break;
-
- default:
- return;
- }
-
- g->g.Powermode = (gPowermode)g->p.ptr;
- return;
-
- case GDISP_CONTROL_ORIENTATION:
- if (g->g.Orientation == (gOrientation)g->p.ptr)
- return;
-
- switch((gOrientation)g->p.ptr) {
- case gOrientation0:
- acquire_bus(g);
-
- write_index(g, 0x36);
- write_data(g, 0x08);
-
- release_bus(g);
- g->g.Height = GDISP_SCREEN_HEIGHT;
- g->g.Width = GDISP_SCREEN_WIDTH;
- break;
-
- case gOrientation90:
- acquire_bus(g);
-
- write_index(g, 0x36);
- write_data(g, 0x68);
-
- release_bus(g);
- g->g.Height = GDISP_SCREEN_WIDTH;
- g->g.Width = GDISP_SCREEN_HEIGHT;
- break;
-
- case gOrientation180:
- acquire_bus(g);
-
- write_index(g, 0x36);
- write_data(g, 0xC8);
-
- release_bus(g);
- g->g.Height = GDISP_SCREEN_HEIGHT;
- g->g.Width = GDISP_SCREEN_WIDTH;
- break;
-
- case gOrientation270:
- acquire_bus(g);
-
- write_index(g, 0x36);
- write_data(g, 0xA8);
-
- release_bus(g);
- g->g.Height = GDISP_SCREEN_WIDTH;
- g->g.Width = GDISP_SCREEN_HEIGHT;
- break;
-
- default:
- return;
- }
-
- g->g.Orientation = (gOrientation)g->p.ptr;
- return;
-
- default:
- return;
- }
-}
-#endif
-
-#endif /* GFX_USE_GDISP */
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ * http://ugfx.io/license.html
+ */
+/* Robert Offner 2017
+ * This is a driver for the RA6963 or T6963 Displays.
+ * It should work with displays up to 240 pixel in width and 64 pixel in height
+ * ATTENTION some newer displays on ebay look like T6963 Type but they're not!
+ * They use a new controller: ST7920. These are easy to identify: NO CS pin but
+ * a PSB Pin which switches from parallel to serial communication mode.
+ * If it cost less than 10.- it is probably a ST7920.
+ *
+ * Version: 0.1
+ *
+ * History:
+ *
+ * v0.1 Initial Release
+ * .) tested with readback and without on a 72MHz STM32F103. Display ws a 128x64
+ * type Graphic LCD (Looks like KS0108 Types). STREAM_READ is not implemented.
+ */
+#include "gfx.h"
+
+#if GFX_USE_GDISP
+#define GDISP_DRIVER_VMT GDISPVMT_RA6963
+
+#include "gdisp_lld_config.h"
+#include "src/gdisp/gdisp_driver.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+#if defined(GDISP_SCREEN_HEIGHT) || defined(GDISP_SCREEN_HEIGHT)
+ #if GFX_COMPILER_WARNING_TYPE == GFX_COMPILER_WARNING_DIRECT
+ #warning "GDISP: This low level driver does not support setting a screen size. It is being ignored."
+ #elif GFX_COMPILER_WARNING_TYPE == GFX_COMPILER_WARNING_MACRO
+ COMPILER_WARNING("GDISP: This low level driver does not support setting a screen size. It is being ignored.")
+ #endif
+ #undef GDISP_SCREEN_WIDTH
+ #undef GDISP_SCREEN_HEIGHT
+#endif
+
+#include "board_RA6963.h"
+
+// RA6963 Commands
+//Register Setting
+#define RA6963_SET_CURSOR_POINTER 0x21
+#define RA6963_SET_OFFSET_REGISTER 0x22
+#define RA6963_SET_ADDRESS_POINTER 0x24
+//Set Control Word
+#define RA6963_SET_TEXT_HOME_ADDRESS 0x40
+#define RA6963_SET_TEXT_AREA 0x41
+#define RA6963_SET_GRAPHIC_HOME_ADDRESS 0x42
+#define RA6963_SET_GRAPHIC_AREA 0x43
+//Mode Set
+#define RA6963_MODE_SET 0x80
+#define RA6963_MODE_OR 0x00
+#define RA6963_MODE_XOR 0x01
+#define RA6963_MODE_AND 0x03
+#define RA6963_MODE_TEXT_ATTRIBUTE 0x04
+#define RA6963_MODE_INTERNAL_CGROM 0x00
+#define RA6963_MODE_EXTERNAL_CGRAM 0x08
+//Display Mode
+#define RA6963_DISPLAY_MODE 0x90
+#define RA6963_CURSOR_BLINK_ON 0x01
+#define RA6963_CURSOR_DISPLAY_ON 0x02
+#define RA6963_TEXT_DISPLAY_ON 0x04
+#define RA6963_GRAPHIC_DISPLAY_ON 0x08
+//Cursor Pattern Select
+#define RA6963_CURSOR_PATTERN_SELECT 0xA0
+#define RA6963_CURSOR_1_LINE 0x00
+#define RA6963_CURSOR_2_LINE 0x01
+#define RA6963_CURSOR_3_LINE 0x02
+#define RA6963_CURSOR_4_LINE 0x03
+#define RA6963_CURSOR_5_LINE 0x04
+#define RA6963_CURSOR_6_LINE 0x05
+#define RA6963_CURSOR_7_LINE 0x06
+#define RA6963_CURSOR_8_LINE 0x07
+//Data Read/Write
+#define RA6963_DATA_WRITE_AND_INCREMENT 0xC0
+#define RA6963_DATA_READ_AND_INCREMENT 0xC1
+#define RA6963_DATA_WRITE_AND_DECREMENT 0xC2
+#define RA6963_DATA_READ_AND_DECREMENT 0xC3
+#define RA6963_DATA_WRITE_AND_NONVARIALBE 0xC4
+#define RA6963_DATA_READ_AND_NONVARIABLE 0xC5
+//Data auto Read/Write
+#define RA6963_SET_DATA_AUTO_WRITE 0xB0
+#define RA6963_SET_DATA_AUTO_READ 0xB1
+#define RA6963_AUTO_RESET 0xB2
+//Screen Peek
+#define RA6963_SCREEN_PEEK 0xE0
+//Screen copy
+#define RA6963_SCREEN_COPY 0xE8
+// Status Register Bits
+#define RA6963_STATUS_BUSY1 0x01
+#define RA6963_STATUS_BUSY2 0x02
+#define RA6963_STATUS_DARRDY 0x04
+#define RA6963_STATUS_DAWRDY 0x08
+
+#ifndef GDISP_SCREEN_HEIGHT
+ #define GDISP_SCREEN_HEIGHT 64
+#endif
+#ifndef GDISP_SCREEN_WIDTH
+ #define GDISP_SCREEN_WIDTH 128
+#endif
+
+#define RA6963_FONT_WIDTH 8
+
+#define RA6963_GRAPHIC_AREA (GDISP_SCREEN_WIDTH / RA6963_FONT_WIDTH) //16
+#define RA6963_TEXT_AREA (GDISP_SCREEN_WIDTH / RA6963_FONT_WIDTH) //16
+#define RA6963_GRAPHIC_SIZE (RA6963_GRAPHIC_AREA * GDISP_SCREEN_HEIGHT) //1024
+#define RA6963_TEXT_SIZE (RA6963_TEXT_AREA * (GDISP_SCREEN_HEIGHT/8))//128
+//#define RA6963_TEXT_HOME 0
+//#define RA6963_GRAPHIC_HOME (RA6963_TEXT_HOME + RA6963_TEXT_SIZE) //128
+#define RA6963_GRAPHIC_HOME 0
+#define RA6963_TEXT_HOME (RA6963_GRAPHIC_HOME + RA6963_GRAPHIC_SIZE)
+//#define RA6963_OFFSET_REGISTER 2
+
+#if !RA6963_NEED_READ
+ #define BUFFSZ (RA6963_GRAPHIC_SIZE)
+ #define RAM(g) ((gU8 *)g->priv)
+ #define POS (((g->p.x) / RA6963_FONT_WIDTH) + ((g->p.y) * RA6963_GRAPHIC_AREA))
+#endif
+#ifndef GDISP_INITIAL_CONTRAST
+ #define GDISP_INITIAL_CONTRAST 50
+#endif
+#ifndef GDISP_INITIAL_BACKLIGHT
+ #define GDISP_INITIAL_BACKLIGHT 100
+#endif
+
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+#ifndef write_data_repeat
+#define write_data_repeat(g, data, count) { int i; for (i = 0; i < count; ++i) write_data (g, data); }
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+LLDSPEC gBool gdisp_lld_init(GDisplay *g) {
+#if RA6963_NEED_READ
+ g->priv = 0;
+#else
+ // The private area is the display surface.
+ g->priv = gfxAlloc(BUFFSZ);
+#endif
+ // Initialise the board interface
+ init_board(g);
+
+#if RA6963_HAS_RESET //Make Hardware Reset
+ setpin_reset(g, gTrue);
+ gfxSleepMilliseconds(100);
+ setpin_reset(g, gFalse);
+#endif
+ gfxSleepMilliseconds(50);
+ //RA6963 needs Data first THEN command!
+
+ write_data(g, (gU8)RA6963_GRAPHIC_HOME); //0
+ write_data(g, (gU8)(RA6963_GRAPHIC_HOME>>8)); //0
+ write_cmd(g, RA6963_SET_GRAPHIC_HOME_ADDRESS); //0x42
+
+ write_data(g, (gU8)RA6963_GRAPHIC_AREA); //16
+ write_data(g, 0); //0
+ write_cmd(g, RA6963_SET_GRAPHIC_AREA); //0x43
+
+ write_data(g, (gU8)RA6963_TEXT_HOME); //0x00
+ write_data(g, (gU8)(RA6963_TEXT_HOME>>8)); //0x04 = 0x400
+ write_cmd(g, RA6963_SET_TEXT_HOME_ADDRESS); //0x40
+
+ write_data(g, (gU8)RA6963_TEXT_AREA); //16
+ write_data(g, (gU8)(RA6963_TEXT_AREA>>8)); //0
+ write_cmd(g, RA6963_SET_TEXT_AREA); //0x41
+
+/* write_data(g, (gU8)RA6963_OFFSET_REGISTER);
+ write_data(g, 0);
+ write_cmd(g, RA6963_SET_OFFSET_REGISTER);*/
+
+ write_data(g, 0x00);
+ write_data(g, 0x00);
+ write_cmd(g, RA6963_SET_ADDRESS_POINTER);
+
+ write_data(g, 0x00);
+ write_data(g, 0x00);
+ write_cmd(g, RA6963_SET_CURSOR_POINTER);
+
+
+ //write_cmd(g, RA6963_CURSOR_PATTERN_SELECT | RA6963_CURSOR_1_LINE);
+ write_cmd(g, RA6963_MODE_SET | RA6963_MODE_OR);
+ //write_cmd(g, RA6963_DISPLAY_MODE | RA6963_TEXT_DISPLAY_ON | RA6963_GRAPHIC_DISPLAY_ON);
+ write_cmd(g, RA6963_DISPLAY_MODE | RA6963_GRAPHIC_DISPLAY_ON);
+
+ // Finish Init
+ post_init_board(g);
+#if RA6963_NEED_BACKLIGHT
+ // Turn on the back-light
+ set_backlight(g, GDISP_INITIAL_BACKLIGHT);
+#endif
+ // Initialise the GDISP structure
+ g->g.Width = GDISP_SCREEN_WIDTH;
+ g->g.Height = GDISP_SCREEN_HEIGHT;
+ g->g.Orientation = gOrientation0;
+ g->g.Powermode = gPowerOn;
+ g->g.Backlight = GDISP_INITIAL_BACKLIGHT;
+ g->g.Contrast = GDISP_INITIAL_CONTRAST;
+
+ return gTrue;
+}
+
+static void set_viewport(GDisplay *g) {
+ if ((g->p.x >= GDISP_SCREEN_WIDTH) || (g->p.y >= GDISP_SCREEN_HEIGHT))
+ return; // 0 + ( x / 8 ) + ( y * 16 )
+ //gU16 addr = (RA6963_GRAPHIC_HOME + ((g->p.x) / RA6963_FONT_WIDTH) + ((g->p.y) * RA6963_GRAPHIC_AREA));
+ gU16 addr = (RA6963_GRAPHIC_HOME + ((g->p.x >> 3) + (g->p.y << 4)));
+ #if GFX_COMPILER_WARNING_TYPE == GFX_COMPILER_WARNING_DIRECT
+ #warning "check function set_viewport about the shift operations if you change the resolution!"
+ #elif GFX_COMPILER_WARNING_TYPE == GFX_COMPILER_WARNING_MACRO
+ COMPILER_WARNING("check function set_viewport about the shift operations if you change the resolution!")
+ #endif
+ write_data(g, (gU8)addr);
+ write_data(g, (gU8)(addr>>8));
+ write_cmd(g, RA6963_SET_ADDRESS_POINTER);
+}
+
+LLDSPEC void gdisp_lld_write_color(GDisplay *g) {
+ gU8 temp;
+
+#if RA6963_NEED_READ
+ temp = read_data(g);
+#else
+ temp = RAM(g)[POS];
+#endif
+
+ if (g->p.color != GFX_WHITE) {
+ temp |= (1 << (RA6963_FONT_WIDTH - 1 - ((g->p.x) % RA6963_FONT_WIDTH)));
+ }
+ else {
+ temp &= ~(1 << (RA6963_FONT_WIDTH - 1 - ((g->p.x) % RA6963_FONT_WIDTH)));
+ }
+
+ write_data(g, temp);
+#if !RA6963_NEED_READ
+ RAM(g)[POS] = temp;
+#endif
+ //write_cmd(g, RA6963_DATA_WRITE_AND_INCREMENT);
+ write_cmd(g, RA6963_DATA_WRITE_AND_NONVARIALBE);
+
+}
+
+LLDSPEC void gdisp_lld_draw_pixel(GDisplay *g) {
+ set_viewport(g);
+ gdisp_lld_write_color(g);
+}
+
+#if GDISP_HARDWARE_STREAM_WRITE
+LLDSPEC void gdisp_lld_write_start(GDisplay *g) {
+ //acquire_bus(g);
+ set_viewport(g);
+}
+
+LLDSPEC void gdisp_lld_write_stop(GDisplay *g) {
+ //release_bus(g);
+}
+#endif
+
+#if GDISP_HARDWARE_STREAM_READ
+LLDSPEC void gdisp_lld_read_start(GDisplay *g) {
+ acquire_bus(g);
+ set_viewport(g);
+ setreadmode(g);
+ dummy_read(g);
+}
+
+LLDSPEC gColor gdisp_lld_read_color(GDisplay *g) {
+ gU16 data;
+
+ data = read_data(g);
+ return gdispNative2Color(data);
+}
+
+LLDSPEC void gdisp_lld_read_stop(GDisplay *g) {
+ setwritemode(g);
+ release_bus(g);
+}
+#endif
+
+#if GDISP_HARDWARE_FILLS
+LLDSPEC void gdisp_lld_fill_area(GDisplay *g) {
+ gU8 data, j;
+ set_viewport(g);
+
+ if (g->p.color != GFX_WHITE) {
+ data = 0xFF; // set dot
+ }
+ else {
+ data = 0; // clr dot
+ }
+ for (j=0; j < (g->p.cy)/8; j++) {
+ write_data_repeat(g, data, (g->p.cx));
+ (g->p.cy) +=8;
+ set_viewport(g);
+ }
+
+}
+#endif // GDISP_HARDWARE_FILLS
+
+#if GDISP_NEED_CONTROL && GDISP_HARDWARE_CONTROL
+LLDSPEC void gdisp_lld_control(GDisplay *g) {
+ switch(g->p.x) {
+ case GDISP_CONTROL_POWER:
+ if (g->g.Powermode == (gPowermode)g->p.ptr)
+ return;
+
+ switch((gPowermode)g->p.ptr) {
+ case gPowerOff:
+ acquire_bus(g);
+ write_index(g, 0x28);
+ gfxSleepMilliseconds(10);
+ write_index(g, 0x10);
+ release_bus(g);
+ break;
+
+ case gPowerOn:
+ acquire_bus(g);
+ write_index(g, 0x11);
+ gfxSleepMilliseconds(120);
+ write_index(g, 0x29);
+ release_bus(g);
+ if (g->g.Powermode != gPowerSleep)
+ gdisp_lld_init(g);
+ break;
+
+ case gPowerSleep:
+ acquire_bus(g);
+ write_index(g, 0x28);
+ gfxSleepMilliseconds(10);
+ write_index(g, 0x10);
+ release_bus(g);
+ break;
+
+ default:
+ return;
+ }
+
+ g->g.Powermode = (gPowermode)g->p.ptr;
+ return;
+
+ case GDISP_CONTROL_ORIENTATION:
+ if (g->g.Orientation == (gOrientation)g->p.ptr)
+ return;
+
+ switch((gOrientation)g->p.ptr) {
+ case gOrientation0:
+ acquire_bus(g);
+
+ write_index(g, 0x36);
+ write_data(g, 0x08);
+
+ release_bus(g);
+ g->g.Height = GDISP_SCREEN_HEIGHT;
+ g->g.Width = GDISP_SCREEN_WIDTH;
+ break;
+
+ case gOrientation90:
+ acquire_bus(g);
+
+ write_index(g, 0x36);
+ write_data(g, 0x68);
+
+ release_bus(g);
+ g->g.Height = GDISP_SCREEN_WIDTH;
+ g->g.Width = GDISP_SCREEN_HEIGHT;
+ break;
+
+ case gOrientation180:
+ acquire_bus(g);
+
+ write_index(g, 0x36);
+ write_data(g, 0xC8);
+
+ release_bus(g);
+ g->g.Height = GDISP_SCREEN_HEIGHT;
+ g->g.Width = GDISP_SCREEN_WIDTH;
+ break;
+
+ case gOrientation270:
+ acquire_bus(g);
+
+ write_index(g, 0x36);
+ write_data(g, 0xA8);
+
+ release_bus(g);
+ g->g.Height = GDISP_SCREEN_WIDTH;
+ g->g.Width = GDISP_SCREEN_HEIGHT;
+ break;
+
+ default:
+ return;
+ }
+
+ g->g.Orientation = (gOrientation)g->p.ptr;
+ return;
+
+ default:
+ return;
+ }
+}
+#endif
+
+#endif /* GFX_USE_GDISP */
diff --git a/drivers/gdisp/RA6963/gdisp_lld_config.h b/drivers/gdisp/RA6963/gdisp_lld_config.h
index 86a1eec3..1af1f382 100755
--- a/drivers/gdisp/RA6963/gdisp_lld_config.h
+++ b/drivers/gdisp/RA6963/gdisp_lld_config.h
@@ -1,25 +1,25 @@
-/*
- * This file is subject to the terms of the GFX License. If a copy of
- * the license was not distributed with this file, you can obtain one at:
- *
- * http://ugfx.io/license.html
- */
-
-//#ifndef _GDISP_LLD_CONFIG_H
-//#define _GDISP_LLD_CONFIG_H
-
-#if GFX_USE_GDISP
-/*===========================================================================*/
-/* Driver hardware support. */
-/*===========================================================================*/
-
-#define GDISP_HARDWARE_STREAM_WRITE GFXOFF
-#define GDISP_HARDWARE_STREAM_READ GFXOFF
-#define GDISP_HARDWARE_CONTROL GFXOFF
-#define GDISP_HARDWARE_DRAWPIXEL GFXON
-#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_MONO
-#define GDISP_HARDWARE_FILLS GFXOFF
-
-#endif /* GFX_USE_GDISP */
-
-//#endif /* _GDISP_LLD_CONFIG_H */
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ * http://ugfx.io/license.html
+ */
+
+//#ifndef _GDISP_LLD_CONFIG_H
+//#define _GDISP_LLD_CONFIG_H
+
+#if GFX_USE_GDISP
+/*===========================================================================*/
+/* Driver hardware support. */
+/*===========================================================================*/
+
+#define GDISP_HARDWARE_STREAM_WRITE GFXOFF
+#define GDISP_HARDWARE_STREAM_READ GFXOFF
+#define GDISP_HARDWARE_CONTROL GFXOFF
+#define GDISP_HARDWARE_DRAWPIXEL GFXON
+#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_MONO
+#define GDISP_HARDWARE_FILLS GFXOFF
+
+#endif /* GFX_USE_GDISP */
+
+//#endif /* _GDISP_LLD_CONFIG_H */
diff --git a/drivers/gdisp/SSD1289/gdisp_lld_config.h b/drivers/gdisp/SSD1289/gdisp_lld_config.h
index 25d444f9..a6778c33 100644
--- a/drivers/gdisp/SSD1289/gdisp_lld_config.h
+++ b/drivers/gdisp/SSD1289/gdisp_lld_config.h
@@ -4,31 +4,31 @@
*
* http://ugfx.io/license.html
*/
-
-#ifndef _GDISP_LLD_CONFIG_H
-#define _GDISP_LLD_CONFIG_H
-
-#if GFX_USE_GDISP
-
-/*===========================================================================*/
-/* Driver hardware support. */
-/*===========================================================================*/
-
+
+#ifndef _GDISP_LLD_CONFIG_H
+#define _GDISP_LLD_CONFIG_H
+
+#if GFX_USE_GDISP
+
+/*===========================================================================*/
+/* Driver hardware support. */
+/*===========================================================================*/
+
#define GDISP_HARDWARE_STREAM_WRITE GFXON
#define GDISP_HARDWARE_STREAM_READ GFXON
#define GDISP_HARDWARE_STREAM_POS GFXON
#define GDISP_HARDWARE_CONTROL GFXON
-#if defined(GDISP_USE_DMA) && GDISP_USE_DMA
+#if defined(GDISP_USE_DMA) && GDISP_USE_DMA
#define GDISP_HARDWARE_FILLS GFXON
#if !defined(GDISP_PIXELFORMAT) || GDISP_PIXELFORMAT == 0x2565
- // Hardware BitBlts are only supported in native pixel format on this controller
+ // Hardware BitBlts are only supported in native pixel format on this controller
#define GDISP_HARDWARE_BITFILLS GFXON
#endif
-#endif
-
-#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_RGB565
-
-#endif /* GFX_USE_GDISP */
-
-#endif /* _GDISP_LLD_CONFIG_H */
+#endif
+
+#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_RGB565
+
+#endif /* GFX_USE_GDISP */
+
+#endif /* _GDISP_LLD_CONFIG_H */
diff --git a/drivers/gdisp/SSD1306/SSD1306.h b/drivers/gdisp/SSD1306/SSD1306.h
index 8ec8b3ad..fd27b16e 100644
--- a/drivers/gdisp/SSD1306/SSD1306.h
+++ b/drivers/gdisp/SSD1306/SSD1306.h
@@ -1,59 +1,59 @@
-/*
- * This file is subject to the terms of the GFX License. If a copy of
- * the license was not distributed with this file, you can obtain one at:
- *
- * http://chibios-gfx.com/license.html
- */
-
-#ifndef _SSD1306_H
-#define _SSD1306_H
-
-#define SSD1306_SETCONTRAST 0x81
-#define SSD1306_DISPLAYALLON_RESUME 0xA4
-#define SSD1306_DISPLAYALLON 0xA5
-#define SSD1306_NORMALDISPLAY 0xA6
-#define SSD1306_INVERTDISPLAY 0xA7
-#define SSD1306_DISPLAYOFF 0xAE
-#define SSD1306_DISPLAYON 0xAF
-
-#define SSD1306_SETDISPLAYOFFSET 0xD3
-#define SSD1306_SETCOMPINS 0xDA
-
-#define SSD1306_SETVCOMDETECT 0xDB
-
-#define SSD1306_SETDISPLAYCLOCKDIV 0xD5
-#define SSD1306_SETPRECHARGE 0xD9
-#define SSD1306_ENABLE_CHARGE_PUMP 0x8D
-
-#define SSD1306_SETMULTIPLEX 0xA8
-#define SSD1306_SETSTARTLINE 0x40
-
-#define SSD1306_MEMORYMODE 0x20
-#define SSD1306_HV_COLUMN_ADDRESS 0x21
-#define SSD1306_HV_PAGE_ADDRESS 0x22
-#define SSD1306_PAM_PAGE_START 0xB0
-
-#define SSD1306_ROWSCANINC 0xC0
-#define SSD1306_ROWSCANDEC 0xC8
-
-#define SSD1306_COLSCANINC 0xA0
-#define SSD1306_COLSCANDEC 0xA1
-
-#define SSD1306_CHARGEPUMP 0x8D
-
-#define SSD1306_EXTERNALVCC 0x1
-#define SSD1306_SWITCHCAPVCC 0x2
-
-#define SSD1306_SETLOWCOLUMN 0x00
-#define SSD1306_SETHIGHCOLUMN 0x10
-
-// Scrolling #defines
-#define SSD1306_SCROLL_ACTIVATE 0x2F
-#define SSD1306_SCROLL_DEACTIVATE 0x2E
-#define SSD1306_SCROLL_SET_VERTICAL_SCROLL_AREA 0xA3
-#define SSD1306_SCROLL_HORIZONTAL_RIGHT 0x26
-#define SSD1306_SCROLL_HORIZONTAL_LEFT 0x27
-#define SSD1306_SCROLL_VERTICAL_AND_HORIZONTAL_RIGHT 0x29
-#define SSD1306_SCROLL_VERTICAL_AND_HORIZONTAL_LEFT 0x2A
-
-#endif /* _SSD1306_H */
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ * http://chibios-gfx.com/license.html
+ */
+
+#ifndef _SSD1306_H
+#define _SSD1306_H
+
+#define SSD1306_SETCONTRAST 0x81
+#define SSD1306_DISPLAYALLON_RESUME 0xA4
+#define SSD1306_DISPLAYALLON 0xA5
+#define SSD1306_NORMALDISPLAY 0xA6
+#define SSD1306_INVERTDISPLAY 0xA7
+#define SSD1306_DISPLAYOFF 0xAE
+#define SSD1306_DISPLAYON 0xAF
+
+#define SSD1306_SETDISPLAYOFFSET 0xD3
+#define SSD1306_SETCOMPINS 0xDA
+
+#define SSD1306_SETVCOMDETECT 0xDB
+
+#define SSD1306_SETDISPLAYCLOCKDIV 0xD5
+#define SSD1306_SETPRECHARGE 0xD9
+#define SSD1306_ENABLE_CHARGE_PUMP 0x8D
+
+#define SSD1306_SETMULTIPLEX 0xA8
+#define SSD1306_SETSTARTLINE 0x40
+
+#define SSD1306_MEMORYMODE 0x20
+#define SSD1306_HV_COLUMN_ADDRESS 0x21
+#define SSD1306_HV_PAGE_ADDRESS 0x22
+#define SSD1306_PAM_PAGE_START 0xB0
+
+#define SSD1306_ROWSCANINC 0xC0
+#define SSD1306_ROWSCANDEC 0xC8
+
+#define SSD1306_COLSCANINC 0xA0
+#define SSD1306_COLSCANDEC 0xA1
+
+#define SSD1306_CHARGEPUMP 0x8D
+
+#define SSD1306_EXTERNALVCC 0x1
+#define SSD1306_SWITCHCAPVCC 0x2
+
+#define SSD1306_SETLOWCOLUMN 0x00
+#define SSD1306_SETHIGHCOLUMN 0x10
+
+// Scrolling #defines
+#define SSD1306_SCROLL_ACTIVATE 0x2F
+#define SSD1306_SCROLL_DEACTIVATE 0x2E
+#define SSD1306_SCROLL_SET_VERTICAL_SCROLL_AREA 0xA3
+#define SSD1306_SCROLL_HORIZONTAL_RIGHT 0x26
+#define SSD1306_SCROLL_HORIZONTAL_LEFT 0x27
+#define SSD1306_SCROLL_VERTICAL_AND_HORIZONTAL_RIGHT 0x29
+#define SSD1306_SCROLL_VERTICAL_AND_HORIZONTAL_LEFT 0x2A
+
+#endif /* _SSD1306_H */
diff --git a/drivers/gdisp/SSD1306/gdisp_lld_config.h b/drivers/gdisp/SSD1306/gdisp_lld_config.h
index b9f5dc11..c7bec267 100644
--- a/drivers/gdisp/SSD1306/gdisp_lld_config.h
+++ b/drivers/gdisp/SSD1306/gdisp_lld_config.h
@@ -1,31 +1,31 @@
-/*
- * This file is subject to the terms of the GFX License. If a copy of
- * the license was not distributed with this file, you can obtain one at:
- *
- * http://ugfx.io/license.html
- */
-
-#ifndef _GDISP_LLD_CONFIG_H
-#define _GDISP_LLD_CONFIG_H
-
-#if GFX_USE_GDISP
-
-/*===========================================================================*/
-/* Driver hardware support. */
-/*===========================================================================*/
-
-#define GDISP_HARDWARE_FLUSH GFXON // This controller requires flushing
-#define GDISP_HARDWARE_DRAWPIXEL GFXON
-#define GDISP_HARDWARE_PIXELREAD GFXON
-#define GDISP_HARDWARE_CONTROL GFXON
-#define GDISP_HARDWARE_FILLS GFXON
-
-#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_MONO
-
-// This controller supports a special gdispControl() to inverse the display.
-// Pass a parameter of 1 for inverse and 0 for normal.
-#define GDISP_CONTROL_INVERSE (GDISP_CONTROL_LLD+0)
-
-#endif /* GFX_USE_GDISP */
-
-#endif /* _GDISP_LLD_CONFIG_H */
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ * http://ugfx.io/license.html
+ */
+
+#ifndef _GDISP_LLD_CONFIG_H
+#define _GDISP_LLD_CONFIG_H
+
+#if GFX_USE_GDISP
+
+/*===========================================================================*/
+/* Driver hardware support. */
+/*===========================================================================*/
+
+#define GDISP_HARDWARE_FLUSH GFXON // This controller requires flushing
+#define GDISP_HARDWARE_DRAWPIXEL GFXON
+#define GDISP_HARDWARE_PIXELREAD GFXON
+#define GDISP_HARDWARE_CONTROL GFXON
+#define GDISP_HARDWARE_FILLS GFXON
+
+#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_MONO
+
+// This controller supports a special gdispControl() to inverse the display.
+// Pass a parameter of 1 for inverse and 0 for normal.
+#define GDISP_CONTROL_INVERSE (GDISP_CONTROL_LLD+0)
+
+#endif /* GFX_USE_GDISP */
+
+#endif /* _GDISP_LLD_CONFIG_H */
diff --git a/drivers/gdisp/SSD1306/readme.txt b/drivers/gdisp/SSD1306/readme.txt
index 6454ad22..659bb9e0 100644
--- a/drivers/gdisp/SSD1306/readme.txt
+++ b/drivers/gdisp/SSD1306/readme.txt
@@ -1,27 +1,27 @@
-Description:
-
-Driver for OLED with 4-wire serial interface and I²C/SPI interface
-
-Know restictions:
-- Driver works only with SSD1306 hooked up over I2C or SPI (include corresponding header)
-- Driver is written for 128x64 pixel displays (128x32 are only partly supported and need small further work)
-- after using uGFX subsystem gdisp_lld_display() has to be called "by hand" to push framebuffer to display
-
-To use this driver:
-
-1. Add in your gfxconf.h:
- a) #define GFX_USE_GDISP GFXON
-
- b) Any optional high level driver defines (see gdisp.h) eg: GDISP_NEED_MULTITHREAD
-
- c) The following are optional - define them if you are not using the defaults below:
- #define GDISP_SCREEN_WIDTH 128
- #define GDISP_SCREEN_HEIGHT 64
-
-2. If you are not using a known board then create a gdisp_lld_board.h file according to
- given example files (or just stick with them) and ensure it is on your include path.
-
-3. To your makefile add the following lines:
- include $(GFXLIB)/drivers/gdisp/SSD1306/gdisp_lld.mk
-
-4. Call gdisp_lld_display() every time you want to update display content
+Description:
+
+Driver for OLED with 4-wire serial interface and I²C/SPI interface
+
+Know restictions:
+- Driver works only with SSD1306 hooked up over I2C or SPI (include corresponding header)
+- Driver is written for 128x64 pixel displays (128x32 are only partly supported and need small further work)
+- after using uGFX subsystem gdisp_lld_display() has to be called "by hand" to push framebuffer to display
+
+To use this driver:
+
+1. Add in your gfxconf.h:
+ a) #define GFX_USE_GDISP GFXON
+
+ b) Any optional high level driver defines (see gdisp.h) eg: GDISP_NEED_MULTITHREAD
+
+ c) The following are optional - define them if you are not using the defaults below:
+ #define GDISP_SCREEN_WIDTH 128
+ #define GDISP_SCREEN_HEIGHT 64
+
+2. If you are not using a known board then create a gdisp_lld_board.h file according to
+ given example files (or just stick with them) and ensure it is on your include path.
+
+3. To your makefile add the following lines:
+ include $(GFXLIB)/drivers/gdisp/SSD1306/gdisp_lld.mk
+
+4. Call gdisp_lld_display() every time you want to update display content
diff --git a/drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c b/drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c
index 081adca7..2a2438e4 100644
--- a/drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c
+++ b/drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c
@@ -1,623 +1,623 @@
-/*
- * This file is subject to the terms of the GFX License. If a copy of
- * the license was not distributed with this file, you can obtain one at:
- *
- * http://ugfx.io/license.html
- */
-
-#include "gfx.h"
-
-#if GFX_USE_GDISP
-
-#define GDISP_DRIVER_VMT GDISPVMT_STM32LTDC
-#include "gdisp_lld_config.h"
-#include "../../../src/gdisp/gdisp_driver.h"
-#include "stm32_ltdc.h"
-#if STM32LTDC_USE_DMA2D
- #include "stm32_dma2d.h"
-#endif
-
-#if defined(GDISP_SCREEN_HEIGHT) || defined(GDISP_SCREEN_HEIGHT)
- #if GFX_COMPILER_WARNING_TYPE == GFX_COMPILER_WARNING_DIRECT
- #warning "GDISP: This low level driver does not support setting a screen size. It is being ignored."
- #elif GFX_COMPILER_WARNING_TYPE == GFX_COMPILER_WARNING_MACRO
- COMPILER_WARNING("GDISP: This low level driver does not support setting a screen size. It is being ignored.")
- #endif
- #undef GDISP_SCREEN_WIDTH
- #undef GDISP_SCREEN_HEIGHT
-#endif
-
-#ifndef STM32LTDC_DMA_CACHE_FLUSH
- #define STM32LTDC_DMA_CACHE_FLUSH GFXOFF
-#endif
-#ifndef STM32LTDC_USE_DMA2D
- #define STM32LTDC_USE_DMA2D GFXOFF
-#endif
-#ifndef STM32LTDC_USE_LAYER2
- #define STM32LTDC_USE_LAYER2 GFXOFF
-#endif
-#ifndef STM32LTDC_USE_RGB565
- #define STM32LTDC_USE_RGB565 GFXOFF
-#endif
-
-// Prevent usage of 2nd layer and double buffering at the same time.
-// See readme.md for more inforamtion.
-#if STM32LTDC_USE_LAYER2 && STM32LTDC_USE_DOUBLEBUFFERING
- #error "GDISP - STM32LTDC: Cannot use 2nd LTDC layer and double buffering at the same time. See the driver's readme.md for more information."
-#endif
-
-// Double buffering requires GDISP_NEED_CONTROL for the buffer swap command
-#if STM32LTDC_USE_DOUBLEBUFFERING && !GDISP_NEED_CONTROL
- #error "GDISP - STM32LTDC: Double buffering requires GDISP_NEED_CONTROL."
-#endif
-
-// Force DMA cache flushing on certain platforms/systems.
-#if STM32LTDC_USE_DMA2D
- #if defined(STM32F7) || defined(STM32H7) || defined(STM32F746xx)
- #undef STM32LTDC_DMA_CACHE_FLUSH
- #define STM32LTDC_DMA_CACHE_FLUSH GFXON
- #endif
-#endif
-
-typedef struct ltdcLayerConfig {
- // Frame
- LLDCOLOR_TYPE* frame; // Frame buffer address
- gCoord width, height; // Frame size in pixels
- gCoord pitch; // Line pitch, in bytes
- gU16 fmt; // Pixel format in LTDC format
-
- // Window
- gCoord x, y; // Start pixel position of the virtual layer
- gCoord cx, cy; // Size of the virtual layer
-
- gU32 defcolor; // Default color, ARGB8888
- gU32 keycolor; // Color key, RGB888
- gU32 blending; // Blending factors
- const gU32* palette; // The palette, RGB888 (can be NULL)
- gU16 palettelen; // Palette length
- gU8 alpha; // Constant alpha factor
- gU8 layerflags; // Layer configuration
-} ltdcLayerConfig;
-
-typedef struct ltdcConfig {
- gCoord width, height; // Screen size
- gCoord hsync, vsync; // Horizontal and Vertical sync pixels
- gCoord hbackporch, vbackporch; // Horizontal and Vertical back porch pixels
- gCoord hfrontporch, vfrontporch; // Horizontal and Vertical front porch pixels
- gU32 syncflags; // Sync flags
- gU32 bgcolor; // Clear screen color RGB888
-
- ltdcLayerConfig bglayer; // Background layer config
- ltdcLayerConfig fglayer; // Foreground layer config
-} ltdcConfig;
-
-#define LTDC_UNUSED_LAYER_CONFIG { 0, 1, 1, 1, LTDC_FMT_L8, 0, 0, 1, 1, 0x000000, 0x000000, LTDC_BLEND_FIX1_FIX2, 0, 0, 0, 0 }
-
-#if GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB565
- #define LTDC_PIXELFORMAT LTDC_FMT_RGB565
- #define LTDC_PIXELBYTES 2
- #define LTDC_PIXELBITS 16
-#elif GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB888
- #define LTDC_PIXELFORMAT LTDC_FMT_ARGB8888
- #define LTDC_PIXELBYTES 4
- #define LTDC_PIXELBITS 32
-#else
- #error "GDISP: STM32LTDC - unsupported pixel format"
-#endif
-
-#include "board_STM32LTDC.h"
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-#ifndef GDISP_INITIAL_CONTRAST
- #define GDISP_INITIAL_CONTRAST 50
-#endif
-#ifndef GDISP_INITIAL_BACKLIGHT
- #define GDISP_INITIAL_BACKLIGHT 100
-#endif
-
-/*===========================================================================*/
-/* Driver local routines. */
-/*===========================================================================*/
-
-#define PIXEL_POS(g, x, y) ((y) * ((ltdcLayerConfig *)g->priv)->pitch + (x) * LTDC_PIXELBYTES)
-#define PIXEL_ADDR(g, pos) ((LLDCOLOR_TYPE *)((gU8 *)((ltdcLayerConfig *)g->priv)->frame+pos))
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-static const ltdcLayerConfig layerOff = LTDC_UNUSED_LAYER_CONFIG;
-
-static void _ltdc_reload(void) {
- LTDC->SRCR |= LTDC_SRCR_IMR;
- while (LTDC->SRCR & (LTDC_SRCR_IMR | LTDC_SRCR_VBR))
- gfxYield();
-}
-
-static void _ltdc_layer_init(LTDC_Layer_TypeDef* pLayReg, const ltdcLayerConfig* pCfg) {
- static const gU8 fmt2Bpp[] = {
- 4, /* LTDC_FMT_ARGB8888 */
- 3, /* LTDC_FMT_RGB888 */
- 2, /* LTDC_FMT_RGB565 */
- 2, /* LTDC_FMT_ARGB1555 */
- 2, /* LTDC_FMT_ARGB4444 */
- 1, /* LTDC_FMT_L8 */
- 1, /* LTDC_FMT_AL44 */
- 2 /* LTDC_FMT_AL88 */
- };
- gU32 start, stop;
-
- // Set the framebuffer dimensions and format
- pLayReg->PFCR = (pLayReg->PFCR & ~LTDC_LxPFCR_PF) | ((gU32)pCfg->fmt & LTDC_LxPFCR_PF);
- pLayReg->CFBAR = (gU32)pCfg->frame & LTDC_LxCFBAR_CFBADD;
- pLayReg->CFBLR = ((((gU32)pCfg->pitch << 16) & LTDC_LxCFBLR_CFBP) | (((gU32)fmt2Bpp[pCfg->fmt] * pCfg->width + 3) & LTDC_LxCFBLR_CFBLL));
- pLayReg->CFBLNR = (gU32)pCfg->height & LTDC_LxCFBLNR_CFBLNBR;
-
- // Set the display window boundaries
- start = (gU32)pCfg->x + driverCfg.hsync + driverCfg.hbackporch;
- stop = start + pCfg->cx - 1;
- pLayReg->WHPCR = ((start << 0) & LTDC_LxWHPCR_WHSTPOS) | ((stop << 16) & LTDC_LxWHPCR_WHSPPOS);
- start = (gU32)pCfg->y + driverCfg.vsync + driverCfg.vbackporch;
- stop = start + pCfg->cy - 1;
- pLayReg->WVPCR = ((start << 0) & LTDC_LxWVPCR_WVSTPOS) | ((stop << 16) & LTDC_LxWVPCR_WVSPPOS);
-
- // Set colors
- pLayReg->DCCR = pCfg->defcolor;
- pLayReg->CKCR = (pLayReg->CKCR & ~0x00FFFFFF) | (pCfg->keycolor & 0x00FFFFFF);
- pLayReg->CACR = (pLayReg->CACR & ~LTDC_LxCACR_CONSTA) | ((gU32)pCfg->alpha & LTDC_LxCACR_CONSTA);
- pLayReg->BFCR = (pLayReg->BFCR & ~(LTDC_LxBFCR_BF1 | LTDC_LxBFCR_BF2)) | ((gU32)pCfg->blending & (LTDC_LxBFCR_BF1 | LTDC_LxBFCR_BF2));
- for (start = 0; start < pCfg->palettelen; start++)
- pLayReg->CLUTWR = ((gU32)start << 24) | (pCfg->palette[start] & 0x00FFFFFF);
-
- // Final flags
- pLayReg->CR = (pLayReg->CR & ~LTDC_LEF_MASK) | ((gU32)pCfg->layerflags & LTDC_LEF_MASK);
-}
-
-static void _ltdc_init(void) {
- // Set up the display scanning
- gU32 hacc, vacc;
-
- // Let the board handle LTDC clock setups
- init_ltdc_clock();
-
- // Turn off the controller and its interrupts
- LTDC->GCR = 0;
- LTDC->IER = 0;
- _ltdc_reload();
-
- // Set synchronization params
- hacc = driverCfg.hsync - 1;
- vacc = driverCfg.vsync - 1;
- LTDC->SSCR = ((hacc << 16) & LTDC_SSCR_HSW) | ((vacc << 0) & LTDC_SSCR_VSH);
-
- // Set accumulated back porch params
- hacc += driverCfg.hbackporch;
- vacc += driverCfg.vbackporch;
- LTDC->BPCR = ((hacc << 16) & LTDC_BPCR_AHBP) | ((vacc << 0) & LTDC_BPCR_AVBP);
-
- // Set accumulated active params
- hacc += driverCfg.width;
- vacc += driverCfg.height;
- LTDC->AWCR = ((hacc << 16) & LTDC_AWCR_AAW) | ((vacc << 0) & LTDC_AWCR_AAH);
-
- // Set accumulated total params
- hacc += driverCfg.hfrontporch;
- vacc += driverCfg.vfrontporch;
- LTDC->TWCR = ((hacc << 16) & LTDC_TWCR_TOTALW) | ((vacc << 0) & LTDC_TWCR_TOTALH);
-
- // Set signal polarities and other flags
- LTDC->GCR = driverCfg.syncflags & (LTDC_EF_MASK & ~LTDC_EF_ENABLE);
-
- // Set background color
- LTDC->BCCR = (LTDC->BCCR & ~0x00FFFFFF) | (driverCfg.bgcolor & 0x00FFFFFF);
-
- // Load the background layer
- _ltdc_layer_init(LTDC_Layer1, &driverCfg.bglayer);
-
- // Load the foreground layer
- _ltdc_layer_init(LTDC_Layer2, &layerOff);
-
- // Interrupt handling
- // Possible flags - LTDC_IER_RRIE, LTDC_IER_LIE, LTDC_IER_FUIE, LTDC_IER_TERRIE etc
- LTDC->IER = 0;
-
- // Set everything going
- _ltdc_reload();
- LTDC->GCR |= LTDC_GCR_LTDCEN;
- _ltdc_reload();
-}
-
-LLDSPEC gBool gdisp_lld_init(GDisplay* g) {
- // Initialize the private structure
- g->priv = 0;
- g->board = 0;
-
- switch(g->controllerdisplay) {
- // Display 0 is the background layer
- case 0:
- // Init the board
- init_board(g);
-
- // Initialise the LTDC controller
- _ltdc_init();
-
- // Initialise DMA2D
- #if STM32LTDC_USE_DMA2D
- dma2d_init();
- #endif
-
- if (!(driverCfg.bglayer.layerflags & LTDC_LEF_ENABLE))
- return gFalse;
-
- g->priv = (void *)&driverCfg.bglayer;
-
- // Finish Init the board
- post_init_board(g);
-
- // Turn on the back-light
- set_backlight(g, GDISP_INITIAL_BACKLIGHT);
-
- break;
-
- // Display 1 is the foreground layer or the 2nd buffer for double buffering
- case 1:
- g->priv = (void *)&driverCfg.fglayer;
-
- #if STM32LTDC_USE_LAYER2
- if (!(driverCfg.fglayer.layerflags & LTDC_LEF_ENABLE))
- return gFalse;
-
- // Load the foreground layer
- _ltdc_layer_init(LTDC_Layer2, &driverCfg.fglayer);
- _ltdc_reload();
-
- // Finish Init the board
- post_init_board(g);
- #endif
-
- break;
-
- // There is only 1 LTDC in the CPU and only the 2 layers in the LTDC.
- default:
- return gFalse;
- }
-
- // Initialise the GDISP structure
- g->g.Width = ((ltdcLayerConfig *)g->priv)->width;
- g->g.Height = ((ltdcLayerConfig *)g->priv)->height;
- g->g.Orientation = gOrientation0;
- g->g.Powermode = gPowerOn;
- g->g.Backlight = GDISP_INITIAL_BACKLIGHT;
- g->g.Contrast = GDISP_INITIAL_CONTRAST;
-
- return gTrue;
-}
-
-LLDSPEC void gdisp_lld_draw_pixel(GDisplay* g) {
- unsigned pos;
-
- #if GDISP_NEED_CONTROL
- switch(g->g.Orientation) {
- case gOrientationPortrait:
- case gOrientationLandscape:
- case gOrientation0:
- default:
- pos = PIXEL_POS(g, g->p.x, g->p.y);
- break;
- case gOrientation90:
- pos = PIXEL_POS(g, g->p.y, g->g.Width-g->p.x-1);
- break;
- case gOrientation180:
- pos = PIXEL_POS(g, g->g.Width-g->p.x-1, g->g.Height-g->p.y-1);
- break;
- case gOrientation270:
- pos = PIXEL_POS(g, g->g.Height-g->p.y-1, g->p.x);
- break;
- }
- #else
- pos = PIXEL_POS(g, g->p.x, g->p.y);
- #endif
-
- #if STM32LTDC_USE_DMA2D
- while(DMA2D->CR & DMA2D_CR_START);
- #endif
-
- #if GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB888
- // As we don't support ARGB pixel types in uGFX yet we will
- // use RGB with an inverted alpha value for compatibility
- // ie. 0x00FFFFFF is fully opaque white, 0xFFFFFFFF is fully transparent white
- PIXEL_ADDR(g, pos)[0] = gdispColor2Native(g->p.color) ^ 0xFF000000;
- #else
- PIXEL_ADDR(g, pos)[0] = gdispColor2Native(g->p.color);
- #endif
-}
-
-LLDSPEC gColor gdisp_lld_get_pixel_color(GDisplay* g) {
- unsigned pos;
- LLDCOLOR_TYPE color;
-
- #if GDISP_NEED_CONTROL
- switch(g->g.Orientation) {
- case gOrientationPortrait:
- case gOrientationLandscape:
- case gOrientation0:
- default:
- pos = PIXEL_POS(g, g->p.x, g->p.y);
- break;
- case gOrientation90:
- pos = PIXEL_POS(g, g->p.y, g->g.Width-g->p.x-1);
- break;
- case gOrientation180:
- pos = PIXEL_POS(g, g->g.Width-g->p.x-1, g->g.Height-g->p.y-1);
- break;
- case gOrientation270:
- pos = PIXEL_POS(g, g->g.Height-g->p.y-1, g->p.x);
- break;
- }
- #else
- pos = PIXEL_POS(g, g->p.x, g->p.y);
- #endif
-
- #if STM32LTDC_USE_DMA2D
- while(DMA2D->CR & DMA2D_CR_START);
- #endif
-
- #if GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB888
- // As we don't support ARGB pixel types in uGFX yet we will
- // use RGB with an inverted alpha value for compatibility
- // ie. 0x00FFFFFF is fully opaque white, 0xFFFFFFFF is fully transparent white
- color = PIXEL_ADDR(g, pos)[0] ^ 0xFF000000;
- #else
- color = PIXEL_ADDR(g, pos)[0];
- #endif
-
- return gdispNative2Color(color);
-}
-
-#if GDISP_NEED_CONTROL
- LLDSPEC void gdisp_lld_control(GDisplay* g) {
- switch(g->p.x) {
- case GDISP_CONTROL_ORIENTATION:
- if (g->g.Orientation == (gOrientation)g->p.ptr)
- return;
- switch((gOrientation)g->p.ptr) {
- case gOrientation0:
- case gOrientation180:
- if (g->g.Orientation == gOrientation90 || g->g.Orientation == gOrientation270) {
- gCoord tmp;
-
- tmp = g->g.Width;
- g->g.Width = g->g.Height;
- g->g.Height = tmp;
- }
- break;
- case gOrientation90:
- case gOrientation270:
- if (g->g.Orientation == gOrientation0 || g->g.Orientation == gOrientation180) {
- gCoord tmp;
-
- tmp = g->g.Width;
- g->g.Width = g->g.Height;
- g->g.Height = tmp;
- }
- break;
- case gOrientationPortrait:
- case gOrientationLandscape:
- default:
- return;
- }
- g->g.Orientation = (gOrientation)g->p.ptr;
- return;
-
- case GDISP_CONTROL_BACKLIGHT:
- if ((unsigned)g->p.ptr > 100) g->p.ptr = (void *)100;
- set_backlight(g, (unsigned)g->p.ptr);
- g->g.Backlight = (unsigned)g->p.ptr;
- return;
-
- #if STM32LTDC_USE_DOUBLEBUFFERING
- case STM32LTDC_CONTROL_SHOW_BUFFER:
- {
- // Wait for end-of-line interrupt
- // We use simple polling here as end-of-line interrupts are very frequent and usually happen in sub-millisecond intervals.
- while (LTDC->ISR & LTDC_ISR_LIF);
-
- // Update framebuffer address in LTDC register
- // As we currently only support one layer when doublebuffering is enabled, this change happens only to layer 1.
- LTDC_Layer1->CFBAR = (gU32)(((ltdcLayerConfig*)g->priv)->frame) & LTDC_LxCFBAR_CFBADD;
-
- // Reload after LTDC config register modifications
- _ltdc_reload();
-
- return;
- }
- #endif
-
- default:
- return;
- }
- }
-#endif
-
-#if STM32LTDC_USE_DMA2D
- #if STM32LTDC_DMA_CACHE_FLUSH
- #if defined(__CC_ARM)
- #define __ugfxDSB() __dsb(0xF)
- #else // GCC like
- #define __ugfxDSB() __ASM volatile ("dsb 0xF":::"memory")
- #endif
- #endif
-
-
- static void dma2d_init(void) {
- // Let the board handle the clock setup
- init_dma2d_clock();
-
- // Output color format
- #if GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB565
- DMA2D->OPFCCR = OPFCCR_RGB565;
- #elif GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB888
- DMA2D->OPFCCR = OPFCCR_ARGB8888;
- #endif
-
- // Foreground color format
- #if GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB565
- DMA2D->FGPFCCR = FGPFCCR_CM_RGB565;
- #elif GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB888
- DMA2D->FGPFCCR = FGPFCCR_CM_ARGB8888;
- #endif
- }
-
- // Uses p.x,p.y p.cx,p.cy p.color
- LLDSPEC void gdisp_lld_fill_area(GDisplay* g)
- {
- gU32 pos;
- gU32 lineadd;
- gU32 shape;
-
- #if GDISP_NEED_CONTROL
- switch(g->g.Orientation) {
- case gOrientationPortrait:
- case gOrientationLandscape:
- case gOrientation0:
- default:
- pos = PIXEL_POS(g, g->p.x, g->p.y);
- lineadd = g->g.Width - g->p.cx;
- shape = (g->p.cx << 16) | (g->p.cy);
- break;
- case gOrientation90:
- pos = PIXEL_POS(g, g->p.y, g->g.Width-g->p.x-g->p.cx);
- lineadd = g->g.Height - g->p.cy;
- shape = (g->p.cy << 16) | (g->p.cx);
- break;
- case gOrientation180:
- pos = PIXEL_POS(g, g->g.Width-g->p.x-g->p.cx, g->g.Height-g->p.y-g->p.cy);
- lineadd = g->g.Width - g->p.cx;
- shape = (g->p.cx << 16) | (g->p.cy);
- break;
- case gOrientation270:
- pos = PIXEL_POS(g, g->g.Height-g->p.y-g->p.cy, g->p.x);
- lineadd = g->g.Height - g->p.cy;
- shape = (g->p.cy << 16) | (g->p.cx);
- break;
- }
- #else
- pos = PIXEL_POS(g, g->p.x, g->p.y);
- lineadd = g->g.Width - g->p.cx;
- shape = (g->p.cx << 16) | (g->p.cy);
- #endif
-
- #if STM32LTDC_DMA_CACHE_FLUSH
- {
- // This is slightly less than optimal as we flush the whole line in the source and destination image
- // instead of just the cx portion but this saves us having to iterate over each line.
- gU32 f, e;
-
- // Data memory barrier
- __ugfxDSB();
-
- // Flush then invalidate the destination area
- e = pos + (g->p.cy > 1 ? ((gU32)((ltdcLayerConfig *)g->priv)->pitch*(shape & 0xFFFF)) : ((shape>>16)*LTDC_PIXELBYTES));
- for(f=(pos & ~31); f < e; f += 32) {
- SCB->DCCIMVAC = f;
- SCB->DCIMVAC = f;
- }
-
- // Data memory barrier
- __ugfxDSB();
- }
- #endif
-
- // Wait until DMA2D is ready
- while(DMA2D->CR & DMA2D_CR_START);
-
- // Start the DMA2D
- DMA2D->OMAR = (gU32)PIXEL_ADDR(g, pos);
- DMA2D->OOR = lineadd;
- DMA2D->NLR = shape;
- #if GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB888
- // As we don't support ARGB pixel types in uGFX yet we will
- // use RGB with an inverted alpha value for compatibility
- // ie. 0x00FFFFFF is fully opaque white, 0xFFFFFFFF is fully transparent white
- DMA2D->OCOLR = (gU32)(gdispColor2Native(g->p.color)) ^ 0xFF000000;
- #else
- DMA2D->OCOLR = (gU32)(gdispColor2Native(g->p.color));
- #endif
- ;
- DMA2D->CR = DMA2D_CR_MODE_R2M | DMA2D_CR_START;
- }
-
- /* Oops - the DMA2D only supports gOrientation0.
- *
- * Where the width is 1 we can trick it for other orientations.
- * That is worthwhile as a width of 1 is common. For other
- * situations we need to fall back to pixel pushing.
- *
- * Additionally, although DMA2D can translate color formats
- * it can only do it for a small range of formats. For any
- * other formats we also need to fall back to pixel pushing.
- *
- * As the code to actually do all that for other than the
- * simplest case (orientation == gOrientation0 and
- * GDISP_PIXELFORMAT == GDISP_LLD_PIXELFORMAT) is very complex
- * we will always pixel push for now. In practice that is OK as
- * access to the framebuffer is fast - probably faster than DMA2D.
- * It just uses more CPU.
- */
- #if GDISP_HARDWARE_BITFILLS
- // Uses p.x,p.y p.cx,p.cy p.x1,p.y1 (=srcx,srcy) p.x2 (=srccx), p.ptr (=buffer)
- LLDSPEC void gdisp_lld_blit_area(GDisplay* g) {
- gU32 srcstart, dststart;
-
- srcstart = LTDC_PIXELBYTES * ((gU32)g->p.x2 * g->p.y1 + g->p.x1) + (gU32)g->p.ptr;
- dststart = (gU32)PIXEL_ADDR(g, PIXEL_POS(g, g->p.x, g->p.y));
-
- #if STM32LTDC_DMA_CACHE_FLUSH
- {
- // This is slightly less than optimal as we flush the whole line in the source and destination image
- // instead of just the cx portion but this saves us having to iterate over each line.
- gU32 f, e;
-
- // Data memory barrier
- __ugfxDSB();
-
- // Flush the source area
- e = srcstart + (g->p.cy > 1 ? ((gU32)g->p.x2*g->p.cy) : (gU32)g->p.cx)*LTDC_PIXELBYTES;
- for(f=(srcstart & ~31); f < e; f += 32)
- SCB->DCCIMVAC = f;
-
- // Flush then invalidate the destination area
- e = dststart + (g->p.cy > 1 ? ((gU32)((ltdcLayerConfig *)g->priv)->pitch*g->p.cy) : ((gU32)g->p.cx*LTDC_PIXELBYTES));
- for(f=(dststart & ~31); f < e; f += 32) {
- SCB->DCCIMVAC = f;
- SCB->DCIMVAC = f;
- }
-
- // Data memory barrier
- __ugfxDSB();
- }
- #endif
-
- // Wait until DMA2D is ready
- while(DMA2D->CR & DMA2D_CR_START);
-
- // Source setup
- DMA2D->FGMAR = srcstart;
- DMA2D->FGOR = g->p.x2 - g->p.cx;
-
- // Output setup
- DMA2D->OMAR = dststart;
- DMA2D->OOR = g->g.Width - g->p.cx;
- DMA2D->NLR = (g->p.cx << 16) | (g->p.cy);
-
- // Set MODE to M2M and Start the process
- DMA2D->CR = DMA2D_CR_MODE_M2M | DMA2D_CR_START;
- }
- #endif
-
-#endif /* STM32LTDC_USE_DMA2D */
-
-#endif /* GFX_USE_GDISP */
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ * http://ugfx.io/license.html
+ */
+
+#include "gfx.h"
+
+#if GFX_USE_GDISP
+
+#define GDISP_DRIVER_VMT GDISPVMT_STM32LTDC
+#include "gdisp_lld_config.h"
+#include "../../../src/gdisp/gdisp_driver.h"
+#include "stm32_ltdc.h"
+#if STM32LTDC_USE_DMA2D
+ #include "stm32_dma2d.h"
+#endif
+
+#if defined(GDISP_SCREEN_HEIGHT) || defined(GDISP_SCREEN_HEIGHT)
+ #if GFX_COMPILER_WARNING_TYPE == GFX_COMPILER_WARNING_DIRECT
+ #warning "GDISP: This low level driver does not support setting a screen size. It is being ignored."
+ #elif GFX_COMPILER_WARNING_TYPE == GFX_COMPILER_WARNING_MACRO
+ COMPILER_WARNING("GDISP: This low level driver does not support setting a screen size. It is being ignored.")
+ #endif
+ #undef GDISP_SCREEN_WIDTH
+ #undef GDISP_SCREEN_HEIGHT
+#endif
+
+#ifndef STM32LTDC_DMA_CACHE_FLUSH
+ #define STM32LTDC_DMA_CACHE_FLUSH GFXOFF
+#endif
+#ifndef STM32LTDC_USE_DMA2D
+ #define STM32LTDC_USE_DMA2D GFXOFF
+#endif
+#ifndef STM32LTDC_USE_LAYER2
+ #define STM32LTDC_USE_LAYER2 GFXOFF
+#endif
+#ifndef STM32LTDC_USE_RGB565
+ #define STM32LTDC_USE_RGB565 GFXOFF
+#endif
+
+// Prevent usage of 2nd layer and double buffering at the same time.
+// See readme.md for more inforamtion.
+#if STM32LTDC_USE_LAYER2 && STM32LTDC_USE_DOUBLEBUFFERING
+ #error "GDISP - STM32LTDC: Cannot use 2nd LTDC layer and double buffering at the same time. See the driver's readme.md for more information."
+#endif
+
+// Double buffering requires GDISP_NEED_CONTROL for the buffer swap command
+#if STM32LTDC_USE_DOUBLEBUFFERING && !GDISP_NEED_CONTROL
+ #error "GDISP - STM32LTDC: Double buffering requires GDISP_NEED_CONTROL."
+#endif
+
+// Force DMA cache flushing on certain platforms/systems.
+#if STM32LTDC_USE_DMA2D
+ #if defined(STM32F7) || defined(STM32H7) || defined(STM32F746xx)
+ #undef STM32LTDC_DMA_CACHE_FLUSH
+ #define STM32LTDC_DMA_CACHE_FLUSH GFXON
+ #endif
+#endif
+
+typedef struct ltdcLayerConfig {
+ // Frame
+ LLDCOLOR_TYPE* frame; // Frame buffer address
+ gCoord width, height; // Frame size in pixels
+ gCoord pitch; // Line pitch, in bytes
+ gU16 fmt; // Pixel format in LTDC format
+
+ // Window
+ gCoord x, y; // Start pixel position of the virtual layer
+ gCoord cx, cy; // Size of the virtual layer
+
+ gU32 defcolor; // Default color, ARGB8888
+ gU32 keycolor; // Color key, RGB888
+ gU32 blending; // Blending factors
+ const gU32* palette; // The palette, RGB888 (can be NULL)
+ gU16 palettelen; // Palette length
+ gU8 alpha; // Constant alpha factor
+ gU8 layerflags; // Layer configuration
+} ltdcLayerConfig;
+
+typedef struct ltdcConfig {
+ gCoord width, height; // Screen size
+ gCoord hsync, vsync; // Horizontal and Vertical sync pixels
+ gCoord hbackporch, vbackporch; // Horizontal and Vertical back porch pixels
+ gCoord hfrontporch, vfrontporch; // Horizontal and Vertical front porch pixels
+ gU32 syncflags; // Sync flags
+ gU32 bgcolor; // Clear screen color RGB888
+
+ ltdcLayerConfig bglayer; // Background layer config
+ ltdcLayerConfig fglayer; // Foreground layer config
+} ltdcConfig;
+
+#define LTDC_UNUSED_LAYER_CONFIG { 0, 1, 1, 1, LTDC_FMT_L8, 0, 0, 1, 1, 0x000000, 0x000000, LTDC_BLEND_FIX1_FIX2, 0, 0, 0, 0 }
+
+#if GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB565
+ #define LTDC_PIXELFORMAT LTDC_FMT_RGB565
+ #define LTDC_PIXELBYTES 2
+ #define LTDC_PIXELBITS 16
+#elif GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB888
+ #define LTDC_PIXELFORMAT LTDC_FMT_ARGB8888
+ #define LTDC_PIXELBYTES 4
+ #define LTDC_PIXELBITS 32
+#else
+ #error "GDISP: STM32LTDC - unsupported pixel format"
+#endif
+
+#include "board_STM32LTDC.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#ifndef GDISP_INITIAL_CONTRAST
+ #define GDISP_INITIAL_CONTRAST 50
+#endif
+#ifndef GDISP_INITIAL_BACKLIGHT
+ #define GDISP_INITIAL_BACKLIGHT 100
+#endif
+
+/*===========================================================================*/
+/* Driver local routines. */
+/*===========================================================================*/
+
+#define PIXEL_POS(g, x, y) ((y) * ((ltdcLayerConfig *)g->priv)->pitch + (x) * LTDC_PIXELBYTES)
+#define PIXEL_ADDR(g, pos) ((LLDCOLOR_TYPE *)((gU8 *)((ltdcLayerConfig *)g->priv)->frame+pos))
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+static const ltdcLayerConfig layerOff = LTDC_UNUSED_LAYER_CONFIG;
+
+static void _ltdc_reload(void) {
+ LTDC->SRCR |= LTDC_SRCR_IMR;
+ while (LTDC->SRCR & (LTDC_SRCR_IMR | LTDC_SRCR_VBR))
+ gfxYield();
+}
+
+static void _ltdc_layer_init(LTDC_Layer_TypeDef* pLayReg, const ltdcLayerConfig* pCfg) {
+ static const gU8 fmt2Bpp[] = {
+ 4, /* LTDC_FMT_ARGB8888 */
+ 3, /* LTDC_FMT_RGB888 */
+ 2, /* LTDC_FMT_RGB565 */
+ 2, /* LTDC_FMT_ARGB1555 */
+ 2, /* LTDC_FMT_ARGB4444 */
+ 1, /* LTDC_FMT_L8 */
+ 1, /* LTDC_FMT_AL44 */
+ 2 /* LTDC_FMT_AL88 */
+ };
+ gU32 start, stop;
+
+ // Set the framebuffer dimensions and format
+ pLayReg->PFCR = (pLayReg->PFCR & ~LTDC_LxPFCR_PF) | ((gU32)pCfg->fmt & LTDC_LxPFCR_PF);
+ pLayReg->CFBAR = (gU32)pCfg->frame & LTDC_LxCFBAR_CFBADD;
+ pLayReg->CFBLR = ((((gU32)pCfg->pitch << 16) & LTDC_LxCFBLR_CFBP) | (((gU32)fmt2Bpp[pCfg->fmt] * pCfg->width + 3) & LTDC_LxCFBLR_CFBLL));
+ pLayReg->CFBLNR = (gU32)pCfg->height & LTDC_LxCFBLNR_CFBLNBR;
+
+ // Set the display window boundaries
+ start = (gU32)pCfg->x + driverCfg.hsync + driverCfg.hbackporch;
+ stop = start + pCfg->cx - 1;
+ pLayReg->WHPCR = ((start << 0) & LTDC_LxWHPCR_WHSTPOS) | ((stop << 16) & LTDC_LxWHPCR_WHSPPOS);
+ start = (gU32)pCfg->y + driverCfg.vsync + driverCfg.vbackporch;
+ stop = start + pCfg->cy - 1;
+ pLayReg->WVPCR = ((start << 0) & LTDC_LxWVPCR_WVSTPOS) | ((stop << 16) & LTDC_LxWVPCR_WVSPPOS);
+
+ // Set colors
+ pLayReg->DCCR = pCfg->defcolor;
+ pLayReg->CKCR = (pLayReg->CKCR & ~0x00FFFFFF) | (pCfg->keycolor & 0x00FFFFFF);
+ pLayReg->CACR = (pLayReg->CACR & ~LTDC_LxCACR_CONSTA) | ((gU32)pCfg->alpha & LTDC_LxCACR_CONSTA);
+ pLayReg->BFCR = (pLayReg->BFCR & ~(LTDC_LxBFCR_BF1 | LTDC_LxBFCR_BF2)) | ((gU32)pCfg->blending & (LTDC_LxBFCR_BF1 | LTDC_LxBFCR_BF2));
+ for (start = 0; start < pCfg->palettelen; start++)
+ pLayReg->CLUTWR = ((gU32)start << 24) | (pCfg->palette[start] & 0x00FFFFFF);
+
+ // Final flags
+ pLayReg->CR = (pLayReg->CR & ~LTDC_LEF_MASK) | ((gU32)pCfg->layerflags & LTDC_LEF_MASK);
+}
+
+static void _ltdc_init(void) {
+ // Set up the display scanning
+ gU32 hacc, vacc;
+
+ // Let the board handle LTDC clock setups
+ init_ltdc_clock();
+
+ // Turn off the controller and its interrupts
+ LTDC->GCR = 0;
+ LTDC->IER = 0;
+ _ltdc_reload();
+
+ // Set synchronization params
+ hacc = driverCfg.hsync - 1;
+ vacc = driverCfg.vsync - 1;
+ LTDC->SSCR = ((hacc << 16) & LTDC_SSCR_HSW) | ((vacc << 0) & LTDC_SSCR_VSH);
+
+ // Set accumulated back porch params
+ hacc += driverCfg.hbackporch;
+ vacc += driverCfg.vbackporch;
+ LTDC->BPCR = ((hacc << 16) & LTDC_BPCR_AHBP) | ((vacc << 0) & LTDC_BPCR_AVBP);
+
+ // Set accumulated active params
+ hacc += driverCfg.width;
+ vacc += driverCfg.height;
+ LTDC->AWCR = ((hacc << 16) & LTDC_AWCR_AAW) | ((vacc << 0) & LTDC_AWCR_AAH);
+
+ // Set accumulated total params
+ hacc += driverCfg.hfrontporch;
+ vacc += driverCfg.vfrontporch;
+ LTDC->TWCR = ((hacc << 16) & LTDC_TWCR_TOTALW) | ((vacc << 0) & LTDC_TWCR_TOTALH);
+
+ // Set signal polarities and other flags
+ LTDC->GCR = driverCfg.syncflags & (LTDC_EF_MASK & ~LTDC_EF_ENABLE);
+
+ // Set background color
+ LTDC->BCCR = (LTDC->BCCR & ~0x00FFFFFF) | (driverCfg.bgcolor & 0x00FFFFFF);
+
+ // Load the background layer
+ _ltdc_layer_init(LTDC_Layer1, &driverCfg.bglayer);
+
+ // Load the foreground layer
+ _ltdc_layer_init(LTDC_Layer2, &layerOff);
+
+ // Interrupt handling
+ // Possible flags - LTDC_IER_RRIE, LTDC_IER_LIE, LTDC_IER_FUIE, LTDC_IER_TERRIE etc
+ LTDC->IER = 0;
+
+ // Set everything going
+ _ltdc_reload();
+ LTDC->GCR |= LTDC_GCR_LTDCEN;
+ _ltdc_reload();
+}
+
+LLDSPEC gBool gdisp_lld_init(GDisplay* g) {
+ // Initialize the private structure
+ g->priv = 0;
+ g->board = 0;
+
+ switch(g->controllerdisplay) {
+ // Display 0 is the background layer
+ case 0:
+ // Init the board
+ init_board(g);
+
+ // Initialise the LTDC controller
+ _ltdc_init();
+
+ // Initialise DMA2D
+ #if STM32LTDC_USE_DMA2D
+ dma2d_init();
+ #endif
+
+ if (!(driverCfg.bglayer.layerflags & LTDC_LEF_ENABLE))
+ return gFalse;
+
+ g->priv = (void *)&driverCfg.bglayer;
+
+ // Finish Init the board
+ post_init_board(g);
+
+ // Turn on the back-light
+ set_backlight(g, GDISP_INITIAL_BACKLIGHT);
+
+ break;
+
+ // Display 1 is the foreground layer or the 2nd buffer for double buffering
+ case 1:
+ g->priv = (void *)&driverCfg.fglayer;
+
+ #if STM32LTDC_USE_LAYER2
+ if (!(driverCfg.fglayer.layerflags & LTDC_LEF_ENABLE))
+ return gFalse;
+
+ // Load the foreground layer
+ _ltdc_layer_init(LTDC_Layer2, &driverCfg.fglayer);
+ _ltdc_reload();
+
+ // Finish Init the board
+ post_init_board(g);
+ #endif
+
+ break;
+
+ // There is only 1 LTDC in the CPU and only the 2 layers in the LTDC.
+ default:
+ return gFalse;
+ }
+
+ // Initialise the GDISP structure
+ g->g.Width = ((ltdcLayerConfig *)g->priv)->width;
+ g->g.Height = ((ltdcLayerConfig *)g->priv)->height;
+ g->g.Orientation = gOrientation0;
+ g->g.Powermode = gPowerOn;
+ g->g.Backlight = GDISP_INITIAL_BACKLIGHT;
+ g->g.Contrast = GDISP_INITIAL_CONTRAST;
+
+ return gTrue;
+}
+
+LLDSPEC void gdisp_lld_draw_pixel(GDisplay* g) {
+ unsigned pos;
+
+ #if GDISP_NEED_CONTROL
+ switch(g->g.Orientation) {
+ case gOrientationPortrait:
+ case gOrientationLandscape:
+ case gOrientation0:
+ default:
+ pos = PIXEL_POS(g, g->p.x, g->p.y);
+ break;
+ case gOrientation90:
+ pos = PIXEL_POS(g, g->p.y, g->g.Width-g->p.x-1);
+ break;
+ case gOrientation180:
+ pos = PIXEL_POS(g, g->g.Width-g->p.x-1, g->g.Height-g->p.y-1);
+ break;
+ case gOrientation270:
+ pos = PIXEL_POS(g, g->g.Height-g->p.y-1, g->p.x);
+ break;
+ }
+ #else
+ pos = PIXEL_POS(g, g->p.x, g->p.y);
+ #endif
+
+ #if STM32LTDC_USE_DMA2D
+ while(DMA2D->CR & DMA2D_CR_START);
+ #endif
+
+ #if GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB888
+ // As we don't support ARGB pixel types in uGFX yet we will
+ // use RGB with an inverted alpha value for compatibility
+ // ie. 0x00FFFFFF is fully opaque white, 0xFFFFFFFF is fully transparent white
+ PIXEL_ADDR(g, pos)[0] = gdispColor2Native(g->p.color) ^ 0xFF000000;
+ #else
+ PIXEL_ADDR(g, pos)[0] = gdispColor2Native(g->p.color);
+ #endif
+}
+
+LLDSPEC gColor gdisp_lld_get_pixel_color(GDisplay* g) {
+ unsigned pos;
+ LLDCOLOR_TYPE color;
+
+ #if GDISP_NEED_CONTROL
+ switch(g->g.Orientation) {
+ case gOrientationPortrait:
+ case gOrientationLandscape:
+ case gOrientation0:
+ default:
+ pos = PIXEL_POS(g, g->p.x, g->p.y);
+ break;
+ case gOrientation90:
+ pos = PIXEL_POS(g, g->p.y, g->g.Width-g->p.x-1);
+ break;
+ case gOrientation180:
+ pos = PIXEL_POS(g, g->g.Width-g->p.x-1, g->g.Height-g->p.y-1);
+ break;
+ case gOrientation270:
+ pos = PIXEL_POS(g, g->g.Height-g->p.y-1, g->p.x);
+ break;
+ }
+ #else
+ pos = PIXEL_POS(g, g->p.x, g->p.y);
+ #endif
+
+ #if STM32LTDC_USE_DMA2D
+ while(DMA2D->CR & DMA2D_CR_START);
+ #endif
+
+ #if GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB888
+ // As we don't support ARGB pixel types in uGFX yet we will
+ // use RGB with an inverted alpha value for compatibility
+ // ie. 0x00FFFFFF is fully opaque white, 0xFFFFFFFF is fully transparent white
+ color = PIXEL_ADDR(g, pos)[0] ^ 0xFF000000;
+ #else
+ color = PIXEL_ADDR(g, pos)[0];
+ #endif
+
+ return gdispNative2Color(color);
+}
+
+#if GDISP_NEED_CONTROL
+ LLDSPEC void gdisp_lld_control(GDisplay* g) {
+ switch(g->p.x) {
+ case GDISP_CONTROL_ORIENTATION:
+ if (g->g.Orientation == (gOrientation)g->p.ptr)
+ return;
+ switch((gOrientation)g->p.ptr) {
+ case gOrientation0:
+ case gOrientation180:
+ if (g->g.Orientation == gOrientation90 || g->g.Orientation == gOrientation270) {
+ gCoord tmp;
+
+ tmp = g->g.Width;
+ g->g.Width = g->g.Height;
+ g->g.Height = tmp;
+ }
+ break;
+ case gOrientation90:
+ case gOrientation270:
+ if (g->g.Orientation == gOrientation0 || g->g.Orientation == gOrientation180) {
+ gCoord tmp;
+
+ tmp = g->g.Width;
+ g->g.Width = g->g.Height;
+ g->g.Height = tmp;
+ }
+ break;
+ case gOrientationPortrait:
+ case gOrientationLandscape:
+ default:
+ return;
+ }
+ g->g.Orientation = (gOrientation)g->p.ptr;
+ return;
+
+ case GDISP_CONTROL_BACKLIGHT:
+ if ((unsigned)g->p.ptr > 100) g->p.ptr = (void *)100;
+ set_backlight(g, (unsigned)g->p.ptr);
+ g->g.Backlight = (unsigned)g->p.ptr;
+ return;
+
+ #if STM32LTDC_USE_DOUBLEBUFFERING
+ case STM32LTDC_CONTROL_SHOW_BUFFER:
+ {
+ // Wait for end-of-line interrupt
+ // We use simple polling here as end-of-line interrupts are very frequent and usually happen in sub-millisecond intervals.
+ while (LTDC->ISR & LTDC_ISR_LIF);
+
+ // Update framebuffer address in LTDC register
+ // As we currently only support one layer when doublebuffering is enabled, this change happens only to layer 1.
+ LTDC_Layer1->CFBAR = (gU32)(((ltdcLayerConfig*)g->priv)->frame) & LTDC_LxCFBAR_CFBADD;
+
+ // Reload after LTDC config register modifications
+ _ltdc_reload();
+
+ return;
+ }
+ #endif
+
+ default:
+ return;
+ }
+ }
+#endif
+
+#if STM32LTDC_USE_DMA2D
+ #if STM32LTDC_DMA_CACHE_FLUSH
+ #if defined(__CC_ARM)
+ #define __ugfxDSB() __dsb(0xF)
+ #else // GCC like
+ #define __ugfxDSB() __ASM volatile ("dsb 0xF":::"memory")
+ #endif
+ #endif
+
+
+ static void dma2d_init(void) {
+ // Let the board handle the clock setup
+ init_dma2d_clock();
+
+ // Output color format
+ #if GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB565
+ DMA2D->OPFCCR = OPFCCR_RGB565;
+ #elif GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB888
+ DMA2D->OPFCCR = OPFCCR_ARGB8888;
+ #endif
+
+ // Foreground color format
+ #if GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB565
+ DMA2D->FGPFCCR = FGPFCCR_CM_RGB565;
+ #elif GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB888
+ DMA2D->FGPFCCR = FGPFCCR_CM_ARGB8888;
+ #endif
+ }
+
+ // Uses p.x,p.y p.cx,p.cy p.color
+ LLDSPEC void gdisp_lld_fill_area(GDisplay* g)
+ {
+ gU32 pos;
+ gU32 lineadd;
+ gU32 shape;
+
+ #if GDISP_NEED_CONTROL
+ switch(g->g.Orientation) {
+ case gOrientationPortrait:
+ case gOrientationLandscape:
+ case gOrientation0:
+ default:
+ pos = PIXEL_POS(g, g->p.x, g->p.y);
+ lineadd = g->g.Width - g->p.cx;
+ shape = (g->p.cx << 16) | (g->p.cy);
+ break;
+ case gOrientation90:
+ pos = PIXEL_POS(g, g->p.y, g->g.Width-g->p.x-g->p.cx);
+ lineadd = g->g.Height - g->p.cy;
+ shape = (g->p.cy << 16) | (g->p.cx);
+ break;
+ case gOrientation180:
+ pos = PIXEL_POS(g, g->g.Width-g->p.x-g->p.cx, g->g.Height-g->p.y-g->p.cy);
+ lineadd = g->g.Width - g->p.cx;
+ shape = (g->p.cx << 16) | (g->p.cy);
+ break;
+ case gOrientation270:
+ pos = PIXEL_POS(g, g->g.Height-g->p.y-g->p.cy, g->p.x);
+ lineadd = g->g.Height - g->p.cy;
+ shape = (g->p.cy << 16) | (g->p.cx);
+ break;
+ }
+ #else
+ pos = PIXEL_POS(g, g->p.x, g->p.y);
+ lineadd = g->g.Width - g->p.cx;
+ shape = (g->p.cx << 16) | (g->p.cy);
+ #endif
+
+ #if STM32LTDC_DMA_CACHE_FLUSH
+ {
+ // This is slightly less than optimal as we flush the whole line in the source and destination image
+ // instead of just the cx portion but this saves us having to iterate over each line.
+ gU32 f, e;
+
+ // Data memory barrier
+ __ugfxDSB();
+
+ // Flush then invalidate the destination area
+ e = pos + (g->p.cy > 1 ? ((gU32)((ltdcLayerConfig *)g->priv)->pitch*(shape & 0xFFFF)) : ((shape>>16)*LTDC_PIXELBYTES));
+ for(f=(pos & ~31); f < e; f += 32) {
+ SCB->DCCIMVAC = f;
+ SCB->DCIMVAC = f;
+ }
+
+ // Data memory barrier
+ __ugfxDSB();
+ }
+ #endif
+
+ // Wait until DMA2D is ready
+ while(DMA2D->CR & DMA2D_CR_START);
+
+ // Start the DMA2D
+ DMA2D->OMAR = (gU32)PIXEL_ADDR(g, pos);
+ DMA2D->OOR = lineadd;
+ DMA2D->NLR = shape;
+ #if GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB888
+ // As we don't support ARGB pixel types in uGFX yet we will
+ // use RGB with an inverted alpha value for compatibility
+ // ie. 0x00FFFFFF is fully opaque white, 0xFFFFFFFF is fully transparent white
+ DMA2D->OCOLR = (gU32)(gdispColor2Native(g->p.color)) ^ 0xFF000000;
+ #else
+ DMA2D->OCOLR = (gU32)(gdispColor2Native(g->p.color));
+ #endif
+ ;
+ DMA2D->CR = DMA2D_CR_MODE_R2M | DMA2D_CR_START;
+ }
+
+ /* Oops - the DMA2D only supports gOrientation0.
+ *
+ * Where the width is 1 we can trick it for other orientations.
+ * That is worthwhile as a width of 1 is common. For other
+ * situations we need to fall back to pixel pushing.
+ *
+ * Additionally, although DMA2D can translate color formats
+ * it can only do it for a small range of formats. For any
+ * other formats we also need to fall back to pixel pushing.
+ *
+ * As the code to actually do all that for other than the
+ * simplest case (orientation == gOrientation0 and
+ * GDISP_PIXELFORMAT == GDISP_LLD_PIXELFORMAT) is very complex
+ * we will always pixel push for now. In practice that is OK as
+ * access to the framebuffer is fast - probably faster than DMA2D.
+ * It just uses more CPU.
+ */
+ #if GDISP_HARDWARE_BITFILLS
+ // Uses p.x,p.y p.cx,p.cy p.x1,p.y1 (=srcx,srcy) p.x2 (=srccx), p.ptr (=buffer)
+ LLDSPEC void gdisp_lld_blit_area(GDisplay* g) {
+ gU32 srcstart, dststart;
+
+ srcstart = LTDC_PIXELBYTES * ((gU32)g->p.x2 * g->p.y1 + g->p.x1) + (gU32)g->p.ptr;
+ dststart = (gU32)PIXEL_ADDR(g, PIXEL_POS(g, g->p.x, g->p.y));
+
+ #if STM32LTDC_DMA_CACHE_FLUSH
+ {
+ // This is slightly less than optimal as we flush the whole line in the source and destination image
+ // instead of just the cx portion but this saves us having to iterate over each line.
+ gU32 f, e;
+
+ // Data memory barrier
+ __ugfxDSB();
+
+ // Flush the source area
+ e = srcstart + (g->p.cy > 1 ? ((gU32)g->p.x2*g->p.cy) : (gU32)g->p.cx)*LTDC_PIXELBYTES;
+ for(f=(srcstart & ~31); f < e; f += 32)
+ SCB->DCCIMVAC = f;
+
+ // Flush then invalidate the destination area
+ e = dststart + (g->p.cy > 1 ? ((gU32)((ltdcLayerConfig *)g->priv)->pitch*g->p.cy) : ((gU32)g->p.cx*LTDC_PIXELBYTES));
+ for(f=(dststart & ~31); f < e; f += 32) {
+ SCB->DCCIMVAC = f;
+ SCB->DCIMVAC = f;
+ }
+
+ // Data memory barrier
+ __ugfxDSB();
+ }
+ #endif
+
+ // Wait until DMA2D is ready
+ while(DMA2D->CR & DMA2D_CR_START);
+
+ // Source setup
+ DMA2D->FGMAR = srcstart;
+ DMA2D->FGOR = g->p.x2 - g->p.cx;
+
+ // Output setup
+ DMA2D->OMAR = dststart;
+ DMA2D->OOR = g->g.Width - g->p.cx;
+ DMA2D->NLR = (g->p.cx << 16) | (g->p.cy);
+
+ // Set MODE to M2M and Start the process
+ DMA2D->CR = DMA2D_CR_MODE_M2M | DMA2D_CR_START;
+ }
+ #endif
+
+#endif /* STM32LTDC_USE_DMA2D */
+
+#endif /* GFX_USE_GDISP */
diff --git a/drivers/gdisp/STM32LTDC/stm32_ltdc.h b/drivers/gdisp/STM32LTDC/stm32_ltdc.h
index e53ae0c6..ab11d5dc 100644
--- a/drivers/gdisp/STM32LTDC/stm32_ltdc.h
+++ b/drivers/gdisp/STM32LTDC/stm32_ltdc.h
@@ -1,138 +1,138 @@
-/*
- * This file is subject to the terms of the GFX License. If a copy of
- * the license was not distributed with this file, you can obtain one at:
- *
- * http://ugfx.io/license.html
- */
-
-#ifndef STM32_LTDC_H
-#define STM32_LTDC_H
-
-// LTDC enable flags
-#define LTDC_EF_ENABLE (1U << 0) /**< LTDC enabled.*/
-#define LTDC_EF_DITHER (1U << 16) /**< Dithering enabled.*/
-#define LTDC_EF_PIXCLK_INVERT (1U << 28) /**< Inverted pixel clock.*/
-#define LTDC_EF_DATAEN_HIGH (1U << 29) /**< Active-high data enable.*/
-#define LTDC_EF_VSYNC_HIGH (1U << 30) /**< Active-high vsync.*/
-#define LTDC_EF_HSYNC_HIGH (1U << 31) /**< Active-high hsync.*/
-
-#define LTDC_EF_MASK (LTDC_EF_ENABLE | LTDC_EF_DITHER | LTDC_EF_PIXCLK_INVERT | LTDC_EF_DATAEN_HIGH | LTDC_EF_VSYNC_HIGH | LTDC_EF_HSYNC_HIGH)
-
-// LTDC layer enable flags
-#define LTDC_LEF_ENABLE (1U << 0) /**< Layer enabled*/
-#define LTDC_LEF_KEYING (1U << 1) /**< Color keying enabled.*/
-#define LTDC_LEF_PALETTE (1U << 4) /**< Palette enabled.*/
-
-#define LTDC_LEF_MASK (LTDC_LEF_ENABLE | LTDC_LEF_KEYING | LTDC_LEF_PALETTE)
-
-// LTDC pixel formats
-#define LTDC_FMT_ARGB8888 0 /**< ARGB-8888 format.*/
-#define LTDC_FMT_RGB888 1 /**< RGB-888 format.*/
-#define LTDC_FMT_RGB565 2 /**< RGB-565 format.*/
-#define LTDC_FMT_ARGB1555 3 /**< ARGB-1555 format.*/
-#define LTDC_FMT_ARGB4444 4 /**< ARGB-4444 format.*/
-#define LTDC_FMT_L8 5 /**< L-8 format.*/
-#define LTDC_FMT_AL44 6 /**< AL-44 format.*/
-#define LTDC_FMT_AL88 7 /**< AL-88 format.*/
-
-// LTDC pixel format aliased raw masks
-#define LTDC_XMASK_ARGB8888 0xFFFFFFFF /**< ARGB-8888 aliased mask.*/
-#define LTDC_XMASK_RGB888 0x00FFFFFF /**< RGB-888 aliased mask.*/
-#define LTDC_XMASK_RGB565 0x00F8FCF8 /**< RGB-565 aliased mask.*/
-#define LTDC_XMASK_ARGB1555 0x80F8F8F8 /**< ARGB-1555 aliased mask.*/
-#define LTDC_XMASK_ARGB4444 0xF0F0F0F0 /**< ARGB-4444 aliased mask.*/
-#define LTDC_XMASK_L8 0x000000FF /**< L-8 aliased mask.*/
-#define LTDC_XMASK_AL44 0xF00000F0 /**< AL-44 aliased mask.*/
-#define LTDC_XMASK_AL88 0xFF0000FF /**< AL-88 aliased mask.*/
-
-// LTDC blending factors
-#define LTDC_BLEND_FIX1_FIX2 0x0405 /**< cnst1; 1 - cnst2 */
-#define LTDC_BLEND_FIX1_MOD2 0x0407 /**< cnst1; 1 - a2 * cnst2 */
-#define LTDC_BLEND_MOD1_FIX2 0x0605 /**< a1 * cnst1; 1 - cnst2 */
-#define LTDC_BLEND_MOD1_MOD2 0x0607 /**< a1 * cnst1; 1 - a2 * cnst2 */
-
-// LTDC parameter bounds
-#define LTDC_MIN_SCREEN_WIDTH 1
-#define LTDC_MIN_SCREEN_HEIGHT 1
-#define LTDC_MAX_SCREEN_WIDTH 800
-#define LTDC_MAX_SCREEN_HEIGHT 600
-
-#define LTDC_MIN_HSYNC_WIDTH 1
-#define LTDC_MIN_VSYNC_HEIGHT 1
-#define LTDC_MAX_HSYNC_WIDTH (1U << 12)
-#define LTDC_MAX_VSYNC_HEIGHT (1U << 11)
-
-#define LTDC_MIN_HBP_WIDTH 0
-#define LTDC_MIN_VBP_HEIGHT 0
-#define LTDC_MAX_HBP_WIDTH (1U << 12)
-#define LTDC_MAX_VBP_HEIGHT (1U << 11)
-
-#define LTDC_MIN_ACC_HBP_WIDTH 1
-#define LTDC_MIN_ACC_VBP_HEIGHT 1
-#define LTDC_MAX_ACC_HBP_WIDTH (1U << 12)
-#define LTDC_MAX_ACC_VBP_HEIGHT (1U << 11)
-
-#define LTDC_MIN_HFP_WIDTH 0
-#define LTDC_MIN_VFP_HEIGHT 0
-#define LTDC_MAX_HFP_WIDTH (1U << 12)
-#define LTDC_MAX_VFP_HEIGHT (1U << 11)
-
-#define LTDC_MIN_ACTIVE_WIDTH 0
-#define LTDC_MIN_ACTIVE_HEIGHT 0
-#define LTDC_MAX_ACTIVE_WIDTH (1U << 12)
-#define LTDC_MAX_ACTIVE_HEIGHT (1U << 11)
-
-#define LTDC_MIN_ACC_ACTIVE_WIDTH 1
-#define LTDC_MIN_ACC_ACTIVE_HEIGHT 1
-#define LTDC_MAX_ACC_ACTIVE_WIDTH (1U << 12)
-#define LTDC_MAX_ACC_ACTIVE_HEIGHT (1U << 11)
-
-#define LTDC_MIN_ACC_TOTAL_WIDTH 1
-#define LTDC_MIN_ACC_TOTAL_HEIGHT 1
-#define LTDC_MAX_ACC_TOTAL_WIDTH (1U << 12)
-#define LTDC_MAX_ACC_TOTAL_HEIGHT (1U << 11)
-
-#define LTDC_MIN_LINE_INTERRUPT_POS 0
-#define LTDC_MAX_LINE_INTERRUPT_POS ((1U << 11) - 1)
-
-#define LTDC_MIN_WINDOW_HSTART 0
-#define LTDC_MIN_WINDOW_HSTART 0
-#define LTDC_MAX_WINDOW_HSTOP ((1U << 12) - 1)
-#define LTDC_MAX_WINDOW_HSTOP ((1U << 12) - 1)
-
-#define LTDC_MIN_WINDOW_VSTART 0
-#define LTDC_MIN_WINDOW_VSTART 0
-#define LTDC_MAX_WINDOW_VSTOP ((1U << 11) - 1)
-#define LTDC_MAX_WINDOW_VSTOP ((1U << 11) - 1)
-
-#define LTDC_MIN_FRAME_WIDTH_BYTES 0
-#define LTDC_MIN_FRAME_HEIGHT_LINES 0
-#define LTDC_MIN_FRAME_PITCH_BYTES 0
-#define LTDC_MAX_FRAME_WIDTH_BYTES ((1U << 13) - 1 - 3)
-#define LTDC_MAX_FRAME_HEIGHT_LINES ((1U << 11) - 1)
-#define LTDC_MAX_FRAME_PITCH_BYTES ((1U << 13) - 1)
-
-#define LTDC_MIN_PIXFMT_ID 0
-#define LTDC_MAX_PIXFMT_ID 7
-
-#define LTDC_MAX_PALETTE_LENGTH 256
-
-// LTDC basic ARGB-8888 colors.
-#define LTDC_COLOR_BLACK 0xFF000000
-#define LTDC_COLOR_MAROON 0xFF800000
-#define LTDC_COLOR_GREEN 0xFF008000
-#define LTDC_COLOR_OLIVE 0xFF808000
-#define LTDC_COLOR_NAVY 0xFF000080
-#define LTDC_COLOR_PURPLE 0xFF800080
-#define LTDC_COLOR_TEAL 0xFF008080
-#define LTDC_COLOR_SILVER 0xFFC0C0C0
-#define LTDC_COLOR_GRAY 0xFF808080
-#define LTDC_COLOR_RED 0xFFFF0000
-#define LTDC_COLOR_LIME 0xFF00FF00
-#define LTDC_COLOR_YELLOW 0xFFFFFF00
-#define LTDC_COLOR_BLUE 0xFF0000FF
-#define LTDC_COLOR_FUCHSIA 0xFFFF00FF
-#define LTDC_COLOR_AQUA 0xFF00FFFF
-#define LTDC_COLOR_WHITE 0xFFFFFFFF
-
-#endif /* STM32_LTDC_H */
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ * http://ugfx.io/license.html
+ */
+
+#ifndef STM32_LTDC_H
+#define STM32_LTDC_H
+
+// LTDC enable flags
+#define LTDC_EF_ENABLE (1U << 0) /**< LTDC enabled.*/
+#define LTDC_EF_DITHER (1U << 16) /**< Dithering enabled.*/
+#define LTDC_EF_PIXCLK_INVERT (1U << 28) /**< Inverted pixel clock.*/
+#define LTDC_EF_DATAEN_HIGH (1U << 29) /**< Active-high data enable.*/
+#define LTDC_EF_VSYNC_HIGH (1U << 30) /**< Active-high vsync.*/
+#define LTDC_EF_HSYNC_HIGH (1U << 31) /**< Active-high hsync.*/
+
+#define LTDC_EF_MASK (LTDC_EF_ENABLE | LTDC_EF_DITHER | LTDC_EF_PIXCLK_INVERT | LTDC_EF_DATAEN_HIGH | LTDC_EF_VSYNC_HIGH | LTDC_EF_HSYNC_HIGH)
+
+// LTDC layer enable flags
+#define LTDC_LEF_ENABLE (1U << 0) /**< Layer enabled*/
+#define LTDC_LEF_KEYING (1U << 1) /**< Color keying enabled.*/
+#define LTDC_LEF_PALETTE (1U << 4) /**< Palette enabled.*/
+
+#define LTDC_LEF_MASK (LTDC_LEF_ENABLE | LTDC_LEF_KEYING | LTDC_LEF_PALETTE)
+
+// LTDC pixel formats
+#define LTDC_FMT_ARGB8888 0 /**< ARGB-8888 format.*/
+#define LTDC_FMT_RGB888 1 /**< RGB-888 format.*/
+#define LTDC_FMT_RGB565 2 /**< RGB-565 format.*/
+#define LTDC_FMT_ARGB1555 3 /**< ARGB-1555 format.*/
+#define LTDC_FMT_ARGB4444 4 /**< ARGB-4444 format.*/
+#define LTDC_FMT_L8 5 /**< L-8 format.*/
+#define LTDC_FMT_AL44 6 /**< AL-44 format.*/
+#define LTDC_FMT_AL88 7 /**< AL-88 format.*/
+
+// LTDC pixel format aliased raw masks
+#define LTDC_XMASK_ARGB8888 0xFFFFFFFF /**< ARGB-8888 aliased mask.*/
+#define LTDC_XMASK_RGB888 0x00FFFFFF /**< RGB-888 aliased mask.*/
+#define LTDC_XMASK_RGB565 0x00F8FCF8 /**< RGB-565 aliased mask.*/
+#define LTDC_XMASK_ARGB1555 0x80F8F8F8 /**< ARGB-1555 aliased mask.*/
+#define LTDC_XMASK_ARGB4444 0xF0F0F0F0 /**< ARGB-4444 aliased mask.*/
+#define LTDC_XMASK_L8 0x000000FF /**< L-8 aliased mask.*/
+#define LTDC_XMASK_AL44 0xF00000F0 /**< AL-44 aliased mask.*/
+#define LTDC_XMASK_AL88 0xFF0000FF /**< AL-88 aliased mask.*/
+
+// LTDC blending factors
+#define LTDC_BLEND_FIX1_FIX2 0x0405 /**< cnst1; 1 - cnst2 */
+#define LTDC_BLEND_FIX1_MOD2 0x0407 /**< cnst1; 1 - a2 * cnst2 */
+#define LTDC_BLEND_MOD1_FIX2 0x0605 /**< a1 * cnst1; 1 - cnst2 */
+#define LTDC_BLEND_MOD1_MOD2 0x0607 /**< a1 * cnst1; 1 - a2 * cnst2 */
+
+// LTDC parameter bounds
+#define LTDC_MIN_SCREEN_WIDTH 1
+#define LTDC_MIN_SCREEN_HEIGHT 1
+#define LTDC_MAX_SCREEN_WIDTH 800
+#define LTDC_MAX_SCREEN_HEIGHT 600
+
+#define LTDC_MIN_HSYNC_WIDTH 1
+#define LTDC_MIN_VSYNC_HEIGHT 1
+#define LTDC_MAX_HSYNC_WIDTH (1U << 12)
+#define LTDC_MAX_VSYNC_HEIGHT (1U << 11)
+
+#define LTDC_MIN_HBP_WIDTH 0
+#define LTDC_MIN_VBP_HEIGHT 0
+#define LTDC_MAX_HBP_WIDTH (1U << 12)
+#define LTDC_MAX_VBP_HEIGHT (1U << 11)
+
+#define LTDC_MIN_ACC_HBP_WIDTH 1
+#define LTDC_MIN_ACC_VBP_HEIGHT 1
+#define LTDC_MAX_ACC_HBP_WIDTH (1U << 12)
+#define LTDC_MAX_ACC_VBP_HEIGHT (1U << 11)
+
+#define LTDC_MIN_HFP_WIDTH 0
+#define LTDC_MIN_VFP_HEIGHT 0
+#define LTDC_MAX_HFP_WIDTH (1U << 12)
+#define LTDC_MAX_VFP_HEIGHT (1U << 11)
+
+#define LTDC_MIN_ACTIVE_WIDTH 0
+#define LTDC_MIN_ACTIVE_HEIGHT 0
+#define LTDC_MAX_ACTIVE_WIDTH (1U << 12)
+#define LTDC_MAX_ACTIVE_HEIGHT (1U << 11)
+
+#define LTDC_MIN_ACC_ACTIVE_WIDTH 1
+#define LTDC_MIN_ACC_ACTIVE_HEIGHT 1
+#define LTDC_MAX_ACC_ACTIVE_WIDTH (1U << 12)
+#define LTDC_MAX_ACC_ACTIVE_HEIGHT (1U << 11)
+
+#define LTDC_MIN_ACC_TOTAL_WIDTH 1
+#define LTDC_MIN_ACC_TOTAL_HEIGHT 1
+#define LTDC_MAX_ACC_TOTAL_WIDTH (1U << 12)
+#define LTDC_MAX_ACC_TOTAL_HEIGHT (1U << 11)
+
+#define LTDC_MIN_LINE_INTERRUPT_POS 0
+#define LTDC_MAX_LINE_INTERRUPT_POS ((1U << 11) - 1)
+
+#define LTDC_MIN_WINDOW_HSTART 0
+#define LTDC_MIN_WINDOW_HSTART 0
+#define LTDC_MAX_WINDOW_HSTOP ((1U << 12) - 1)
+#define LTDC_MAX_WINDOW_HSTOP ((1U << 12) - 1)
+
+#define LTDC_MIN_WINDOW_VSTART 0
+#define LTDC_MIN_WINDOW_VSTART 0
+#define LTDC_MAX_WINDOW_VSTOP ((1U << 11) - 1)
+#define LTDC_MAX_WINDOW_VSTOP ((1U << 11) - 1)
+
+#define LTDC_MIN_FRAME_WIDTH_BYTES 0
+#define LTDC_MIN_FRAME_HEIGHT_LINES 0
+#define LTDC_MIN_FRAME_PITCH_BYTES 0
+#define LTDC_MAX_FRAME_WIDTH_BYTES ((1U << 13) - 1 - 3)
+#define LTDC_MAX_FRAME_HEIGHT_LINES ((1U << 11) - 1)
+#define LTDC_MAX_FRAME_PITCH_BYTES ((1U << 13) - 1)
+
+#define LTDC_MIN_PIXFMT_ID 0
+#define LTDC_MAX_PIXFMT_ID 7
+
+#define LTDC_MAX_PALETTE_LENGTH 256
+
+// LTDC basic ARGB-8888 colors.
+#define LTDC_COLOR_BLACK 0xFF000000
+#define LTDC_COLOR_MAROON 0xFF800000
+#define LTDC_COLOR_GREEN 0xFF008000
+#define LTDC_COLOR_OLIVE 0xFF808000
+#define LTDC_COLOR_NAVY 0xFF000080
+#define LTDC_COLOR_PURPLE 0xFF800080
+#define LTDC_COLOR_TEAL 0xFF008080
+#define LTDC_COLOR_SILVER 0xFFC0C0C0
+#define LTDC_COLOR_GRAY 0xFF808080
+#define LTDC_COLOR_RED 0xFFFF0000
+#define LTDC_COLOR_LIME 0xFF00FF00
+#define LTDC_COLOR_YELLOW 0xFFFFFF00
+#define LTDC_COLOR_BLUE 0xFF0000FF
+#define LTDC_COLOR_FUCHSIA 0xFFFF00FF
+#define LTDC_COLOR_AQUA 0xFF00FFFF
+#define LTDC_COLOR_WHITE 0xFFFFFFFF
+
+#endif /* STM32_LTDC_H */
diff --git a/drivers/gdisp/TestStub/gdisp_lld_config.h b/drivers/gdisp/TestStub/gdisp_lld_config.h
index a49c94bb..139f0126 100644
--- a/drivers/gdisp/TestStub/gdisp_lld_config.h
+++ b/drivers/gdisp/TestStub/gdisp_lld_config.h
@@ -4,21 +4,21 @@
*
* http://ugfx.io/license.html
*/
-
-#ifndef _GDISP_LLD_CONFIG_H
-#define _GDISP_LLD_CONFIG_H
-
-#if GFX_USE_GDISP
-
-/*===========================================================================*/
-/* Driver hardware support. */
-/*===========================================================================*/
-
+
+#ifndef _GDISP_LLD_CONFIG_H
+#define _GDISP_LLD_CONFIG_H
+
+#if GFX_USE_GDISP
+
+/*===========================================================================*/
+/* Driver hardware support. */
+/*===========================================================================*/
+
#define GDISP_HARDWARE_DRAWPIXEL GFXON
-#define GDISP_HARDWARE_PIXELREAD GFXON
-
-#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_RGB565
-
-#endif /* GFX_USE_GDISP */
-
-#endif /* _GDISP_LLD_CONFIG_H */
+#define GDISP_HARDWARE_PIXELREAD GFXON
+
+#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_RGB565
+
+#endif /* GFX_USE_GDISP */
+
+#endif /* _GDISP_LLD_CONFIG_H */
diff --git a/drivers/gdisp/readme.txt b/drivers/gdisp/readme.txt
index ecc2ba85..8658f845 100644
--- a/drivers/gdisp/readme.txt
+++ b/drivers/gdisp/readme.txt
@@ -1,45 +1,45 @@
-A list of current display drivers:
-
-AlteraFramereader - Support for the "Altera Frame Reader IP Core"
-ED060SC4 - E-Ink display
-framebuffer - Supports any non-palletized, non-bitpacked color display with a framebuffer
-Fb24bpp - Same as 'framebuffer' driver but supports RGB888 and BGR888 packed framebuffer formats.
-HX8347D - Mid-sized color LCD displays eg RGB565 320x240
-ILI9320 - Mid-sized color LCD displays eg RGB565 320x240
-ILI9325 - Mid-sized color LCD displays eg RGB565 320x240
-ILI9341 - Mid-sized color LCD displays eg RGB565 320x240
-ILI9342 - Mid-sized color LCD displays eg RGB565 320x240
-ILI93xx - Mid-sized color LCD displays eg RGB565 320x240 (attempt at a common driver)
-ILI9481 - Mid-sized color LCD displays eg RGB565 320x240
-KS0108 - Small monochrome LCD
-LGDP4532 - Mid-sized color LCD displays eg RGB565 320x240
-Nokia6610GE8 - Small (130x130) 12bit color LCD
-Nokia6610GE12 - Small (130x130) 12bit color LCD (untested)
-PCD8544 - Small monochrome LCD
-PCF8812 - Small monochrome LCD
-R61505U - Mid-sized color LCD displays eg RGB565 320x240
-RA6963 - Small monochrome LCD
-RA8875 - Mid-sized color LCD displays eg RGB565 320x240
-S6D1121 - Mid-sized color LCD displays eg RGB565 320x240
-SPFD54124B - Mid-sized color LCD displays eg RGB565 320x240
-SSD1289 - Mid-sized color LCD displays eg RGB565 320x240
-SSD1306 - Small monochrome LCD
-SSD1322 - Small 16 level grayscale LCD
-SSD1331 - Small hardware accelerated OLED display RGB565 96x64
-SSD1351 - Mid-sized color LCD displays eg RGB565 320x240
-SSD1848 - Small grayscale LCD eg 2-Bit 130x130
-SSD1963 - Mid-sized color LCD displays eg RGB565 320x240
-SSD2119 - Mid-sized color LCD displays eg RGB565 320x240
-ST7565 - Small monochrome LCD
-STM32LTDC - STM32 ART graphics STM32F4 and STM32F7 series CPU's
-TestStub - NULL driver just to test compile
-TLS8204 - Small monochrome LCD
-UC8173 - E-Ink display driver
-UC1601s - Small (64x132) monochrome LCD
-UC1610 - Small (78x64 or 160x104) 4 level grayscale LCD
-UC8175 - Small E-Ink display
-WS29EPD - Small E-Ink display by WaveShare
-QImage - Driver that allows rendering into a QImage object (of the Qt framework)
-uGFXnet - Remote Network display (in drivers/multiple/uGFXnet directory)
-Win32 - Microsoft Windows (in drivers/multiple/Win32 directory)
-X - X Windows (Xlib) (in drivers/multiple/X directory)
+A list of current display drivers:
+
+AlteraFramereader - Support for the "Altera Frame Reader IP Core"
+ED060SC4 - E-Ink display
+framebuffer - Supports any non-palletized, non-bitpacked color display with a framebuffer
+Fb24bpp - Same as 'framebuffer' driver but supports RGB888 and BGR888 packed framebuffer formats.
+HX8347D - Mid-sized color LCD displays eg RGB565 320x240
+ILI9320 - Mid-sized color LCD displays eg RGB565 320x240
+ILI9325 - Mid-sized color LCD displays eg RGB565 320x240
+ILI9341 - Mid-sized color LCD displays eg RGB565 320x240
+ILI9342 - Mid-sized color LCD displays eg RGB565 320x240
+ILI93xx - Mid-sized color LCD displays eg RGB565 320x240 (attempt at a common driver)
+ILI9481 - Mid-sized color LCD displays eg RGB565 320x240
+KS0108 - Small monochrome LCD
+LGDP4532 - Mid-sized color LCD displays eg RGB565 320x240
+Nokia6610GE8 - Small (130x130) 12bit color LCD
+Nokia6610GE12 - Small (130x130) 12bit color LCD (untested)
+PCD8544 - Small monochrome LCD
+PCF8812 - Small monochrome LCD
+R61505U - Mid-sized color LCD displays eg RGB565 320x240
+RA6963 - Small monochrome LCD
+RA8875 - Mid-sized color LCD displays eg RGB565 320x240
+S6D1121 - Mid-sized color LCD displays eg RGB565 320x240
+SPFD54124B - Mid-sized color LCD displays eg RGB565 320x240
+SSD1289 - Mid-sized color LCD displays eg RGB565 320x240
+SSD1306 - Small monochrome LCD
+SSD1322 - Small 16 level grayscale LCD
+SSD1331 - Small hardware accelerated OLED display RGB565 96x64
+SSD1351 - Mid-sized color LCD displays eg RGB565 320x240
+SSD1848 - Small grayscale LCD eg 2-Bit 130x130
+SSD1963 - Mid-sized color LCD displays eg RGB565 320x240
+SSD2119 - Mid-sized color LCD displays eg RGB565 320x240
+ST7565 - Small monochrome LCD
+STM32LTDC - STM32 ART graphics STM32F4 and STM32F7 series CPU's
+TestStub - NULL driver just to test compile
+TLS8204 - Small monochrome LCD
+UC8173 - E-Ink display driver
+UC1601s - Small (64x132) monochrome LCD
+UC1610 - Small (78x64 or 160x104) 4 level grayscale LCD
+UC8175 - Small E-Ink display
+WS29EPD - Small E-Ink display by WaveShare
+QImage - Driver that allows rendering into a QImage object (of the Qt framework)
+uGFXnet - Remote Network display (in drivers/multiple/uGFXnet directory)
+Win32 - Microsoft Windows (in drivers/multiple/Win32 directory)
+X - X Windows (Xlib) (in drivers/multiple/X directory)
diff --git a/drivers/ginput/toggle/Pal/ginput_lld_toggle_config.h b/drivers/ginput/toggle/Pal/ginput_lld_toggle_config.h
index d7bb341d..249081ba 100644
--- a/drivers/ginput/toggle/Pal/ginput_lld_toggle_config.h
+++ b/drivers/ginput/toggle/Pal/ginput_lld_toggle_config.h
@@ -3,16 +3,16 @@
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.io/license.html
- */
-
-#ifndef _GINPUT_LLD_TOGGLE_CONFIG_H
-#define _GINPUT_LLD_TOGGLE_CONFIG_H
-
-#if GFX_USE_GINPUT && GINPUT_NEED_TOGGLE
-
-/* Include the user supplied board definitions */
-#include "ginput_lld_toggle_board.h"
-
-#endif /* GFX_USE_GDISP && GINPUT_NEED_TOGGLE */
-
-#endif /* _GINPUT_LLD_TOGGLE_CONFIG_H */
+ */
+
+#ifndef _GINPUT_LLD_TOGGLE_CONFIG_H
+#define _GINPUT_LLD_TOGGLE_CONFIG_H
+
+#if GFX_USE_GINPUT && GINPUT_NEED_TOGGLE
+
+/* Include the user supplied board definitions */
+#include "ginput_lld_toggle_board.h"
+
+#endif /* GFX_USE_GDISP && GINPUT_NEED_TOGGLE */
+
+#endif /* _GINPUT_LLD_TOGGLE_CONFIG_H */
diff --git a/drivers/ginput/toggle/Pal/readme.txt b/drivers/ginput/toggle/Pal/readme.txt
index 0eeb341d..908a4219 100644
--- a/drivers/ginput/toggle/Pal/readme.txt
+++ b/drivers/ginput/toggle/Pal/readme.txt
@@ -1,13 +1,13 @@
-To use this driver:
-
-1. Add in your gfxconf.h:
- a) #define GFX_USE_GINPUT GFXON
- #define GINPUT_NEED_TOGGLE GFXON
- d) If you are not using a known board then create a ginput_lld_toggle_board.h file
- and ensure it is on your include path.
- Use the ginput_lld_toggle_board_example.h file as a basis.
- Currently known boards are:
- Olimex SAM7-EX256
-
-2. To your makefile add the following lines:
- include $(GFXLIB)/drivers/ginput/toggle/Pal/driver.mk
+To use this driver:
+
+1. Add in your gfxconf.h:
+ a) #define GFX_USE_GINPUT GFXON
+ #define GINPUT_NEED_TOGGLE GFXON
+ d) If you are not using a known board then create a ginput_lld_toggle_board.h file
+ and ensure it is on your include path.
+ Use the ginput_lld_toggle_board_example.h file as a basis.
+ Currently known boards are:
+ Olimex SAM7-EX256
+
+2. To your makefile add the following lines:
+ include $(GFXLIB)/drivers/ginput/toggle/Pal/driver.mk
diff --git a/drivers/ginput/touch/ADS7843/gmouse_lld_ADS7843.c b/drivers/ginput/touch/ADS7843/gmouse_lld_ADS7843.c
index 12176bdf..4a9515b6 100644
--- a/drivers/ginput/touch/ADS7843/gmouse_lld_ADS7843.c
+++ b/drivers/ginput/touch/ADS7843/gmouse_lld_ADS7843.c
@@ -1,80 +1,80 @@
-/*
- * This file is subject to the terms of the GFX License. If a copy of
- * the license was not distributed with this file, you can obtain one at:
- *
- * http://ugfx.io/license.html
- */
-
-#include "gfx.h"
-
-#if (GFX_USE_GINPUT && GINPUT_NEED_MOUSE)
-
-#define GMOUSE_DRIVER_VMT GMOUSEVMT_ADS7843
-#include "../../../../src/ginput/ginput_driver_mouse.h"
-
-// Get the hardware interface
-#include "gmouse_lld_ADS7843_board.h"
-
-#define CMD_X 0xD1
-#define CMD_Y 0x91
-#define CMD_ENABLE_IRQ 0x80
-
-static gBool MouseXYZ(GMouse* m, GMouseReading* pdr)
-{
- (void)m;
-
- // No buttons
- pdr->buttons = 0;
- pdr->z = 0;
-
- if (getpin_pressed(m)) {
- pdr->z = 1; // Set to Z_MAX as we are pressed
-
- aquire_bus(m);
-
- read_value(m, CMD_X); // Dummy read - disable PenIRQ
- pdr->x = read_value(m, CMD_X); // Read X-Value
-
- read_value(m, CMD_Y); // Dummy read - disable PenIRQ
- pdr->y = read_value(m, CMD_Y); // Read Y-Value
-
- read_value(m, CMD_ENABLE_IRQ); // Enable IRQ
-
- release_bus(m);
- }
- return gTrue;
-}
-
-const GMouseVMT const GMOUSE_DRIVER_VMT[1] = {{
- {
- GDRIVER_TYPE_TOUCH,
- GMOUSE_VFLG_TOUCH | GMOUSE_VFLG_CALIBRATE | GMOUSE_VFLG_CAL_TEST |
- GMOUSE_VFLG_ONLY_DOWN | GMOUSE_VFLG_POORUPDOWN,
- sizeof(GMouse)+GMOUSE_ADS7843_BOARD_DATA_SIZE,
- _gmouseInitDriver,
- _gmousePostInitDriver,
- _gmouseDeInitDriver
- },
- 1, // z_max - (currently?) not supported
- 0, // z_min - (currently?) not supported
- 1, // z_touchon
- 0, // z_touchoff
- { // pen_jitter
- GMOUSE_ADS7843_PEN_CALIBRATE_ERROR, // calibrate
- GMOUSE_ADS7843_PEN_CLICK_ERROR, // click
- GMOUSE_ADS7843_PEN_MOVE_ERROR // move
- },
- { // finger_jitter
- GMOUSE_ADS7843_FINGER_CALIBRATE_ERROR, // calibrate
- GMOUSE_ADS7843_FINGER_CLICK_ERROR, // click
- GMOUSE_ADS7843_FINGER_MOVE_ERROR // move
- },
- init_board, // init
- 0, // deinit
- MouseXYZ, // get
- 0, // calsave
- 0 // calload
-}};
-
-#endif /* GFX_USE_GINPUT && GINPUT_NEED_MOUSE */
-
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ * http://ugfx.io/license.html
+ */
+
+#include "gfx.h"
+
+#if (GFX_USE_GINPUT && GINPUT_NEED_MOUSE)
+
+#define GMOUSE_DRIVER_VMT GMOUSEVMT_ADS7843
+#include "../../../../src/ginput/ginput_driver_mouse.h"
+
+// Get the hardware interface
+#include "gmouse_lld_ADS7843_board.h"
+
+#define CMD_X 0xD1
+#define CMD_Y 0x91
+#define CMD_ENABLE_IRQ 0x80
+
+static gBool MouseXYZ(GMouse* m, GMouseReading* pdr)
+{
+ (void)m;
+
+ // No buttons
+ pdr->buttons = 0;
+ pdr->z = 0;
+
+ if (getpin_pressed(m)) {
+ pdr->z = 1; // Set to Z_MAX as we are pressed
+
+ aquire_bus(m);
+
+ read_value(m, CMD_X); // Dummy read - disable PenIRQ
+ pdr->x = read_value(m, CMD_X); // Read X-Value
+
+ read_value(m, CMD_Y); // Dummy read - disable PenIRQ
+ pdr->y = read_value(m, CMD_Y); // Read Y-Value
+
+ read_value(m, CMD_ENABLE_IRQ); // Enable IRQ
+
+ release_bus(m);
+ }
+ return gTrue;
+}
+
+const GMouseVMT const GMOUSE_DRIVER_VMT[1] = {{
+ {
+ GDRIVER_TYPE_TOUCH,
+ GMOUSE_VFLG_TOUCH | GMOUSE_VFLG_CALIBRATE | GMOUSE_VFLG_CAL_TEST |
+ GMOUSE_VFLG_ONLY_DOWN | GMOUSE_VFLG_POORUPDOWN,
+ sizeof(GMouse)+GMOUSE_ADS7843_BOARD_DATA_SIZE,
+ _gmouseInitDriver,
+ _gmousePostInitDriver,
+ _gmouseDeInitDriver
+ },
+ 1, // z_max - (currently?) not supported
+ 0, // z_min - (currently?) not supported
+ 1, // z_touchon
+ 0, // z_touchoff
+ { // pen_jitter
+ GMOUSE_ADS7843_PEN_CALIBRATE_ERROR, // calibrate
+ GMOUSE_ADS7843_PEN_CLICK_ERROR, // click
+ GMOUSE_ADS7843_PEN_MOVE_ERROR // move
+ },
+ { // finger_jitter
+ GMOUSE_ADS7843_FINGER_CALIBRATE_ERROR, // calibrate
+ GMOUSE_ADS7843_FINGER_CLICK_ERROR, // click
+ GMOUSE_ADS7843_FINGER_MOVE_ERROR // move
+ },
+ init_board, // init
+ 0, // deinit
+ MouseXYZ, // get
+ 0, // calsave
+ 0 // calload
+}};
+
+#endif /* GFX_USE_GINPUT && GINPUT_NEED_MOUSE */
+
diff --git a/drivers/multiple/Win32/ginput_lld_toggle_config.h b/drivers/multiple/Win32/ginput_lld_toggle_config.h
index d4bd9f9d..2923a0f6 100644
--- a/drivers/multiple/Win32/ginput_lld_toggle_config.h
+++ b/drivers/multiple/Win32/ginput_lld_toggle_config.h
@@ -3,37 +3,37 @@
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.io/license.html
- */
-
-#ifndef _GINPUT_LLD_TOGGLE_CONFIG_H
-#define _GINPUT_LLD_TOGGLE_CONFIG_H
-
-#if GFX_USE_GINPUT && GINPUT_NEED_TOGGLE
-
-#define GINPUT_TOGGLE_POLL_PERIOD gDelayForever // We are interrupt driven (or polled - either works here)
+ */
+
+#ifndef _GINPUT_LLD_TOGGLE_CONFIG_H
+#define _GINPUT_LLD_TOGGLE_CONFIG_H
+
+#if GFX_USE_GINPUT && GINPUT_NEED_TOGGLE
+
+#define GINPUT_TOGGLE_POLL_PERIOD gDelayForever // We are interrupt driven (or polled - either works here)
// This driver is unique in that it can support 8 buttons per window across multiple windows.
// GINPUT_TOGGLE_CONFIG_ENTRIES just must be less than the number of GDISP windows (GDISP_DRIVER_COUNT_WIN32).
// DEPRECATED: Currently only supports a single window with buttons until toggles use GDriver
-#ifndef GINPUT_TOGGLE_CONFIG_ENTRIES
+#ifndef GINPUT_TOGGLE_CONFIG_ENTRIES
#define GINPUT_TOGGLE_CONFIG_ENTRIES 1 // The total number of GToggleConfig entries
-#endif
+#endif
// The total number of toggle inputs
#define GINPUT_TOGGLE_NUM_PORTS (8 * GINPUT_TOGGLE_CONFIG_ENTRIES)
-
-#define GINPUT_TOGGLE_SW1 0 // Switch 1 - Toggle
-#define GINPUT_TOGGLE_SW2 1 // Switch 2 - Toggle
-#define GINPUT_TOGGLE_SW3 2 // Switch 3 - Toggle
-#define GINPUT_TOGGLE_SW4 3 // Switch 4 - Toggle
-
-#define GINPUT_TOGGLE_MOMENTARY1 4 // Switch 5 - Momentary
-#define GINPUT_TOGGLE_MOMENTARY2 5 // Switch 6 - Momentary
-#define GINPUT_TOGGLE_MOMENTARY3 6 // Switch 7 - Momentary
-#define GINPUT_TOGGLE_MOMENTARY4 7 // Switch 8 - Momentary
+
+#define GINPUT_TOGGLE_SW1 0 // Switch 1 - Toggle
+#define GINPUT_TOGGLE_SW2 1 // Switch 2 - Toggle
+#define GINPUT_TOGGLE_SW3 2 // Switch 3 - Toggle
+#define GINPUT_TOGGLE_SW4 3 // Switch 4 - Toggle
+
+#define GINPUT_TOGGLE_MOMENTARY1 4 // Switch 5 - Momentary
+#define GINPUT_TOGGLE_MOMENTARY2 5 // Switch 6 - Momentary
+#define GINPUT_TOGGLE_MOMENTARY3 6 // Switch 7 - Momentary
+#define GINPUT_TOGGLE_MOMENTARY4 7 // Switch 8 - Momentary
// This pattern of switch and momentary action is repeated across all windows.
-
-#endif /* GFX_USE_GDISP && GINPUT_NEED_TOGGLE */
-
-#endif /* _GINPUT_LLD_TOGGLE_CONFIG_H */
+
+#endif /* GFX_USE_GDISP && GINPUT_NEED_TOGGLE */
+
+#endif /* _GINPUT_LLD_TOGGLE_CONFIG_H */
diff --git a/drivers/multiple/Win32/readme.txt b/drivers/multiple/Win32/readme.txt
index 47080f73..6aae58a7 100644
--- a/drivers/multiple/Win32/readme.txt
+++ b/drivers/multiple/Win32/readme.txt
@@ -1,29 +1,29 @@
-To use this driver:
-
-This driver is special in that it implements both the gdisp low level driver,
-optionally a touchscreen driver, and optionally a toggle driver.
-
-1. Add in your gfxconf.h:
- a) #define GFX_USE_GDISP GFXON
- b) Optionally #define GFX_USE_GINPUT GFXON
- #define GINPUT_USE_MOUSE GFXON
- #define GINPUT_USE_TOGGLE GFXON
- c) Any optional high level driver defines (see gdisp.h) eg: GDISP_NEED_MULTITHREAD
- d) Optionally the following (with appropriate values):
- #define GDISP_SCREEN_WIDTH 640
- #define GDISP_SCREEN_HEIGHT 480
-
-
-2. To your makefile add the following lines:
- include $(GFXLIB)/gfx.mk
- include $(GFXLIB)/drivers/multiple/Win32/driver.mk
-
- However, consider using the Win32 board file instead as this does include all
- the possible drivers that can be used (eg. for the GAUDIO module) by using:
-
- include $(GFXLIB)/gfx.mk
- include $(GFXLIB)/boards/base/Win32/board.mk
-
-
-3. Modify your makefile to add -lws2_32 and -lgdi32 to the DLIBS line. i.e.
- DLIBS = -lws2_32 -lgdi32
+To use this driver:
+
+This driver is special in that it implements both the gdisp low level driver,
+optionally a touchscreen driver, and optionally a toggle driver.
+
+1. Add in your gfxconf.h:
+ a) #define GFX_USE_GDISP GFXON
+ b) Optionally #define GFX_USE_GINPUT GFXON
+ #define GINPUT_USE_MOUSE GFXON
+ #define GINPUT_USE_TOGGLE GFXON
+ c) Any optional high level driver defines (see gdisp.h) eg: GDISP_NEED_MULTITHREAD
+ d) Optionally the following (with appropriate values):
+ #define GDISP_SCREEN_WIDTH 640
+ #define GDISP_SCREEN_HEIGHT 480
+
+
+2. To your makefile add the following lines:
+ include $(GFXLIB)/gfx.mk
+ include $(GFXLIB)/drivers/multiple/Win32/driver.mk
+
+ However, consider using the Win32 board file instead as this does include all
+ the possible drivers that can be used (eg. for the GAUDIO module) by using:
+
+ include $(GFXLIB)/gfx.mk
+ include $(GFXLIB)/boards/base/Win32/board.mk
+
+
+3. Modify your makefile to add -lws2_32 and -lgdi32 to the DLIBS line. i.e.
+ DLIBS = -lws2_32 -lgdi32
diff --git a/gfx.mk b/gfx.mk
index c359e75e..62b13e4f 100644
--- a/gfx.mk
+++ b/gfx.mk
@@ -1,71 +1,71 @@
-# This file is subject to the terms of the GFX License. If a copy of
-# the license was not distributed with this file, you can obtain one at:
-#
-# http://ugfx.io/license.html
-
-GFXINC += $(GFXLIB)
-
-ifeq ($(GFXSINGLEMAKE),yes)
- GFXSRC += $(GFXLIB)/src/gfx_mk.c
-else
- GFXSRC += $(GFXLIB)/src/gfx.c
- include $(GFXLIB)/src/gos/gos.mk
- include $(GFXLIB)/src/gdriver/gdriver.mk
- include $(GFXLIB)/src/gqueue/gqueue.mk
- include $(GFXLIB)/src/gdisp/gdisp.mk
- include $(GFXLIB)/src/gevent/gevent.mk
- include $(GFXLIB)/src/gtimer/gtimer.mk
- include $(GFXLIB)/src/gwin/gwin.mk
- include $(GFXLIB)/src/ginput/ginput.mk
- include $(GFXLIB)/src/gadc/gadc.mk
- include $(GFXLIB)/src/gaudio/gaudio.mk
- include $(GFXLIB)/src/gmisc/gmisc.mk
- include $(GFXLIB)/src/gfile/gfile.mk
- include $(GFXLIB)/src/gtrans/gtrans.mk
-endif
-
-# Include the boards and drivers
-ifneq ($(GFXBOARD),)
- include $(GFXLIB)/boards/base/$(GFXBOARD)/board.mk
-endif
-ifneq ($(GFXDRIVERS),)
- include $(patsubst %,$(GFXLIB)/drivers/%/driver.mk,$(GFXDRIVERS))
-endif
-ifneq ($(GFXDEMO),)
- include $(GFXLIB)/demos/$(GFXDEMO)/demo.mk
-endif
-
-# Include the operating system define
-ifeq ($(OPT_OS),arduino)
- GFXDEFS += GFX_USE_OS_ARDUINO=GFXON
-endif
-ifeq ($(OPT_OS),win32)
- GFXDEFS += GFX_USE_OS_WIN32=GFXON
-endif
-ifeq ($(OPT_OS),win32.chibios)
- GFXDEFS += GFX_USE_OS_CHIBIOS=GFXON
-endif
-ifeq ($(OPT_OS),win32.raw32)
- GFXDEFS += GFX_USE_OS_RAW32=GFXON
-endif
-ifeq ($(OPT_OS),linux)
- GFXDEFS += GFX_USE_OS_LINUX=GFXON
-endif
-ifeq ($(OPT_OS),osx)
- GFXDEFS += GFX_USE_OS_OSX=GFXON
-endif
-ifeq ($(OPT_OS),chibios)
- GFXDEFS += GFX_USE_OS_CHIBIOS=GFXON
-endif
-ifeq ($(OPT_OS),freertos)
- GFXDEFS += GFX_USE_OS_FREERTOS=GFXON
-endif
-ifeq ($(OPT_OS),ecos)
- GFXDEFS += GFX_USE_OS_ECOS=GFXON
-endif
-ifeq ($(OPT_OS),rawrtos)
- GFXDEFS += GFX_USE_OS_RAWRTOS=GFXON
-endif
-ifeq ($(OPT_OS),raw32)
- GFXDEFS += GFX_USE_OS_RAW32=GFXON
-endif
+# This file is subject to the terms of the GFX License. If a copy of
+# the license was not distributed with this file, you can obtain one at:
+#
+# http://ugfx.io/license.html
+
+GFXINC += $(GFXLIB)
+
+ifeq ($(GFXSINGLEMAKE),yes)
+ GFXSRC += $(GFXLIB)/src/gfx_mk.c
+else
+ GFXSRC += $(GFXLIB)/src/gfx.c
+ include $(GFXLIB)/src/gos/gos.mk
+ include $(GFXLIB)/src/gdriver/gdriver.mk
+ include $(GFXLIB)/src/gqueue/gqueue.mk
+ include $(GFXLIB)/src/gdisp/gdisp.mk
+ include $(GFXLIB)/src/gevent/gevent.mk
+ include $(GFXLIB)/src/gtimer/gtimer.mk
+ include $(GFXLIB)/src/gwin/gwin.mk
+ include $(GFXLIB)/src/ginput/ginput.mk
+ include $(GFXLIB)/src/gadc/gadc.mk
+ include $(GFXLIB)/src/gaudio/gaudio.mk
+ include $(GFXLIB)/src/gmisc/gmisc.mk
+ include $(GFXLIB)/src/gfile/gfile.mk
+ include $(GFXLIB)/src/gtrans/gtrans.mk
+endif
+
+# Include the boards and drivers
+ifneq ($(GFXBOARD),)
+ include $(GFXLIB)/boards/base/$(GFXBOARD)/board.mk
+endif
+ifneq ($(GFXDRIVERS),)
+ include $(patsubst %,$(GFXLIB)/drivers/%/driver.mk,$(GFXDRIVERS))
+endif
+ifneq ($(GFXDEMO),)
+ include $(GFXLIB)/demos/$(GFXDEMO)/demo.mk
+endif
+
+# Include the operating system define
+ifeq ($(OPT_OS),arduino)
+ GFXDEFS += GFX_USE_OS_ARDUINO=GFXON
+endif
+ifeq ($(OPT_OS),win32)
+ GFXDEFS += GFX_USE_OS_WIN32=GFXON
+endif
+ifeq ($(OPT_OS),win32.chibios)
+ GFXDEFS += GFX_USE_OS_CHIBIOS=GFXON
+endif
+ifeq ($(OPT_OS),win32.raw32)
+ GFXDEFS += GFX_USE_OS_RAW32=GFXON
+endif
+ifeq ($(OPT_OS),linux)
+ GFXDEFS += GFX_USE_OS_LINUX=GFXON
+endif
+ifeq ($(OPT_OS),osx)
+ GFXDEFS += GFX_USE_OS_OSX=GFXON
+endif
+ifeq ($(OPT_OS),chibios)
+ GFXDEFS += GFX_USE_OS_CHIBIOS=GFXON
+endif
+ifeq ($(OPT_OS),freertos)
+ GFXDEFS += GFX_USE_OS_FREERTOS=GFXON
+endif
+ifeq ($(OPT_OS),ecos)
+ GFXDEFS += GFX_USE_OS_ECOS=GFXON
+endif
+ifeq ($(OPT_OS),rawrtos)
+ GFXDEFS += GFX_USE_OS_RAWRTOS=GFXON
+endif
+ifeq ($(OPT_OS),raw32)
+ GFXDEFS += GFX_USE_OS_RAW32=GFXON
+endif
diff --git a/readme.txt b/readme.txt
index 5eb44912..a3454312 100644
--- a/readme.txt
+++ b/readme.txt
@@ -1,5 +1,5 @@
-Homepage: http://ugfx.io
-Documentation: http://wiki.ugfx.io
-API-Reference: http://api.ugfx.io
-Forum: http://community.ugfx.io
-uGFX-Studio: http://studio.ugfx.io
+Homepage: http://ugfx.io
+Documentation: http://wiki.ugfx.io
+API-Reference: http://api.ugfx.io
+Forum: http://community.ugfx.io
+uGFX-Studio: http://studio.ugfx.io
diff --git a/src/gos/gos_zephyr.h b/src/gos/gos_zephyr.h
index a1dfe778..deb7fb36 100644
--- a/src/gos/gos_zephyr.h
+++ b/src/gos/gos_zephyr.h
@@ -1,92 +1,92 @@
-/*
- * This file is subject to the terms of the GFX License. If a copy of
- * the license was not distributed with this file, you can obtain one at:
- *
- * http://ugfx.io/license.html
- */
-
-/**
- * @file src/gos/gos_zephyr.h
- * @brief GOS - Operating System Support header file for Zephyr RTOS.
- * Zephyr SDK 0.9.1
- */
-
-#ifndef _GOS_ZEPHYR_H
-#define _GOS_ZEPHYR_H
-
-#if GFX_USE_OS_ZEPHYR
-
-#include
-
-/*===========================================================================*/
-/* Type definitions */
-/*===========================================================================*/
-
-typedef s32_t gDelay;
-typedef u32_t gTicks;
-typedef u32_t gSemcount;
-typedef void gThreadreturn;
-typedef int gThreadpriority;
-
-#define GFX_THREAD_FUNCTION(fnName, param) gThreadreturn fnName(void* param, void* p2, void* p3)
-
-#define GFX_THREAD_STACK(name, sz) K_THREAD_STACK_DEFINE(name, sz)
-
-#define gfxThreadReturn(retval) return
-
-#define gDelayNone K_NO_WAIT
-#define gDelayForever K_FOREVER
-#define gSemMaxCount ((gSemcount)(((unsigned long)((gSemcount)(-1))) >> 1))
-#define gThreadpriorityLow CONFIG_NUM_PREEMPT_PRIORITIES-1
-#define gThreadpriorityNormal 1
-#define gThreadpriorityHigh 0
-
-typedef struct k_sem gSem;
-
-typedef struct k_mutex gMutex;
-
-typedef k_tid_t gThread;
-
-/*===========================================================================*/
-/* Function declarations. */
-/*===========================================================================*/
-
-#define gfxHalt(msg) do{}while(0)
-#define gfxExit() do{}while(0)
-
-// Don't forget to set CONFIG_HEAP_MEM_POOL_SIZE
-#define gfxAlloc(sz) k_malloc(sz)
-#define gfxFree(ptr) k_free(ptr)
-#define gfxRealloc(ptr, oldsz, newsz) do{}while(0)
-
-#define gfxYield() k_yield()
-#define gfxSleepMilliseconds(ms) k_sleep(ms)
-#define gfxSleepMicroseconds(us) do{}while(0)
-#define gfxMillisecondsToTicks(ms) CONFIG_SYS_CLOCK_TICKS_PER_SEC*ms/1000
-gTicks gfxSystemTicks();
-
-#define gfxSystemLock() k_sched_lock()
-#define gfxSystemUnlock() k_sched_unlock()
-
-#define gfxMutexInit(pmutex) k_mutex_init(pmutex)
-#define gfxMutexDestroy(pmutex) do{}while(0)
-#define gfxMutexEnter(pmutex) k_mutex_lock(pmutex, K_FOREVER)
-#define gfxMutexExit(pmutex) k_mutex_unlock(pmutex)
-
-#define gfxSemInit(psem, val, limit) k_sem_init(psem, val, limit)
-#define gfxSemDestroy(psem) do{}while(0)
-#define gfxSemWait(psem, ms) (k_sem_take(psem, ms) == 0) ? gTrue : gFalse
-#define gfxSemWaitI(psem) (k_sem_take(psem, K_NO_WAIT) == 0) ? gTrue : gFalse
-#define gfxSemSignal(psem) k_sem_give(psem)
-#define gfxSemSignalI(psem) k_sem_give(psem)
-#define gfxSemCounter(psem) k_sem_count_get(psem)
-#define gfxSemCounterI(psem) k_sem_count_get(psem)
-
-#define gfxThreadCreate(stackarea, stacksz, prio, fn, param)\
- k_thread_spawn(stackarea, stacksz, fn, param, NULL, NULL, prio, 0, K_NO_WAIT)
-#define gfxThreadWait(thread) 0
-#define gfxThreadMe() k_current_get()
-#define gfxThreadClose(thread) k_thread_abort(thread)
-
-#endif /* GFX_USE_OS_ZEPHYR */
-#endif /* _GOS_H */
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ * http://ugfx.io/license.html
+ */
+
+/**
+ * @file src/gos/gos_zephyr.h
+ * @brief GOS - Operating System Support header file for Zephyr RTOS.
+ * Zephyr SDK 0.9.1
+ */
+
+#ifndef _GOS_ZEPHYR_H
+#define _GOS_ZEPHYR_H
+
+#if GFX_USE_OS_ZEPHYR
+
+#include
+
+/*===========================================================================*/
+/* Type definitions */
+/*===========================================================================*/
+
+typedef s32_t gDelay;
+typedef u32_t gTicks;
+typedef u32_t gSemcount;
+typedef void gThreadreturn;
+typedef int gThreadpriority;
+
+#define GFX_THREAD_FUNCTION(fnName, param) gThreadreturn fnName(void* param, void* p2, void* p3)
+
+#define GFX_THREAD_STACK(name, sz) K_THREAD_STACK_DEFINE(name, sz)
+
+#define gfxThreadReturn(retval) return
+
+#define gDelayNone K_NO_WAIT
+#define gDelayForever K_FOREVER
+#define gSemMaxCount ((gSemcount)(((unsigned long)((gSemcount)(-1))) >> 1))
+#define gThreadpriorityLow CONFIG_NUM_PREEMPT_PRIORITIES-1
+#define gThreadpriorityNormal 1
+#define gThreadpriorityHigh 0
+
+typedef struct k_sem gSem;
+
+typedef struct k_mutex gMutex;
+
+typedef k_tid_t gThread;
+
+/*===========================================================================*/
+/* Function declarations. */
+/*===========================================================================*/
+
+#define gfxHalt(msg) do{}while(0)
+#define gfxExit() do{}while(0)
+
+// Don't forget to set CONFIG_HEAP_MEM_POOL_SIZE
+#define gfxAlloc(sz) k_malloc(sz)
+#define gfxFree(ptr) k_free(ptr)
+#define gfxRealloc(ptr, oldsz, newsz) do{}while(0)
+
+#define gfxYield() k_yield()
+#define gfxSleepMilliseconds(ms) k_sleep(ms)
+#define gfxSleepMicroseconds(us) do{}while(0)
+#define gfxMillisecondsToTicks(ms) CONFIG_SYS_CLOCK_TICKS_PER_SEC*ms/1000
+gTicks gfxSystemTicks();
+
+#define gfxSystemLock() k_sched_lock()
+#define gfxSystemUnlock() k_sched_unlock()
+
+#define gfxMutexInit(pmutex) k_mutex_init(pmutex)
+#define gfxMutexDestroy(pmutex) do{}while(0)
+#define gfxMutexEnter(pmutex) k_mutex_lock(pmutex, K_FOREVER)
+#define gfxMutexExit(pmutex) k_mutex_unlock(pmutex)
+
+#define gfxSemInit(psem, val, limit) k_sem_init(psem, val, limit)
+#define gfxSemDestroy(psem) do{}while(0)
+#define gfxSemWait(psem, ms) (k_sem_take(psem, ms) == 0) ? gTrue : gFalse
+#define gfxSemWaitI(psem) (k_sem_take(psem, K_NO_WAIT) == 0) ? gTrue : gFalse
+#define gfxSemSignal(psem) k_sem_give(psem)
+#define gfxSemSignalI(psem) k_sem_give(psem)
+#define gfxSemCounter(psem) k_sem_count_get(psem)
+#define gfxSemCounterI(psem) k_sem_count_get(psem)
+
+#define gfxThreadCreate(stackarea, stacksz, prio, fn, param)\
+ k_thread_spawn(stackarea, stacksz, fn, param, NULL, NULL, prio, 0, K_NO_WAIT)
+#define gfxThreadWait(thread) 0
+#define gfxThreadMe() k_current_get()
+#define gfxThreadClose(thread) k_thread_abort(thread)
+
+#endif /* GFX_USE_OS_ZEPHYR */
+#endif /* _GOS_H */
diff --git a/src/gwin/gwin_widget.c b/src/gwin/gwin_widget.c
index 08af9ccf..23bfb2ca 100644
--- a/src/gwin/gwin_widget.c
+++ b/src/gwin/gwin_widget.c
@@ -1,751 +1,751 @@
-/*
- * This file is subject to the terms of the GFX License. If a copy of
- * the license was not distributed with this file, you can obtain one at:
- *
- * http://ugfx.io/license.html
- */
-
-/**
- * @file src/gwin/gwin_widget.c
- * @brief GWIN sub-system widget code
- */
-
-#include "../../gfx.h"
-
-#if GFX_USE_GWIN && GWIN_NEED_WIDGET
-
-#include
-
-#include "gwin_class.h"
-
-// Our listener for events for widgets
-static GListener gl;
-
-#if (GFX_USE_GINPUT && GINPUT_NEED_KEYBOARD) || GWIN_NEED_KEYBOARD
- // Our current focus window
- static GHandle _widgetInFocus;
-#endif
-
-// Our default style - a white background theme
-const GWidgetStyle WhiteWidgetStyle = {
- HTML2COLOR(0xFFFFFF), // window background
- HTML2COLOR(0x2A8FCD), // focused
-
- // enabled color set
- {
- HTML2COLOR(0x000000), // text
- HTML2COLOR(0x404040), // edge
- HTML2COLOR(0xE0E0E0), // fill
- HTML2COLOR(0x00E000) // progress - active area
- },
-
- // disabled color set
- {
- HTML2COLOR(0xC0C0C0), // text
- HTML2COLOR(0x808080), // edge
- HTML2COLOR(0xE0E0E0), // fill
- HTML2COLOR(0xC0E0C0) // progress - active area
- },
-
- // pressed color set
- {
- HTML2COLOR(0x404040), // text
- HTML2COLOR(0x404040), // edge
- HTML2COLOR(0x808080), // fill
- HTML2COLOR(0x00E000) // progress - active area
- }
-};
-
-/* Our black style */
-const GWidgetStyle BlackWidgetStyle = {
- HTML2COLOR(0x000000), // window background
- HTML2COLOR(0x2A8FCD), // focused
-
- // enabled color set
- {
- HTML2COLOR(0xC0C0C0), // text
- HTML2COLOR(0xC0C0C0), // edge
- HTML2COLOR(0x606060), // fill
- HTML2COLOR(0x008000) // progress - active area
- },
-
- // disabled color set
- {
- HTML2COLOR(0x808080), // text
- HTML2COLOR(0x404040), // edge
- HTML2COLOR(0x404040), // fill
- HTML2COLOR(0x004000) // progress - active area
- },
-
- // pressed color set
- {
- HTML2COLOR(0xFFFFFF), // text
- HTML2COLOR(0xC0C0C0), // edge
- HTML2COLOR(0xE0E0E0), // fill
- HTML2COLOR(0x008000) // progress - active area
- }
-};
-
-static const GWidgetStyle * defaultStyle = &BlackWidgetStyle;
-
-// We use these everywhere in this file
-#define gw ((GWidgetObject *)gh)
-#define wvmt ((gwidgetVMT *)gh->vmt)
-
-// Process an event
-static void gwidgetEvent(void *param, GEvent *pe) {
- #define pme ((GEventMouse *)pe)
- #define pke ((GEventKeyboard *)pe)
- #define pte ((GEventToggle *)pe)
- #define pde ((GEventDial *)pe)
-
- #if GFX_USE_GINPUT
- #if GINPUT_NEED_MOUSE
- GHandle h;
- #endif
- #if GINPUT_NEED_MOUSE || GINPUT_NEED_TOGGLE || GINPUT_NEED_DIAL || GINPUT_NEED_KEYBOARD
- GHandle gh;
- #endif
- #if GINPUT_NEED_TOGGLE || GINPUT_NEED_DIAL
- gU16 role;
- #endif
- #endif
-
- (void) param;
-
- // Process various events
- switch (pe->type) {
-
- #if GFX_USE_GINPUT && GINPUT_NEED_MOUSE
- case GEVENT_MOUSE:
- case GEVENT_TOUCH:
- // Cycle through all windows
- for (gh = 0, h = gwinGetNextWindow(0); h; h = gwinGetNextWindow(h)) {
-
- // The window must be on this display and visible to be relevant
- if (h->display != pme->display || !(h->flags & GWIN_FLG_SYSVISIBLE))
- continue;
-
- // Is the mouse currently captured by this widget?
- if ((h->flags & (GWIN_FLG_WIDGET|GWIN_FLG_MOUSECAPTURE)) == (GWIN_FLG_WIDGET|GWIN_FLG_MOUSECAPTURE)) {
- gh = h;
- if ((pme->buttons & GMETA_MOUSE_UP)) {
- gh->flags &= ~GWIN_FLG_MOUSECAPTURE;
- if (wvmt->MouseUp)
- wvmt->MouseUp(gw, pme->x - gh->x, pme->y - gh->y);
- } else if (wvmt->MouseMove)
- wvmt->MouseMove(gw, pme->x - gh->x, pme->y - gh->y);
-
- // There is only ever one captured mouse. Prevent normal mouse processing if there is a captured mouse
- gh = 0;
-
- break;
- }
-
- // Save the highest z-order window that the mouse is over
- if (pme->x >= h->x && pme->x < h->x + h->width && pme->y >= h->y && pme->y < h->y + h->height)
- gh = h;
- }
-
- // Process any mouse down over the highest order window if it is an enabled widget
- if (gh && (gh->flags & (GWIN_FLG_WIDGET|GWIN_FLG_SYSENABLED)) == (GWIN_FLG_WIDGET|GWIN_FLG_SYSENABLED)) {
- if ((pme->buttons & GMETA_MOUSE_DOWN)) {
- gh->flags |= GWIN_FLG_MOUSECAPTURE;
-
- #if (GFX_USE_GINPUT && GINPUT_NEED_KEYBOARD) || GWIN_NEED_KEYBOARD
- // We should try and capture the focus on this window.
- // If we can't then we don't change the focus
- gwinSetFocus(gh);
- #endif
-
- if (wvmt->MouseDown)
- wvmt->MouseDown(gw, pme->x - gh->x, pme->y - gh->y);
- }
- }
- break;
- #endif
-
- #if (GFX_USE_GINPUT && GINPUT_NEED_KEYBOARD) || GWIN_NEED_KEYBOARD
- case GEVENT_KEYBOARD:
- // If Tab key pressed then set focus to next widget
- if (pke->bytecount == 1 && pke->c[0] == GKEY_TAB) {
- if (!(pke->keystate & GKEYSTATE_KEYUP))
- _gwinMoveFocus();
- break;
- }
-
- // Otherwise, send keyboard events only to widget in focus
- if (_widgetInFocus)
- ((gwidgetVMT*)_widgetInFocus->vmt)->KeyboardEvent((GWidgetObject*)_widgetInFocus, pke);
- break;
- #endif
-
- #if GFX_USE_GINPUT && GINPUT_NEED_TOGGLE
- case GEVENT_TOGGLE:
- // Cycle through all windows
- for(gh = gwinGetNextWindow(0); gh; gh = gwinGetNextWindow(gh)) {
-
- // check if it a widget that is enabled and visible
- if ((gh->flags & (GWIN_FLG_WIDGET|GWIN_FLG_SYSENABLED|GWIN_FLG_SYSVISIBLE)) != (GWIN_FLG_WIDGET|GWIN_FLG_SYSENABLED|GWIN_FLG_SYSVISIBLE))
- continue;
-
- for(role = 0; role < wvmt->toggleroles; role++) {
- if (wvmt->ToggleGet(gw, role) == pte->instance) {
- if (pte->on) {
- if (wvmt->ToggleOn)
- wvmt->ToggleOn(gw, role);
- } else {
- if (wvmt->ToggleOff)
- wvmt->ToggleOff(gw, role);
- }
- }
- }
- }
- break;
- #endif
-
- #if GFX_USE_GINPUT && GINPUT_NEED_DIAL
- case GEVENT_DIAL:
- // Cycle through all windows
- for(gh = gwinGetNextWindow(0); gh; gh = gwinGetNextWindow(gh)) {
-
- // check if it a widget that is enabled and visible
- if ((gh->flags & (GWIN_FLG_WIDGET|GWIN_FLG_SYSENABLED|GWIN_FLG_SYSVISIBLE)) != (GWIN_FLG_WIDGET|GWIN_FLG_SYSENABLED|GWIN_FLG_SYSVISIBLE))
- continue;
-
- for(role = 0; role < wvmt->dialroles; role++) {
- if (wvmt->DialGet(gw, role) == pte->instance) {
- if (wvmt->DialMove)
- wvmt->DialMove(gw, role, pde->value, pde->maxvalue);
- }
- }
- }
- break;
- #endif
-
- default:
- break;
- }
-
- #undef pme
- #undef pte
- #undef pke
- #undef pde
-}
-
-#if (GFX_USE_GINPUT && GINPUT_NEED_KEYBOARD) || GWIN_NEED_KEYBOARD
- GHandle gwinGetFocus(void) {
- return _widgetInFocus;
- }
-
- gBool gwinSetFocus(GHandle gh) {
- GHandle oldFocus;
-
- // Do we already have the focus?
- if (gh == _widgetInFocus)
- return gTrue;
-
- // The new window must be NULLL or a visible enabled widget with a keyboard handler
- if (!gh || ((gh->flags & (GWIN_FLG_WIDGET|GWIN_FLG_ENABLED|GWIN_FLG_SYSENABLED|GWIN_FLG_VISIBLE|GWIN_FLG_SYSVISIBLE)) == (GWIN_FLG_WIDGET|GWIN_FLG_ENABLED|GWIN_FLG_SYSENABLED|GWIN_FLG_VISIBLE|GWIN_FLG_SYSVISIBLE)
- && ((gwidgetVMT*)gh->vmt)->KeyboardEvent)) {
- // Move the current focus
- oldFocus = _widgetInFocus;
- _widgetInFocus = gh;
- if (oldFocus) _gwinUpdate(oldFocus);
- if (gh) _gwinUpdate(gh);
- return gTrue;
- }
- return gFalse;
- }
-
- void _gwinMoveFocus(void) {
- GHandle gh;
- gBool looponce;
-
- // Find a new focus window (one may or may not exist).
- looponce = gFalse;
- for(gh = gwinGetNextWindow(_widgetInFocus); ; gh = gwinGetNextWindow(gh)) {
- if (!gh && !looponce) {
- looponce = gTrue;
- gh = gwinGetNextWindow(0);
- }
- if (gwinSetFocus(gh))
- break;
- }
- }
-
- void _gwinFixFocus(GHandle gh) {
- GHandle oldFocus;
-
- if ((gh->flags & (GWIN_FLG_WIDGET|GWIN_FLG_ENABLED|GWIN_FLG_SYSENABLED|GWIN_FLG_VISIBLE|GWIN_FLG_SYSVISIBLE)) == (GWIN_FLG_WIDGET|GWIN_FLG_ENABLED|GWIN_FLG_SYSENABLED|GWIN_FLG_VISIBLE|GWIN_FLG_SYSVISIBLE)
- && ((gwidgetVMT*)gh->vmt)->KeyboardEvent) {
-
- // We are a candidate to be able to claim the focus
-
- // Claim the focus if no-one else has
- if (!_widgetInFocus)
- _widgetInFocus = gh;
-
- return;
- }
-
- // We have lost any right to the focus
-
- // Did we have the focus
- if (gh != _widgetInFocus)
- return;
-
- // We did - we need to find a new focus window
- oldFocus = _widgetInFocus;
- for(gh = gwinGetNextWindow(oldFocus); gh && gh != oldFocus; gh = gwinGetNextWindow(gh)) {
-
- // Must be a visible enabled widget with a keyboard handler
- if ((gh->flags & (GWIN_FLG_WIDGET|GWIN_FLG_ENABLED|GWIN_FLG_SYSENABLED|GWIN_FLG_VISIBLE|GWIN_FLG_SYSVISIBLE)) == (GWIN_FLG_WIDGET|GWIN_FLG_ENABLED|GWIN_FLG_SYSENABLED|GWIN_FLG_VISIBLE|GWIN_FLG_SYSVISIBLE)
- && ((gwidgetVMT*)gh->vmt)->KeyboardEvent) {
-
- // Grab the focus for the new window
- _widgetInFocus = gh;
-
- // This new window still needs to be marked for redraw (but don't actually do it yet).
- gh->flags |= GWIN_FLG_NEEDREDRAW;
- // RedrawPending |= DOREDRAW_VISIBLES; - FIX LATER
- return;
- }
- }
-
- // No-one has the right to the focus
- _widgetInFocus = 0;
- }
-
- void _gwidgetDrawFocusRect(GWidgetObject *gx, gCoord x, gCoord y, gCoord cx, gCoord cy) {
- gCoord i;
-
- // Don't do anything if we don't have the focus
- if (&gx->g != _widgetInFocus)
- return;
-
- // Use the very simplest possible focus rectangle for now
- for (i = 0; i < GWIN_FOCUS_HIGHLIGHT_WIDTH; i++) {
- gdispGDrawBox(gx->g.display, gx->g.x+x+i, gx->g.y+y+i, cx-2*i, cy-2*i, gx->pstyle->focus);
- }
- }
-
- #if GDISP_NEED_CIRCLE
- void _gwidgetDrawFocusCircle(GWidgetObject *gx, gCoord radius) {
- gCoord i;
-
- // Don't do anything if we don't have the focus
- if (&gx->g != _widgetInFocus)
- return;
-
- for (i = 0; i < GWIN_FOCUS_HIGHLIGHT_WIDTH; i++) {
- gdispGDrawCircle(gx->g.display, gx->g.x + radius, gx->g.y + radius, radius + i, gx->pstyle->focus);
- }
- }
- #endif
-#endif
-
-#if GFX_USE_GINPUT && GINPUT_NEED_TOGGLE
- static GHandle FindToggleUser(gU16 instance) {
- GHandle gh;
- gU16 role;
-
- for(gh = gwinGetNextWindow(0); gh; gh = gwinGetNextWindow(gh)) {
- if (!(gh->flags & GWIN_FLG_WIDGET)) // check if it a widget
- continue;
-
- for(role = 0; role < wvmt->toggleroles; role++) {
- if (wvmt->ToggleGet(gw, role) == instance)
- return gh;
- }
- }
- return 0;
- }
-#endif
-
-#if GFX_USE_GINPUT && GINPUT_NEED_DIAL
- static GHandle FindDialUser(gU16 instance) {
- GHandle gh;
- gU16 role;
-
- for(gh = gwinGetNextWindow(0); gh; gh = gwinGetNextWindow(gh)) {
- if (!(gh->flags & GWIN_FLG_WIDGET)) // check if it a widget
- continue;
-
- for(role = 0; role < wvmt->dialroles; role++) {
- if (wvmt->DialGet(gw, role) == instance)
- return gh;
- }
- }
- return 0;
- }
-#endif
-
-void _gwidgetInit(void)
-{
- geventListenerInit(&gl);
- geventRegisterCallback(&gl, gwidgetEvent, 0);
- #if GINPUT_NEED_MOUSE
- geventAttachSource(&gl, ginputGetMouse(GMOUSE_ALL_INSTANCES), GLISTEN_MOUSEMETA|GLISTEN_MOUSEDOWNMOVES);
- #endif
- #if GINPUT_NEED_KEYBOARD || GWIN_NEED_KEYBOARD
- geventAttachSource(&gl, ginputGetKeyboard(GKEYBOARD_ALL_INSTANCES), GLISTEN_KEYUP);
- #endif
-}
-
-void _gwidgetDeinit(void)
-{
- /* ToDo */
-}
-
-GHandle _gwidgetCreate(GDisplay *g, GWidgetObject *pgw, const GWidgetInit *pInit, const gwidgetVMT *vmt) {
- if (!(pgw = (GWidgetObject *)_gwindowCreate(g, &pgw->g, &pInit->g, &vmt->g, GWIN_FLG_WIDGET|GWIN_FLG_ENABLED|GWIN_FLG_SYSENABLED)))
- return 0;
-
- #if GWIN_NEED_CONTAINERS
- // This window can't be system enabled if the parent is not enabled
- if (pgw->g.parent && !(pgw->g.parent->flags & GWIN_FLG_SYSENABLED))
- pgw->g.flags &= ~GWIN_FLG_SYSENABLED;
- #endif
- pgw->text = pInit->text ? pInit->text : "";
- pgw->fnDraw = pInit->customDraw ? pInit->customDraw : vmt->DefaultDraw;
- pgw->fnParam = pInit->customParam;
- pgw->pstyle = pInit->customStyle ? pInit->customStyle : defaultStyle;
- #if GWIN_WIDGET_TAGS
- pgw->tag = pInit->tag;
- #endif
-
- return &pgw->g;
-}
-
-void _gwidgetDestroy(GHandle gh) {
- #if GFX_USE_GINPUT && (GINPUT_NEED_TOGGLE || GINPUT_NEED_DIAL)
- gU16 role, instance;
- #endif
-
- // Make the window is invisible so it is not eligible for focus
- gh->flags &= ~GWIN_FLG_VISIBLE;
- _gwinFixFocus(gh);
-
- // Deallocate the text (if necessary)
- if ((gh->flags & GWIN_FLG_ALLOCTXT)) {
- gh->flags &= ~GWIN_FLG_ALLOCTXT;
- gfxFree((void *)gw->text);
- }
-
- #if GFX_USE_GINPUT && GINPUT_NEED_TOGGLE
- // Detach any toggles from this object
- for(role = 0; role < wvmt->toggleroles; role++) {
- instance = wvmt->ToggleGet(gw, role);
- if (instance != GWIDGET_NO_INSTANCE) {
- wvmt->ToggleAssign(gw, role, GWIDGET_NO_INSTANCE);
- if (!FindToggleUser(instance))
- geventDetachSource(&gl, ginputGetToggle(instance));
- }
- }
- #endif
-
- #if GFX_USE_GINPUT && GINPUT_NEED_DIAL
- // Detach any dials from this object
- for(role = 0; role < wvmt->dialroles; role++) {
- instance = wvmt->DialGet(gw, role);
- if (instance != GWIDGET_NO_INSTANCE) {
- wvmt->DialAssign(gw, role, GWIDGET_NO_INSTANCE);
- if (!FindDialUser(instance))
- geventDetachSource(&gl, ginputGetDial(instance));
- }
- }
- #endif
-
- // Remove any listeners on this object.
- geventDetachSourceListeners((GSourceHandle)gh);
-}
-
-void _gwidgetRedraw(GHandle gh) {
- if (!(gh->flags & GWIN_FLG_SYSVISIBLE))
- return;
-
- gw->fnDraw(gw, gw->fnParam);
-}
-
-void _gwinSendEvent(GHandle gh, GEventType type) {
- GSourceListener * psl;
- GEventGWin * pge;
-
- // Trigger a GWIN Event
- psl = 0;
- while ((psl = geventGetSourceListener(GWIDGET_SOURCE, psl))) {
- if (!(pge = (GEventGWin *)geventGetEventBuffer(psl)))
- continue;
- pge->type = type;
- pge->gwin = gh;
- #if GWIN_WIDGET_TAGS
- pge->tag = (gh->flags & GWIN_FLG_WIDGET) ? ((GWidgetObject *)gh)->tag : 0;
- #endif
- geventSendEvent(psl);
- }
-}
-
-void gwinWidgetClearInit(GWidgetInit *pwi) {
- char *p;
- unsigned len;
-
- for(p = (char *)pwi, len = sizeof(GWidgetInit); len; len--)
- *p++ = 0;
-}
-
-void gwinSetDefaultStyle(const GWidgetStyle *pstyle, gBool updateAll) {
- if (!pstyle)
- pstyle = &BlackWidgetStyle;
-
- if (updateAll) {
- GHandle gh;
-
- for(gh = gwinGetNextWindow(0); gh; gh = gwinGetNextWindow(gh)) {
- if ((gh->flags & GWIN_FLG_WIDGET) && ((GWidgetObject *)gh)->pstyle == defaultStyle)
- gwinSetStyle(gh, pstyle);
- else
- gwinRedraw(gh);
- }
- }
- gwinSetDefaultBgColor(pstyle->background);
- defaultStyle = pstyle;
-}
-
-/**
- * @brief Get the current default style.
- *
- * @api
- */
-const GWidgetStyle *gwinGetDefaultStyle(void) {
- return defaultStyle;
-}
-
-void gwinSetText(GHandle gh, const char *text, gBool useAlloc) {
- if (!(gh->flags & GWIN_FLG_WIDGET))
- return;
-
- // Dispose of the old string
- if ((gh->flags & GWIN_FLG_ALLOCTXT)) {
- gh->flags &= ~GWIN_FLG_ALLOCTXT;
- if (gw->text) {
- gfxFree((void *)gw->text);
- gw->text = "";
- }
- }
-
- // Alloc the new text if required
- if (!text || !*text)
- gw->text = "";
- else if (useAlloc) {
- char *str;
-
- if ((str = gfxAlloc(strlen(text)+1))) {
- gh->flags |= GWIN_FLG_ALLOCTXT;
- strcpy(str, text);
- }
- gw->text = (const char *)str;
- } else
- gw->text = text;
- _gwinUpdate(gh);
-}
-
-#if GFX_USE_GFILE && GFILE_NEED_PRINTG && GFILE_NEED_STRINGS
- #include
-
- void gwinPrintg(GHandle gh, const char * fmt, ...) {
- char *str;
- va_list va;
- int size;
-
- if (!(gh->flags & GWIN_FLG_WIDGET))
- return;
-
- // Dispose of the old string
- if ((gh->flags & GWIN_FLG_ALLOCTXT)) {
- gh->flags &= ~GWIN_FLG_ALLOCTXT;
- if (gw->text) {
- gfxFree((void *)gw->text);
- gw->text = "";
- }
- }
-
- // Alloc the new text
- va_start (va, fmt);
-
- size = vsnprintg(0, 0, fmt, va) + 1; //determine the buffer size required
-
- if ((str = gfxAlloc(size))) {
- gh->flags |= GWIN_FLG_ALLOCTXT;
- vsnprintg(str, size, fmt, va);
- gw->text = (const char *)str;
- } else
- gw->text = "";
-
- va_end (va);
-
- _gwinUpdate(gh);
- }
-#endif
-
-const char *gwinGetText(GHandle gh) {
- if (!(gh->flags & GWIN_FLG_WIDGET))
- return 0;
-
- return gw->text;
-}
-
-gBool gwinIsWidget(GHandle gh) {
- if (gh->flags & GWIN_FLG_WIDGET) {
- return gTrue;
- }
-
- return gFalse;
-}
-
-void gwinSetStyle(GHandle gh, const GWidgetStyle *pstyle) {
- if (!(gh->flags & GWIN_FLG_WIDGET))
- return;
-
- gw->pstyle = pstyle ? pstyle : defaultStyle;
- gh->bgcolor = gw->pstyle->background;
- gh->color = gw->pstyle->enabled.text;
-
- _gwinUpdate(gh);
-}
-
-const GWidgetStyle *gwinGetStyle(GHandle gh) {
- if (!(gh->flags & GWIN_FLG_WIDGET))
- return 0;
-
- return gw->pstyle;
-}
-
-void gwinSetCustomDraw(GHandle gh, CustomWidgetDrawFunction fn, void *param) {
- if (!(gh->flags & GWIN_FLG_WIDGET))
- return;
-
- gw->fnDraw = fn ? fn : wvmt->DefaultDraw;
- gw->fnParam = param;
- _gwinUpdate(gh);
-}
-
-gBool gwinAttachListener(GListener *pl) {
- return geventAttachSource(pl, GWIDGET_SOURCE, 0);
-}
-
-#if GFX_USE_GINPUT && GINPUT_NEED_MOUSE
- gBool DEPRECATED("This call can now be removed. Attaching the mouse to GWIN is now automatic.") gwinAttachMouse(gU16 instance) {
- // This is now a NULL event because we automatically attach to all mice in the system.
- (void) instance;
- return gTrue;
- }
-#endif
-
-#if GFX_USE_GINPUT && GINPUT_NEED_TOGGLE
- gBool gwinAttachToggle(GHandle gh, gU16 role, gU16 instance) {
- GSourceHandle gsh;
- gU16 oi;
-
- // Is this a widget
- if (!(gh->flags & GWIN_FLG_WIDGET))
- return gFalse;
-
- // Is the role valid
- if (role >= wvmt->toggleroles)
- return gFalse;
-
- // Is this a valid device
- if (!(gsh = ginputGetToggle(instance)))
- return gFalse;
-
- // Is this already done?
- oi = wvmt->ToggleGet(gw, role);
- if (instance == oi)
- return gTrue;
-
- // Remove the old instance
- if (oi != GWIDGET_NO_INSTANCE) {
- wvmt->ToggleAssign(gw, role, GWIDGET_NO_INSTANCE);
- if (!FindToggleUser(oi))
- geventDetachSource(&gl, ginputGetToggle(oi));
- }
-
- // Assign the new
- wvmt->ToggleAssign(gw, role, instance);
- return geventAttachSource(&gl, gsh, GLISTEN_TOGGLE_ON|GLISTEN_TOGGLE_OFF);
- }
-
- gBool gwinDetachToggle(GHandle gh, gU16 role) {
- gU16 oi;
-
- // Is this a widget
- if (!(gh->flags & GWIN_FLG_WIDGET))
- return gFalse;
-
- // Is the role valid
- if (role >= ((gwidgetVMT *)gh->vmt)->toggleroles)
- return gFalse;
-
- oi = ((gwidgetVMT *)gh->vmt)->ToggleGet(gw, role);
-
- // Remove the instance
- if (oi != GWIDGET_NO_INSTANCE) {
- ((gwidgetVMT *)gh->vmt)->ToggleAssign(gw, role, GWIDGET_NO_INSTANCE);
- if (!FindToggleUser(oi))
- geventDetachSource(&gl, ginputGetToggle(oi));
- }
- return gTrue;
- }
-
-#endif
-
-#if GFX_USE_GINPUT && GINPUT_NEED_DIAL
- gBool gwinAttachDial(GHandle gh, gU16 role, gU16 instance) {
- GSourceHandle gsh;
- gU16 oi;
-
- if (!(gh->flags & GWIN_FLG_WIDGET))
- return gFalse;
-
- // Is the role valid
- if (role >= wvmt->dialroles)
- return gFalse;
-
- // Is this a valid device
- if (!(gsh = ginputGetDial(instance)))
- return gFalse;
-
- // Is this already done?
- oi = wvmt->DialGet(gw, role);
- if (instance == oi)
- return gTrue;
-
- // Remove the old instance
- if (oi != GWIDGET_NO_INSTANCE) {
- wvmt->DialAssign(gw, role, GWIDGET_NO_INSTANCE);
- if (!FindDialUser(oi))
- geventDetachSource(&gl, ginputGetDial(oi));
- }
-
- // Assign the new
- wvmt->DialAssign(gw, role, instance);
- return geventAttachSource(&gl, gsh, 0);
- }
-#endif
-
-#if GWIN_WIDGET_TAGS
- void gwinSetTag(GHandle gh, WidgetTag tag) {
- if ((gh->flags & GWIN_FLG_WIDGET))
- gw->tag = tag;
- }
-
- WidgetTag gwinGetTag(GHandle gh) {
- return ((gh->flags & GWIN_FLG_WIDGET)) ? gw->tag : 0;
- }
-#endif
-
-#undef gw
-#undef wvmt
-
-#endif /* GFX_USE_GWIN && GWIN_NEED_WIDGET */
+/*
+ * This file is subject to the terms of the GFX License. If a copy of
+ * the license was not distributed with this file, you can obtain one at:
+ *
+ * http://ugfx.io/license.html
+ */
+
+/**
+ * @file src/gwin/gwin_widget.c
+ * @brief GWIN sub-system widget code
+ */
+
+#include "../../gfx.h"
+
+#if GFX_USE_GWIN && GWIN_NEED_WIDGET
+
+#include
+
+#include "gwin_class.h"
+
+// Our listener for events for widgets
+static GListener gl;
+
+#if (GFX_USE_GINPUT && GINPUT_NEED_KEYBOARD) || GWIN_NEED_KEYBOARD
+ // Our current focus window
+ static GHandle _widgetInFocus;
+#endif
+
+// Our default style - a white background theme
+const GWidgetStyle WhiteWidgetStyle = {
+ HTML2COLOR(0xFFFFFF), // window background
+ HTML2COLOR(0x2A8FCD), // focused
+
+ // enabled color set
+ {
+ HTML2COLOR(0x000000), // text
+ HTML2COLOR(0x404040), // edge
+ HTML2COLOR(0xE0E0E0), // fill
+ HTML2COLOR(0x00E000) // progress - active area
+ },
+
+ // disabled color set
+ {
+ HTML2COLOR(0xC0C0C0), // text
+ HTML2COLOR(0x808080), // edge
+ HTML2COLOR(0xE0E0E0), // fill
+ HTML2COLOR(0xC0E0C0) // progress - active area
+ },
+
+ // pressed color set
+ {
+ HTML2COLOR(0x404040), // text
+ HTML2COLOR(0x404040), // edge
+ HTML2COLOR(0x808080), // fill
+ HTML2COLOR(0x00E000) // progress - active area
+ }
+};
+
+/* Our black style */
+const GWidgetStyle BlackWidgetStyle = {
+ HTML2COLOR(0x000000), // window background
+ HTML2COLOR(0x2A8FCD), // focused
+
+ // enabled color set
+ {
+ HTML2COLOR(0xC0C0C0), // text
+ HTML2COLOR(0xC0C0C0), // edge
+ HTML2COLOR(0x606060), // fill
+ HTML2COLOR(0x008000) // progress - active area
+ },
+
+ // disabled color set
+ {
+ HTML2COLOR(0x808080), // text
+ HTML2COLOR(0x404040), // edge
+ HTML2COLOR(0x404040), // fill
+ HTML2COLOR(0x004000) // progress - active area
+ },
+
+ // pressed color set
+ {
+ HTML2COLOR(0xFFFFFF), // text
+ HTML2COLOR(0xC0C0C0), // edge
+ HTML2COLOR(0xE0E0E0), // fill
+ HTML2COLOR(0x008000) // progress - active area
+ }
+};
+
+static const GWidgetStyle * defaultStyle = &BlackWidgetStyle;
+
+// We use these everywhere in this file
+#define gw ((GWidgetObject *)gh)
+#define wvmt ((gwidgetVMT *)gh->vmt)
+
+// Process an event
+static void gwidgetEvent(void *param, GEvent *pe) {
+ #define pme ((GEventMouse *)pe)
+ #define pke ((GEventKeyboard *)pe)
+ #define pte ((GEventToggle *)pe)
+ #define pde ((GEventDial *)pe)
+
+ #if GFX_USE_GINPUT
+ #if GINPUT_NEED_MOUSE
+ GHandle h;
+ #endif
+ #if GINPUT_NEED_MOUSE || GINPUT_NEED_TOGGLE || GINPUT_NEED_DIAL || GINPUT_NEED_KEYBOARD
+ GHandle gh;
+ #endif
+ #if GINPUT_NEED_TOGGLE || GINPUT_NEED_DIAL
+ gU16 role;
+ #endif
+ #endif
+
+ (void) param;
+
+ // Process various events
+ switch (pe->type) {
+
+ #if GFX_USE_GINPUT && GINPUT_NEED_MOUSE
+ case GEVENT_MOUSE:
+ case GEVENT_TOUCH:
+ // Cycle through all windows
+ for (gh = 0, h = gwinGetNextWindow(0); h; h = gwinGetNextWindow(h)) {
+
+ // The window must be on this display and visible to be relevant
+ if (h->display != pme->display || !(h->flags & GWIN_FLG_SYSVISIBLE))
+ continue;
+
+ // Is the mouse currently captured by this widget?
+ if ((h->flags & (GWIN_FLG_WIDGET|GWIN_FLG_MOUSECAPTURE)) == (GWIN_FLG_WIDGET|GWIN_FLG_MOUSECAPTURE)) {
+ gh = h;
+ if ((pme->buttons & GMETA_MOUSE_UP)) {
+ gh->flags &= ~GWIN_FLG_MOUSECAPTURE;
+ if (wvmt->MouseUp)
+ wvmt->MouseUp(gw, pme->x - gh->x, pme->y - gh->y);
+ } else if (wvmt->MouseMove)
+ wvmt->MouseMove(gw, pme->x - gh->x, pme->y - gh->y);
+
+ // There is only ever one captured mouse. Prevent normal mouse processing if there is a captured mouse
+ gh = 0;
+
+ break;
+ }
+
+ // Save the highest z-order window that the mouse is over
+ if (pme->x >= h->x && pme->x < h->x + h->width && pme->y >= h->y && pme->y < h->y + h->height)
+ gh = h;
+ }
+
+ // Process any mouse down over the highest order window if it is an enabled widget
+ if (gh && (gh->flags & (GWIN_FLG_WIDGET|GWIN_FLG_SYSENABLED)) == (GWIN_FLG_WIDGET|GWIN_FLG_SYSENABLED)) {
+ if ((pme->buttons & GMETA_MOUSE_DOWN)) {
+ gh->flags |= GWIN_FLG_MOUSECAPTURE;
+
+ #if (GFX_USE_GINPUT && GINPUT_NEED_KEYBOARD) || GWIN_NEED_KEYBOARD
+ // We should try and capture the focus on this window.
+ // If we can't then we don't change the focus
+ gwinSetFocus(gh);
+ #endif
+
+ if (wvmt->MouseDown)
+ wvmt->MouseDown(gw, pme->x - gh->x, pme->y - gh->y);
+ }
+ }
+ break;
+ #endif
+
+ #if (GFX_USE_GINPUT && GINPUT_NEED_KEYBOARD) || GWIN_NEED_KEYBOARD
+ case GEVENT_KEYBOARD:
+ // If Tab key pressed then set focus to next widget
+ if (pke->bytecount == 1 && pke->c[0] == GKEY_TAB) {
+ if (!(pke->keystate & GKEYSTATE_KEYUP))
+ _gwinMoveFocus();
+ break;
+ }
+
+ // Otherwise, send keyboard events only to widget in focus
+ if (_widgetInFocus)
+ ((gwidgetVMT*)_widgetInFocus->vmt)->KeyboardEvent((GWidgetObject*)_widgetInFocus, pke);
+ break;
+ #endif
+
+ #if GFX_USE_GINPUT && GINPUT_NEED_TOGGLE
+ case GEVENT_TOGGLE:
+ // Cycle through all windows
+ for(gh = gwinGetNextWindow(0); gh; gh = gwinGetNextWindow(gh)) {
+
+ // check if it a widget that is enabled and visible
+ if ((gh->flags & (GWIN_FLG_WIDGET|GWIN_FLG_SYSENABLED|GWIN_FLG_SYSVISIBLE)) != (GWIN_FLG_WIDGET|GWIN_FLG_SYSENABLED|GWIN_FLG_SYSVISIBLE))
+ continue;
+
+ for(role = 0; role < wvmt->toggleroles; role++) {
+ if (wvmt->ToggleGet(gw, role) == pte->instance) {
+ if (pte->on) {
+ if (wvmt->ToggleOn)
+ wvmt->ToggleOn(gw, role);
+ } else {
+ if (wvmt->ToggleOff)
+ wvmt->ToggleOff(gw, role);
+ }
+ }
+ }
+ }
+ break;
+ #endif
+
+ #if GFX_USE_GINPUT && GINPUT_NEED_DIAL
+ case GEVENT_DIAL:
+ // Cycle through all windows
+ for(gh = gwinGetNextWindow(0); gh; gh = gwinGetNextWindow(gh)) {
+
+ // check if it a widget that is enabled and visible
+ if ((gh->flags & (GWIN_FLG_WIDGET|GWIN_FLG_SYSENABLED|GWIN_FLG_SYSVISIBLE)) != (GWIN_FLG_WIDGET|GWIN_FLG_SYSENABLED|GWIN_FLG_SYSVISIBLE))
+ continue;
+
+ for(role = 0; role < wvmt->dialroles; role++) {
+ if (wvmt->DialGet(gw, role) == pte->instance) {
+ if (wvmt->DialMove)
+ wvmt->DialMove(gw, role, pde->value, pde->maxvalue);
+ }
+ }
+ }
+ break;
+ #endif
+
+ default:
+ break;
+ }
+
+ #undef pme
+ #undef pte
+ #undef pke
+ #undef pde
+}
+
+#if (GFX_USE_GINPUT && GINPUT_NEED_KEYBOARD) || GWIN_NEED_KEYBOARD
+ GHandle gwinGetFocus(void) {
+ return _widgetInFocus;
+ }
+
+ gBool gwinSetFocus(GHandle gh) {
+ GHandle oldFocus;
+
+ // Do we already have the focus?
+ if (gh == _widgetInFocus)
+ return gTrue;
+
+ // The new window must be NULLL or a visible enabled widget with a keyboard handler
+ if (!gh || ((gh->flags & (GWIN_FLG_WIDGET|GWIN_FLG_ENABLED|GWIN_FLG_SYSENABLED|GWIN_FLG_VISIBLE|GWIN_FLG_SYSVISIBLE)) == (GWIN_FLG_WIDGET|GWIN_FLG_ENABLED|GWIN_FLG_SYSENABLED|GWIN_FLG_VISIBLE|GWIN_FLG_SYSVISIBLE)
+ && ((gwidgetVMT*)gh->vmt)->KeyboardEvent)) {
+ // Move the current focus
+ oldFocus = _widgetInFocus;
+ _widgetInFocus = gh;
+ if (oldFocus) _gwinUpdate(oldFocus);
+ if (gh) _gwinUpdate(gh);
+ return gTrue;
+ }
+ return gFalse;
+ }
+
+ void _gwinMoveFocus(void) {
+ GHandle gh;
+ gBool looponce;
+
+ // Find a new focus window (one may or may not exist).
+ looponce = gFalse;
+ for(gh = gwinGetNextWindow(_widgetInFocus); ; gh = gwinGetNextWindow(gh)) {
+ if (!gh && !looponce) {
+ looponce = gTrue;
+ gh = gwinGetNextWindow(0);
+ }
+ if (gwinSetFocus(gh))
+ break;
+ }
+ }
+
+ void _gwinFixFocus(GHandle gh) {
+ GHandle oldFocus;
+
+ if ((gh->flags & (GWIN_FLG_WIDGET|GWIN_FLG_ENABLED|GWIN_FLG_SYSENABLED|GWIN_FLG_VISIBLE|GWIN_FLG_SYSVISIBLE)) == (GWIN_FLG_WIDGET|GWIN_FLG_ENABLED|GWIN_FLG_SYSENABLED|GWIN_FLG_VISIBLE|GWIN_FLG_SYSVISIBLE)
+ && ((gwidgetVMT*)gh->vmt)->KeyboardEvent) {
+
+ // We are a candidate to be able to claim the focus
+
+ // Claim the focus if no-one else has
+ if (!_widgetInFocus)
+ _widgetInFocus = gh;
+
+ return;
+ }
+
+ // We have lost any right to the focus
+
+ // Did we have the focus
+ if (gh != _widgetInFocus)
+ return;
+
+ // We did - we need to find a new focus window
+ oldFocus = _widgetInFocus;
+ for(gh = gwinGetNextWindow(oldFocus); gh && gh != oldFocus; gh = gwinGetNextWindow(gh)) {
+
+ // Must be a visible enabled widget with a keyboard handler
+ if ((gh->flags & (GWIN_FLG_WIDGET|GWIN_FLG_ENABLED|GWIN_FLG_SYSENABLED|GWIN_FLG_VISIBLE|GWIN_FLG_SYSVISIBLE)) == (GWIN_FLG_WIDGET|GWIN_FLG_ENABLED|GWIN_FLG_SYSENABLED|GWIN_FLG_VISIBLE|GWIN_FLG_SYSVISIBLE)
+ && ((gwidgetVMT*)gh->vmt)->KeyboardEvent) {
+
+ // Grab the focus for the new window
+ _widgetInFocus = gh;
+
+ // This new window still needs to be marked for redraw (but don't actually do it yet).
+ gh->flags |= GWIN_FLG_NEEDREDRAW;
+ // RedrawPending |= DOREDRAW_VISIBLES; - FIX LATER
+ return;
+ }
+ }
+
+ // No-one has the right to the focus
+ _widgetInFocus = 0;
+ }
+
+ void _gwidgetDrawFocusRect(GWidgetObject *gx, gCoord x, gCoord y, gCoord cx, gCoord cy) {
+ gCoord i;
+
+ // Don't do anything if we don't have the focus
+ if (&gx->g != _widgetInFocus)
+ return;
+
+ // Use the very simplest possible focus rectangle for now
+ for (i = 0; i < GWIN_FOCUS_HIGHLIGHT_WIDTH; i++) {
+ gdispGDrawBox(gx->g.display, gx->g.x+x+i, gx->g.y+y+i, cx-2*i, cy-2*i, gx->pstyle->focus);
+ }
+ }
+
+ #if GDISP_NEED_CIRCLE
+ void _gwidgetDrawFocusCircle(GWidgetObject *gx, gCoord radius) {
+ gCoord i;
+
+ // Don't do anything if we don't have the focus
+ if (&gx->g != _widgetInFocus)
+ return;
+
+ for (i = 0; i < GWIN_FOCUS_HIGHLIGHT_WIDTH; i++) {
+ gdispGDrawCircle(gx->g.display, gx->g.x + radius, gx->g.y + radius, radius + i, gx->pstyle->focus);
+ }
+ }
+ #endif
+#endif
+
+#if GFX_USE_GINPUT && GINPUT_NEED_TOGGLE
+ static GHandle FindToggleUser(gU16 instance) {
+ GHandle gh;
+ gU16 role;
+
+ for(gh = gwinGetNextWindow(0); gh; gh = gwinGetNextWindow(gh)) {
+ if (!(gh->flags & GWIN_FLG_WIDGET)) // check if it a widget
+ continue;
+
+ for(role = 0; role < wvmt->toggleroles; role++) {
+ if (wvmt->ToggleGet(gw, role) == instance)
+ return gh;
+ }
+ }
+ return 0;
+ }
+#endif
+
+#if GFX_USE_GINPUT && GINPUT_NEED_DIAL
+ static GHandle FindDialUser(gU16 instance) {
+ GHandle gh;
+ gU16 role;
+
+ for(gh = gwinGetNextWindow(0); gh; gh = gwinGetNextWindow(gh)) {
+ if (!(gh->flags & GWIN_FLG_WIDGET)) // check if it a widget
+ continue;
+
+ for(role = 0; role < wvmt->dialroles; role++) {
+ if (wvmt->DialGet(gw, role) == instance)
+ return gh;
+ }
+ }
+ return 0;
+ }
+#endif
+
+void _gwidgetInit(void)
+{
+ geventListenerInit(&gl);
+ geventRegisterCallback(&gl, gwidgetEvent, 0);
+ #if GINPUT_NEED_MOUSE
+ geventAttachSource(&gl, ginputGetMouse(GMOUSE_ALL_INSTANCES), GLISTEN_MOUSEMETA|GLISTEN_MOUSEDOWNMOVES);
+ #endif
+ #if GINPUT_NEED_KEYBOARD || GWIN_NEED_KEYBOARD
+ geventAttachSource(&gl, ginputGetKeyboard(GKEYBOARD_ALL_INSTANCES), GLISTEN_KEYUP);
+ #endif
+}
+
+void _gwidgetDeinit(void)
+{
+ /* ToDo */
+}
+
+GHandle _gwidgetCreate(GDisplay *g, GWidgetObject *pgw, const GWidgetInit *pInit, const gwidgetVMT *vmt) {
+ if (!(pgw = (GWidgetObject *)_gwindowCreate(g, &pgw->g, &pInit->g, &vmt->g, GWIN_FLG_WIDGET|GWIN_FLG_ENABLED|GWIN_FLG_SYSENABLED)))
+ return 0;
+
+ #if GWIN_NEED_CONTAINERS
+ // This window can't be system enabled if the parent is not enabled
+ if (pgw->g.parent && !(pgw->g.parent->flags & GWIN_FLG_SYSENABLED))
+ pgw->g.flags &= ~GWIN_FLG_SYSENABLED;
+ #endif
+ pgw->text = pInit->text ? pInit->text : "";
+ pgw->fnDraw = pInit->customDraw ? pInit->customDraw : vmt->DefaultDraw;
+ pgw->fnParam = pInit->customParam;
+ pgw->pstyle = pInit->customStyle ? pInit->customStyle : defaultStyle;
+ #if GWIN_WIDGET_TAGS
+ pgw->tag = pInit->tag;
+ #endif
+
+ return &pgw->g;
+}
+
+void _gwidgetDestroy(GHandle gh) {
+ #if GFX_USE_GINPUT && (GINPUT_NEED_TOGGLE || GINPUT_NEED_DIAL)
+ gU16 role, instance;
+ #endif
+
+ // Make the window is invisible so it is not eligible for focus
+ gh->flags &= ~GWIN_FLG_VISIBLE;
+ _gwinFixFocus(gh);
+
+ // Deallocate the text (if necessary)
+ if ((gh->flags & GWIN_FLG_ALLOCTXT)) {
+ gh->flags &= ~GWIN_FLG_ALLOCTXT;
+ gfxFree((void *)gw->text);
+ }
+
+ #if GFX_USE_GINPUT && GINPUT_NEED_TOGGLE
+ // Detach any toggles from this object
+ for(role = 0; role < wvmt->toggleroles; role++) {
+ instance = wvmt->ToggleGet(gw, role);
+ if (instance != GWIDGET_NO_INSTANCE) {
+ wvmt->ToggleAssign(gw, role, GWIDGET_NO_INSTANCE);
+ if (!FindToggleUser(instance))
+ geventDetachSource(&gl, ginputGetToggle(instance));
+ }
+ }
+ #endif
+
+ #if GFX_USE_GINPUT && GINPUT_NEED_DIAL
+ // Detach any dials from this object
+ for(role = 0; role < wvmt->dialroles; role++) {
+ instance = wvmt->DialGet(gw, role);
+ if (instance != GWIDGET_NO_INSTANCE) {
+ wvmt->DialAssign(gw, role, GWIDGET_NO_INSTANCE);
+ if (!FindDialUser(instance))
+ geventDetachSource(&gl, ginputGetDial(instance));
+ }
+ }
+ #endif
+
+ // Remove any listeners on this object.
+ geventDetachSourceListeners((GSourceHandle)gh);
+}
+
+void _gwidgetRedraw(GHandle gh) {
+ if (!(gh->flags & GWIN_FLG_SYSVISIBLE))
+ return;
+
+ gw->fnDraw(gw, gw->fnParam);
+}
+
+void _gwinSendEvent(GHandle gh, GEventType type) {
+ GSourceListener * psl;
+ GEventGWin * pge;
+
+ // Trigger a GWIN Event
+ psl = 0;
+ while ((psl = geventGetSourceListener(GWIDGET_SOURCE, psl))) {
+ if (!(pge = (GEventGWin *)geventGetEventBuffer(psl)))
+ continue;
+ pge->type = type;
+ pge->gwin = gh;
+ #if GWIN_WIDGET_TAGS
+ pge->tag = (gh->flags & GWIN_FLG_WIDGET) ? ((GWidgetObject *)gh)->tag : 0;
+ #endif
+ geventSendEvent(psl);
+ }
+}
+
+void gwinWidgetClearInit(GWidgetInit *pwi) {
+ char *p;
+ unsigned len;
+
+ for(p = (char *)pwi, len = sizeof(GWidgetInit); len; len--)
+ *p++ = 0;
+}
+
+void gwinSetDefaultStyle(const GWidgetStyle *pstyle, gBool updateAll) {
+ if (!pstyle)
+ pstyle = &BlackWidgetStyle;
+
+ if (updateAll) {
+ GHandle gh;
+
+ for(gh = gwinGetNextWindow(0); gh; gh = gwinGetNextWindow(gh)) {
+ if ((gh->flags & GWIN_FLG_WIDGET) && ((GWidgetObject *)gh)->pstyle == defaultStyle)
+ gwinSetStyle(gh, pstyle);
+ else
+ gwinRedraw(gh);
+ }
+ }
+ gwinSetDefaultBgColor(pstyle->background);
+ defaultStyle = pstyle;
+}
+
+/**
+ * @brief Get the current default style.
+ *
+ * @api
+ */
+const GWidgetStyle *gwinGetDefaultStyle(void) {
+ return defaultStyle;
+}
+
+void gwinSetText(GHandle gh, const char *text, gBool useAlloc) {
+ if (!(gh->flags & GWIN_FLG_WIDGET))
+ return;
+
+ // Dispose of the old string
+ if ((gh->flags & GWIN_FLG_ALLOCTXT)) {
+ gh->flags &= ~GWIN_FLG_ALLOCTXT;
+ if (gw->text) {
+ gfxFree((void *)gw->text);
+ gw->text = "";
+ }
+ }
+
+ // Alloc the new text if required
+ if (!text || !*text)
+ gw->text = "";
+ else if (useAlloc) {
+ char *str;
+
+ if ((str = gfxAlloc(strlen(text)+1))) {
+ gh->flags |= GWIN_FLG_ALLOCTXT;
+ strcpy(str, text);
+ }
+ gw->text = (const char *)str;
+ } else
+ gw->text = text;
+ _gwinUpdate(gh);
+}
+
+#if GFX_USE_GFILE && GFILE_NEED_PRINTG && GFILE_NEED_STRINGS
+ #include
+
+ void gwinPrintg(GHandle gh, const char * fmt, ...) {
+ char *str;
+ va_list va;
+ int size;
+
+ if (!(gh->flags & GWIN_FLG_WIDGET))
+ return;
+
+ // Dispose of the old string
+ if ((gh->flags & GWIN_FLG_ALLOCTXT)) {
+ gh->flags &= ~GWIN_FLG_ALLOCTXT;
+ if (gw->text) {
+ gfxFree((void *)gw->text);
+ gw->text = "";
+ }
+ }
+
+ // Alloc the new text
+ va_start (va, fmt);
+
+ size = vsnprintg(0, 0, fmt, va) + 1; //determine the buffer size required
+
+ if ((str = gfxAlloc(size))) {
+ gh->flags |= GWIN_FLG_ALLOCTXT;
+ vsnprintg(str, size, fmt, va);
+ gw->text = (const char *)str;
+ } else
+ gw->text = "";
+
+ va_end (va);
+
+ _gwinUpdate(gh);
+ }
+#endif
+
+const char *gwinGetText(GHandle gh) {
+ if (!(gh->flags & GWIN_FLG_WIDGET))
+ return 0;
+
+ return gw->text;
+}
+
+gBool gwinIsWidget(GHandle gh) {
+ if (gh->flags & GWIN_FLG_WIDGET) {
+ return gTrue;
+ }
+
+ return gFalse;
+}
+
+void gwinSetStyle(GHandle gh, const GWidgetStyle *pstyle) {
+ if (!(gh->flags & GWIN_FLG_WIDGET))
+ return;
+
+ gw->pstyle = pstyle ? pstyle : defaultStyle;
+ gh->bgcolor = gw->pstyle->background;
+ gh->color = gw->pstyle->enabled.text;
+
+ _gwinUpdate(gh);
+}
+
+const GWidgetStyle *gwinGetStyle(GHandle gh) {
+ if (!(gh->flags & GWIN_FLG_WIDGET))
+ return 0;
+
+ return gw->pstyle;
+}
+
+void gwinSetCustomDraw(GHandle gh, CustomWidgetDrawFunction fn, void *param) {
+ if (!(gh->flags & GWIN_FLG_WIDGET))
+ return;
+
+ gw->fnDraw = fn ? fn : wvmt->DefaultDraw;
+ gw->fnParam = param;
+ _gwinUpdate(gh);
+}
+
+gBool gwinAttachListener(GListener *pl) {
+ return geventAttachSource(pl, GWIDGET_SOURCE, 0);
+}
+
+#if GFX_USE_GINPUT && GINPUT_NEED_MOUSE
+ gBool DEPRECATED("This call can now be removed. Attaching the mouse to GWIN is now automatic.") gwinAttachMouse(gU16 instance) {
+ // This is now a NULL event because we automatically attach to all mice in the system.
+ (void) instance;
+ return gTrue;
+ }
+#endif
+
+#if GFX_USE_GINPUT && GINPUT_NEED_TOGGLE
+ gBool gwinAttachToggle(GHandle gh, gU16 role, gU16 instance) {
+ GSourceHandle gsh;
+ gU16 oi;
+
+ // Is this a widget
+ if (!(gh->flags & GWIN_FLG_WIDGET))
+ return gFalse;
+
+ // Is the role valid
+ if (role >= wvmt->toggleroles)
+ return gFalse;
+
+ // Is this a valid device
+ if (!(gsh = ginputGetToggle(instance)))
+ return gFalse;
+
+ // Is this already done?
+ oi = wvmt->ToggleGet(gw, role);
+ if (instance == oi)
+ return gTrue;
+
+ // Remove the old instance
+ if (oi != GWIDGET_NO_INSTANCE) {
+ wvmt->ToggleAssign(gw, role, GWIDGET_NO_INSTANCE);
+ if (!FindToggleUser(oi))
+ geventDetachSource(&gl, ginputGetToggle(oi));
+ }
+
+ // Assign the new
+ wvmt->ToggleAssign(gw, role, instance);
+ return geventAttachSource(&gl, gsh, GLISTEN_TOGGLE_ON|GLISTEN_TOGGLE_OFF);
+ }
+
+ gBool gwinDetachToggle(GHandle gh, gU16 role) {
+ gU16 oi;
+
+ // Is this a widget
+ if (!(gh->flags & GWIN_FLG_WIDGET))
+ return gFalse;
+
+ // Is the role valid
+ if (role >= ((gwidgetVMT *)gh->vmt)->toggleroles)
+ return gFalse;
+
+ oi = ((gwidgetVMT *)gh->vmt)->ToggleGet(gw, role);
+
+ // Remove the instance
+ if (oi != GWIDGET_NO_INSTANCE) {
+ ((gwidgetVMT *)gh->vmt)->ToggleAssign(gw, role, GWIDGET_NO_INSTANCE);
+ if (!FindToggleUser(oi))
+ geventDetachSource(&gl, ginputGetToggle(oi));
+ }
+ return gTrue;
+ }
+
+#endif
+
+#if GFX_USE_GINPUT && GINPUT_NEED_DIAL
+ gBool gwinAttachDial(GHandle gh, gU16 role, gU16 instance) {
+ GSourceHandle gsh;
+ gU16 oi;
+
+ if (!(gh->flags & GWIN_FLG_WIDGET))
+ return gFalse;
+
+ // Is the role valid
+ if (role >= wvmt->dialroles)
+ return gFalse;
+
+ // Is this a valid device
+ if (!(gsh = ginputGetDial(instance)))
+ return gFalse;
+
+ // Is this already done?
+ oi = wvmt->DialGet(gw, role);
+ if (instance == oi)
+ return gTrue;
+
+ // Remove the old instance
+ if (oi != GWIDGET_NO_INSTANCE) {
+ wvmt->DialAssign(gw, role, GWIDGET_NO_INSTANCE);
+ if (!FindDialUser(oi))
+ geventDetachSource(&gl, ginputGetDial(oi));
+ }
+
+ // Assign the new
+ wvmt->DialAssign(gw, role, instance);
+ return geventAttachSource(&gl, gsh, 0);
+ }
+#endif
+
+#if GWIN_WIDGET_TAGS
+ void gwinSetTag(GHandle gh, WidgetTag tag) {
+ if ((gh->flags & GWIN_FLG_WIDGET))
+ gw->tag = tag;
+ }
+
+ WidgetTag gwinGetTag(GHandle gh) {
+ return ((gh->flags & GWIN_FLG_WIDGET)) ? gw->tag : 0;
+ }
+#endif
+
+#undef gw
+#undef wvmt
+
+#endif /* GFX_USE_GWIN && GWIN_NEED_WIDGET */