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Adding STM32F439i-EVAL board files

spinbox_widget
Joel Bodenmann 5 years ago
parent
commit
37fc27ac6b
  1. 30
      boards/base/STM32F439i-Eval/CubeHal/board.mk
  2. 163
      boards/base/STM32F439i-Eval/CubeHal/board_STM32LTDC.h
  3. 89
      boards/base/STM32F439i-Eval/CubeHal/gmouse_lld_EXC7200_board.h
  4. 460
      boards/base/STM32F439i-Eval/CubeHal/stm324x9i_eval_sdram.c
  5. 163
      boards/base/STM32F439i-Eval/CubeHal/stm324x9i_eval_sdram.h
  6. 190
      boards/base/STM32F439i-Eval/CubeHal/stm32f439i_raw32_interrupts.c
  7. 561
      boards/base/STM32F439i-Eval/CubeHal/stm32f439i_raw32_startup.s
  8. 685
      boards/base/STM32F439i-Eval/CubeHal/stm32f439i_raw32_system.c
  9. 88
      boards/base/STM32F439i-Eval/CubeHal/stm32f439i_raw32_ugfx.c
  10. 189
      boards/base/STM32F439i-Eval/CubeHal/stm32f439nihx_flash.ld
  11. 1
      docs/releases.txt

30
boards/base/STM32F439i-Eval/CubeHal/board.mk

@ -0,0 +1,30 @@
GFXINC += $(GFXLIB)/boards/base/STM32F439i-Eval/CubeHAL
GFXSRC += $(GFXLIB)/boards/base/STM32F439i-Eval/CubeHAL/stm324x9i_eval_sdram.c
ifeq ($(OPT_OS),raw32)
GFXDEFS += STM32F439xx
GFXSRC += $(STMHAL)/Src/stm32f4xx_hal.c \
$(STMHAL)/Src/stm32f4xx_hal_cortex.c \
$(STMHAL)/Src/stm32f4xx_hal_rcc.c \
$(STMHAL)/Src/stm32f4xx_hal_rcc_ex.h \
$(STMHAL)/Src/stm32f4xx_hal_gpio.c \
$(STMHAL)/Src/stm32f4xx_hal_pwr.c \
$(STMHAL)/Src/stm32f4xx_hal_pwr_ex.c \
$(STMHAL)/Src/stm32f4xx_hal_sdram.c \
$(STMHAL)/Src/stm32f4xx_hal_dma.c \
$(STMHAL)/Src/stm32f4xx_hal_ltdc.c \
$(STMHAL)/Src/stm32f4xx_hal_i2c.c \
$(STMHAL)/Src/stm32f4xx_ll_fmc.c
GFXSRC += $(GFXLIB)/boards/base/STM32F439i-Eval/CubeHAL/stm32f439i_raw32_startup.s \
$(GFXLIB)/boards/base/STM32F439i-Eval/CubeHAL/stm32f439i_raw32_ugfx.c \
$(GFXLIB)/boards/base/STM32F439i-Eval/CubeHAL/stm32f439i_raw32_system.c \
$(GFXLIB)/boards/base/STM32F439i-Eval/CubeHAL/stm32f439i_raw32_interrupts.c
GFXDEFS += GFX_OS_PRE_INIT_FUNCTION=Raw32OSInit GFX_OS_INIT_NO_WARNING=TRUE
GFXINC += $(CMSIS)/Device/ST/STM32F4xx/Include \
$(CMSIS)/Include \
$(STMHAL)/Inc
LDSCRIPT = $(GFXLIB)/boards/base/STM32F439i-Eval/CubeHAL/stm32f439nihx_flash.ld
endif
include $(GFXLIB)/drivers/gdisp/STM32LTDC/driver.mk
include $(GFXLIB)/drivers/ginput/touch/EXC7200/driver.mk

163
boards/base/STM32F439i-Eval/CubeHal/board_STM32LTDC.h

@ -0,0 +1,163 @@
/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.org/license.html
*/
#ifndef _GDISP_LLD_BOARD_H
#define _GDISP_LLD_BOARD_H
// Avoid naming collisions with CubeHAL
#undef Red
#undef Green
#undef Blue
// Include CubeHAL
#include "stm32f4xx_hal.h"
#include "stm324x9i_eval_sdram.h"
// Panel parameters
#define AMPIRE640480_WIDTH ((uint16_t)640) /* LCD PIXEL WIDTH */
#define AMPIRE640480_HEIGHT ((uint16_t)480) /* LCD PIXEL HEIGHT */
#define AMPIRE640480_HSYNC ((uint16_t)30) /* Horizontal synchronization */
#define AMPIRE640480_HBP ((uint16_t)114) /* Horizontal back porch */
#define AMPIRE640480_HFP ((uint16_t)16) /* Horizontal front porch */
#define AMPIRE640480_VSYNC ((uint16_t)3) /* Vertical synchronization */
#define AMPIRE640480_VBP ((uint16_t)32) /* Vertical back porch */
#define AMPIRE640480_VFP ((uint16_t)10) /* Vertical front porch */
#define AMPIRE640480_FREQUENCY_DIVIDER 3 /* LCD Frequency divider */
static const ltdcConfig driverCfg = {
640, 480, // Width, Height (pixels)
30, 3, // Horizontal, Vertical sync (pixels)
114, 32, // Horizontal, Vertical back porch (pixels)
16, 10, // Horizontal, Vertical front porch (pixels)
0, // Sync flags
0x000000, // Clear color (RGB888)
{ // Background layer config
(LLDCOLOR_TYPE *)SDRAM_DEVICE_ADDR, // Frame buffer address
640, 480, // Width, Height (pixels)
640 * LTDC_PIXELBYTES, // Line pitch (bytes)
LTDC_PIXELFORMAT, // Pixel format
0, 0, // Start pixel position (x, y)
640, 480, // Size of virtual layer (cx, cy)
LTDC_COLOR_FUCHSIA, // Default color (ARGB8888)
0x980088, // Color key (RGB888)
LTDC_BLEND_FIX1_FIX2, // Blending factors
0, // Palette (RGB888, can be NULL)
0, // Palette length
0xFF, // Constant alpha factor
LTDC_LEF_ENABLE // Layer configuration flags
},
LTDC_UNUSED_LAYER_CONFIG // Foreground layer config
};
#define LCD_MAX_PCLK ((uint8_t)0x00)
static LTDC_HandleTypeDef hltdc_eval;
static uint32_t PCLK_profile = LCD_MAX_PCLK;
static void configureLcdPins(void)
{
GPIO_InitTypeDef GPIO_Init_Structure;
PCLK_profile = LCD_MAX_PCLK;
// LTDC configuration
hltdc_eval.Init.HorizontalSync = (AMPIRE640480_HSYNC - 1);
hltdc_eval.Init.VerticalSync = (AMPIRE640480_VSYNC - 1);
hltdc_eval.Init.AccumulatedHBP = (AMPIRE640480_HSYNC + AMPIRE640480_HBP - 1);
hltdc_eval.Init.AccumulatedVBP = (AMPIRE640480_VSYNC + AMPIRE640480_VBP - 1);
hltdc_eval.Init.AccumulatedActiveH = (AMPIRE640480_HEIGHT + AMPIRE640480_VSYNC + AMPIRE640480_VBP - 1);
hltdc_eval.Init.AccumulatedActiveW = (AMPIRE640480_WIDTH + AMPIRE640480_HSYNC + AMPIRE640480_HBP - 1);
hltdc_eval.Init.TotalHeigh = (AMPIRE640480_HEIGHT + AMPIRE640480_VSYNC + AMPIRE640480_VBP + AMPIRE640480_VFP - 1);
hltdc_eval.Init.TotalWidth = (AMPIRE640480_WIDTH + AMPIRE640480_HSYNC + AMPIRE640480_HBP + AMPIRE640480_HFP - 1);
hltdc_eval.LayerCfg->ImageWidth = AMPIRE640480_WIDTH;
hltdc_eval.LayerCfg->ImageHeight = AMPIRE640480_HEIGHT;
hltdc_eval.Init.Backcolor.Blue = 0;
hltdc_eval.Init.Backcolor.Green = 0;
hltdc_eval.Init.Backcolor.Red = 0;
hltdc_eval.Init.HSPolarity = LTDC_HSPOLARITY_AL;
hltdc_eval.Init.VSPolarity = LTDC_VSPOLARITY_AL;
hltdc_eval.Init.DEPolarity = LTDC_DEPOLARITY_AL;
hltdc_eval.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
hltdc_eval.Instance = LTDC;
HAL_LTDC_Init(&hltdc_eval);
// LCD clock configuration
static RCC_PeriphCLKInitTypeDef periph_clk_init_struct;
periph_clk_init_struct.PLLSAI.PLLSAIN = 151;
periph_clk_init_struct.PeriphClockSelection = RCC_PERIPHCLK_LTDC;
periph_clk_init_struct.PLLSAI.PLLSAIR = 3;
periph_clk_init_struct.PLLSAIDivR = RCC_PLLSAIDIVR_2;
HAL_RCCEx_PeriphCLKConfig(&periph_clk_init_struct);
// Enable peripheral clocks
__LTDC_CLK_ENABLE();
__DMA2D_CLK_ENABLE();
__GPIOI_CLK_ENABLE();
__GPIOJ_CLK_ENABLE();
__GPIOK_CLK_ENABLE();
/*** LTDC Pins configuration ***/
// GPIOI
GPIO_Init_Structure.Pin = GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
GPIO_Init_Structure.Mode = GPIO_MODE_AF_PP;
GPIO_Init_Structure.Pull = GPIO_NOPULL;
GPIO_Init_Structure.Speed = GPIO_SPEED_FAST;
GPIO_Init_Structure.Alternate = GPIO_AF14_LTDC;
HAL_GPIO_Init(GPIOI, &GPIO_Init_Structure);
// GPIOJ
GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | \
GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | \
GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | \
GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
GPIO_Init_Structure.Mode = GPIO_MODE_AF_PP;
GPIO_Init_Structure.Pull = GPIO_NOPULL;
GPIO_Init_Structure.Speed = GPIO_SPEED_FAST;
GPIO_Init_Structure.Alternate = GPIO_AF14_LTDC;
HAL_GPIO_Init(GPIOJ, &GPIO_Init_Structure);
// GPIOK configuration
GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | \
GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7;
GPIO_Init_Structure.Mode = GPIO_MODE_AF_PP;
GPIO_Init_Structure.Pull = GPIO_NOPULL;
GPIO_Init_Structure.Speed = GPIO_SPEED_FAST;
GPIO_Init_Structure.Alternate = GPIO_AF14_LTDC;
HAL_GPIO_Init(GPIOK, &GPIO_Init_Structure);
}
static GFXINLINE void init_board(GDisplay* g)
{
// As we are not using multiple displays we set g->board to NULL as we don't use it
g->board = 0;
switch(g->controllerdisplay) {
case 0:
// Set pin directions
configureLcdPins();
// Initialise the SDRAM
BSP_SDRAM_Init();
break;
}
}
static GFXINLINE void post_init_board(GDisplay* g)
{
(void) g;
}
static GFXINLINE void set_backlight(GDisplay* g, uint8_t percent)
{
(void) g;
}
#endif /* _GDISP_LLD_BOARD_H */

89
boards/base/STM32F439i-Eval/CubeHal/gmouse_lld_EXC7200_board.h

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/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.org/license.html
*/
/*
* Peripheral : I2C1
* SDA : PB9
* SCL : PB6
*/
#ifndef _GINPUT_LLD_MOUSE_BOARD_H
#define _GINPUT_LLD_MOUSE_BOARD_H
#include "stm32f4xx_hal_rcc.h"
#include "stm32f4xx_hal_dma.h"
#include "stm32f4xx_hal_gpio.h"
#include "stm32f4xx_hal_i2c.h"
// Resolution and Accuracy Settings
#define GMOUSE_EXC7200_PEN_CALIBRATE_ERROR 8
#define GMOUSE_EXC7200_PEN_CLICK_ERROR 6
#define GMOUSE_EXC7200_PEN_MOVE_ERROR 4
#define GMOUSE_EXC7200_FINGER_CALIBRATE_ERROR 14
#define GMOUSE_EXC7200_FINGER_CLICK_ERROR 18
#define GMOUSE_EXC7200_FINGER_MOVE_ERROR 14
// Number of bytes for the private area of this board file
#define GMOUSE_EXC7200_BOARD_DATA_SIZE 0
// The slave address of the I2C EXC7200
#define EXC7200_SLAVE_ADDR 0x08
static I2C_HandleTypeDef _i2cHandle;
static bool_t init_board(GMouse* m, unsigned driverinstance)
{
GPIO_InitTypeDef GPIO_InitStruct;
(void)m;
// Enable peripheral clocks
__HAL_RCC_I2C1_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
// SCL pin setup
GPIO_InitStruct.Pin = GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
// SDA pin setup
GPIO_InitStruct.Pin = GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
// Initialize the I2C peripheral
_i2cHandle.Instance = I2C1;
_i2cHandle.Init.ClockSpeed = 400000;
_i2cHandle.Init.DutyCycle = I2C_DUTYCYCLE_2;
_i2cHandle.Init.OwnAddress1 = 0;
_i2cHandle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
_i2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLED;
_i2cHandle.Init.OwnAddress2 = 0;
_i2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLED;
_i2cHandle.Init.NoStretchMode = I2C_NOSTRETCH_DISABLED;
HAL_I2C_Init(&_i2cHandle);
return TRUE;
}
static bool_t read_bytes(GMouse* m, uint8_t reg, uint8_t* buffer, uint8_t nbrBytes)
{
(void)m;
HAL_I2C_Master_Transmit(&_i2cHandle, (uint16_t)EXC7200_SLAVE_ADDR, (uint8_t*)&reg, 1, 10000);
HAL_I2C_Master_Receive(&_i2cHandle, (uint16_t)EXC7200_SLAVE_ADDR, buffer, nbrBytes, 10000);
return TRUE;
}
#endif /* _GINPUT_LLD_MOUSE_BOARD_H */

460
boards/base/STM32F439i-Eval/CubeHal/stm324x9i_eval_sdram.c

@ -0,0 +1,460 @@
/**
******************************************************************************
* @file stm324x9i_eval_sdram.c
* @author MCD Application Team
* @version V2.2.3
* @date 22-April-2016
* @brief This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory
* device mounted on STM324x9I-EVAL evaluation board.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* File Info : -----------------------------------------------------------------
User NOTES
1. How To use this driver:
--------------------------
- This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted
on STM324x9I-EVAL evaluation board.
- This driver does not need a specific component driver for the SDRAM device
to be included with.
2. Driver description:
---------------------
+ Initialization steps:
o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This
function includes the MSP layer hardware resources initialization and the
FMC controller configuration to interface with the external SDRAM memory.
o It contains the SDRAM initialization sequence to program the SDRAM external
device using the function BSP_SDRAM_Initialization_sequence(). Note that this
sequence is standard for all SDRAM devices, but can include some differences
from a device to another. If it is the case, the right sequence should be
implemented separately.
+ SDRAM read/write operations
o SDRAM external memory can be accessed with read/write operations once it is
initialized.
Read/write operation can be performed with AHB access using the functions
BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions
BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA().
o The AHB access is performed with 32-bit width transaction, the DMA transfer
configuration is fixed at single (no burst) word transfer (see the
SDRAM_MspInit() static function).
o User can implement his own functions for read/write access with his desired
configurations.
o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler()
is called in IRQ handler file, to serve the generated interrupt once the DMA
transfer is complete.
o You can send a command to the SDRAM device in runtime using the function
BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between
the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure.
------------------------------------------------------------------------------*/
/* Includes ------------------------------------------------------------------*/
#undef Red
#undef Green
#undef Blue
#include "stm324x9i_eval_sdram.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup STM324x9I_EVAL
* @{
*/
/** @defgroup STM324x9I_EVAL_SDRAM STM324x9I EVAL SDRAM
* @{
*/
/** @defgroup STM324x9I_EVAL_SDRAM_Private_Types_Definitions STM324x9I EVAL SDRAM Private Types Definitions
* @{
*/
/**
* @}
*/
/** @defgroup STM324x9I_EVAL_SDRAM_Private_Defines STM324x9I EVAL SDRAM Private Defines
* @{
*/
/**
* @}
*/
/** @defgroup STM324x9I_EVAL_SDRAM_Private_Macros STM324x9I EVAL SDRAM Private Macros
* @{
*/
/**
* @}
*/
/** @defgroup STM324x9I_EVAL_SDRAM_Private_Variables STM324x9I EVAL SDRAM Private Variables
* @{
*/
static SDRAM_HandleTypeDef sdramHandle;
static FMC_SDRAM_TimingTypeDef Timing;
static FMC_SDRAM_CommandTypeDef Command;
/**
* @}
*/
/** @defgroup STM324x9I_EVAL_SDRAM_Private_Function_Prototypes STM324x9I EVAL SDRAM Private Function Prototypes
* @{
*/
static void SDRAM_MspInit(void);
/**
* @}
*/
/** @defgroup STM324x9I_EVAL_SDRAM_Private_Functions STM324x9I EVAL SDRAM Private Functions
* @{
*/
/**
* @brief Initializes the SDRAM device.
* @retval SDRAM status
*/
uint8_t BSP_SDRAM_Init(void)
{
static uint8_t sdramstatus = SDRAM_ERROR;
/* SDRAM device configuration */
sdramHandle.Instance = FMC_SDRAM_DEVICE;
/* Timing configuration for 90Mhz as SD clock frequency (System clock is up to 180Mhz */
Timing.LoadToActiveDelay = 2;
Timing.ExitSelfRefreshDelay = 7;
Timing.SelfRefreshTime = 4;
Timing.RowCycleDelay = 7;
Timing.WriteRecoveryTime = 2;
Timing.RPDelay = 2;
Timing.RCDDelay = 2;
sdramHandle.Init.SDBank = FMC_SDRAM_BANK1;
sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9;
sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD;
sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
/* SDRAM controller initialization */
SDRAM_MspInit();
if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)
{
sdramstatus = SDRAM_ERROR;
}
else
{
sdramstatus = SDRAM_OK;
}
/* SDRAM initialization sequence */
BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
return sdramstatus;
}
/**
* @brief Programs the SDRAM device.
* @param RefreshCount: SDRAM refresh counter value
*/
void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
{
__IO uint32_t tmpmrd = 0;
/* Step 1: Configure a clock configuration enable command */
Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
Command.AutoRefreshNumber = 1;
Command.ModeRegisterDefinition = 0;
/* Send the command */
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
/* Step 2: Insert 100 us minimum delay */
/* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
HAL_Delay(1);
/* Step 3: Configure a PALL (precharge all) command */
Command.CommandMode = FMC_SDRAM_CMD_PALL;
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
Command.AutoRefreshNumber = 1;
Command.ModeRegisterDefinition = 0;
/* Send the command */
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
/* Step 4: Configure an Auto Refresh command */
Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
Command.AutoRefreshNumber = 8;
Command.ModeRegisterDefinition = 0;
/* Send the command */
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
/* Step 5: Program the external memory mode register */
tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
SDRAM_MODEREG_CAS_LATENCY_3 |\
SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
Command.AutoRefreshNumber = 1;
Command.ModeRegisterDefinition = tmpmrd;
/* Send the command */
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
/* Step 6: Set the refresh rate counter */
/* Set the device refresh rate */
HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount);
}
/**
* @brief Reads an mount of data from the SDRAM memory in polling mode.
* @param uwStartAddress: Read start address
* @param pData: Pointer to data to be read
* @param uwDataSize: Size of read data from the memory
* @retval SDRAM status
*/
uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
{
if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
{
return SDRAM_ERROR;
}
else
{
return SDRAM_OK;
}
}
/**
* @brief Reads an mount of data from the SDRAM memory in DMA mode.
* @param uwStartAddress: Read start address
* @param pData: Pointer to data to be read
* @param uwDataSize: Size of read data from the memory
* @retval SDRAM status
*/
uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
{
if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
{
return SDRAM_ERROR;
}
else
{
return SDRAM_OK;
}
}
/**
* @brief Writes an mount of data to the SDRAM memory in polling mode.
* @param uwStartAddress: Write start address
* @param pData: Pointer to data to be written
* @param uwDataSize: Size of written data from the memory
* @retval SDRAM status
*/
uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
{
if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
{
return SDRAM_ERROR;
}
else
{
return SDRAM_OK;
}
}
/**
* @brief Writes an mount of data to the SDRAM memory in DMA mode.
* @param uwStartAddress: Write start address
* @param pData: Pointer to data to be written
* @param uwDataSize: Size of written data from the memory
* @retval SDRAM status
*/
uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
{
if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
{
return SDRAM_ERROR;
}
else
{
return SDRAM_OK;
}
}
/**
* @brief Sends command to the SDRAM bank.
* @param SdramCmd: Pointer to SDRAM command structure
* @retval HAL status
*/
uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
{
if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK)
{
return SDRAM_ERROR;
}
else
{
return SDRAM_OK;
}
}
/**
* @brief Handles SDRAM DMA transfer interrupt request.
*/
void BSP_SDRAM_DMA_IRQHandler(void)
{
HAL_DMA_IRQHandler(sdramHandle.hdma);
}
/**
* @brief Initializes SDRAM MSP.
*/
static void SDRAM_MspInit(void)
{
static DMA_HandleTypeDef dmaHandle;
GPIO_InitTypeDef GPIO_Init_Structure;
SDRAM_HandleTypeDef *hsdram = &sdramHandle;
/* Enable FMC clock */
__FMC_CLK_ENABLE();
/* Enable chosen DMAx clock */
__DMAx_CLK_ENABLE();
/* Enable GPIOs clock */
__GPIOD_CLK_ENABLE();
__GPIOE_CLK_ENABLE();
__GPIOF_CLK_ENABLE();
__GPIOG_CLK_ENABLE();
__GPIOH_CLK_ENABLE();
__GPIOI_CLK_ENABLE();
/* Common GPIO configuration */
GPIO_Init_Structure.Mode = GPIO_MODE_AF_PP;
GPIO_Init_Structure.Pull = GPIO_PULLUP;
GPIO_Init_Structure.Speed = GPIO_SPEED_FAST;
GPIO_Init_Structure.Alternate = GPIO_AF12_FMC;
/* GPIOD configuration */
GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8| GPIO_PIN_9 | GPIO_PIN_10 |\
GPIO_PIN_14 | GPIO_PIN_15;
HAL_GPIO_Init(GPIOD, &GPIO_Init_Structure);
/* GPIOE configuration */
GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
GPIO_PIN_15;
HAL_GPIO_Init(GPIOE, &GPIO_Init_Structure);
/* GPIOF configuration */
GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
GPIO_PIN_15;
HAL_GPIO_Init(GPIOF, &GPIO_Init_Structure);
/* GPIOG configuration */
GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\
GPIO_PIN_15;
HAL_GPIO_Init(GPIOG, &GPIO_Init_Structure);
/* GPIOH configuration */
GPIO_Init_Structure.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_9 |\
GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
GPIO_PIN_15;
HAL_GPIO_Init(GPIOH, &GPIO_Init_Structure);
/* GPIOI configuration */
GPIO_Init_Structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 |\
GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_9 | GPIO_PIN_10;
HAL_GPIO_Init(GPIOI, &GPIO_Init_Structure);
/* Configure common DMA parameters */
dmaHandle.Init.Channel = SDRAM_DMAx_CHANNEL;
dmaHandle.Init.Direction = DMA_MEMORY_TO_MEMORY;
dmaHandle.Init.PeriphInc = DMA_PINC_ENABLE;
dmaHandle.Init.MemInc = DMA_MINC_ENABLE;
dmaHandle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
dmaHandle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
dmaHandle.Init.Mode = DMA_NORMAL;
dmaHandle.Init.Priority = DMA_PRIORITY_HIGH;
dmaHandle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
dmaHandle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
dmaHandle.Init.MemBurst = DMA_MBURST_SINGLE;
dmaHandle.Init.PeriphBurst = DMA_PBURST_SINGLE;
dmaHandle.Instance = SDRAM_DMAx_STREAM;
/* Associate the DMA handle */
__HAL_LINKDMA(hsdram, hdma, dmaHandle);
/* Deinitialize the stream for new transfer */
HAL_DMA_DeInit(&dmaHandle);
/* Configure the DMA stream */
HAL_DMA_Init(&dmaHandle);
/* NVIC configuration for DMA transfer complete interrupt */
HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

163
boards/base/STM32F439i-Eval/CubeHal/stm324x9i_eval_sdram.h

@ -0,0 +1,163 @@
/**
******************************************************************************
* @file stm324x9i_eval_sdram.h
* @author MCD Application Team
* @version V2.2.3
* @date 22-April-2016
* @brief This file contains the common defines and functions prototypes for
* the stm324x9i_eval_sdram.c driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM324x9I_EVAL_SDRAM_H
#define __STM324x9I_EVAL_SDRAM_H
#undef Red
#undef Green
#undef Blue
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup STM324x9I_EVAL
* @{
*/
/** @addtogroup STM324x9I_EVAL_SDRAM
* @{
*/
/** @defgroup STM324x9I_EVAL_SDRAM_Exported_Types STM324x9I EVAL SDRAM Exported Types
* @{
*/
/**
* @brief SDRAM status structure definition
*/
#define SDRAM_OK 0x00
#define SDRAM_ERROR 0x01
/**
* @}
*/
/** @defgroup STM324x9I_EVAL_SDRAM_Exported_Constants STM324x9I EVAL SDRAM Exported Constants
* @{
*/
#define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000)
#define SDRAM_DEVICE_SIZE ((uint32_t)0x800000) /* SDRAM device size in MBytes */
/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */
/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16 */
#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_32
#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2
/* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */
#define REFRESH_COUNT ((uint32_t)0x0569) /* SDRAM refresh counter (90Mhz SD clock) */
#define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
/* DMA definitions for SDRAM DMA transfer */
#define __DMAx_CLK_ENABLE __DMA2_CLK_ENABLE
#define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0
#define SDRAM_DMAx_STREAM DMA2_Stream0
#define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn
#define SDRAM_DMAx_IRQHandler DMA2_Stream0_IRQHandler
/**
* @brief FMC SDRAM Mode definition register defines
*/
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
/**
* @}
*/
/** @defgroup STM324x9I_EVAL_SDRAM_Exported_Macro STM324x9I EVAL SDRAM Exported Macro
* @{
*/
/**
* @}
*/
/** @defgroup STM324x9I_EVAL_SDRAM_Exported_Functions STM324x9I EVAL SDRAM Exported Functions
* @{
*/
uint8_t BSP_SDRAM_Init(void);
void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount);
uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
void BSP_SDRAM_DMA_IRQHandler(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM324x9I_EVAL_SDRAM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

190
boards/base/STM32F439i-Eval/CubeHal/stm32f439i_raw32_interrupts.c

@ -0,0 +1,190 @@
/**
******************************************************************************
* @file Templates/Src/stm32f4xx_it.c
* @author MCD Application Team
* @version V1.3.4
* @date 06-May-2016
* @brief Main Interrupt Service Routines.
* This file provides template for all exceptions handler and
* peripherals interrupt service routine.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#undef Red
#undef Green
#undef Blue
#include "stm32f4xx_hal_conf.h"
#include "stm32f4xx_hal.h"
/** @addtogroup STM32F4xx_HAL_Examples
* @{
*/
/** @addtogroup Templates
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/******************************************************************************/
/* Cortex-M4 Processor Exceptions Handlers */
/******************************************************************************/
/**
* @brief This function handles NMI exception.
* @param None
* @retval None
*/
void NMI_Handler(void)
{
}
/**
* @brief This function handles Hard Fault exception.
* @param None
* @retval None
*/
void HardFault_Handler(void)
{
/* Go to infinite loop when Hard Fault exception occurs */
while (1)
{
}
}
/**
* @brief This function handles Memory Manage exception.
* @param None
* @retval None
*/
void MemManage_Handler(void)
{
/* Go to infinite loop when Memory Manage exception occurs */
while (1)
{
}
}
/**
* @brief This function handles Bus Fault exception.
* @param None
* @retval None
*/
void BusFault_Handler(void)
{
/* Go to infinite loop when Bus Fault exception occurs */
while (1)
{
}
}
/**
* @brief This function handles Usage Fault exception.
* @param None
* @retval None
*/
void UsageFault_Handler(void)
{
/* Go to infinite loop when Usage Fault exception occurs */
while (1)
{
}
}
/**
* @brief This function handles SVCall exception.
* @param None
* @retval None
*/
void SVC_Handler(void)
{
}
/**
* @brief This function handles Debug Monitor exception.
* @param None
* @retval None
*/
void DebugMon_Handler(void)
{
}
/**
* @brief This function handles PendSVC exception.
* @param None
* @retval None
*/
void PendSV_Handler(void)
{
}
/**
* @brief This function handles SysTick Handler.
* @param None
* @retval None
*/
void SysTick_Handler(void)
{
HAL_IncTick();
}
/******************************************************************************/
/* STM32F4xx Peripherals Interrupt Handlers */
/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
/* available peripheral interrupt handler's name please refer to the startup */
/* file (startup_stm32f4xx.s). */
/******************************************************************************/
/**
* @brief This function handles PPP interrupt request.
* @param None
* @retval None
*/
/*void PPP_IRQHandler(void)
{
}*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

561
boards/base/STM32F439i-Eval/CubeHal/stm32f439i_raw32_startup.s

@ -0,0 +1,561 @@
/**
******************************************************************************
* @file startup_stm32f429xx.s
* @author MCD Application Team
* @version V1.3.4
* @date 06-May-2016
* @brief STM32F429xx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_IRQHandler /* PVD through EXTI Line detection */
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word CAN1_TX_IRQHandler /* CAN1 TX */
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDIO_IRQHandler /* SDIO */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word ETH_IRQHandler /* Ethernet */
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
.word CAN2_TX_IRQHandler /* CAN2 TX */
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
.word OTG_FS_IRQHandler /* USB OTG FS */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_IRQHandler /* DCMI */
.word 0 /* Reserved */
.word HASH_RNG_IRQHandler /* Hash and Rng */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word SPI6_IRQHandler /* SPI6 */
.word SAI1_IRQHandler /* SAI1 */
.word LTDC_IRQHandler /* LTDC_IRQHandler */
.word LTDC_ER_IRQHandler /* LTDC_ER_IRQHandler */
.word DMA2D_IRQHandler /* DMA2D */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM9_IRQHandler
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
.weak TIM1_UP_TIM10_IRQHandler
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM11_IRQHandler
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak OTG_FS_WKUP_IRQHandler
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler