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Updates for the EMBEST board and a small fix to the SSD2119 driver.

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This commit is contained in:
inmarket 2014-12-15 18:17:52 +10:00
parent 21a26eb762
commit 3936c63061
3 changed files with 13 additions and 10 deletions
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11
boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h
View File

@ -29,8 +29,8 @@
* the PWM frequency should be somewhere between 200 Hz to 200 kHz.
*/
static const PWMConfig pwmcfg = {
1000000, /* 1 MHz PWM clock frequency. */
100, /* PWM period is 100 cycles. */
20000, /* 20 KHz PWM clock frequency. */
100, /* PWM period is 100 cycles. */
0,
{
{PWM_OUTPUT_ACTIVE_HIGH, 0},
@ -75,8 +75,11 @@ static inline void init_board(GDisplay *g) {
palSetBusMode(&busE, PAL_MODE_ALTERNATE(12));
/* FSMC timing register configuration */
FSMC_Bank1->BTCR[0 + 1] = (FSMC_BTR1_ADDSET_2 | FSMC_BTR1_ADDSET_1) \
| (FSMC_BTR1_DATAST_2 | FSMC_BTR1_DATAST_1) \
// FSMC_Bank1->BTCR[0 + 1] = (FSMC_BTR1_ADDSET_2 | FSMC_BTR1_ADDSET_1) \
// | (FSMC_BTR1_DATAST_2 | FSMC_BTR1_DATAST_1) \
// | FSMC_BTR1_BUSTURN_0;
FSMC_Bank1->BTCR[0 + 1] = (FSMC_BTR1_ADDSET_3 | FSMC_BTR1_ADDSET_0) \
| (FSMC_BTR1_DATAST_3 | FSMC_BTR1_DATAST_0) \
| FSMC_BTR1_BUSTURN_0;
/* Bank1 NOR/PSRAM control register configuration

2
boards/base/Embest-STM32-DMSTF4BB/gmouse_lld_STMPE811_board.h
View File

@ -39,7 +39,7 @@
static const I2CConfig i2ccfg = {
OPMODE_I2C,
400000,
200000, // Conservative please
FAST_DUTY_CYCLE_2,
};

10
drivers/gdisp/SSD2119/gdisp_lld_SSD2119.c
View File

@ -152,7 +152,7 @@ LLDSPEC bool_t gdisp_lld_init(GDisplay* g) {
gfxSleepMicroseconds(5);
// Configure pixel color format and MCU interface parameters.
write_reg(g, SSD2119_REG_ENTRY_MODE, 0x6830); // ENTRY_MODE_DEFAULT
write_reg(g, SSD2119_REG_ENTRY_MODE, 0x6838); // ENTRY_MODE_DEFAULT
gfxSleepMicroseconds(5);
// Set analog parameters.
@ -267,7 +267,7 @@ LLDSPEC bool_t gdisp_lld_init(GDisplay* g) {
#if GDISP_HARDWARE_FILLS && defined(GDISP_USE_DMA)
LLDSPEC void gdisp_lld_fill_area(GDisplay* g) {
uint16_t c;
LLDCOLOR_TYPE c;
c = gdispColor2Native(g->p.color);
acquire_bus(g);
@ -285,7 +285,7 @@ LLDSPEC bool_t gdisp_lld_init(GDisplay* g) {
LLDSPEC void gdisp_lld_blit_area(GDisplay* g) {
pixel_t* buffer;
coord_t ynct;
coord_t ycnt;
buffer = (pixel_t*)g->p.ptr + g->p.x1 + g->p.y1 * g->p.x2;
@ -355,8 +355,8 @@ LLDSPEC bool_t gdisp_lld_init(GDisplay* g) {
switch((orientation_t)g->p.ptr) {
case GDISP_ROTATE_0:
acquire_bus(g);
/* ID = 11 AM = 0 */
write_reg(g, SSD2119_REG_ENTRY_MODE, 0x6830);
/* ID = 11 AM = 1 */
write_reg(g, SSD2119_REG_ENTRY_MODE, 0x6838);
release_bus(g);
g->g.Height = GDISP_SCREEN_HEIGHT;
g->g.Width = GDISP_SCREEN_WIDTH;