More STM32F746-Discovery changes.
This commit is contained in:
parent
d4ef20f47e
commit
470868f51a
12 changed files with 233 additions and 3406 deletions
|
@ -1,29 +1,22 @@
|
|||
GFXINC += $(GFXLIB)/boards/base/STM32F746-Discovery \
|
||||
$(STMHAL)/Inc
|
||||
GFXSRC += $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c \
|
||||
$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c \
|
||||
$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f7_i2c.c
|
||||
|
||||
ifeq ($(OPT_OS),raw32)
|
||||
HAL = $(STMHAL)
|
||||
GFXDEFS += STM32F746xx
|
||||
GFXSRC += $(HAL)/Src/stm32f7xx_hal.c \
|
||||
$(HAL)/Src/stm32f7xx_hal_cortex.c \
|
||||
$(HAL)/Src/stm32f7xx_hal_flash.c \
|
||||
$(HAL)/Src/stm32f7xx_hal_flash_ex.c \
|
||||
$(HAL)/Src/stm32f7xx_hal_rcc.c \
|
||||
$(HAL)/Src/stm32f7xx_hal_rcc_ex.h \
|
||||
$(HAL)/Src/stm32f7xx_hal_gpio.c \
|
||||
$(HAL)/Src/stm32f7xx_hal_pwr.c \
|
||||
$(HAL)/Src/stm32f7xx_hal_pwr_ex.c \
|
||||
$(HAL)/Src/stm32f7xx_hal_sdram.c \
|
||||
$(HAL)/Src/stm32f7xx_hal_dma.c
|
||||
GFXSRC += $(STMHAL)/Src/stm32f7xx_hal.c \
|
||||
$(STMHAL)/Src/stm32f7xx_hal_cortex.c \
|
||||
$(STMHAL)/Src/stm32f7xx_hal_rcc.c \
|
||||
$(STMHAL)/Src/stm32f7xx_hal_rcc_ex.h \
|
||||
$(STMHAL)/Src/stm32f7xx_hal_gpio.c \
|
||||
$(STMHAL)/Src/stm32f7xx_hal_pwr.c \
|
||||
$(STMHAL)/Src/stm32f7xx_hal_pwr_ex.c
|
||||
GFXSRC += $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_startup.s \
|
||||
$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c \
|
||||
$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c \
|
||||
$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_interrupts.c
|
||||
GFXDEFS += GFX_OS_EXTRA_INIT_FUNCTION=Raw32OSInit GFX_OS_INIT_NO_WARNING=TRUE
|
||||
SRCFLAGS+= -std=c99
|
||||
GFXINC += $(CMSIS)/Device/ST/STM32F7xx/Include \
|
||||
$(CMSIS)/Include \
|
||||
$(STMHAL)/Inc
|
||||
|
|
|
@ -8,8 +8,9 @@
|
|||
#ifndef _GDISP_LLD_BOARD_H
|
||||
#define _GDISP_LLD_BOARD_H
|
||||
|
||||
#include "stm32f7xx_ll_fmc.h"
|
||||
#include "stm32f746g_discovery_sdram.h"
|
||||
#include "stm32f7xx_hal_rcc.h"
|
||||
#include "stm32f7xx_hal_gpio.h"
|
||||
#include <string.h>
|
||||
|
||||
#if !GFX_USE_OS_CHIBIOS
|
||||
|
|
|
@ -55,7 +55,8 @@ LDFLAGS =
|
|||
SRC =
|
||||
|
||||
OBJS =
|
||||
DEFS = GFX_OS_HEAP_SIZE=40960
|
||||
#DEFS = GFX_OS_HEAP_SIZE=40960
|
||||
DEFS =
|
||||
LIBS =
|
||||
INCPATH =
|
||||
|
||||
|
|
|
@ -65,7 +65,7 @@
|
|||
/* #define HAL_NAND_MODULE_ENABLED */
|
||||
/* #define HAL_NOR_MODULE_ENABLED */
|
||||
/* #define HAL_SRAM_MODULE_ENABLED */
|
||||
#define HAL_SDRAM_MODULE_ENABLED
|
||||
//#define HAL_SDRAM_MODULE_ENABLED
|
||||
/* #define HAL_HASH_MODULE_ENABLED */
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
/* #define HAL_I2C_MODULE_ENABLED */
|
||||
|
|
|
@ -56,6 +56,7 @@ SRC =
|
|||
|
||||
OBJS =
|
||||
DEFS = GFX_OS_HEAP_SIZE=40960
|
||||
#DEFS =
|
||||
LIBS =
|
||||
INCPATH =
|
||||
|
||||
|
|
|
@ -65,7 +65,7 @@
|
|||
/* #define HAL_NAND_MODULE_ENABLED */
|
||||
/* #define HAL_NOR_MODULE_ENABLED */
|
||||
/* #define HAL_SRAM_MODULE_ENABLED */
|
||||
#define HAL_SDRAM_MODULE_ENABLED
|
||||
//#define HAL_SDRAM_MODULE_ENABLED
|
||||
/* #define HAL_HASH_MODULE_ENABLED */
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
/* #define HAL_I2C_MODULE_ENABLED */
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -44,127 +44,13 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_rcc.h"
|
||||
#include "stm32f7xx_hal_rcc_ex.h"
|
||||
#include "stm32f7xx_hal_dma.h"
|
||||
#include "stm32f7xx_hal_gpio.h"
|
||||
#include "stm32f7xx_hal_sdram.h"
|
||||
#include "stm32f7xx_ll_fmc.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32746G_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32746G_DISCOVERY_SDRAM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Types STM32746G_DISCOVERY_SDRAM Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SDRAM status structure definition
|
||||
*/
|
||||
#define SDRAM_OK ((uint8_t)0x00)
|
||||
#define SDRAM_ERROR ((uint8_t)0x01)
|
||||
|
||||
/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Constants STM32746G_DISCOVERY_SDRAM Exported Constants
|
||||
* @{
|
||||
*/
|
||||
#define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000)
|
||||
#define SDRAM_DEVICE_SIZE ((uint32_t)0x800000) /* SDRAM device size in MBytes */
|
||||
|
||||
/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */
|
||||
#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16
|
||||
|
||||
#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2
|
||||
/* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */
|
||||
|
||||
#define REFRESH_COUNT ((uint32_t)0x0603) /* SDRAM refresh counter (100Mhz SD clock) */
|
||||
|
||||
#define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
|
||||
|
||||
/* DMA definitions for SDRAM DMA transfer */
|
||||
#define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
|
||||
#define __DMAx_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
|
||||
#define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0
|
||||
#define SDRAM_DMAx_STREAM DMA2_Stream0
|
||||
#define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn
|
||||
#define SDRAM_DMAx_IRQHandler DMA2_Stream0_IRQHandler
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FMC SDRAM Mode definition register defines
|
||||
*/
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
|
||||
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
|
||||
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
|
||||
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
|
||||
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Macro STM32746G_DISCOVERY_SDRAM Exported Macro
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32746G_DISCOVERY_SDRAM_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
uint8_t BSP_SDRAM_Init(void);
|
||||
uint8_t BSP_SDRAM_DeInit(void);
|
||||
void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount);
|
||||
uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
|
||||
uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
|
||||
uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
|
||||
uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
|
||||
uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
|
||||
void BSP_SDRAM_DMA_IRQHandler(void);
|
||||
|
||||
/* These functions can be modified in case the current settings (e.g. DMA stream)
|
||||
need to be changed for specific application needs */
|
||||
void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params);
|
||||
void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
void BSP_SDRAM_Init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32746G_DISCOVERY_SDRAM_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
#endif
|
||||
|
|
|
@ -1,6 +1,7 @@
|
|||
#include "gfx.h"
|
||||
#include "stm32f7xx_hal.h"
|
||||
|
||||
#if !GFX_USE_OS_CHIBIOS
|
||||
systemticks_t gfxSystemTicks(void)
|
||||
{
|
||||
return HAL_GetTick();
|
||||
|
@ -10,13 +11,12 @@ systemticks_t gfxMillisecondsToTicks(delaytime_t ms)
|
|||
{
|
||||
return ms;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void SystemClock_Config(void);
|
||||
static void CPU_CACHE_Enable(void);
|
||||
|
||||
void Raw32OSInit(void) {
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
|
||||
|
||||
/* Enable the CPU Cache */
|
||||
CPU_CACHE_Enable();
|
||||
|
||||
|
@ -31,6 +31,7 @@ void Raw32OSInit(void) {
|
|||
/* Configure the system clock to 216 MHz */
|
||||
SystemClock_Config();
|
||||
|
||||
#if !GFX_USE_OS_CHIBIOS
|
||||
// LED - for testing
|
||||
GPIO_InitTypeDef GPIO_InitStruct;
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_1;
|
||||
|
@ -39,6 +40,7 @@ void Raw32OSInit(void) {
|
|||
GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
|
||||
__GPIOI_CLK_ENABLE();
|
||||
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
@ -64,48 +66,6 @@ void Raw32OSInit(void) {
|
|||
*/
|
||||
void SystemClock_Config(void)
|
||||
{
|
||||
#if 0
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct;
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct;
|
||||
HAL_StatusTypeDef ret = HAL_OK;
|
||||
|
||||
/* Enable HSE Oscillator and activate PLL with HSE as source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
||||
RCC_OscInitStruct.PLL.PLLM = 12;
|
||||
RCC_OscInitStruct.PLL.PLLN = 192; // 432
|
||||
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
||||
RCC_OscInitStruct.PLL.PLLQ = 2; // 9
|
||||
|
||||
ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
if(ret != HAL_OK)
|
||||
{
|
||||
while(1) { ; }
|
||||
}
|
||||
|
||||
/* Activate the OverDrive to reach the 200/216 MHz Frequency */
|
||||
ret = HAL_PWREx_EnableOverDrive();
|
||||
if(ret != HAL_OK)
|
||||
{
|
||||
while(1) { ; }
|
||||
}
|
||||
|
||||
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
|
||||
|
||||
ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6); // FLASH_LATENCY_7
|
||||
if(ret != HAL_OK)
|
||||
{
|
||||
while(1) { ; }
|
||||
}
|
||||
#else
|
||||
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct;
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct;
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
|
||||
|
@ -143,7 +103,6 @@ void SystemClock_Config(void)
|
|||
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
|
||||
|
||||
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
@ -158,13 +158,13 @@ gfxThreadHandle gfxThreadCreate(void *stackarea, size_t stacksz, threadpriority_
|
|||
{
|
||||
if (!stackarea) {
|
||||
if (!stacksz) stacksz = 256;
|
||||
return chThdCreateFromHeap(0, stacksz, prio, fn, param);
|
||||
return chThdCreateFromHeap(0, stacksz, prio, (tfunc_t)fn, param);
|
||||
}
|
||||
|
||||
if (!stacksz)
|
||||
return 0;
|
||||
|
||||
return chThdCreateStatic(stackarea, stacksz, prio, fn, param);
|
||||
return chThdCreateStatic(stackarea, stacksz, prio, (tfunc_t)fn, param);
|
||||
}
|
||||
|
||||
#endif /* GFX_USE_OS_CHIBIOS */
|
||||
|
|
Loading…
Add table
Reference in a new issue