Adding HY-MiniSTM32V board support
Joel Bodenmann
parent
606eeff79f
commit
514d91d6cf
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GFXINC += $(GFXLIB)/boards/base/HY-MiniSTM32V
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GFXSRC +=
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GFXDEFS += -DGFX_USE_CHIBIOS=TRUE
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include $(GFXLIB)/boards/base/HY-MiniSTM32V/chibios_board/board.mk
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include $(GFXLIB)/drivers/gdisp/SSD1289/driver.mk
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include $(GFXLIB)/drivers/ginput/touch/ADS7843/driver.mk
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/*
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* This file is subject to the terms of the GFX License. If a copy of
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* the license was not distributed with this file, you can obtain one at:
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*
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* http://ugfx.org/license.html
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*/
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#ifndef GDISP_LLD_BOARD_H
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#define GDISP_LLD_BOARD_H
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/*
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* Board file for HY-MiniSTM32V board from HAOYU (China).
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* www.powermcu.com or www.hotmcu.com.
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*/
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/*
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* NOTE: In order to make this work you need to set:
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* STM32_PWM_USE_TIM3 TRUE in mcuconf.h
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* HAL_USE_PWM TRUE in halconf.h
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*/
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/*
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* TM3 ch2 is connected to LCD BL_CNT (PB5)
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*/
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static const PWMConfig pwmcfg =
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{
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100000, // frequency
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100, // period
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NULL, // callback
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{
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{PWM_OUTPUT_DISABLED, 0},
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{PWM_OUTPUT_ACTIVE_HIGH, 0},
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{PWM_OUTPUT_DISABLED, 0},
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{PWM_OUTPUT_DISABLED, 0}
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},
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0, // cr2
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0, // dier
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};
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/*
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* LCD_RS is on A16 (PD11)
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*/
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#define GDISP_REG (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
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#define GDISP_RAM (*((volatile uint16_t *) 0x60020000)) /* RS = 1 */
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/*
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* STM32_DMA1_STREAM7
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* NOTE: conflicts w/ USART2_TX, TIM2_CH2, TIM2_CH4, TIM4_UP, I2C1_RX in case
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*/
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#define GDISP_DMA_STREAM STM32_DMA1_STREAM7
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#define FSMC_BANK 0
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static inline void init_board(GDisplay *g) {
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/*
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* As we are not using multiple displays we set g->board to NULL as we don't
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* use it.
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*/
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g->board = 0;
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switch(g->controllerdisplay) {
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/*
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* Set up for Display 0
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*/
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case 0:
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/* FSMC setup for F1 */
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rccEnableAHB(RCC_AHBENR_FSMCEN, 0);
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/* Group pins for FSMC setup as alternate function */
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IOBus busD = { GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) | \
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(1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | \
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(1 << 14) | (1 << 15), 0 };
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IOBus busE = { GPIOE, (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | \
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(1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) | \
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(1 << 15), 0 };
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/* FSMC sa alternate function */
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palSetBusMode(&busD, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
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palSetBusMode(&busE, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
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/*
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* NOTE: stm32F10x.h is FAULTY on FSMC
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* NOTE: Used hardcore bit shifting below
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* NOTE: All timings for 72MHz HCLK - should be revised for lower HCLK
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*/
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/* FSMC timing - Read: DATAST = 0x20; all the rest = 0.
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* 100ns cycle time for SSD1289 as per DataSheet
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*/
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FSMC_Bank1->BTCR[FSMC_BANK+1] = (0x20 << 8);
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/* FSMC timing - Write: DATAST = 0x01, ADDSET = 0x01 all the rest = 0.
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* 1000ns cycle time for SSD1289 as per DataSheet
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*/
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FSMC_Bank1E->BWTR[FSMC_BANK] = (0x1 << 8) | (0x01 << 0);
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/* Bank1 NOR/SRAM control register configuration
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* Note: different read and write cycle timing
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*/
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FSMC_Bank1->BTCR[FSMC_BANK] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | \
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FSMC_BCR1_MBKEN | FSMC_BCR1_EXTMOD;
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/* DMA Setup. */
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#if defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM)
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if (dmaStreamAllocate(GDISP_DMA_STREAM, 0, 0, 0))
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gfxExit();
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dmaStreamSetMemory0(GDISP_DMA_STREAM, &GDISP_RAM);
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dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | \
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STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | \
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STM32_DMA_CR_DIR_M2M);
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#endif
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/* Display backlight control */
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/* TIM3 ch2 (PB5) connected to LCD BL_CNT */
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pwmStart(&PWMD3, &pwmcfg);
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palSetPadMode(GPIOB, 5, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
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pwmEnableChannel(&PWMD3, 1, 100);
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break;
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}
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}
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static inline void post_init_board(GDisplay *g) {
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(void) g;
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}
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static inline void setpin_reset(GDisplay *g, bool_t state) {
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(void) g;
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if(state) {}
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else {}
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}
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static inline void set_backlight(GDisplay *g, uint8_t percent) {
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(void) g;
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if (percent > 100) { percent = 100; }
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pwmEnableChannel(&PWMD3, 1, percent);
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}
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static inline void acquire_bus(GDisplay *g) {
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(void) g;
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}
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static inline void release_bus(GDisplay *g) {
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(void) g;
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}
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static inline void write_index(GDisplay *g, uint16_t index) {
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(void) g;
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GDISP_REG = index;
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}
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static inline void write_data(GDisplay *g, uint16_t data) {
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(void) g;
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GDISP_RAM = data;
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}
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static inline void setreadmode(GDisplay *g) {
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(void) g;
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}
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static inline void setwritemode(GDisplay *g) {
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(void) g;
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}
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static inline uint16_t read_data(GDisplay *g) {
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(void) g;
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return GDISP_RAM;
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}
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#if defined(GDISP_USE_DMA) || defined(__DOXYGEN__)
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static inline void dma_with_noinc(GDisplay *g, color_t *buffer, int area) {
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(void) g;
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dmaStreamSetPeripheral(GDISP_DMA_STREAM, buffer);
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dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | \
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STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | \
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STM32_DMA_CR_DIR_M2M);
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for (; area > 0; area -= 65535) {
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dmaStreamSetTransactionSize(GDISP_DMA_STREAM, area > 65535 ? 65535 : area);
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dmaStreamEnable(GDISP_DMA_STREAM);
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dmaWaitCompletion(GDISP_DMA_STREAM);
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}
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}
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static inline void dma_with_inc(GDisplay *g, color_t *buffer, int area) {
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(void) g;
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dmaStreamSetPeripheral(GDISP_DMA_STREAM, buffer);
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dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PINC | \
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STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | \
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STM32_DMA_CR_DIR_M2M);
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for (; area > 0; area -= 65535) {
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dmaStreamSetTransactionSize(GDISP_DMA_STREAM, area > 65535 ? 65535 : area);
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dmaStreamEnable(GDISP_DMA_STREAM);
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dmaWaitCompletion(GDISP_DMA_STREAM);
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}
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}
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#endif
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#endif /* GDISP_LLD_BOARD_H */
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@ -0,0 +1,81 @@
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#include "ch.h"
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#include "hal.h"
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/*
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* Board file for HY-MiniSTM32V board from HAOYU (China).
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* www.powermcu.com or www.hotmcu.com.
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*/
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/**
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* @brief PAL setup.
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* @details Digital I/O ports static configuration as defined in @p board.h.
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* This variable is used by the HAL when initializing the PAL driver.
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*/
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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const PALConfig pal_default_config =
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{
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{VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
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{VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
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{VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
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{VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
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{VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
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{VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH},
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{VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH},
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};
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#endif
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/*
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* Early initialization code.
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* This initialization must be performed just after stack setup and before
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* any other initialization.
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*/
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void __early_init(void) {
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stm32_clock_init();
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}
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#if HAL_USE_MMC_SPI
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/*
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* Board-related functions related to the MMC_SPI driver.
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* Inserted when PD3 is low.
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*/
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bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
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(void)mmcp;
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return !palReadPad(GPIOD, GPIOD_SD_CD);
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}
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/*
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* No wp information available. Assume not protected
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*/
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bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
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(void)mmcp;
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return false;
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}
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#endif
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/*
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* Board-specific initialization code.
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*/
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void boardInit(void) {
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/* TIM3 partial remap for display BL_CNT on ch 2 (PB5). */
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AFIO->MAPR |= AFIO_MAPR_TIM3_REMAP_1;
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}
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@ -0,0 +1,277 @@
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/*
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ChibiOS/RT - Copyright (C) 2006-2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#ifndef _BOARD_H_
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#define _BOARD_H_
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/*
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* Board file for HY-MiniSTM32V board from HAOYU (China).
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* www.powermcu.com or www.hotmcu.com.
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*/
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/*
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* Board identifier.
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*/
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#define BOARD_HY_MINI_STM32V
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#define BOARD_NAME "HY-MiniSTM32V"
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/*
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* Board frequencies.
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*/
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#define STM32_LSECLK 32768
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#define STM32_HSECLK 8000000
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/*
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* MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
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*/
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#define STM32F10X_HD
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/*
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* IO pins assignments.
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*/
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#define GPIOA_PIN0 0
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#define GPIOA_PIN1 1
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#define GPIOA_PIN2 2
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#define GPIOA_PIN3 3
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#define GPIOA_TP_CS 4
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#define GPIOA_SPI_SCK 5
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#define GPIOA_SPI_MISO 6
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#define GPIOA_SPI_MOSI 7
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#define GPIOA_PIN8 8
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#define GPIOA_USART1_TX 9
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#define GPIOA_USART1_RX 10
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#define GPIOA_USB_DM 11
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#define GPIOA_USB_DP 12
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#define GPIOA_PIN13 13
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#define GPIOA_PIN14 14
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#define GPIOA_PIN15 15
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#define GPIOB_LED1 0
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#define GPIOB_LED2 1
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#define GPIOB_USER_KEYB 2
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#define GPIOB_PIN3 3
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#define GPIOB_PIN4 4
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#define GPIOB_BL_CNT 5
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#define GPIOB_TP_IRQ 6
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#define GPIOB_USB_EN 7
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#define GPIOB_PIN8 8
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#define GPIOB_PIN9 9
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#define GPIOB_PIN10 10
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#define GPIOB_PIN11 11
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#define GPIOB_PIN12 12
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#define GPIOB_PIN13 13
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#define GPIOB_PIN14 14
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#define GPIOB_PIN15 15
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#define GPIOC_PIN0 0
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#define GPIOC_PIN1 1
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#define GPIOC_PIN2 2
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#define GPIOC_PIN3 3
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#define GPIOC_PIN4 4
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#define GPIOC_PIN5 5
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#define GPIOC_PIN6 6
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#define GPIOC_PIN7 7
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#define GPIOC_SDIO_D0 8
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#define GPIOC_SDIO_D1 9
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#define GPIOC_SDIO_D2 10
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#define GPIOC_SDIO_D3 11
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#define GPIOC_SDIO_CK 12
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#define GPIOC_USER_KEYA 13
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#define GPIOC_PIN14 14
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#define GPIOC_PIN15 15
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#define GPIOD_FSMC_D2 0
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#define GPIOD_FSMC_D3 1
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#define GPIOD_SDIO_CMD 2
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#define GPIOD_SD_CD 3
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#define GPIOD_LCD_RD 4
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#define GPIOD_LCD_WR 5
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#define GPIOD_PIN6 6
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#define GPIOD_LCD_CS 7
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#define GPIOD_FSMC_D13 8
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#define GPIOD_FSMC_D14 9
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#define GPIOD_FSMC_D15 10
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#define GPIOD_LCD_RS 11
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#define GPIOD_PIN12 12
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#define GPIOD_PIN13 13
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#define GPIOD_FSMC_D0 14
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#define GPIOD_FSMC_D1 15
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#define GPIOE_PIN0 0
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#define GPIOE_PIN1 1
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#define GPIOE_PIN2 2
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#define GPIOE_PIN3 3
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#define GPIOE_PIN4 4
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#define GPIOE_PIN5 5
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#define GPIOE_PIN6 6
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#define GPIOE_FSMC_D4 7
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#define GPIOE_FSMC_D5 8
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#define GPIOE_FSMC_D6 9
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#define GPIOE_FSMC_D7 10
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#define GPIOE_FSMC_D8 11
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#define GPIOE_FSMC_D9 12
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#define GPIOE_FSMC_D10 13
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#define GPIOE_FSMC_D11 14
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#define GPIOE_FSMC_D12 15
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/*
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* I/O ports initial setup, this configuration is established soon after reset
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* in the initialization code.
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*
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* The digits have the following meaning:
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* 0 - Analog input.
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* 1 - Push Pull output 10MHz.
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* 2 - Push Pull output 2MHz.
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* 3 - Push Pull output 50MHz.
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* 4 - Digital input.
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* 5 - Open Drain output 10MHz.
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* 6 - Open Drain output 2MHz.
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* 7 - Open Drain output 50MHz.
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* 8 - Digital input with PullUp or PullDown resistor depending on ODR.
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* 9 - Alternate Push Pull output 10MHz.
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* A - Alternate Push Pull output 2MHz.
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* B - Alternate Push Pull output 50MHz.
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* C - Reserved.
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* D - Alternate Open Drain output 10MHz.
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* E - Alternate Open Drain output 2MHz.
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* F - Alternate Open Drain output 50MHz.
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* Please refer to the STM32 Reference Manual for details.
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*/
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/*
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* Port A setup.
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* Everything input with pull-up except:
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* PA4 - Push Pull output 50MHz (TP_CS)
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* PA5 - Alternate Push Pull output 50MHz (SPI_SCK)
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* PA6 - Digital input (SPI_MISO)
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* PA7 - Alternate Push Pull output 50MHz (SPI_MOSI)
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* PA9 - Alternate Push Pull output 50MHz (USART1_TX)
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* PA10 - Digital input (USART1_RX)
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* PA11 - Digital input (USB_DM)
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*/
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#define VAL_GPIOACRL 0xB4B38888 /* PA7...PA0 */
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#define VAL_GPIOACRH 0x888844B8 /* PA15...PA8 */
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#define VAL_GPIOAODR 0xFFFFFFFF
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/*
|
||||
* Port B setup.
|
||||
* Everything input with pull-up except:
|
||||
* PB0 - Push Pull output 50MHz (LED1)
|
||||
* PB1 - Push Pull output 50MHz (LED2)
|
||||
* PB2 - Digital input (USER_KEYB)
|
||||
* PB5 - Alternate Push Pull output 50MHz (BL_CNT)
|
||||
* PB6 - Digital input (TP_IRQ)
|
||||
* PB7 - Push Pull output 50MHz (init low) (USB_EN)
|
||||
*/
|
||||
|
||||
#define VAL_GPIOBCRL 0x34B88433 /* PB7...PB0 */
|
||||
#define VAL_GPIOBCRH 0x88888888 /* PB15...PB8 */
|
||||
#define VAL_GPIOBODR 0xFFFF7FFC
|
||||
|
||||
/*
|
||||
* Port C setup.
|
||||
* Everything input with pull-up except:
|
||||
* PC8 - Digital input (SDIO_D0)
|
||||
* PC9 - Digital input (SDIO_D1)
|
||||
* PC10 - Digital input (SDIO_D2)
|
||||
* PC11 - Digital input (SDIO_D3)
|
||||
* PC12 - Digital input (SDIO_CK)
|
||||
* PC13 - Digital input (GPIOC_USER_KEYA)
|
||||
*/
|
||||
#define VAL_GPIOCCRL 0x88888888 /* PC7...PC0 */
|
||||
#define VAL_GPIOCCRH 0x88444444 /* PC15...PC8 */
|
||||
#define VAL_GPIOCODR 0xFFFFFFFF
|
||||
|
||||
/*
|
||||
* Port D setup.
|
||||
* Everything input with pull-up except:
|
||||
* PD0 - Alternate Push Pull output 50MHz (FSMC_D2)
|
||||
* PD1 - Alternate Push Pull output 50MHz (FSMC_D1)
|
||||
* PD2 - Digital input (SDIO_CMD)
|
||||
* PD3 - Digital input (SD_CD)
|
||||
* PD4 - Alternate Push Pull output 50MHz (LCD_RD)
|
||||
* PD5 - Alternate Push Pull output 50MHz (LCD_WR)
|
||||
* PD7 - Alternate Push Pull output 50MHz (LCD_CS)
|
||||
* PD8 - Alternate Push Pull output 50MHz (FSMC_D13)
|
||||
* PD9 - Alternate Push Pull output 50MHz (FSMC_D14)
|
||||
* PD10 - Alternate Push Pull output 50MHz (FSMC_D15)
|
||||
* PD11 - Alternate Push Pull output 50MHz (LCD_RS)
|
||||
* PD14 - Alternate Push Pull output 50MHz (FSMC_D0)
|
||||
* PD15 - Alternate Push Pull output 50MHz (FSMC_D1)
|
||||
*/
|
||||
|
||||
#define VAL_GPIODCRL 0xB8BB44BB /* PD7...PD0 */
|
||||
#define VAL_GPIODCRH 0xBB88BBBB /* PD15...PD8 */
|
||||
#define VAL_GPIODODR 0xFFFFFFFF
|
||||
|
||||
/*
|
||||
* Port E setup.
|
||||
* Everything input with pull-up except:
|
||||
* PE7 - Alternate Push Pull output 50MHz (FSMC_D4)
|
||||
* PE8 - Alternate Push Pull output 50MHz (FSMC_D5)
|
||||
* PE9 - Alternate Push Pull output 50MHz (FSMC_D6)
|
||||
* PE10 - Alternate Push Pull output 50MHz (FSMC_D7)
|
||||
* PE11 - Alternate Push Pull output 50MHz (FSMC_D8)
|
||||
* PE12 - Alternate Push Pull output 50MHz (FSMC_D9)
|
||||
* PE13 - Alternate Push Pull output 50MHz (FSMC_D10)
|
||||
* PE14 - Alternate Push Pull output 50MHz (FSMC_D11)
|
||||
* PE15 - Alternate Push Pull output 50MHz (FSMC_D12)
|
||||
*/
|
||||
|
||||
#define VAL_GPIOECRL 0xB8888888 /* PE7...PE0 */
|
||||
#define VAL_GPIOECRH 0xBBBBBBBB /* PE15...PE8 */
|
||||
#define VAL_GPIOEODR 0xFFFFFFFF
|
||||
|
||||
/*
|
||||
* Port F setup.
|
||||
* Everything input with pull-up
|
||||
*/
|
||||
|
||||
#define VAL_GPIOFCRL 0x88888888 /* PF7...PE0 */
|
||||
#define VAL_GPIOFCRH 0x88888888 /* PF15...PE8 */
|
||||
#define VAL_GPIOFODR 0xFFFFFFFF
|
||||
|
||||
/*
|
||||
* Port G setup.
|
||||
* Everything input with pull-up
|
||||
*/
|
||||
|
||||
#define VAL_GPIOGCRL 0x88888888 /* PG7...PE0 */
|
||||
#define VAL_GPIOGCRH 0x88888888 /* PG15...PE8 */
|
||||
#define VAL_GPIOGODR 0xFFFFFFFF
|
||||
|
||||
/*
|
||||
* USB bus activation macro, required by the USB driver.
|
||||
*/
|
||||
#define usb_lld_connect_bus(usbp) palClearPad(GPIOB, GPIOB_USB_EN)
|
||||
|
||||
/*
|
||||
* USB bus de-activation macro, required by the USB driver.
|
||||
*/
|
||||
#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOB, GPIOB_USB_EN)
|
||||
|
||||
#if !defined(_FROM_ASM_)
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void boardInit(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _FROM_ASM_ */
|
||||
|
||||
#endif /* _BOARD_H_ */
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
BOARDINC = $(GFXLIB)/boards/base/HY-MiniSTM32V/chibios_board
|
||||
BOARDSRC = $(BOARDINC)/board.c \
|
||||
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* This file is subject to the terms of the GFX License. If a copy of
|
||||
* the license was not distributed with this file, you can obtain one at:
|
||||
*
|
||||
* http://ugfx.org/license.html
|
||||
*/
|
||||
|
||||
/*
|
||||
* Board file for HY-MiniSTM32V board from HAOYU (China).
|
||||
* www.powermcu.com or www.hotmcu.com.
|
||||
*/
|
||||
|
||||
/*
|
||||
* NOTE: In order to make this work you need to set:
|
||||
* STM32_SPI_USE_SPI1 TRUE in mcuconf.h
|
||||
* HAL_USE_SPI TRUE in halconf.h
|
||||
*/
|
||||
|
||||
#ifndef _GINPUT_LLD_MOUSE_BOARD_H
|
||||
#define _GINPUT_LLD_MOUSE_BOARD_H
|
||||
|
||||
// Resolution and Accuracy Settings
|
||||
#define GMOUSE_ADS7843_PEN_CALIBRATE_ERROR 8
|
||||
#define GMOUSE_ADS7843_PEN_CLICK_ERROR 6
|
||||
#define GMOUSE_ADS7843_PEN_MOVE_ERROR 4
|
||||
#define GMOUSE_ADS7843_FINGER_CALIBRATE_ERROR 14
|
||||
#define GMOUSE_ADS7843_FINGER_CLICK_ERROR 18
|
||||
#define GMOUSE_ADS7843_FINGER_MOVE_ERROR 14
|
||||
|
||||
// How much extra data to allocate at the end of the GMouse structure for the board's use
|
||||
#define BOARD_DATA_SIZE 0
|
||||
|
||||
static const SPIConfig spicfg = {
|
||||
0,
|
||||
GPIOA,
|
||||
GPIOA_TP_CS,
|
||||
SPI_CR1_BR_1 | SPI_CR1_BR_0, /* Might be tweaked for faster transfer. */
|
||||
};
|
||||
|
||||
/*
|
||||
* ADS7843 (clone chip) is connected to SPI1 w/o remap
|
||||
* TP_CS PA4
|
||||
* SPI_SCK PA5
|
||||
* SPI_MISO PA6
|
||||
* SPI_MOSI PA7
|
||||
* TP_IRQ PB6
|
||||
*/
|
||||
|
||||
static bool_t init_board(GMouse* m, unsigned driverinstance) {
|
||||
(void) m;
|
||||
(void) driverinstance;
|
||||
|
||||
palSetPadMode(GPIOA, 4, PAL_MODE_OUTPUT_PUSHPULL);
|
||||
palSetPadMode(GPIOA, 5, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
|
||||
palSetPadMode(GPIOA, 6, PAL_MODE_INPUT_PULLUP);
|
||||
palSetPadMode(GPIOA, 7, PAL_MODE_STM32_ALTERNATE_PUSHPULL);
|
||||
palSetPadMode(GPIOB, 6, PAL_MODE_INPUT);
|
||||
|
||||
spiStart(&SPID1, &spicfg);
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* PB6 is connected to TP_IRQ (low active).
|
||||
*/
|
||||
static inline bool_t getpin_pressed(GMouse* m) {
|
||||
(void)m;
|
||||
return (!palReadPad(GPIOB, 6));
|
||||
}
|
||||
|
||||
/*
|
||||
* PA4 is connected to TP_CS (low active):
|
||||
*/
|
||||
static inline void aquire_bus(GMouse* m) {
|
||||
(void)m;
|
||||
spiAcquireBus(&SPID1);
|
||||
palClearPad(GPIOA, 4);
|
||||
}
|
||||
|
||||
static inline void release_bus(GMouse* m) {
|
||||
(void)m;
|
||||
palSetPad(GPIOA, 4);
|
||||
spiReleaseBus(&SPID1);
|
||||
}
|
||||
|
||||
static inline uint16_t read_value(GMouse* m, uint16_t port) {
|
||||
(void)m;
|
||||
static uint8_t txbuf[3] = {0};
|
||||
static uint8_t rxbuf[3] = {0};
|
||||
uint16_t ret;
|
||||
|
||||
txbuf[0] = port;
|
||||
spiExchange(&SPID1, 3, txbuf, rxbuf);
|
||||
ret = (rxbuf[1] << 5) | (rxbuf[2] >> 3);
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif /* _GINPUT_LLD_MOUSE_BOARD_H */
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
This directory contains the interface for the HY-MiniSTM32V board
|
||||
running ChibiOS/RT.
|
||||
|
||||
As this is not a standard ChibiOS/RT supported board, the necessary board files have
|
||||
also been provided in the chibios_board directory
|
||||
|
||||
Loading…
Reference in New Issue