From 5a1f527fcfa9e6bd69517be78481dc7688cb6522 Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Fri, 10 Jul 2015 14:50:12 +0200 Subject: [PATCH] working on the LTDC driver (not done yet and also hacky code) --- boards/base/STM32F746-Discovery/board_STM32LTDC.h | 8 +++++--- drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c | 2 +- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/boards/base/STM32F746-Discovery/board_STM32LTDC.h b/boards/base/STM32F746-Discovery/board_STM32LTDC.h index 33f6e2cb..53940ad2 100644 --- a/boards/base/STM32F746-Discovery/board_STM32LTDC.h +++ b/boards/base/STM32F746-Discovery/board_STM32LTDC.h @@ -12,6 +12,8 @@ #include "stm32f746g_discovery_sdram.h" #include +#include "RGB565_480x272.h" + static const ltdcConfig driverCfg = { 480, 270, // Width, Height (pixels) 41, 10, // Horizontal, Vertical sync (pixels) @@ -21,7 +23,7 @@ static const ltdcConfig driverCfg = { 0x000000, // Clear color (RGB888) { // Background layer config - (LLDCOLOR_TYPE *)SDRAM_BANK_ADDR, // Frame buffer address + (LLDCOLOR_TYPE *)RGB565_480x272, // Frame buffer address 480, 270, // Width, Height (pixels) 480 * LTDC_PIXELBYTES, // Line pitch (bytes) LTDC_PIXELFORMAT, // Pixel format @@ -60,14 +62,14 @@ static inline void init_board(GDisplay *g) { /* PLLSAI activation.*/ RCC->PLLSAICFGR = (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24); - RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST; + RCC->DCKCFGR1 = (RCC->DCKCFGR1 & ~RCC_DCKCFGR1_PLLSAIDIVR) | STM32_PLLSAIR_POST; RCC->CR |= RCC_CR_PLLSAION; // Initialise the SDRAM SDRAM_Init(); // Clear the SDRAM - memset((void *)SDRAM_BANK_ADDR, 0, 0x400000); + //memset((void *)SDRAM_BANK_ADDR, 0, 0x400000); break; } diff --git a/drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c b/drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c index 118b6874..a6a185ee 100644 --- a/drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c +++ b/drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c @@ -153,7 +153,7 @@ static void LTDC_Init(void) RCC->APB2RSTR = 0; /* Enable the LTDC clock.*/ - RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | (1 << 16); /* /4 */ + RCC->DCKCFGR1 = (RCC->DCKCFGR1 & ~RCC_DCKCFGR1_PLLSAIDIVR) | (1 << 16); /* /4 */ // Enable the module RCC->APB2ENR |= RCC_APB2ENR_LTDCEN;