Updates to STM32F746-Discovery support
Clean out a lot of junk
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3 changed files with 10 additions and 381 deletions
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@ -1,5 +1,4 @@
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GFXINC += $(GFXLIB)/boards/base/STM32F746-Discovery \
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$(STMHAL)/Inc
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GFXINC += $(GFXLIB)/boards/base/STM32F746-Discovery
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GFXSRC += $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c \
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$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f7_i2c.c
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@ -1,68 +1,4 @@
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/**
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******************************************************************************
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* @file system_stm32f7xx.c
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* @author MCD Application Team
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* @version V1.0.0
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* @date 25-June-2015
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* @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
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*
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* This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32f7xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32f7xx_system
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* @{
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*/
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/** @addtogroup STM32F7xx_System_Private_Includes
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* @{
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*/
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#include "gfx.h"
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#include "stm32f7xx.h"
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#if !defined (HSE_VALUE)
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@ -73,85 +9,18 @@
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#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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/**
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* @}
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*/
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/** @addtogroup STM32F7xx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F7xx_System_Private_Defines
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* @{
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*/
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/************************* Miscellaneous Configuration ************************/
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/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
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on EVAL board as data memory */
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/* #define DATA_IN_ExtSRAM */
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/* #define DATA_IN_ExtSDRAM */
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#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
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#error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
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#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/******************************************************************************/
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/**
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* @}
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*/
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#if !GFX_USE_OS_CHIBIOS
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uint32_t SystemCoreClock = HSI_VALUE;
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#endif
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/** @addtogroup STM32F7xx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F7xx_System_Private_Variables
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* @{
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*/
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/* This variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = 16000000;
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__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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/**
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* @}
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*/
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/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
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* @{
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*/
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#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
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static void SystemInit_ExtMemCtl(void);
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#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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/**
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* @}
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*/
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/** @addtogroup STM32F7xx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system
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* Initialize the Embedded Flash Interface, the PLL and update the
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@ -186,10 +55,6 @@ void SystemInit(void)
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/* Disable all interrupts */
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RCC->CIR = 0x00000000;
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#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
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SystemInit_ExtMemCtl();
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#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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@ -282,225 +147,3 @@ void SystemCoreClockUpdate(void)
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SystemCoreClock >>= tmp;
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}
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#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
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/**
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* @brief Setup the external memory controller.
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* Called in startup_stm32f7xx.s before jump to main.
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* This function configures the external memories (SRAM/SDRAM)
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* This SRAM/SDRAM will be used as program data memory (including heap and stack).
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* @param None
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* @retval None
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*/
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void SystemInit_ExtMemCtl(void)
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{
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#if defined (DATA_IN_ExtSDRAM)
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register uint32_t tmpreg = 0, timeout = 0xFFFF;
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register uint32_t index;
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/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
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clock */
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RCC->AHB1ENR |= 0x000001F8;
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/* Connect PDx pins to FMC Alternate function */
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GPIOD->AFR[0] = 0x000000CC;
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GPIOD->AFR[1] = 0xCC000CCC;
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/* Configure PDx pins in Alternate function mode */
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GPIOD->MODER = 0xA02A000A;
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/* Configure PDx pins speed to 50 MHz */
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GPIOD->OSPEEDR = 0xA02A000A;
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/* Configure PDx pins Output type to push-pull */
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GPIOD->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PDx pins */
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GPIOD->PUPDR = 0x00000000;
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/* Connect PEx pins to FMC Alternate function */
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GPIOE->AFR[0] = 0xC00000CC;
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GPIOE->AFR[1] = 0xCCCCCCCC;
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/* Configure PEx pins in Alternate function mode */
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GPIOE->MODER = 0xAAAA800A;
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/* Configure PEx pins speed to 50 MHz */
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GPIOE->OSPEEDR = 0xAAAA800A;
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/* Configure PEx pins Output type to push-pull */
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GPIOE->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PEx pins */
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GPIOE->PUPDR = 0x00000000;
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/* Connect PFx pins to FMC Alternate function */
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GPIOF->AFR[0] = 0xCCCCCCCC;
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GPIOF->AFR[1] = 0xCCCCCCCC;
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/* Configure PFx pins in Alternate function mode */
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GPIOF->MODER = 0xAA800AAA;
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/* Configure PFx pins speed to 50 MHz */
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GPIOF->OSPEEDR = 0xAA800AAA;
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/* Configure PFx pins Output type to push-pull */
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GPIOF->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PFx pins */
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GPIOF->PUPDR = 0x00000000;
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/* Connect PGx pins to FMC Alternate function */
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GPIOG->AFR[0] = 0xCCCCCCCC;
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GPIOG->AFR[1] = 0xCCCCCCCC;
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/* Configure PGx pins in Alternate function mode */
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GPIOG->MODER = 0xAAAAAAAA;
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/* Configure PGx pins speed to 50 MHz */
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GPIOG->OSPEEDR = 0xAAAAAAAA;
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/* Configure PGx pins Output type to push-pull */
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GPIOG->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PGx pins */
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GPIOG->PUPDR = 0x00000000;
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/* Connect PHx pins to FMC Alternate function */
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GPIOH->AFR[0] = 0x00C0CC00;
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GPIOH->AFR[1] = 0xCCCCCCCC;
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/* Configure PHx pins in Alternate function mode */
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GPIOH->MODER = 0xAAAA08A0;
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/* Configure PHx pins speed to 50 MHz */
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GPIOH->OSPEEDR = 0xAAAA08A0;
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/* Configure PHx pins Output type to push-pull */
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GPIOH->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PHx pins */
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GPIOH->PUPDR = 0x00000000;
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/* Connect PIx pins to FMC Alternate function */
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GPIOI->AFR[0] = 0xCCCCCCCC;
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GPIOI->AFR[1] = 0x00000CC0;
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/* Configure PIx pins in Alternate function mode */
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GPIOI->MODER = 0x0028AAAA;
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/* Configure PIx pins speed to 50 MHz */
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GPIOI->OSPEEDR = 0x0028AAAA;
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/* Configure PIx pins Output type to push-pull */
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GPIOI->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PIx pins */
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GPIOI->PUPDR = 0x00000000;
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/*-- FMC Configuration ------------------------------------------------------*/
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/* Enable the FMC interface clock */
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RCC->AHB3ENR |= 0x00000001;
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/* Configure and enable SDRAM bank1 */
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FMC_Bank5_6->SDCR[0] = 0x000019E0;
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FMC_Bank5_6->SDTR[0] = 0x01115351;
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/* SDRAM initialization sequence */
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/* Clock enable command */
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FMC_Bank5_6->SDCMR = 0x00000011;
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tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
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while((tmpreg != 0) && (timeout-- > 0))
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{
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tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
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}
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/* Delay */
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for (index = 0; index<1000; index++);
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/* PALL command */
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FMC_Bank5_6->SDCMR = 0x00000012;
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timeout = 0xFFFF;
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while((tmpreg != 0) && (timeout-- > 0))
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{
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tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
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}
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/* Auto refresh command */
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FMC_Bank5_6->SDCMR = 0x00000073;
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timeout = 0xFFFF;
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while((tmpreg != 0) && (timeout-- > 0))
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{
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tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
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}
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/* MRD register program */
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FMC_Bank5_6->SDCMR = 0x00046014;
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timeout = 0xFFFF;
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while((tmpreg != 0) && (timeout-- > 0))
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{
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tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
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}
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/* Set refresh count */
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tmpreg = FMC_Bank5_6->SDRTR;
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FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
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/* Disable write protection */
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tmpreg = FMC_Bank5_6->SDCR[0];
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FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
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#endif /* DATA_IN_ExtSDRAM */
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#if defined(DATA_IN_ExtSRAM)
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/*-- GPIOs Configuration -----------------------------------------------------*/
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/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
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RCC->AHB1ENR |= 0x00000078;
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/* Connect PDx pins to FMC Alternate function */
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GPIOD->AFR[0] = 0x00CCC0CC;
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GPIOD->AFR[1] = 0xCCCCCCCC;
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/* Configure PDx pins in Alternate function mode */
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GPIOD->MODER = 0xAAAA0A8A;
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/* Configure PDx pins speed to 100 MHz */
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GPIOD->OSPEEDR = 0xFFFF0FCF;
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/* Configure PDx pins Output type to push-pull */
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GPIOD->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PDx pins */
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GPIOD->PUPDR = 0x00000000;
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/* Connect PEx pins to FMC Alternate function */
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GPIOE->AFR[0] = 0xC00CC0CC;
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GPIOE->AFR[1] = 0xCCCCCCCC;
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/* Configure PEx pins in Alternate function mode */
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GPIOE->MODER = 0xAAAA828A;
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/* Configure PEx pins speed to 100 MHz */
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GPIOE->OSPEEDR = 0xFFFFC3CF;
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/* Configure PEx pins Output type to push-pull */
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GPIOE->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PEx pins */
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GPIOE->PUPDR = 0x00000000;
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/* Connect PFx pins to FMC Alternate function */
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GPIOF->AFR[0] = 0x00CCCCCC;
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GPIOF->AFR[1] = 0xCCCC0000;
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/* Configure PFx pins in Alternate function mode */
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GPIOF->MODER = 0xAA000AAA;
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/* Configure PFx pins speed to 100 MHz */
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GPIOF->OSPEEDR = 0xFF000FFF;
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/* Configure PFx pins Output type to push-pull */
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GPIOF->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PFx pins */
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GPIOF->PUPDR = 0x00000000;
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/* Connect PGx pins to FMC Alternate function */
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GPIOG->AFR[0] = 0x00CCCCCC;
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GPIOG->AFR[1] = 0x000000C0;
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/* Configure PGx pins in Alternate function mode */
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GPIOG->MODER = 0x00085AAA;
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/* Configure PGx pins speed to 100 MHz */
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GPIOG->OSPEEDR = 0x000CAFFF;
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/* Configure PGx pins Output type to push-pull */
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GPIOG->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PGx pins */
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GPIOG->PUPDR = 0x00000000;
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/*-- FMC/FSMC Configuration --------------------------------------------------*/
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/* Enable the FMC/FSMC interface clock */
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RCC->AHB3ENR |= 0x00000001;
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/* Configure and enable Bank1_SRAM2 */
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FMC_Bank1->BTCR[2] = 0x00001011;
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FMC_Bank1->BTCR[3] = 0x00000201;
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FMC_Bank1E->BWTR[2] = 0x0fffffff;
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#endif /* DATA_IN_ExtSRAM */
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}
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#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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@ -19,8 +19,10 @@ static void SystemClock_Config(void);
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static void CPU_CACHE_Enable(void);
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void Raw32OSInit(void) {
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/* Enable the CPU Cache */
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CPU_CACHE_Enable();
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/* Enable the CPU Cache's */
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SCB_EnableICache(); // Enable I-Cache
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SCB_EnableDCache(); // Enable D-Cache
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/* STM32F7xx HAL library initialization:
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- Configure the Flash ART accelerator on ITCM interface
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@ -106,18 +108,3 @@ void SystemClock_Config(void)
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HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
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}
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/**
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* @brief CPU L1-Cache enable.
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* @param None
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* @retval None
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*/
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static void CPU_CACHE_Enable(void)
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{
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/* Enable I-Cache */
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SCB_EnableICache();
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/* Enable D-Cache */
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SCB_EnableDCache();
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}
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