Adding GPIO to SSD1963
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mobyfab
parent
f47bbcb9a7
commit
75a3a98228
2 changed files with 112 additions and 36 deletions
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@ -29,7 +29,6 @@
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#include "ch.h"
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#include "hal.h"
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#include "gdisp.h"
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#include "ssd1963.h"
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#if HAL_USE_GDISP || defined(__DOXYGEN__)
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@ -74,11 +73,10 @@
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/* Driver exported functions. */
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/*===========================================================================*/
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/* ---- Required Routines ---- */
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/*
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The following 2 routines are required.
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All other routines are optional.
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*/
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#include "ssd1963.h"
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#if defined(LCD_USE_FSMC)
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__inline void GDISP_LLD(writeindex)(uint8_t cmd) {
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LCD_REG = cmd;
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}
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@ -102,11 +100,11 @@ __inline uint8_t GDISP_LLD(readreg)(uint8_t lcdReg) {
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}
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__inline void GDISP_LLD(writestreamstart)(void) {
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LCD_REG = SSD1963_WRITE_MEMORY_START;
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GDISP_LLD(writeindex)(SSD1963_WRITE_MEMORY_START);
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}
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__inline void GDISP_LLD(readstreamstart)(void) {
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LCD_REG = SSD1963_READ_MEMORY_START;
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GDISP_LLD(writeindex)(SSD1963_READ_MEMORY_START);
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}
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__inline void GDISP_LLD(writestream)(uint16_t *buffer, uint16_t size) {
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@ -122,6 +120,80 @@ __inline void GDISP_LLD(readstream)(uint16_t *buffer, size_t size) {
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buffer[i] = LCD_RAM;
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}
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}
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#elif defined(LCD_USE_GPIO)
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__inline void GDISP_LLD(writeindex)(uint8_t cmd) {
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Set_CS; Set_RS; Set_WR; Clr_RD;
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palWritePort(LCD_DATA_PORT, cmd);
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Clr_CS;
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}
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__inline void GDISP_LLD(writereg)(uint16_t lcdReg,uint16_t lcdRegValue) {
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Set_CS; Set_RS; Set_WR; Clr_RD;
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palWritePort(LCD_DATA_PORT, lcdReg);
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Clr_RS;
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palWritePort(LCD_DATA_PORT, lcdRegValue);
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Clr_CS;
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}
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__inline void GDISP_LLD(writedata)(uint16_t data) {
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Set_CS; Clr_RS; Set_WR; Clr_RD;
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palWritePort(LCD_DATA_PORT, data);
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Clr_CS;
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}
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__inline uint16_t GDISP_LLD(readdata)(void) {
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Set_CS; Clr_RS; Clr_WR; Set_RD;
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uint16_t data = palReadPort(LCD_DATA_PORT);
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Clr_CS;
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return data;
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}
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__inline uint8_t GDISP_LLD(readreg)(uint8_t lcdReg) {
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Set_CS; Set_RS; Clr_WR; Set_RD;
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palWritePort(LCD_DATA_PORT, lcdReg);
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Clr_RS;
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uint16_t data = palReadPort(LCD_DATA_PORT);
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Clr_CS;
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return data;
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}
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__inline void GDISP_LLD(writestreamstart)(void) {
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GDISP_LLD(writeindex)(SSD1963_WRITE_MEMORY_START);
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}
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__inline void GDISP_LLD(readstreamstart)(void) {
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GDISP_LLD(writeindex)(SSD1963_READ_MEMORY_START);
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}
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__inline void GDISP_LLD(writestream)(uint16_t *buffer, uint16_t size) {
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uint16_t i;
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Set_CS; Clr_RS; Set_WR; Clr_RD;
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for(i = 0; i < size; i++) {
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Set_WR;
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palWritePort(LCD_DATA_PORT, buffer[i]);
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Clr_WR;
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}
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Clr_CS;
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}
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__inline void GDISP_LLD(readstream)(uint16_t *buffer, size_t size) {
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uint16_t i;
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Set_CS; Clr_RS; Clr_WR; Set_RD;
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for(i = 0; i < size; i++) {
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Set_RD;
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buffer[i] = palReadPort(LCD_DATA_PORT);
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Clr_RD;
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}
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}
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#endif
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/* ---- Required Routines ---- */
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/*
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The following 2 routines are required.
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All other routines are optional.
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*/
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/**
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* @brief Low level GDISP driver initialisation.
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* @return TRUE if successful, FALSE on error.
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@ -139,17 +211,19 @@ bool_t GDISP_LLD(init)(void) {
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GDISP.Backlight = 100;
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GDISP.Contrast = 50;
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#ifdef LCD_USE_FSMC
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#if defined(LCD_USE_FSMC)
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#if defined(STM32F1XX)
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/* FSMC setup. TODO: this only works for STM32F1 */
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#if defined(STM32F1XX) || defined(STM32F3XX)
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/* FSMC setup for F1/F3 */
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rccEnableAHB(RCC_AHBENR_FSMCEN, 0);
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/* TODO: pin setup */
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#elif defined(STM32F4XX)
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/* STM32F4 FSMC init */
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#elif defined(STM32F4XX) || defined(STM32F2XX)
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/* STM32F2-F4 FSMC init */
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rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0);
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#else
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#error "FSMC not implemented for this device"
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#endif
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/* set pins to FSMC mode */
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IOBus busD = {GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) | (1 << 7) | (1 << 8) |
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(1 << 9) | (1 << 10) | (1 << 11) | (1 << 14) | (1 << 15), 0};
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@ -159,10 +233,8 @@ bool_t GDISP_LLD(init)(void) {
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palSetBusMode(&busD, PAL_MODE_ALTERNATE(12));
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palSetBusMode(&busE, PAL_MODE_ALTERNATE(12));
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#else
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#error "FSMC not implemented for this device"
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#endif
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const int FSMC_Bank = 0;
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const unsigned char FSMC_Bank = 0;
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/* FSMC timing */
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FSMC_Bank1->BTCR[FSMC_Bank+1] = (FSMC_BTR1_ADDSET_1 | FSMC_BTR1_ADDSET_3) \
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| (FSMC_BTR1_DATAST_1 | FSMC_BTR1_DATAST_3) \
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@ -171,9 +243,18 @@ bool_t GDISP_LLD(init)(void) {
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/* Bank1 NOR/SRAM control register configuration
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* This is actually not needed as already set by default after reset */
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FSMC_Bank1->BTCR[FSMC_Bank] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
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#endif
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GDISP_LLD(writeindex)(SSD1963_SOFT_RESET); chThdSleepMicroseconds(100);
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#elif defined(LCD_USE_GPIO)
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IOBus busCMD = {LCD_CMD_PORT, (1 << LCD_CS) | (1 << LCD_RS) | (1 << LCD_WR) | (1 << LCD_RD), 0};
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IOBus busDATA = {LCD_CMD_PORT, 0xFFFFF, 0};
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palSetBusMode(&busCMD, PAL_MODE_OUTPUT_PUSHPULL);
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palSetBusMode(&busDATA, PAL_MODE_OUTPUT_PUSHPULL);
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#else
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#error "Please define LCD_USE_FSMC or LCD_USE_GPIO"
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#endif
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GDISP_LLD(writeindex)(SSD1963_SOFT_RESET);
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chThdSleepMicroseconds(100);
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/* Driver PLL config */
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GDISP_LLD(writeindex)(SSD1963_SET_PLL_MN);
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@ -189,7 +270,8 @@ bool_t GDISP_LLD(init)(void) {
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GDISP_LLD(writedata)(0x03);
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chThdSleepMicroseconds(200);
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GDISP_LLD(writeindex)(SSD1963_SOFT_RESET); chThdSleepMicroseconds(100);
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GDISP_LLD(writeindex)(SSD1963_SOFT_RESET);
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chThdSleepMicroseconds(100);
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/* Screen size */
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GDISP_LLD(writeindex)(SSD1963_SET_LCD_MODE);
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@ -236,9 +318,9 @@ bool_t GDISP_LLD(init)(void) {
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/* Turn on */
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GDISP_LLD(writeindex)(SSD1963_SET_DISPLAY_ON);
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#ifdef LCD_USE_FSMC
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#if defined(LCD_USE_FSMC)
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/* FSMC delay reduced as the controller now runs at full speed */
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FSMC_Bank1->BTCR[FSMC_Bank+1] = FSMC_BTR1_ADDSET_0 | (FSMC_BTR1_DATAST_2 | FSMC_BTR1_DATAST_0) | FSMC_BTR1_BUSTURN_0 ;
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FSMC_Bank1->BTCR[FSMC_Bank+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_1 | FSMC_BTR1_BUSTURN_0 ;
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FSMC_Bank1->BTCR[FSMC_Bank] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
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#endif
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@ -31,7 +31,7 @@
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#include "gdisp_lld_panel.h"
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#ifdef LCD_USE_GPIO
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#if defined(LCD_USE_GPIO)
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#define Set_CS palSetPad(LCD_CMD_PORT, LCD_CS);
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#define Clr_CS palClearPad(LCD_CMD_PORT, LCD_CS);
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#define Set_RS palSetPad(LCD_CMD_PORT, LCD_RS);
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@ -42,16 +42,10 @@
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#define Clr_RD palClearPad(LCD_CMD_PORT, LCD_RD);
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#endif
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#ifdef LCD_USE_SPI
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/* TODO */
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#endif
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#ifdef LCD_USE_FSMC
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/* Using FSMC A16 as RS */
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#define LCD_REG (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
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#define LCD_RAM (*((volatile uint16_t *) 0x60020000)) /* RS = 1 */
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#if defined(LCD_USE_FSMC)
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/* Using FSMC A16 as RS */
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#define LCD_REG (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
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#define LCD_RAM (*((volatile uint16_t *) 0x60020000)) /* RS = 1 */
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#endif
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#define mHIGH(x) (x >> 8)
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