SSD2119: make use of DMA
This is mostly a copy from Eddie's work posted here: http://forum.chibios.org/phpbb/viewtopic.php?f=11&t=851#p11054 No work was done towards making it work as fast as possible. Tested with: https://github.com/etmatrix/ChibiOS-GFX-Example/blob/master/bench/main.c Results show performance of ~5.34 Mpx/s with use of DMA compared to ~4.78 Mpx/s without.ugfx_release_2.6
Mateusz Tomaszkiewicz
parent
b28eb3eefd
commit
767188ed8d
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@ -240,13 +240,13 @@ bool_t gdisp_lld_init(void) {
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write_reg(SSD2119_REG_Y_RAM_ADDR, 0x00);
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delay(5);
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// Release the bus
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// Release the bus
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release_bus();
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/* Turn on the backlight */
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set_backlight(GDISP_INITIAL_BACKLIGHT);
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/* Initialise the GDISP structure */
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/* Initialise the GDISP structure */
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GDISP.Width = GDISP_SCREEN_WIDTH;
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GDISP.Height = GDISP_SCREEN_HEIGHT;
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GDISP.Orientation = GDISP_ROTATE_0;
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@ -309,14 +309,33 @@ void gdisp_lld_draw_pixel(coord_t x, coord_t y, color_t color) {
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* @notapi
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*/
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void gdisp_lld_clear(color_t color) {
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unsigned i;
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unsigned area;
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area = GDISP_SCREEN_WIDTH * GDISP_SCREEN_HEIGHT;
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acquire_bus();
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reset_viewport();
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set_cursor(0, 0);
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stream_start();
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for(i = 0; i < GDISP_SCREEN_WIDTH * GDISP_SCREEN_HEIGHT; i++)
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write_data(color);
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#if defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM)
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uint8_t i;
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dmaStreamSetPeripheral(GDISP_DMA_STREAM, &color);
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dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
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for (i = area / 65535; i; i--) {
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dmaStreamSetTransactionSize(GDISP_DMA_STREAM, 65535);
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dmaStreamEnable(GDISP_DMA_STREAM);
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dmaWaitCompletion(GDISP_DMA_STREAM);
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}
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dmaStreamSetTransactionSize(GDISP_DMA_STREAM, area % 65535);
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dmaStreamEnable(GDISP_DMA_STREAM);
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dmaWaitCompletion(GDISP_DMA_STREAM);
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#else
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uint32_t index;
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for(index = 0; index < area; index++)
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write_data(color);
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#endif // defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM)
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stream_stop();
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release_bus();
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}
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@ -334,7 +353,7 @@ void gdisp_lld_draw_pixel(coord_t x, coord_t y, color_t color) {
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* @notapi
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*/
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void gdisp_lld_fill_area(coord_t x, coord_t y, coord_t cx, coord_t cy, color_t color) {
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unsigned i, area;
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unsigned area;
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#if GDISP_NEED_VALIDATION || GDISP_NEED_CLIP
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if (x < GDISP.clipx0) { cx -= GDISP.clipx0 - x; x = GDISP.clipx0; }
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@ -349,8 +368,25 @@ void gdisp_lld_draw_pixel(coord_t x, coord_t y, color_t color) {
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acquire_bus();
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set_viewport(x, y, cx, cy);
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stream_start();
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for(i = 0; i < area; i++)
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write_data(color);
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#if defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM)
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uint8_t i;
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dmaStreamSetPeripheral(GDISP_DMA_STREAM, &color);
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dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
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for (i = area / 65535; i; i--) {
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dmaStreamSetTransactionSize(GDISP_DMA_STREAM, 65535);
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dmaStreamEnable(GDISP_DMA_STREAM);
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dmaWaitCompletion(GDISP_DMA_STREAM);
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}
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dmaStreamSetTransactionSize(GDISP_DMA_STREAM, area % 65535);
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dmaStreamEnable(GDISP_DMA_STREAM);
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dmaWaitCompletion(GDISP_DMA_STREAM);
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#else
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uint32_t index;
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for(index = 0; index < area; index++)
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write_data(color);
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#endif // defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM)
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stream_stop();
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release_bus();
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}
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@ -370,8 +406,6 @@ void gdisp_lld_draw_pixel(coord_t x, coord_t y, color_t color) {
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* @notapi
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*/
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void gdisp_lld_blit_area_ex(coord_t x, coord_t y, coord_t cx, coord_t cy, coord_t srcx, coord_t srcy, coord_t srccx, const pixel_t *buffer) {
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coord_t endx, endy;
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unsigned lg;
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#if GDISP_NEED_VALIDATION || GDISP_NEED_CLIP
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if (x < GDISP.clipx0) { cx -= GDISP.clipx0 - x; srcx += GDISP.clipx0 - x; x = GDISP.clipx0; }
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@ -382,17 +416,36 @@ void gdisp_lld_draw_pixel(coord_t x, coord_t y, color_t color) {
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if (y+cy > GDISP.clipy1) cy = GDISP.clipy1 - y;
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#endif
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buffer += srcx + srcy * srccx;
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acquire_bus();
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set_viewport(x, y, cx, cy);
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stream_start();
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endx = srcx + cx;
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endy = y + cy;
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lg = srccx - cx;
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buffer += srcx + srcy * srccx;
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for(; y < endy; y++, buffer += lg)
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for(x=srcx; x < endx; x++)
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write_data(*buffer++);
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#if defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM)
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uint32_t area = cx * cy;
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uint8_t i;
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dmaStreamSetPeripheral(GDISP_DMA_STREAM, buffer);
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dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PINC | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
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for (i = area / 65535; i; i--) {
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dmaStreamSetTransactionSize(GDISP_DMA_STREAM, 65535);
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dmaStreamEnable(GDISP_DMA_STREAM);
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dmaWaitCompletion(GDISP_DMA_STREAM);
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}
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dmaStreamSetTransactionSize(GDISP_DMA_STREAM, area % 65535);
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dmaStreamEnable(GDISP_DMA_STREAM);
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dmaWaitCompletion(GDISP_DMA_STREAM);
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#else
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coord_t endx, endy;
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uint32_t lg;
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endx = srcx + cx;
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endy = y + cy;
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lg = srccx - cx;
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for(; y < endy; y++, buffer += lg)
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for(x=srcx; x < endx; x++)
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write_data(*buffer++);
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#endif // defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM)
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stream_stop();
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release_bus();
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}
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@ -418,8 +471,16 @@ void gdisp_lld_draw_pixel(coord_t x, coord_t y, color_t color) {
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acquire_bus();
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set_cursor(x, y);
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stream_start();
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color = read_data(); // dummy read
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/* FSMC timing */
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FSMC_Bank1->BTCR[FSMC_Bank + 1] = FSMC_BTR1_ADDSET_3 | FSMC_BTR1_DATAST_3 | FSMC_BTR1_BUSTURN_0;
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color = read_data(); // dummy read
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color = read_data();
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/* FSMC timing */
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FSMC_Bank1->BTCR[FSMC_Bank + 1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0;
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stream_stop();
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release_bus();
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@ -450,8 +511,8 @@ void gdisp_lld_draw_pixel(coord_t x, coord_t y, color_t color) {
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if (x < GDISP.clipx0) { cx -= GDISP.clipx0 - x; x = GDISP.clipx0; }
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if (y < GDISP.clipy0) { cy -= GDISP.clipy0 - y; y = GDISP.clipy0; }
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if (!lines || cx <= 0 || cy <= 0 || x >= GDISP.clipx1 || y >= GDISP.clipy1) return;
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if (x+cx > GDISP.clipx1) cx = GDISP.clipx1 - x;
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if (y+cy > GDISP.clipy1) cy = GDISP.clipy1 - y;
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if (x+cx > GDISP.clipx1) cx = GDISP.clipx1 - x;
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if (y+cy > GDISP.clipy1) cy = GDISP.clipy1 - y;
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#endif
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abslines = lines < 0 ? -lines : lines;
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@ -474,9 +535,17 @@ void gdisp_lld_draw_pixel(coord_t x, coord_t y, color_t color) {
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/* read row0 into the buffer and then write at row1*/
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set_viewport(x, row0, cx, 1);
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stream_start();
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j = read_data(); // dummy read
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/* FSMC timing */
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FSMC_Bank1->BTCR[FSMC_Bank + 1] = FSMC_BTR1_ADDSET_3 | FSMC_BTR1_DATAST_3 | FSMC_BTR1_BUSTURN_0;
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j = read_data(); // dummy read
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for (j = 0; (coord_t)j < cx; j++)
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buf[j] = read_data();
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/* FSMC timing */
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FSMC_Bank1->BTCR[FSMC_Bank + 1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0;
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stream_stop();
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set_viewport(x, row1, cx, 1);
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@ -16,38 +16,60 @@
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#ifndef _GDISP_LLD_BOARD_H
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#define _GDISP_LLD_BOARD_H
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#define GDISP_USE_DMA
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#define GDISP_DMA_STREAM STM32_DMA2_STREAM6
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/* Using FSMC A19 (PE3) as DC */
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#define GDISP_REG (*((volatile uint16_t *) 0x60000000)) /* DC = 0 */
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#define GDISP_RAM (*((volatile uint16_t *) 0x60100000)) /* DC = 1 */
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#define GDISP_REG (*((volatile uint16_t *) 0x60000000)) /* DC = 0 */
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#define GDISP_RAM (*((volatile uint16_t *) 0x60100000)) /* DC = 1 */
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#define SET_RST palSetPad(GPIOD, 3);
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#define CLR_RST palClearPad(GPIOD, 3);
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#define SET_RST palSetPad(GPIOD, 3);
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#define CLR_RST palClearPad(GPIOD, 3);
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/* PWM configuration structure. We use timer 4 channel 2 (orange LED on board). */
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const unsigned char FSMC_Bank = 0;
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/*
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* PWM configuration structure. We use timer 4 channel 2 (orange LED on board).
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* The reason for so high clock is that with any lower, onboard coil is squeaking.
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* The major disadvantage of this clock is a lack of linearity between PWM duty
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* cycle width and brightness. In fact only with low preset one sees any change
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* (eg. duty cycle between 1-20). Feel free to adjust this, maybe only my board
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* behaves like this.
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*/
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static const PWMConfig pwmcfg = {
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1000000, /* 1 MHz PWM clock frequency. */
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100, /* PWM period is 100 cycles. */
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NULL,
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{
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{PWM_OUTPUT_ACTIVE_HIGH, NULL},
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{PWM_OUTPUT_ACTIVE_HIGH, NULL},
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{PWM_OUTPUT_ACTIVE_HIGH, NULL},
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{PWM_OUTPUT_ACTIVE_HIGH, NULL}
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},
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0
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1000000, /* 1 MHz PWM clock frequency. */
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100, /* PWM period is 100 cycles. */
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NULL,
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{
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{PWM_OUTPUT_ACTIVE_HIGH, NULL},
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{PWM_OUTPUT_ACTIVE_HIGH, NULL},
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{PWM_OUTPUT_ACTIVE_HIGH, NULL},
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{PWM_OUTPUT_ACTIVE_HIGH, NULL}
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},
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0
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};
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/**
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* @brief Initialise the board for the display.
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* @notes This board definition uses GPIO and assumes exclusive access to these GPIO pins
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* @notes This board definition uses GPIO and assumes exclusive access to these GPIO pins
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*
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* @notapi
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*/
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static inline void init_board(void) {
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unsigned char FSMC_Bank;
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/* STM32F4 FSMC init */
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rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0);
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#if defined(STM32F4XX) || defined(STM32F2XX)
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/* STM32F4 FSMC init */
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rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0);
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#if defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM)
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if (dmaStreamAllocate(GDISP_DMA_STREAM, 0, NULL, NULL))
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gfxExit();
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dmaStreamSetMemory0(GDISP_DMA_STREAM, &GDISP_RAM);
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dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
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#endif
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#else
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#error "FSMC not implemented for this device"
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#endif
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/* Group pins */
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IOBus busD = {GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) | (1 << 7) | (1 << 8) |
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@ -60,10 +82,11 @@ static inline void init_board(void) {
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palSetBusMode(&busD, PAL_MODE_ALTERNATE(12));
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palSetBusMode(&busE, PAL_MODE_ALTERNATE(12));
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FSMC_Bank = 0;
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/* FSMC timing */
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// FSMC_Bank1->BTCR[FSMC_Bank+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0 ;
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/* FSMC timing */
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FSMC_Bank1->BTCR[FSMC_Bank+1] = (FSMC_BTR1_ADDSET_1 | FSMC_BTR1_ADDSET_3) \
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FSMC_Bank1->BTCR[FSMC_Bank + 1] = (FSMC_BTR1_ADDSET_1 | FSMC_BTR1_ADDSET_3) \
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| (FSMC_BTR1_DATAST_1 | FSMC_BTR1_DATAST_3) \
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| (FSMC_BTR1_BUSTURN_1 | FSMC_BTR1_BUSTURN_3) ;
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