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For all source files update integer types to the new gI8 etc type names

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This commit is contained in:
inmarket 2018-11-03 10:51:23 +10:00
parent 8bd70d953b
commit 7c5a6c928f
389 changed files with 2994 additions and 2961 deletions
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2
boards/addons/gdisp/board_ED060SC4_example.h
View file

@ -119,7 +119,7 @@ static GFXINLINE void setpin_sph(GDisplay *g, gBool on) {
}
/* Set the state of the D0-D7 (source driver Data) pins. */
static GFXINLINE void setpins_data(GDisplay *g, uint8_t value) {
static GFXINLINE void setpins_data(GDisplay *g, gU8 value) {
(void) g;
palWriteGroup(GPIOB, 0xFF, GPIOB_EINK_D0, value);
}

8
boards/addons/gdisp/board_HX8347D_stm32f4discovery.h
View file

@ -112,7 +112,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
}
}
static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
pwmEnableChannel(&PWMD4, 1, percent);
}
@ -140,7 +140,7 @@ static GFXINLINE void busmode8(GDisplay *g) {
spiStart(&SPID1, &spi1cfg_8bit);
}
static GFXINLINE void write_index(GDisplay *g, uint8_t index) {
static GFXINLINE void write_index(GDisplay *g, gU8 index) {
(void) g;
CLR_DATA;
SPI1->DR = index;
@ -148,13 +148,13 @@ static GFXINLINE void write_index(GDisplay *g, uint8_t index) {
SET_DATA;
}
static GFXINLINE void write_data(GDisplay *g, uint8_t data) {
static GFXINLINE void write_data(GDisplay *g, gU8 data) {
(void) g;
SPI1->DR = data;
while(((SPI1->SR & SPI_SR_TXE) == 0) || ((SPI1->SR & SPI_SR_BSY) != 0));
}
static GFXINLINE void write_ram16(GDisplay *g, uint16_t data) {
static GFXINLINE void write_ram16(GDisplay *g, gU16 data) {
(void) g;
SPI1->DR = data;
while((SPI1->SR & SPI_SR_TXE) == 0);

10
boards/addons/gdisp/board_ILI9320_olimex_pic32mx_lcd.h
View file

@ -76,7 +76,7 @@ static noinline void setpin_reset(GDisplay *g, gBool state) {
palSetPad(IOPORTA, 7);
}
static void set_backlight(GDisplay *g, uint8_t percent) {
static void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
if (percentage)
palClearPad(IOPORTD, 3);
@ -92,8 +92,8 @@ static GFXINLINE void release_bus(GDisplay *g) {
(void) g;
}
static noinline void write_index(GDisplay *g, uint16_t index) {
volatile uint16_t dummy;
static noinline void write_index(GDisplay *g, gU16 index) {
volatile gU16 dummy;
(void) g;
PmpWaitBusy();
@ -106,7 +106,7 @@ static noinline void write_index(GDisplay *g, uint16_t index) {
(void)dummy;
}
static noinline void write_data(GDisplay *g, uint16_t data) {
static noinline void write_data(GDisplay *g, gU16 data) {
(void) g;
PMDIN = data;
PmpWaitBusy();
@ -120,7 +120,7 @@ static GFXINLINE void setwritemode(GDisplay *g) {
(void) g;
}
static noinline uint16_t read_data(GDisplay *g) {
static noinline gU16 read_data(GDisplay *g) {
(void) g;
PmpWaitBusy();
return PMDIN;

12
boards/addons/gdisp/board_ILI9325_hy_stm32_100p.h
View file

@ -31,8 +31,8 @@
// For a multiple display configuration we would put all this in a structure and then
// set g->board to that structure.
#define GDISP_REG (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
#define GDISP_RAM (*((volatile uint16_t *) 0x60020000)) /* RS = 1 */
#define GDISP_REG (*((volatile gU16 *) 0x60000000)) /* RS = 0 */
#define GDISP_RAM (*((volatile gU16 *) 0x60020000)) /* RS = 1 */
static GFXINLINE void init_board(GDisplay *g) {
@ -76,7 +76,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
palSetPad(GPIOE, GPIOE_TFT_RST);
}
static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
(void)percent;
}
@ -89,12 +89,12 @@ static GFXINLINE void release_bus(GDisplay *g) {
(void) g;
}
static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
static GFXINLINE void write_index(GDisplay *g, gU16 index) {
(void) g;
GDISP_REG = index;
}
static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
static GFXINLINE void write_data(GDisplay *g, gU16 data) {
(void) g;
GDISP_RAM = data;
}
@ -107,7 +107,7 @@ static GFXINLINE void setwritemode(GDisplay *g) {
(void) g;
}
static GFXINLINE uint16_t read_data(GDisplay *g) {
static GFXINLINE gU16 read_data(GDisplay *g) {
(void) g;
return GDISP_RAM;
}

12
boards/addons/gdisp/board_ILI9341_spi.h
View file

@ -43,7 +43,7 @@ static const SPIConfig spi2cfg = {
(SPI_CR1_MSTR | SPI_CR1_SPE | SPI_CR1_SSM | SPI_CR1_SSI)
};
static void send_data(uint16_t data);
static void send_data(gU16 data);
/**
* @brief Initialise the board for the display.
@ -105,7 +105,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
*
* @notapi
*/
static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
(void) percent;
}
@ -139,7 +139,7 @@ static GFXINLINE void release_bus(GDisplay *g) {
*
* @notapi
*/
static GFXINLINE void send_data(uint16_t data) {
static GFXINLINE void send_data(gU16 data) {
// http://forum.easyelectronics.ru/viewtopic.php?p=262122#p262122
while (!(SPI2->SR & SPI_SR_TXE)); // ïðè âõîäå íà îòïðàâêó ïðîâåðÿåì - à ïóñòîé ëè SPI_DR
SPI2->DR = data; // çàãðóçèëè â SPI_DR êîä êîìàíäû
@ -154,7 +154,7 @@ static GFXINLINE void send_data(uint16_t data) {
*
* @notapi
*/
static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
static GFXINLINE void write_index(GDisplay *g, gU16 index) {
(void) g;
while (SPI2->SR & SPI_SR_BSY);
@ -177,7 +177,7 @@ static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
*
* @notapi
*/
static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
static GFXINLINE void write_data(GDisplay *g, gU16 data) {
(void) g;
send_data(data);
@ -213,7 +213,7 @@ static GFXINLINE void setwritemode(GDisplay *g) {
*
* @notapi
*/
static GFXINLINE uint16_t read_data(GDisplay *g) {
static GFXINLINE gU16 read_data(GDisplay *g) {
(void) g;
return 0;
}

10
boards/addons/gdisp/board_ILI9481_firebullstm32f103.h
View file

@ -58,7 +58,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
(void) state;
}
static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
(void) percent;
}
@ -71,13 +71,13 @@ static GFXINLINE void release_bus(GDisplay *g) {
(void) g;
}
static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
static GFXINLINE void write_index(GDisplay *g, gU16 index) {
(void) g;
palWritePort(GPIOE, index);
CLR_RS; CLR_WR; SET_WR; SET_RS;
}
static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
static GFXINLINE void write_data(GDisplay *g, gU16 data) {
(void) g;
palWritePort(GPIOE, data);
CLR_WR; SET_WR;
@ -95,8 +95,8 @@ static GFXINLINE void setwritemode(GDisplay *g) {
palSetGroupMode(GPIOE, PAL_WHOLE_PORT, 0, PAL_MODE_OUTPUT_PUSHPULL);
}
static GFXINLINE uint16_t read_data(GDisplay *g) {
uint16_t value;
static GFXINLINE gU16 read_data(GDisplay *g) {
gU16 value;
(void) g;
CLR_RD;

14
boards/addons/gdisp/board_ILI9488_stm32f4cube_hal.h
View file

@ -10,8 +10,8 @@
#include "stm32f4xx_hal.h"
#define GDISP_REG (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
#define GDISP_RAM (*((volatile uint16_t *) 0x60020000)) /* RS = 1 */
#define GDISP_REG (*((volatile gU16 *) 0x60000000)) /* RS = 0 */
#define GDISP_RAM (*((volatile gU16 *) 0x60020000)) /* RS = 1 */
static GFXINLINE void init_board(GDisplay *g)
{
@ -108,7 +108,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state)
}
}
static GFXINLINE void set_backlight(GDisplay* g, uint8_t percent)
static GFXINLINE void set_backlight(GDisplay* g, gU8 percent)
{
(void) g;
@ -129,14 +129,14 @@ static GFXINLINE void release_bus(GDisplay* g)
(void) g;
}
static GFXINLINE void write_index(GDisplay* g, uint16_t index)
static GFXINLINE void write_index(GDisplay* g, gU16 index)
{
(void) g;
GDISP_REG = index;
}
static GFXINLINE void write_data(GDisplay* g, uint16_t data)
static GFXINLINE void write_data(GDisplay* g, gU16 data)
{
(void) g;
@ -153,11 +153,11 @@ static GFXINLINE void setwritemode(GDisplay* g)
(void) g;
}
static GFXINLINE uint16_t read_data(GDisplay* g)
static GFXINLINE gU16 read_data(GDisplay* g)
{
(void) g;
return (uint16_t)GDISP_RAM;
return (gU16)GDISP_RAM;
}
#endif /* _GDISP_LLD_BOARD_H */

12
boards/addons/gdisp/board_S6D1121_olimex_e407.h
View file

@ -18,8 +18,8 @@
// For a multiple display configuration we would put all this in a structure and then
// set g->board to that structure.
#define GDISP_REG (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
#define GDISP_RAM (*((volatile uint16_t *) 0x60020000)) /* RS = 1 */
#define GDISP_REG (*((volatile gU16 *) 0x60000000)) /* RS = 0 */
#define GDISP_RAM (*((volatile gU16 *) 0x60020000)) /* RS = 1 */
static GFXINLINE void init_board(GDisplay *g) {
@ -55,7 +55,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
(void) state;
}
static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
(void) percent;
}
@ -68,12 +68,12 @@ static GFXINLINE void release_bus(GDisplay *g) {
(void) g;
}
static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
static GFXINLINE void write_index(GDisplay *g, gU16 index) {
(void) g;
GDISP_REG = index;
}
static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
static GFXINLINE void write_data(GDisplay *g, gU16 data) {
(void) g;
GDISP_RAM = data;
}
@ -86,7 +86,7 @@ static GFXINLINE void setwritemode(GDisplay *g) {
(void) g;
}
static GFXINLINE uint16_t read_data(GDisplay *g) {
static GFXINLINE gU16 read_data(GDisplay *g) {
(void) g;
return GDISP_RAM;
}

16
boards/addons/gdisp/board_SPFD54124B_stm32f3.h
View file

@ -37,7 +37,7 @@
#if USE_HARD_SPI
#if GFX_USE_OS_CHIBIOS
static int32_t thdPriority = 0;
static gI32 thdPriority = 0;
#endif
/*
@ -58,9 +58,9 @@ static GFXINLINE void soft_spi_sck(void){
palClearPad(SPFD54124B_SPI_PORT, SPFD54124B_SPI_SCK);
}
static GFXINLINE void soft_spi_write_9bit(uint16_t data){
static GFXINLINE void soft_spi_write_9bit(gU16 data){
uint8_t i;
gU8 i;
// activate lcd by low on CS pin
palClearPad(SPFD54124B_SPI_PORT, SPFD54124B_SPI_NSS);
@ -131,7 +131,7 @@ static GFXINLINE void acquire_bus(GDisplay *g) {
(void) g;
#if USE_HARD_SPI
#if GFX_USE_OS_CHIBIOS
thdPriority = (int32_t)chThdGetPriority();
thdPriority = (gI32)chThdGetPriority();
chThdSetPriority(HIGHPRIO);
#endif
spiAcquireBus(&SPFD54124B_SPID);
@ -148,10 +148,10 @@ static GFXINLINE void release_bus(GDisplay *g) {
#endif
}
static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
static GFXINLINE void write_data(GDisplay *g, gU16 data) {
(void) g;
uint16_t b;
gU16 b;
#if USE_HARD_SPI
@ -176,7 +176,7 @@ static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
}
static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
static GFXINLINE void write_index(GDisplay *g, gU16 index) {
(void) g;
#if USE_HARD_SPI
@ -195,7 +195,7 @@ static GFXINLINE void post_init_board(GDisplay *g) {
(void) g;
}
static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
(void) percent;
}

12
boards/addons/gdisp/board_SSD1289_stm32f4discovery.h
View file

@ -18,8 +18,8 @@
// For a multiple display configuration we would put all this in a structure and then
// set g->board to that structure.
#define GDISP_REG ((volatile uint16_t *) 0x60000000)[0] /* RS = 0 */
#define GDISP_RAM ((volatile uint16_t *) 0x60020000)[0] /* RS = 1 */
#define GDISP_REG ((volatile gU16 *) 0x60000000)[0] /* RS = 0 */
#define GDISP_RAM ((volatile gU16 *) 0x60020000)[0] /* RS = 1 */
#define GDISP_DMA_STREAM STM32_DMA2_STREAM6
#define FSMC_BANK 0
@ -114,7 +114,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
(void) state;
}
static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
pwmEnableChannel(&PWMD3, 2, percent);
}
@ -127,12 +127,12 @@ static GFXINLINE void release_bus(GDisplay *g) {
(void) g;
}
static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
static GFXINLINE void write_index(GDisplay *g, gU16 index) {
(void) g;
GDISP_REG = index;
}
static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
static GFXINLINE void write_data(GDisplay *g, gU16 data) {
(void) g;
GDISP_RAM = data;
}
@ -147,7 +147,7 @@ static GFXINLINE void setwritemode(GDisplay *g) {
FSMC_Bank1->BTCR[FSMC_BANK+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0; /* FSMC timing */
}
static GFXINLINE uint16_t read_data(GDisplay *g) {
static GFXINLINE gU16 read_data(GDisplay *g) {
(void) g;
return GDISP_RAM;
}

6
boards/addons/gdisp/board_SSD1306_chibios_16.1.3_stm32f4.h
View file

@ -72,17 +72,17 @@ static GFXINLINE void release_bus(GDisplay* g)
spiReleaseBus(SPI_DRIVER);
}
static GFXINLINE void write_cmd(GDisplay* g, uint8_t cmd)
static GFXINLINE void write_cmd(GDisplay* g, gU8 cmd)
{
(void)g;
static uint8_t buf;
static gU8 buf;
palClearPad(DC_PORT, DC_PAD);
buf = cmd;
spiSend(SPI_DRIVER, 1, &buf);
}
static GFXINLINE void write_data(GDisplay* g, uint8_t* data, uint16_t length)
static GFXINLINE void write_data(GDisplay* g, gU8* data, gU16 length)
{
(void)g;

10
boards/addons/gdisp/board_SSD1306_i2c.h
View file

@ -46,7 +46,7 @@
static I2CConfig i2cconfig;
#if GFX_USE_OS_CHIBIOS
static int32_t thdPriority = 0;
static gI32 thdPriority = 0;
#endif
static GFXINLINE void init_board(GDisplay *g) {
@ -93,7 +93,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
static GFXINLINE void acquire_bus(GDisplay *g) {
(void) g;
#if GFX_USE_OS_CHIBIOS
thdPriority = (int32_t)chThdGetPriority();
thdPriority = (gI32)chThdGetPriority();
chThdSetPriority(HIGHPRIO);
#endif
i2cAcquireBus(&I2CD1);
@ -107,8 +107,8 @@ static GFXINLINE void release_bus(GDisplay *g) {
i2cReleaseBus(&I2CD1);
}
static GFXINLINE void write_cmd(GDisplay *g, uint8_t cmd) {
uint8_t command[2];
static GFXINLINE void write_cmd(GDisplay *g, gU8 cmd) {
gU8 command[2];
(void) g;
command[0] = 0x00; // Co = 0, D/C = 0
@ -119,7 +119,7 @@ static GFXINLINE void write_cmd(GDisplay *g, uint8_t cmd) {
i2cStop(&I2CD1);
}
static GFXINLINE void write_data(GDisplay *g, uint8_t* data, uint16_t length) {
static GFXINLINE void write_data(GDisplay *g, gU8* data, gU16 length) {
(void) g;
i2cStart(&I2CD1, &i2cconfig);

8
boards/addons/gdisp/board_SSD1963_fsmc.h
View file

@ -32,8 +32,8 @@ static const LCD_Parameters DisplayTimings[] = {
// set g->board to that structure.
/* Using FSMC A16 as RS */
#define GDISP_REG (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
#define GDISP_RAM (*((volatile uint16_t *) 0x60020000)) /* RS = 1 */
#define GDISP_REG (*((volatile gU16 *) 0x60000000)) /* RS = 0 */
#define GDISP_RAM (*((volatile gU16 *) 0x60020000)) /* RS = 1 */
static GFXINLINE void init_board(GDisplay *g) {
@ -94,12 +94,12 @@ static GFXINLINE void release_bus(GDisplay *g) {
(void) g;
}
static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
static GFXINLINE void write_index(GDisplay *g, gU16 index) {
(void) g;
GDISP_REG = index;
}
static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
static GFXINLINE void write_data(GDisplay *g, gU16 data) {
(void) g;
GDISP_RAM = data;
}

4
boards/addons/gdisp/board_SSD1963_gpio.h
View file

@ -87,14 +87,14 @@ static GFXINLINE void release_bus(GDisplay *g) {
Clr_CS;
}
static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
static GFXINLINE void write_index(GDisplay *g, gU16 index) {
(void) g;
Set_RS; Clr_RD; Set_WR;
palWritePort(GDISP_DATA_PORT, index);
Clr_WR;
}
static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
static GFXINLINE void write_data(GDisplay *g, gU16 data) {
(void) g;
Clr_RS; Clr_RD; Set_WR;
palWritePort(GDISP_DATA_PORT, data);

6
boards/addons/gdisp/board_UC8173_nordic_nrf52_sdk11.h
View file

@ -94,7 +94,7 @@ static GFXINLINE void release_bus(GDisplay* g)
nrf_gpio_pin_set(PIN_CS);
}
static GFXINLINE void write_cmd(GDisplay* g, uint8_t cmd)
static GFXINLINE void write_cmd(GDisplay* g, gU8 cmd)
{
(void)g;
@ -102,7 +102,7 @@ static GFXINLINE void write_cmd(GDisplay* g, uint8_t cmd)
nrf_drv_spi_transfer(&spi, &cmd, 1, 0, 0);
}
static GFXINLINE void write_data(GDisplay* g, uint8_t data)
static GFXINLINE void write_data(GDisplay* g, gU8 data)
{
(void)g;
@ -110,7 +110,7 @@ static GFXINLINE void write_data(GDisplay* g, uint8_t data)
nrf_drv_spi_transfer(&spi, &data, 1, 0, 0);
}
static GFXINLINE void write_data_burst(GDisplay* g, uint8_t* data, uint8_t length)
static GFXINLINE void write_data_burst(GDisplay* g, gU8* data, gU8 length)
{
(void)g;

8
boards/addons/ginput/touch/ADS7843/ginput_lld_mouse_board_olimex_stm32_e407.h
View file

@ -66,14 +66,14 @@ static GFXINLINE void release_bus(GMouse* m) {
//TOUCHSCREEN_SPI_EPILOGUE();
}
static GFXINLINE uint16_t read_value(GMouse* m, uint16_t port) {
static uint8_t txbuf[3] = {0};
static uint8_t rxbuf[3] = {0};
static GFXINLINE gU16 read_value(GMouse* m, gU16 port) {
static gU8 txbuf[3] = {0};
static gU8 rxbuf[3] = {0};
(void) m;
txbuf[0] = port;
spiExchange(&SPID2, 3, txbuf, rxbuf);
return ((uint16_t)rxbuf[1] << 5) | (rxbuf[2] >> 3);
return ((gU16)rxbuf[1] << 5) | (rxbuf[2] >> 3);
}
#endif /* _GINPUT_LLD_MOUSE_BOARD_H */

8
boards/addons/ginput/touch/ADS7843/ginput_lld_mouse_board_st_stm32f4_discovery.h
View file

@ -80,15 +80,15 @@ static GFXINLINE void release_bus(GMouse* m) {
spiReleaseBus(&SPID2);
}
static GFXINLINE uint16_t read_value(GMouse* m, uint16_t port) {
static uint8_t txbuf[3] = {0};
static uint8_t rxbuf[3] = {0};
static GFXINLINE gU16 read_value(GMouse* m, gU16 port) {
static gU8 txbuf[3] = {0};
static gU8 rxbuf[3] = {0};
(void) m;
txbuf[0] = port;
spiExchange(&SPID2, 3, txbuf, rxbuf);
return ((uint16_t)rxbuf[1] << 5) | (rxbuf[2] >> 3);
return ((gU16)rxbuf[1] << 5) | (rxbuf[2] >> 3);
}
#endif /* _GINPUT_LLD_MOUSE_BOARD_H */

8
boards/addons/ginput/touch/ADS7843/stm32f4cube_hal.h
View file

@ -123,11 +123,11 @@ static GFXINLINE void release_bus(GMouse* m)
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_4, GPIO_PIN_SET);
}
static GFXINLINE uint16_t read_value(GMouse* m, uint16_t reg)
static GFXINLINE gU16 read_value(GMouse* m, gU16 reg)
{
uint8_t txbuf[3] = {0, 0, 0};
uint8_t rxbuf[3] = {0, 0, 0};
uint16_t ret;
gU8 txbuf[3] = {0, 0, 0};
gU8 rxbuf[3] = {0, 0, 0};
gU16 ret;
(void)m;

4
boards/base/Altera-MAX10-Neek/board_alteraframereader.h
View file

@ -10,13 +10,13 @@
#define FRAMEREADER_BASE ALT_VIP_VFR_0_BASE
#if GDISP_NEED_CONTROL
static void board_backlight(GDisplay* g, uint8_t percent)
static void board_backlight(GDisplay* g, gU8 percent)
{
(void) g;
(void) percent;
}
static void board_contrast(GDisplay* g, uint8_t percent)
static void board_contrast(GDisplay* g, gU8 percent)
{
(void) g;
(void) percent;

14
boards/base/Altera-MAX10-Neek/gmouse_lld_FT5316_board.h
View file

@ -76,29 +76,29 @@ static gBool init_board(GMouse* m, unsigned instance)
return gTrue;
}
static void write_reg(GMouse* m, uint8_t reg, uint8_t val)
static void write_reg(GMouse* m, gU8 reg, gU8 val)
{
(void)m;
device_write(FT5316_I2C_SLAVE_ADDRESS, reg, val);
}
static uint8_t read_byte(GMouse* m, uint8_t reg)
static gU8 read_byte(GMouse* m, gU8 reg)
{
(void)m;
uint8_t ret = 0;
gU8 ret = 0;
ret = (uint8_t)device_read(FT5316_I2C_SLAVE_ADDRESS, reg);
ret = (gU8)device_read(FT5316_I2C_SLAVE_ADDRESS, reg);
return ret;
}
static uint16_t read_word(GMouse* m, uint8_t reg)
static gU16 read_word(GMouse* m, gU8 reg)
{
(void)m;
uint16_t ret = 0;
gU16 ret = 0;
ret = (uint16_t)device_read(FT5316_I2C_SLAVE_ADDRESS, reg);
ret = (gU16)device_read(FT5316_I2C_SLAVE_ADDRESS, reg);
return ret;
}

8
boards/base/ArduinoTinyScreen/gfx/board_SSD1331.cpp
View file

@ -26,9 +26,9 @@
// Wire address of the SX1505 chip
#define GPIO_ADDR 0x20
static void writeGPIO(uint8_t regAddr, uint8_t regData)
static void writeGPIO(gU8 regAddr, gU8 regData)
{
uint8_t oldTWBR=TWBR;
gU8 oldTWBR=TWBR;
TWBR=0;
Wire.beginTransmission(GPIO_ADDR + LCD_BOARD_ID);
Wire.write(regAddr);
@ -69,7 +69,7 @@ void SSD1331_releasebus(void) {
isDataMode = isCmdMode = false;
}
void SSD1331_write_cmd(uint8_t cmd) {
void SSD1331_write_cmd(gU8 cmd) {
if (!isCmdMode) {
writeGPIO(GPIO_RegData,GPIO_CMD_START);
isDataMode = false;
@ -78,7 +78,7 @@ void SSD1331_write_cmd(uint8_t cmd) {
SPI.transfer(cmd);
}
void SSD1331_write_data(uint8_t data) {
void SSD1331_write_data(gU8 data) {
if (!isDataMode) {
writeGPIO(GPIO_RegData,GPIO_DATA_START);
isDataMode = true;

4
boards/base/ArduinoTinyScreen/gfx/board_SSD1331.h
View file

@ -25,8 +25,8 @@ void SSD1331_init_board(void);
void SSD1331_setpin_reset(int state);
void SSD1331_aquirebus(void);
void SSD1331_releasebus(void);
void SSD1331_write_cmd(uint8_t cmd);
void SSD1331_write_data(uint8_t data);
void SSD1331_write_cmd(gU8 cmd);
void SSD1331_write_data(gU8 data);
#ifdef __cplusplus
}

12
boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h
View file

@ -12,8 +12,8 @@
// set g->board to that structure.
/* Using FSMC A19 (PE3) as DC */
#define GDISP_REG (*((volatile uint16_t *) 0x60000000)) /* DC = 0 */
#define GDISP_RAM (*((volatile uint16_t *) 0x60100000)) /* DC = 1 */
#define GDISP_REG (*((volatile gU16 *) 0x60000000)) /* DC = 0 */
#define GDISP_RAM (*((volatile gU16 *) 0x60100000)) /* DC = 1 */
#define GDISP_DMA_STREAM STM32_DMA2_STREAM6
#define SET_RST palSetPad(GPIOD, 3);
@ -108,7 +108,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
}
}
static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
pwmEnableChannel(&PWMD4, 1, percent);
}
@ -121,12 +121,12 @@ static GFXINLINE void release_bus(GDisplay *g) {
(void) g;
}
static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
static GFXINLINE void write_index(GDisplay *g, gU16 index) {
(void) g;
GDISP_REG = index;
}
static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
static GFXINLINE void write_data(GDisplay *g, gU16 data) {
(void) g;
GDISP_RAM = data;
}
@ -139,7 +139,7 @@ static GFXINLINE void setwritemode(GDisplay *g) {
(void) g;
}
static GFXINLINE uint16_t read_data(GDisplay *g) {
static GFXINLINE gU16 read_data(GDisplay *g) {
(void) g;
return GDISP_RAM;
}

14
boards/base/Embest-STM32-DMSTF4BB/gmouse_lld_STMPE811_board.h
View file

@ -77,8 +77,8 @@ static GFXINLINE void release_bus(GMouse* m) {
}
static void write_reg(GMouse* m, uint8_t reg, uint8_t val) {
uint8_t txbuf[2];
static void write_reg(GMouse* m, gU8 reg, gU8 val) {
gU8 txbuf[2];
(void) m;
txbuf[0] = reg;
@ -89,8 +89,8 @@ static void write_reg(GMouse* m, uint8_t reg, uint8_t val) {
i2cReleaseBus(&I2CD1);
}
static uint8_t read_byte(GMouse* m, uint8_t reg) {
uint8_t rxbuf[1];
static gU8 read_byte(GMouse* m, gU8 reg) {
gU8 rxbuf[1];
(void) m;
rxbuf[0] = 0;
@ -102,8 +102,8 @@ static uint8_t read_byte(GMouse* m, uint8_t reg) {
return rxbuf[0];
}
static uint16_t read_word(GMouse* m, uint8_t reg) {
uint8_t rxbuf[2];
static gU16 read_word(GMouse* m, gU8 reg) {
gU8 rxbuf[2];
(void) m;
rxbuf[0] = 0;
@ -113,7 +113,7 @@ static uint16_t read_word(GMouse* m, uint8_t reg) {
i2cMasterTransmitTimeout(&I2CD1, STMPE811_ADDR, &reg, 1, rxbuf, 2, MS2ST(STMPE811_TIMEOUT));
i2cReleaseBus(&I2CD1);
return (((uint16_t)rxbuf[0]) << 8) | rxbuf[1];
return (((gU16)rxbuf[0]) << 8) | rxbuf[1];
}
#endif /* _GINPUT_LLD_MOUSE_BOARD_H */

8
boards/base/FireBull-STM32F103-FB/board_SSD1289.h
View file

@ -56,7 +56,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state)
/* Nothing to do here - reset pin tied to Vcc */
}
static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent)
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent)
{
(void) g;
(void) percent;
@ -74,7 +74,7 @@ static GFXINLINE void release_bus(GDisplay *g)
(void) g;
}
static GFXINLINE void write_index(GDisplay *g, uint16_t index)
static GFXINLINE void write_index(GDisplay *g, gU16 index)
{
(void) g;
@ -85,7 +85,7 @@ static GFXINLINE void write_index(GDisplay *g, uint16_t index)
SET_RS;
}
static GFXINLINE void write_data(GDisplay *g, uint16_t data)
static GFXINLINE void write_data(GDisplay *g, gU16 data)
{
(void) g;
@ -112,7 +112,7 @@ static GFXINLINE void setwritemode(GDisplay *g)
palSetGroupMode(GPIOE, PAL_WHOLE_PORT, 0, PAL_MODE_OUTPUT_PUSHPULL);
}
static GFXINLINE uint16_t read_data(GDisplay *g) {
static GFXINLINE gU16 read_data(GDisplay *g) {
(void) g;
return palReadPort(GPIOE);

8
boards/base/FireBull-STM32F103-FB/gmouse_lld_ADS7843_board.h
View file

@ -66,11 +66,11 @@ static GFXINLINE void release_bus(GMouse* m)
spiReleaseBus(&SPID1);
}
static GFXINLINE uint16_t read_value(GMouse* m, uint16_t port)
static GFXINLINE gU16 read_value(GMouse* m, gU16 port)
{
static uint8_t txbuf[3] = {0};
static uint8_t rxbuf[3] = {0};
uint16_t ret;
static gU8 txbuf[3] = {0};
static gU8 rxbuf[3] = {0};
gU16 ret;
(void) m;
txbuf[0] = port;

12
boards/base/HY-MiniSTM32V/board_SSD1289.h
View file

@ -40,8 +40,8 @@ static const PWMConfig pwmcfg =
/*
* LCD_RS is on A16 (PD11)
*/
#define GDISP_REG (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
#define GDISP_RAM (*((volatile uint16_t *) 0x60020000)) /* RS = 1 */
#define GDISP_REG (*((volatile gU16 *) 0x60000000)) /* RS = 0 */
#define GDISP_RAM (*((volatile gU16 *) 0x60020000)) /* RS = 1 */
/*
* STM32_DMA1_STREAM7
* NOTE: conflicts w/ USART2_TX, TIM2_CH2, TIM2_CH4, TIM4_UP, I2C1_RX in case
@ -131,7 +131,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
else {}
}
static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
if (percent > 100) { percent = 100; }
pwmEnableChannel(&PWMD3, 1, percent);
@ -145,12 +145,12 @@ static GFXINLINE void release_bus(GDisplay *g) {
(void) g;
}
static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
static GFXINLINE void write_index(GDisplay *g, gU16 index) {
(void) g;
GDISP_REG = index;
}
static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
static GFXINLINE void write_data(GDisplay *g, gU16 data) {
(void) g;
GDISP_RAM = data;
}
@ -163,7 +163,7 @@ static GFXINLINE void setwritemode(GDisplay *g) {
(void) g;
}
static GFXINLINE uint16_t read_data(GDisplay *g) {
static GFXINLINE gU16 read_data(GDisplay *g) {
(void) g;
return GDISP_RAM;
}

8
boards/base/HY-MiniSTM32V/gmouse_lld_ADS7843_board.h
View file

@ -83,11 +83,11 @@ static GFXINLINE void release_bus(GMouse* m) {
spiReleaseBus(&SPID1);
}
static GFXINLINE uint16_t read_value(GMouse* m, uint16_t port) {
static GFXINLINE gU16 read_value(GMouse* m, gU16 port) {
(void)m;
static uint8_t txbuf[3] = {0};
static uint8_t rxbuf[3] = {0};
uint16_t ret;
static gU8 txbuf[3] = {0};
static gU8 rxbuf[3] = {0};
gU16 ret;
txbuf[0] = port;
spiExchange(&SPID1, 3, txbuf, rxbuf);

4
boards/base/Linux-Framebuffer/board_framebuffer.h
View file

@ -203,12 +203,12 @@
#endif
#if GDISP_NEED_CONTROL
static void board_backlight(GDisplay *g, uint8_t percent) {
static void board_backlight(GDisplay *g, gU8 percent) {
(void) g;
(void) percent;
}
static void board_contrast(GDisplay *g, uint8_t percent) {
static void board_contrast(GDisplay *g, gU8 percent) {
(void) g;
(void) percent;
}

10
boards/base/Marlin/board_RA8875.h
View file

@ -15,8 +15,8 @@
// For a multiple display configuration we would put all this in a structure and then
// set g->board to that structure.
#define GDISP_RAM (*((volatile uint16_t *) 0x68000000)) /* RS = 0 */
#define GDISP_REG (*((volatile uint16_t *) 0x68020000)) /* RS = 1 */
#define GDISP_RAM (*((volatile gU16 *) 0x68000000)) /* RS = 0 */
#define GDISP_REG (*((volatile gU16 *) 0x68020000)) /* RS = 1 */
#define FSMC_BANK 4
@ -83,13 +83,13 @@ static GFXINLINE void release_bus(GDisplay *g) {
(void) g;
}
static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
static GFXINLINE void write_index(GDisplay *g, gU16 index) {
(void) g;
GDISP_REG = index;
}
static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
static GFXINLINE void write_data(GDisplay *g, gU16 data) {
(void) g;
GDISP_RAM = data;
@ -103,7 +103,7 @@ static GFXINLINE void setwritemode(GDisplay *g) {
(void) g;
}
static GFXINLINE uint16_t read_data(GDisplay *g) {
static GFXINLINE gU16 read_data(GDisplay *g) {
(void) g;
return GDISP_RAM;

14
boards/base/Marlin/gmouse_lld_FT5x06_board.h
View file

@ -51,8 +51,8 @@ static GFXINLINE void release_bus(GMouse* m) {
}
static void write_reg(GMouse* m, uint8_t reg, uint8_t val) {
uint8_t txbuf[2];
static void write_reg(GMouse* m, gU8 reg, gU8 val) {
gU8 txbuf[2];
(void) m;
txbuf[0] = reg;
@ -63,8 +63,8 @@ static void write_reg(GMouse* m, uint8_t reg, uint8_t val) {
i2cReleaseBus(&I2CD2);
}
static uint8_t read_byte(GMouse* m, uint8_t reg) {
uint8_t rxbuf[1];
static gU8 read_byte(GMouse* m, gU8 reg) {
gU8 rxbuf[1];
(void) m;
rxbuf[0] = 0;
@ -76,8 +76,8 @@ static uint8_t read_byte(GMouse* m, uint8_t reg) {
return rxbuf[0];
}
static uint16_t read_word(GMouse* m, uint8_t reg) {
uint8_t rxbuf[2];
static gU16 read_word(GMouse* m, gU8 reg) {
gU8 rxbuf[2];
(void) m;
rxbuf[0] = 0;
@ -87,7 +87,7 @@ static uint16_t read_word(GMouse* m, uint8_t reg) {
i2cMasterTransmitTimeout(&I2CD2, FT5x06_ADDR, &reg, 1, rxbuf, 2, MS2ST(FT5x06_TIMEOUT));
i2cReleaseBus(&I2CD2);
return (((uint16_t)rxbuf[0]) << 8) | rxbuf[1];
return (((gU16)rxbuf[0]) << 8) | rxbuf[1];
}
#endif /* _GINPUT_LLD_MOUSE_BOARD_H */

26
boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/flash_memory.c
View file

@ -19,10 +19,10 @@ static const SPIConfig flash_spicfg = {
};
bool flash_is_write_busy(void) {
static uint8_t is_write_busy_cmd[1];
static gU8 is_write_busy_cmd[1];
is_write_busy_cmd[0] = _SERIAL_FLASH_CMD_RDSR;
uint8_t result[1];
gU8 result[1];
spiAcquireBus(&SPID3);
spiStart(&SPID3, &flash_spicfg);
@ -44,9 +44,9 @@ void flash_write_enable(void) {
spiReleaseBus(&SPID3);
}
void flash_sector_erase(uint32_t sector) {
void flash_sector_erase(gU32 sector) {
flash_write_enable();
static uint8_t sector_erase_cmd[4];
static gU8 sector_erase_cmd[4];
sector_erase_cmd[0] = _SERIAL_FLASH_CMD_SER;
sector_erase_cmd[1] = (sector >> 16) & 0xFF;
sector_erase_cmd[2] = (sector >> 8) & 0xFF;
@ -64,8 +64,8 @@ void flash_sector_erase(uint32_t sector) {
while(flash_is_write_busy());
}
void flash_read(uint32_t address, size_t bytes, uint8_t *out) {
static uint8_t sector_read_cmd[4];
void flash_read(gU32 address, gMemSize bytes, gU8 *out) {
static gU8 sector_read_cmd[4];
sector_read_cmd[0] = _SERIAL_FLASH_CMD_READ;
sector_read_cmd[1] = (address >> 16) & 0xFF;
sector_read_cmd[2] = (address >> 8) & 0xFF;
@ -80,8 +80,8 @@ void flash_read(uint32_t address, size_t bytes, uint8_t *out) {
spiReleaseBus(&SPID3);
}
void flash_write(uint32_t address, size_t bytes, const uint8_t *data) {
static uint8_t flash_write_cmd[4];
void flash_write(gU32 address, gMemSize bytes, const gU8 *data) {
static gU8 flash_write_cmd[4];
flash_write_enable();
@ -103,21 +103,21 @@ void flash_write(uint32_t address, size_t bytes, const uint8_t *data) {
}
bool flash_tp_calibrated(void) {
uint8_t out[1];
gU8 out[1];
flash_read(0x0F0000, 1, out);
return (out[0] == 0x01);
}
void flash_tp_calibration_save(uint16_t instance, const uint8_t *calbuf, size_t sz) {
void flash_tp_calibration_save(gU16 instance, const gU8 *calbuf, gMemSize sz) {
if (instance) return;
flash_sector_erase(0x0F0000);
uint8_t calibrated = 0x01;
gU8 calibrated = 0x01;
flash_write(0x0F0000, 1, &calibrated);
flash_write(0x0F0001, sz, calbuf);
}
const char *flash_tp_calibration_load(uint16_t instance) {
static uint8_t foo[24];
const char *flash_tp_calibration_load(gU16 instance) {
static gU8 foo[24];
if (instance) return 0;
if (!flash_tp_calibrated()) return 0;

10
boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/flash_memory.h
View file

@ -1,6 +1,6 @@
void flash_sector_erase(uint32_t sector);
void flash_read(uint32_t address, size_t bytes, uint8_t *out);
void flash_write(uint32_t address, size_t bytes, const uint8_t *data);
void flash_sector_erase(gU32 sector);
void flash_read(gU32 address, gMemSize bytes, gU8 *out);
void flash_write(gU32 address, gMemSize bytes, const gU8 *data);
bool flash_tp_calibrated(void);
void flash_tp_calibration_save(uint16_t instance, const uint8_t *calbuf, size_t sz);
const char *flash_tp_calibration_load(uint16_t instance);
void flash_tp_calibration_save(gU16 instance, const gU8 *calbuf, gMemSize sz);
const char *flash_tp_calibration_load(gU16 instance);

8
boards/base/Mikromedia-Plus-STM32-M4/board_SSD1963.h
View file

@ -87,7 +87,7 @@ static GFXINLINE void release_bus(GDisplay *g) {
SET_CS;
}
static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
static GFXINLINE void write_index(GDisplay *g, gU16 index) {
(void) g;
CLR_DC;
@ -97,7 +97,7 @@ static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
SET_DC;
}
static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
static GFXINLINE void write_data(GDisplay *g, gU16 data) {
(void) g;
palWriteBus(&busDataLo, (data & 0xFF));
@ -117,8 +117,8 @@ static GFXINLINE void setwritemode(GDisplay *g) {
palSetBusMode(&busDataHi, PAL_MODE_OUTPUT_PUSHPULL);
}
static GFXINLINE uint16_t read_data(GDisplay *g) {
uint16_t data;
static GFXINLINE gU16 read_data(GDisplay *g) {
gU16 data;
(void) g;
CLR_RD;

14
boards/base/Mikromedia-Plus-STM32-M4/gmouse_lld_STMPE610_board.h
View file

@ -77,8 +77,8 @@ static GFXINLINE void release_bus(GMouse* m) {
}
static void write_reg(GMouse* m, uint8_t reg, uint8_t val) {
uint8_t txbuf[2];
static void write_reg(GMouse* m, gU8 reg, gU8 val) {
gU8 txbuf[2];
(void) m;
txbuf[0] = reg;
@ -89,8 +89,8 @@ static void write_reg(GMouse* m, uint8_t reg, uint8_t val) {
i2cReleaseBus(&I2CD1);
}
static uint8_t read_byte(GMouse* m, uint8_t reg) {
uint8_t rxbuf[1];
static gU8 read_byte(GMouse* m, gU8 reg) {
gU8 rxbuf[1];
(void) m;
rxbuf[0] = 0;
@ -102,8 +102,8 @@ static uint8_t read_byte(GMouse* m, uint8_t reg) {
return rxbuf[0];
}
static uint16_t read_word(GMouse* m, uint8_t reg) {
uint8_t rxbuf[2];
static gU16 read_word(GMouse* m, gU8 reg) {
gU8 rxbuf[2];
(void) m;
rxbuf[0] = 0;
@ -113,7 +113,7 @@ static uint16_t read_word(GMouse* m, uint8_t reg) {
i2cMasterTransmitTimeout(&I2CD1, STMPE610_ADDR, &reg, 1, rxbuf, 2, MS2ST(STMPE610_TIMEOUT));
i2cReleaseBus(&I2CD1);
return (((uint16_t)rxbuf[0]) << 8) | rxbuf[1];
return (((gU16)rxbuf[0]) << 8) | rxbuf[1];
}
#endif /* _GINPUT_LLD_MOUSE_BOARD_H */

26
boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/flash_memory.c
View file

@ -19,10 +19,10 @@ static const SPIConfig flash_spicfg = {
};
bool flash_is_write_busy(void) {
static uint8_t is_write_busy_cmd[1];
static gU8 is_write_busy_cmd[1];
is_write_busy_cmd[0] = _SERIAL_FLASH_CMD_RDSR;
uint8_t result[1];
gU8 result[1];
spiAcquireBus(&SPID3);
spiStart(&SPID3, &flash_spicfg);
@ -44,9 +44,9 @@ void flash_write_enable(void) {
spiReleaseBus(&SPID3);
}
void flash_sector_erase(uint32_t sector) {
void flash_sector_erase(gU32 sector) {
flash_write_enable();
static uint8_t sector_erase_cmd[4];
static gU8 sector_erase_cmd[4];
sector_erase_cmd[0] = _SERIAL_FLASH_CMD_SER;
sector_erase_cmd[1] = (sector >> 16) & 0xFF;
sector_erase_cmd[2] = (sector >> 8) & 0xFF;
@ -64,8 +64,8 @@ void flash_sector_erase(uint32_t sector) {
while(flash_is_write_busy());
}
void flash_read(uint32_t address, size_t bytes, uint8_t *out) {
static uint8_t sector_read_cmd[4];
void flash_read(gU32 address, gMemSize bytes, gU8 *out) {
static gU8 sector_read_cmd[4];
sector_read_cmd[0] = _SERIAL_FLASH_CMD_READ;
sector_read_cmd[1] = (address >> 16) & 0xFF;
sector_read_cmd[2] = (address >> 8) & 0xFF;
@ -80,8 +80,8 @@ void flash_read(uint32_t address, size_t bytes, uint8_t *out) {
spiReleaseBus(&SPID3);
}
void flash_write(uint32_t address, size_t bytes, const uint8_t *data) {
static uint8_t flash_write_cmd[4];
void flash_write(gU32 address, gMemSize bytes, const gU8 *data) {
static gU8 flash_write_cmd[4];
flash_write_enable();
@ -103,21 +103,21 @@ void flash_write(uint32_t address, size_t bytes, const uint8_t *data) {
}
bool flash_tp_calibrated(void) {
uint8_t out[1];
gU8 out[1];
flash_read(0x0F0000, 1, out);
return (out[0] == 0x01);
}
void flash_tp_calibration_save(uint16_t instance, const uint8_t *calbuf, size_t sz) {
void flash_tp_calibration_save(gU16 instance, const gU8 *calbuf, gMemSize sz) {
if (instance) return;
flash_sector_erase(0x0F0000);
uint8_t calibrated = 0x01;
gU8 calibrated = 0x01;
flash_write(0x0F0000, 1, &calibrated);
flash_write(0x0F0001, sz, calbuf);
}
const char *flash_tp_calibration_load(uint16_t instance) {
static uint8_t foo[24];
const char *flash_tp_calibration_load(gU16 instance) {
static gU8 foo[24];
if (instance) return 0;
if (!flash_tp_calibrated()) return 0;

10
boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/flash_memory.h
View file

@ -1,6 +1,6 @@
void flash_sector_erase(uint32_t sector);
void flash_read(uint32_t address, size_t bytes, uint8_t *out);
void flash_write(uint32_t address, size_t bytes, const uint8_t *data);
void flash_sector_erase(gU32 sector);
void flash_read(gU32 address, gMemSize bytes, gU8 *out);
void flash_write(gU32 address, gMemSize bytes, const gU8 *data);
bool flash_tp_calibrated(void);
void flash_tp_calibration_save(uint16_t instance, const uint8_t *calbuf, size_t sz);
const char *flash_tp_calibration_load(uint16_t instance);
void flash_tp_calibration_save(gU16 instance, const gU8 *calbuf, gMemSize sz);
const char *flash_tp_calibration_load(gU16 instance);

14
boards/base/Mikromedia-STM32-M4-ILI9341/board_ILI9341.h
View file

@ -49,7 +49,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
}
}
static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
// TODO: can probably pwm this
if(percent) {
@ -76,19 +76,19 @@ static GFXINLINE void release_bus(GDisplay *g) {
*
* @notapi
*/
static GFXINLINE void ili9341_delay(uint16_t dly) {
static uint16_t i;
static GFXINLINE void ili9341_delay(gU16 dly) {
static gU16 i;
for(i = 0; i < dly; i++)
asm("nop");
}
static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
static GFXINLINE void write_index(GDisplay *g, gU16 index) {
(void) g;
palWriteGroup(GPIOE, 0x00FF, 0, index);
CLR_RS; CLR_WR; ili9341_delay(1); SET_WR; ili9341_delay(1); SET_RS;
}
static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
static GFXINLINE void write_data(GDisplay *g, gU16 data) {
(void) g;
palWriteGroup(GPIOE, 0x00FF, 0, data);
CLR_WR; ili9341_delay(1); SET_WR; ili9341_delay(1);
@ -106,8 +106,8 @@ static GFXINLINE void setwritemode(GDisplay *g) {
palSetGroupMode(GPIOE, PAL_WHOLE_PORT, 0, PAL_MODE_OUTPUT_PUSHPULL);
}
static GFXINLINE uint16_t read_data(GDisplay *g) {
uint16_t value;
static GFXINLINE gU16 read_data(GDisplay *g) {
gU16 value;
(void) g;
CLR_RD;
value = palReadPort(GPIOE);

6
boards/base/Olimex-SAM7EX256-GE12/board_Nokia6610GE12.h
View file

@ -141,7 +141,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
palSetPad(IOPORT1, PIOA_LCD_RESET);
}
static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
if (percent == 100) {
/* Turn the pin on - No PWM */
@ -175,7 +175,7 @@ static GFXINLINE void release_bus(GDisplay *g) {
(void) g;
}
static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
static GFXINLINE void write_index(GDisplay *g, gU16 index) {
(void) g;
// wait for the previous transfer to complete
while(!(pSPI->SPI_SR & AT91C_SPI_TDRE));
@ -183,7 +183,7 @@ static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
pSPI->SPI_TDR = index & 0xFF;
}
static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
static GFXINLINE void write_data(GDisplay *g, gU16 data) {
(void) g;
// wait for the previous transfer to complete
while(!(pSPI->SPI_SR & AT91C_SPI_TDRE));

6
boards/base/Olimex-SAM7EX256-GE8/board_Nokia6610GE8.h
View file

@ -139,7 +139,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
palSetPad(IOPORT1, PIOA_LCD_RESET);
}
static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
if (percent == 100) {
/* Turn the pin on - No PWM */
@ -173,7 +173,7 @@ static GFXINLINE void release_bus(GDisplay *g) {
(void) g;
}
static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
static GFXINLINE void write_index(GDisplay *g, gU16 index) {
(void) g;
// wait for the previous transfer to start
while(!(pSPI->SPI_SR & AT91C_SPI_TDRE));
@ -181,7 +181,7 @@ static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
pSPI->SPI_TDR = index & 0xFF;
}
static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
static GFXINLINE void write_data(GDisplay *g, gU16 data) {
(void) g;
// wait for the previous transfer to start
while(!(pSPI->SPI_SR & AT91C_SPI_TDRE));

8
boards/base/Olimex-SAM7EX256-GE8/board_SSD1306_i2c.h
View file

@ -81,7 +81,7 @@
#define I2C_WAITCOMPLETE()
#define I2C_WRITECMDBYTE(cmd) { \
uint8_t data[2]; \
gU8 data[2]; \
data[0] = 0; \
data[1] = cmd; \
i2cMasterTransmitTimeout (UEXT_I2C, I2C_ADDRESS, data, 2, 0, 0, gDelayForever); \
@ -107,7 +107,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
(void) state;
}
static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
(void) percent;
}
@ -125,7 +125,7 @@ static GFXINLINE void release_bus(GDisplay *g) {
I2C_RELEASEBUS();
}
static GFXINLINE void write_cmd(GDisplay *g, uint8_t cmd) {
static GFXINLINE void write_cmd(GDisplay *g, gU8 cmd) {
(void) g;
I2C_WAITCOMPLETE();
@ -134,7 +134,7 @@ static GFXINLINE void write_cmd(GDisplay *g, uint8_t cmd) {
I2C_WRITECMDBYTE(cmd);
}
static GFXINLINE void write_data(GDisplay *g, uint8_t* data, uint16_t length) {
static GFXINLINE void write_data(GDisplay *g, gU8* data, gU16 length) {
(void) g;
I2C_WAITCOMPLETE();

10
boards/base/Olimex-SAM7EX256-GE8/board_SSD1306_spi.h
View file

@ -63,8 +63,8 @@
static void spi_delay(volatile unsigned long a) { while (a!=0) a--; }
static void spi_write(uint8_t data) {
uint8_t bit;
static void spi_write(gU8 data) {
gU8 bit;
for(bit = 0x80; bit; bit >>= 1) {
if(data & bit)
@ -185,7 +185,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
PinSet(PORT_RESET, PIN_RESET);
}
static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
(void) percent;
}
@ -203,7 +203,7 @@ static GFXINLINE void release_bus(GDisplay *g) {
SPI_RELEASEBUS();
}
static GFXINLINE void write_cmd(GDisplay *g, uint8_t cmd) {
static GFXINLINE void write_cmd(GDisplay *g, gU8 cmd) {
(void) g;
// Command mode please
@ -213,7 +213,7 @@ static GFXINLINE void write_cmd(GDisplay *g, uint8_t cmd) {
SPI_WRITEBYTE(cmd);
}
static GFXINLINE void write_data(GDisplay *g, uint8_t* data, uint16_t length) {
static GFXINLINE void write_data(GDisplay *g, gU8* data, gU16 length) {
(void) g;
// Data mode please

10
boards/base/Olimex-SAM7EX256-GE8/board_SSD1331.h
View file

@ -63,8 +63,8 @@
static void spi_delay(volatile unsigned long a) { while (a!=0) a--; }
static void spi_write(uint8_t data) {
uint8_t bit;
static void spi_write(gU8 data) {
gU8 bit;
for(bit = 0x80; bit; bit >>= 1) {
if(data & bit)
@ -182,7 +182,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
PinSet(PORT_RESET, PIN_RESET);
}
static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
(void) percent;
}
@ -200,7 +200,7 @@ static GFXINLINE void release_bus(GDisplay *g) {
SPI_RELEASEBUS();
}
static GFXINLINE void write_cmd(GDisplay *g, uint8_t cmd) {
static GFXINLINE void write_cmd(GDisplay *g, gU8 cmd) {
(void) g;
// Command mode please
@ -210,7 +210,7 @@ static GFXINLINE void write_cmd(GDisplay *g, uint8_t cmd) {
SPI_WRITEBYTE(cmd);
}
static GFXINLINE void write_data(GDisplay *g, uint8_t data) {
static GFXINLINE void write_data(GDisplay *g, gU8 data) {
(void) g;
// Data mode please

10
boards/base/Olimex-SAM7EX256-GE8/board_TLS8204.h
View file

@ -49,8 +49,8 @@
static void spi_delay(volatile unsigned long a) { while (a!=0) a--; }
static void spi_write(uint8_t data) {
uint8_t bit;
static void spi_write(gU8 data) {
gU8 bit;
for(bit = 0x80; bit; bit >>= 1) {
if(data & bit)
@ -171,7 +171,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
PinSet(PORT_RESET, PIN_RESET);
}
static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
(void) percent;
}
@ -189,7 +189,7 @@ static GFXINLINE void release_bus(GDisplay *g) {
SPI_RELEASEBUS();
}
static GFXINLINE void write_cmd(GDisplay *g, uint8_t cmd) {
static GFXINLINE void write_cmd(GDisplay *g, gU8 cmd) {
(void) g;
// Command mode please
@ -199,7 +199,7 @@ static GFXINLINE void write_cmd(GDisplay *g, uint8_t cmd) {
SPI_WRITEBYTE(cmd);
}
static GFXINLINE void write_data(GDisplay *g, uint8_t* data, uint16_t length) {
static GFXINLINE void write_data(GDisplay *g, gU8* data, gU16 length) {
(void) g;
// Data mode please

6
boards/base/Olimex-SAM7EX256-GE8/gaudio_play_board.h
View file

@ -33,9 +33,9 @@ static GPTConfig gptcfg = {
GPT_TRIGGER_NONE, // trigger
};
static uint16_t lastvalue;
static gU16 lastvalue;
static gBool gaudio_play_pwm_setup(uint32_t frequency, ArrayDataFormat format) {
static gBool gaudio_play_pwm_setup(gU32 frequency, ArrayDataFormat format) {
if (format == ARRAY_DATA_10BITUNSIGNED)
pwmcfg.period = 1024;
else if (format == ARRAY_DATA_8BITUNSIGNED)
@ -65,7 +65,7 @@ static void gaudio_play_pwm_stop(void) {
pwmStop(&PWMD1);
}
static void gaudio_play_pwm_setI(uint16_t value) {
static void gaudio_play_pwm_setI(gU16 value) {
if (value != lastvalue) {
lastvalue = value;
pwmEnableChannelI(&PWMD1, 0, value);

2
boards/base/Olimex-SAM7EX256-GE8/gaudio_record_board.h
View file

@ -30,7 +30,7 @@
#define GAUDIO_RECORD_MICROPHONE 0
#ifdef GAUDIO_RECORD_IMPLEMENTATION
static uint32_t gaudio_gadc_physdevs[GAUDIO_RECORD_NUM_CHANNELS] = {
static gU32 gaudio_gadc_physdevs[GAUDIO_RECORD_NUM_CHANNELS] = {
GADC_PHYSDEV_MICROPHONE,
};
#endif

12
boards/base/Olimex-STM32-LCD/board_ILI9320.h
View file

@ -10,8 +10,8 @@
// For a multiple display configuration we would put all this in a structure and then
// set g->board to that structure.
#define GDISP_REG (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
#define GDISP_RAM (*((volatile uint16_t *) 0x60100000)) /* RS = 1 */
#define GDISP_REG (*((volatile gU16 *) 0x60000000)) /* RS = 0 */
#define GDISP_RAM (*((volatile gU16 *) 0x60100000)) /* RS = 1 */
static GFXINLINE void init_board(GDisplay *g) {
@ -54,7 +54,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
palSetPad(GPIOE, GPIOE_TFT_RST);
}
static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
if(percent)
@ -71,13 +71,13 @@ static GFXINLINE void release_bus(GDisplay *g) {
(void) g;
}
static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
static GFXINLINE void write_index(GDisplay *g, gU16 index) {
(void) g;
GDISP_REG = index;
}
static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
static GFXINLINE void write_data(GDisplay *g, gU16 data) {
(void) g;
GDISP_RAM = data;
@ -91,7 +91,7 @@ static GFXINLINE void setwritemode(GDisplay *g) {
(void) g;
}
static GFXINLINE uint16_t read_data(GDisplay *g) {
static GFXINLINE gU16 read_data(GDisplay *g) {
(void) g;
return GDISP_RAM;

2
boards/base/Olimex-STM32-LCD/gmouse_lld_MCU_board.h
View file

@ -75,7 +75,7 @@ static gBool init_board(GMouse *m, unsigned driverinstance) {
static gBool read_xyz(GMouse *m, GMouseReading *prd) {
adcsample_t samples[ADC_NUM_CHANNELS * ADC_BUF_DEPTH];
uint16_t val1, val2;
gU16 val1, val2;
(void) m;
// No buttons and assume touch off

10
boards/base/RaspberryPi/FreeRTOS/mmio.h
View file

@ -6,16 +6,16 @@
#include <stdint.h>
// write to MMIO register
static GFXINLINE void mmio_write(uint32_t reg, uint32_t data) {
uint32_t *ptr = (uint32_t*)reg;
static GFXINLINE void mmio_write(gU32 reg, gU32 data) {
gU32 *ptr = (gU32*)reg;
asm volatile("str %[data], [%[reg]]"
: : [reg]"r"(ptr), [data]"r"(data));
}
// read from MMIO register
static GFXINLINE uint32_t mmio_read(uint32_t reg) {
uint32_t *ptr = (uint32_t*)reg;
uint32_t data;
static GFXINLINE gU32 mmio_read(gU32 reg) {
gU32 *ptr = (gU32*)reg;
gU32 data;
asm volatile("ldr %[data], [%[reg]]"
: [data]"=r"(data) : [reg]"r"(ptr));
return data;

8
boards/base/RaspberryPi/FreeRTOS/uart.c
View file

@ -46,12 +46,12 @@ enum {
/*
* delay function
* int32_t delay: number of cycles to delay
* gI32 delay: number of cycles to delay
*
* This just loops <delay> times in a way that the compiler
* wont optimize away.
*/
static void delay(int32_t count) {
static void delay(gI32 count) {
asm volatile("__delay_%=: subs %[count], %[count], #1; bne __delay_%=\n"
: : [count]"r"(count) : "cc");
}
@ -102,9 +102,9 @@ void uart_init() {
/*
* Transmit a byte via UART0.
* uint8_t Byte: byte to send.
* gU8 Byte: byte to send.
*/
void uart_putc(uint8_t byte) {
void uart_putc(gU8 byte) {
// wait for UART to become ready to transmit
while (1) {
if (!(mmio_read(UART0_FR) & (1 << 5))) {

4
boards/base/RaspberryPi/FreeRTOS/uart.h
View file

@ -12,9 +12,9 @@ void uart_init();
/*
* Transmit a byte via UART0.
* uint8_t Byte: byte to send.
* gU8 Byte: byte to send.
*/
void uart_putc(uint8_t byte);
void uart_putc(gU8 byte);
/*
* print a string to the UART one character at a time

24
boards/base/RaspberryPi/board_framebuffer.h
View file

@ -26,16 +26,16 @@
#include "rpi_mailbox.h"
typedef struct FrameBufferDescription {
uint32_t width;
uint32_t height;
uint32_t vWidth;
uint32_t vHeight;
uint32_t pitch;
uint32_t bitDepth;
uint32_t x;
uint32_t y;
gU32 width;
gU32 height;
gU32 vWidth;
gU32 vHeight;
gU32 pitch;
gU32 bitDepth;
gU32 x;
gU32 y;
void * pointer;
uint32_t size;
gU32 size;
} FrameBufferDescription;
static FrameBufferDescription FrameBufferInfo __attribute__((aligned (16))) = { 1024, 768, 1024, 768, 0, 24, 0, 0, 0, 0 };
@ -49,7 +49,7 @@
FrameBufferInfo.vHeight = GDISP_SCREEN_HEIGHT;
FrameBufferInfo.bitDepth = LLDCOLOR_BITS;
rpi_writemailbox(1, 0x40000000 + (uint32_t) &FrameBufferInfo);
rpi_writemailbox(1, 0x40000000 + (gU32) &FrameBufferInfo);
if (rpi_readmailbox(1) != 0)
gfxHalt("Could not set display parameters")
@ -70,12 +70,12 @@
#endif
#if GDISP_NEED_CONTROL
static void board_backlight(GDisplay *g, uint8_t percent) {
static void board_backlight(GDisplay *g, gU8 percent) {
(void) g;
(void) percent;
}
static void board_contrast(GDisplay *g, uint8_t percent) {
static void board_contrast(GDisplay *g, gU8 percent) {
(void) g;
(void) percent;
}

14
boards/base/STM32F429i-Discovery/chibios/board_STM32LTDC.h
View file

@ -82,8 +82,8 @@ static void release_bus(GDisplay *g) {
spiUnselect(SPI_PORT);
}
static void write_index(GDisplay *g, uint8_t index) {
static uint8_t sindex;
static void write_index(GDisplay *g, gU8 index) {
static gU8 sindex;
(void) g;
palClearPad(DC_PORT, DC_PIN);
@ -91,8 +91,8 @@ static void write_index(GDisplay *g, uint8_t index) {
spiSend(SPI_PORT, 1, &sindex);
}
static void write_data(GDisplay *g, uint8_t data) {
static uint8_t sdata;
static void write_data(GDisplay *g, gU8 data) {
static gU8 sdata;
(void) g;
palSetPad(DC_PORT, DC_PIN);
@ -108,7 +108,7 @@ static void Init9341(GDisplay *g) {
#define REG_COMMAND 0x0100
#define REG_DELAY 0x0200
static const uint16_t initdata[] = {
static const gU16 initdata[] = {
REG_COMMAND | ILI9341_CMD_RESET,
REG_DELAY | 5,
REG_COMMAND | ILI9341_CMD_DISPLAY_OFF,
@ -152,7 +152,7 @@ static void Init9341(GDisplay *g) {
REG_COMMAND | ILI9341_SET_MEM
};
const uint16_t *p;
const gU16 *p;
acquire_bus(g);
for(p = initdata; p < &initdata[sizeof(initdata)/sizeof(initdata[0])]; p++) {
@ -206,7 +206,7 @@ static GFXINLINE void post_init_board(GDisplay *g) {
(void) g;
}
static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
(void) percent;
}

14
boards/base/STM32F429i-Discovery/chibios/gmouse_lld_STMPE811_board.h
View file

@ -84,8 +84,8 @@ static GFXINLINE void release_bus(GMouse* m) {
}
static void write_reg(GMouse* m, uint8_t reg, uint8_t val) {
uint8_t txbuf[2];
static void write_reg(GMouse* m, gU8 reg, gU8 val) {
gU8 txbuf[2];
(void) m;
txbuf[0] = reg;
@ -96,8 +96,8 @@ static void write_reg(GMouse* m, uint8_t reg, uint8_t val) {
i2cReleaseBus(&I2CD3);
}
static uint8_t read_byte(GMouse* m, uint8_t reg) {
uint8_t rxbuf[1];
static gU8 read_byte(GMouse* m, gU8 reg) {
gU8 rxbuf[1];
(void) m;
rxbuf[0] = 0;
@ -109,8 +109,8 @@ static uint8_t read_byte(GMouse* m, uint8_t reg) {
return rxbuf[0];
}
static uint16_t read_word(GMouse* m, uint8_t reg) {
uint8_t rxbuf[2];
static gU16 read_word(GMouse* m, gU8 reg) {
gU8 rxbuf[2];
(void) m;
rxbuf[0] = 0;
@ -120,7 +120,7 @@ static uint16_t read_word(GMouse* m, uint8_t reg) {
i2cMasterTransmitTimeout(&I2CD3, STMPE811_ADDR, &reg, 1, rxbuf, 2, MS2ST(STMPE811_TIMEOUT));
i2cReleaseBus(&I2CD3);
return (((uint16_t)rxbuf[0]) << 8) | rxbuf[1];
return (((gU16)rxbuf[0]) << 8) | rxbuf[1];
}
#endif /* _GINPUT_LLD_MOUSE_BOARD_H */

16
boards/base/STM32F429i-Discovery/chibios/stm32f429i_discovery_sdram.c
View file

@ -182,7 +182,7 @@ void SDRAM_Init(void)
void SDRAM_InitSequence(void)
{
FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
uint32_t tmpr = 0;
gU32 tmpr = 0;
/* Step 3 --------------------------------------------------------------------*/
/* Configure a clock configuration enable command */
@ -240,7 +240,7 @@ void SDRAM_InitSequence(void)
/* Step 7 --------------------------------------------------------------------*/
/* Program the external memory mode register */
tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 |
tmpr = (gU32)SDRAM_MODEREG_BURST_LENGTH_2 |
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
SDRAM_MODEREG_CAS_LATENCY_3 |
SDRAM_MODEREG_OPERATING_MODE_STANDARD |
@ -279,9 +279,9 @@ void SDRAM_InitSequence(void)
* @param uwBufferSize: number of words to write.
* @retval None.
*/
void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize)
void SDRAM_WriteBuffer(gU32* pBuffer, gU32 uwWriteAddress, gU32 uwBufferSize)
{
__IO uint32_t write_pointer = (uint32_t)uwWriteAddress;
__IO gU32 write_pointer = (gU32)uwWriteAddress;
/* Disable write protection */
FMC_SDRAMWriteProtectionConfig(FMC_Bank2_SDRAM, DISABLE);
@ -295,7 +295,7 @@ void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBu
for (; uwBufferSize != 0; uwBufferSize--)
{
/* Transfer data to the memory */
*(uint32_t *) (SDRAM_BANK_ADDR + write_pointer) = *pBuffer++;
*(gU32 *) (SDRAM_BANK_ADDR + write_pointer) = *pBuffer++;
/* Increment the address*/
write_pointer += 4;
@ -311,9 +311,9 @@ void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBu
* @param uwBufferSize: number of words to write.
* @retval None.
*/
void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize)
void SDRAM_ReadBuffer(gU32* pBuffer, gU32 uwReadAddress, gU32 uwBufferSize)
{
__IO uint32_t write_pointer = (uint32_t)uwReadAddress;
__IO gU32 write_pointer = (gU32)uwReadAddress;
/* Wait until the SDRAM controller is ready */
@ -324,7 +324,7 @@ void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBuff
/* Read data */
for(; uwBufferSize != 0x00; uwBufferSize--)
{
*pBuffer++ = *(__IO uint32_t *)(SDRAM_BANK_ADDR + write_pointer );
*pBuffer++ = *(__IO gU32 *)(SDRAM_BANK_ADDR + write_pointer );
/* Increment the address*/
write_pointer += 4;

28
boards/base/STM32F429i-Discovery/chibios/stm32f429i_discovery_sdram.h
View file

@ -43,7 +43,7 @@
/**
* @brief FMC SDRAM Bank address
*/
#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000)
#define SDRAM_BANK_ADDR ((gU32)0xD0000000)
/**
* @brief FMC SDRAM Memory Width
@ -72,22 +72,22 @@
/**
* @brief FMC SDRAM Mode definition register defines
*/
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
#define SDRAM_MODEREG_BURST_LENGTH_1 ((gU16)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((gU16)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((gU16)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((gU16)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((gU16)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((gU16)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((gU16)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((gU16)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((gU16)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((gU16)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((gU16)0x0200)
void SDRAM_Init(void);
void SDRAM_InitSequence(void);
void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize);
void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize);
void SDRAM_WriteBuffer(gU32* pBuffer, gU32 uwWriteAddress, gU32 uwBufferSize);
void SDRAM_ReadBuffer(gU32* pBuffer, gU32 uwReadAddress, gU32 uwBufferSize);
#ifdef __cplusplus
}

136
boards/base/STM32F429i-Discovery/chibios/stm32f4xx_fmc.c
View file

@ -57,24 +57,24 @@
/* --------------------- FMC registers bit mask ---------------------------- */
/* FMC BCRx Mask */
#define BCR_MBKEN_SET ((uint32_t)0x00000001)
#define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE)
#define BCR_FACCEN_SET ((uint32_t)0x00000040)
#define BCR_MBKEN_SET ((gU32)0x00000001)
#define BCR_MBKEN_RESET ((gU32)0x000FFFFE)
#define BCR_FACCEN_SET ((gU32)0x00000040)
/* FMC PCRx Mask */
#define PCR_PBKEN_SET ((uint32_t)0x00000004)
#define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB)
#define PCR_ECCEN_SET ((uint32_t)0x00000040)
#define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF)
#define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008)
#define PCR_PBKEN_SET ((gU32)0x00000004)
#define PCR_PBKEN_RESET ((gU32)0x000FFFFB)
#define PCR_ECCEN_SET ((gU32)0x00000040)
#define PCR_ECCEN_RESET ((gU32)0x000FFFBF)
#define PCR_MEMORYTYPE_NAND ((gU32)0x00000008)
/* FMC SDCRx write protection Mask*/
#define SDCR_WriteProtection_RESET ((uint32_t)0x00007DFF)
#define SDCR_WriteProtection_RESET ((gU32)0x00007DFF)
/* FMC SDCMR Mask*/
#define SDCMR_CTB1_RESET ((uint32_t)0x003FFFEF)
#define SDCMR_CTB2_RESET ((uint32_t)0x003FFFF7)
#define SDCMR_CTB1_2_RESET ((uint32_t)0x003FFFE7)
#define SDCMR_CTB1_RESET ((gU32)0x003FFFEF)
#define SDCMR_CTB2_RESET ((gU32)0x003FFFF7)
#define SDCMR_CTB1_2_RESET ((gU32)0x003FFFE7)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
@ -134,7 +134,7 @@
* @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4
* @retval None
*/
void FMC_NORSRAMDeInit(uint32_t FMC_Bank)
void FMC_NORSRAMDeInit(gU32 FMC_Bank)
{
/* Check the parameter */
assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank));
@ -163,7 +163,7 @@ void FMC_NORSRAMDeInit(uint32_t FMC_Bank)
*/
void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
{
uint32_t tmpr = 0;
gU32 tmpr = 0;
/* Check the parameters */
assert_param(IS_FMC_NORSRAM_BANK(FMC_NORSRAMInitStruct->FMC_Bank));
@ -190,7 +190,7 @@ void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
/* NOR/SRAM Bank control register configuration */
FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] =
(uint32_t)FMC_NORSRAMInitStruct->FMC_DataAddressMux |
(gU32)FMC_NORSRAMInitStruct->FMC_DataAddressMux |
FMC_NORSRAMInitStruct->FMC_MemoryType |
FMC_NORSRAMInitStruct->FMC_MemoryDataWidth |
FMC_NORSRAMInitStruct->FMC_BurstAccessMode |
@ -207,22 +207,22 @@ void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
if(FMC_NORSRAMInitStruct->FMC_MemoryType == FMC_MemoryType_NOR)
{
FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] |= (uint32_t)BCR_FACCEN_SET;
FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] |= (gU32)BCR_FACCEN_SET;
}
/* Configure Continuous clock feature when bank2..4 is used */
if((FMC_NORSRAMInitStruct->FMC_ContinousClock == FMC_CClock_SyncAsync) && (FMC_NORSRAMInitStruct->FMC_Bank != FMC_Bank1_NORSRAM1))
{
tmpr = (uint32_t)((FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1]) & ~(((uint32_t)0x0F) << 20));
tmpr = (gU32)((FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1]) & ~(((gU32)0x0F) << 20));
FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1] |= FMC_NORSRAMInitStruct->FMC_ContinousClock;
FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1] |= FMC_BurstAccessMode_Enable;
FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1] = (uint32_t)(tmpr | (((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision)-1) << 20));
FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1] = (gU32)(tmpr | (((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision)-1) << 20));
}
/* NOR/SRAM Bank timing register configuration */
FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank+1] =
(uint32_t)FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime |
(gU32)FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime |
(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime << 4) |
(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime << 8) |
(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration << 16) |
@ -241,7 +241,7 @@ void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode));
FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] =
(uint32_t)FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime |
(gU32)FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime |
(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime << 4 )|
(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime << 8) |
((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision) << 20) |
@ -306,7 +306,7 @@ void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
* @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState)
void FMC_NORSRAMCmd(gU32 FMC_Bank, FunctionalState NewState)
{
assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank));
assert_param(IS_FUNCTIONAL_STATE(NewState));
@ -379,7 +379,7 @@ void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState)
* @arg FMC_Bank3_NAND: FMC Bank3 NAND
* @retval None
*/
void FMC_NANDDeInit(uint32_t FMC_Bank)
void FMC_NANDDeInit(gU32 FMC_Bank)
{
/* Check the parameter */
assert_param(IS_FMC_NAND_BANK(FMC_Bank));
@ -412,7 +412,7 @@ void FMC_NANDDeInit(uint32_t FMC_Bank)
*/
void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct)
{
uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
gU32 tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
/* Check the parameters */
assert_param(IS_FMC_NAND_BANK(FMC_NANDInitStruct->FMC_Bank));
@ -432,7 +432,7 @@ void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct)
assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime));
/* Set the tmppcr value according to FMC_NANDInitStruct parameters */
tmppcr = (uint32_t)FMC_NANDInitStruct->FMC_Waitfeature |
tmppcr = (gU32)FMC_NANDInitStruct->FMC_Waitfeature |
PCR_MEMORYTYPE_NAND |
FMC_NANDInitStruct->FMC_MemoryDataWidth |
FMC_NANDInitStruct->FMC_ECC |
@ -441,13 +441,13 @@ void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct)
(FMC_NANDInitStruct->FMC_TARSetupTime << 13);
/* Set tmppmem value according to FMC_CommonSpaceTimingStructure parameters */
tmppmem = (uint32_t)FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime |
tmppmem = (gU32)FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime |
(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) |
(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)|
(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24);
/* Set tmppatt value according to FMC_AttributeSpaceTimingStructure parameters */
tmppatt = (uint32_t)FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime |
tmppatt = (gU32)FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime |
(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) |
(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)|
(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24);
@ -504,7 +504,7 @@ void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct)
* @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState)
void FMC_NANDCmd(gU32 FMC_Bank, FunctionalState NewState)
{
assert_param(IS_FMC_NAND_BANK(FMC_Bank));
assert_param(IS_FUNCTIONAL_STATE(NewState));
@ -544,7 +544,7 @@ void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState)
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState)
void FMC_NANDECCCmd(gU32 FMC_Bank, FunctionalState NewState)
{
assert_param(IS_FMC_NAND_BANK(FMC_Bank));
assert_param(IS_FUNCTIONAL_STATE(NewState));
@ -583,9 +583,9 @@ void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState)
* @arg FMC_Bank3_NAND: FMC Bank3 NAND
* @retval The Error Correction Code (ECC) value.
*/
uint32_t FMC_GetECC(uint32_t FMC_Bank)
gU32 FMC_GetECC(gU32 FMC_Bank)
{
uint32_t eccval = 0x00000000;
gU32 eccval = 0x00000000;
if(FMC_Bank == FMC_Bank2_NAND)
{
@ -686,25 +686,25 @@ void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct)
assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime));
/* Set the PCR4 register value according to FMC_PCCARDInitStruct parameters */
FMC_Bank4->PCR4 = (uint32_t)FMC_PCCARDInitStruct->FMC_Waitfeature |
FMC_Bank4->PCR4 = (gU32)FMC_PCCARDInitStruct->FMC_Waitfeature |
FMC_NAND_MemoryDataWidth_16b |
(FMC_PCCARDInitStruct->FMC_TCLRSetupTime << 9) |
(FMC_PCCARDInitStruct->FMC_TARSetupTime << 13);
/* Set PMEM4 register value according to FMC_CommonSpaceTimingStructure parameters */
FMC_Bank4->PMEM4 = (uint32_t)FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime |
FMC_Bank4->PMEM4 = (gU32)FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime |
(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) |
(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)|
(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24);
/* Set PATT4 register value according to FMC_AttributeSpaceTimingStructure parameters */
FMC_Bank4->PATT4 = (uint32_t)FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime |
FMC_Bank4->PATT4 = (gU32)FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime |
(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) |
(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)|
(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24);
/* Set PIO4 register value according to FMC_IOSpaceTimingStructure parameters */
FMC_Bank4->PIO4 = (uint32_t)FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime |
FMC_Bank4->PIO4 = (gU32)FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime |
(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime << 8) |
(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime << 16)|
(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime << 24);
@ -814,7 +814,7 @@ void FMC_PCCARDCmd(FunctionalState NewState)
* @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
* @retval None
*/
void FMC_SDRAMDeInit(uint32_t FMC_Bank)
void FMC_SDRAMDeInit(gU32 FMC_Bank)
{
/* Check the parameter */
assert_param(IS_FMC_SDRAM_BANK(FMC_Bank));
@ -837,10 +837,10 @@ void FMC_SDRAMDeInit(uint32_t FMC_Bank)
void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
{
/* temporary registers */
uint32_t tmpr1 = 0;
uint32_t tmpr2 = 0;
uint32_t tmpr3 = 0;
uint32_t tmpr4 = 0;
gU32 tmpr1 = 0;
gU32 tmpr2 = 0;
gU32 tmpr3 = 0;
gU32 tmpr4 = 0;
/* Check the parameters */
@ -866,7 +866,7 @@ void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
assert_param(IS_FMC_RCD_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay));
/* SDRAM bank control register configuration */
tmpr1 = (uint32_t)FMC_SDRAMInitStruct->FMC_ColumnBitsNumber |
tmpr1 = (gU32)FMC_SDRAMInitStruct->FMC_ColumnBitsNumber |
FMC_SDRAMInitStruct->FMC_RowBitsNumber |
FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth |
FMC_SDRAMInitStruct->FMC_InternalBankNumber |
@ -882,7 +882,7 @@ void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
}
else /* SDCR2 "don't care" bits configuration */
{
tmpr3 = (uint32_t)FMC_SDRAMInitStruct->FMC_SDClockPeriod |
tmpr3 = (gU32)FMC_SDRAMInitStruct->FMC_SDClockPeriod |
FMC_SDRAMInitStruct->FMC_ReadBurst |
FMC_SDRAMInitStruct->FMC_ReadPipeDelay;
@ -892,7 +892,7 @@ void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
/* SDRAM bank timing register configuration */
if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM )
{
tmpr2 = (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |
tmpr2 = (gU32)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |
(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) |
(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) |
(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |
@ -904,12 +904,12 @@ void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
}
else /* SDTR "don't care bits configuration */
{
tmpr2 = (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |
tmpr2 = (gU32)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |
(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) |
(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) |
(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16);
tmpr4 = (uint32_t)(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |
tmpr4 = (gU32)(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |
(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20);
FMC_Bank5_6->SDTR[FMC_Bank1_SDRAM] = tmpr4;
@ -956,7 +956,7 @@ void FMC_SDRAMStructInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
*/
void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct)
{
uint32_t tmpr = 0x0;
gU32 tmpr = 0x0;
/* check parameters */
assert_param(IS_FMC_COMMAND_MODE(FMC_SDRAMCommandStruct->FMC_CommandMode));
@ -964,7 +964,7 @@ void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct)
assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber));
assert_param(IS_FMC_MODE_REGISTER(FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition));
tmpr = (uint32_t)(FMC_SDRAMCommandStruct->FMC_CommandMode |
tmpr = (gU32)(FMC_SDRAMCommandStruct->FMC_CommandMode |
FMC_SDRAMCommandStruct->FMC_CommandTarget |
(((FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber)-1)<<5) |
((FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition)<<9));
@ -980,9 +980,9 @@ void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct)
* FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
* @retval The FMC SDRAM bank mode status
*/
uint32_t FMC_GetModeStatus(uint32_t SDRAM_Bank)
gU32 FMC_GetModeStatus(gU32 SDRAM_Bank)
{
uint32_t tmpreg = 0;
gU32 tmpreg = 0;
/* Check the parameter */
assert_param(IS_FMC_SDRAM_BANK(SDRAM_Bank));
@ -990,11 +990,11 @@ uint32_t FMC_GetModeStatus(uint32_t SDRAM_Bank)
/* Get the busy flag status */
if(SDRAM_Bank == FMC_Bank1_SDRAM)
{
tmpreg = (uint32_t)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES1);
tmpreg = (gU32)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES1);
}
else
{
tmpreg = ((uint32_t)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES2) >> 2);
tmpreg = ((gU32)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES2) >> 2);
}
/* Return the mode status */
@ -1006,7 +1006,7 @@ uint32_t FMC_GetModeStatus(uint32_t SDRAM_Bank)
* @param FMC_Count: specifies the Refresh timer count.
* @retval None
*/
void FMC_SetRefreshCount(uint32_t FMC_Count)
void FMC_SetRefreshCount(gU32 FMC_Count)
{
/* check the parameters */
assert_param(IS_FMC_REFRESH_COUNT(FMC_Count));
@ -1020,7 +1020,7 @@ void FMC_SetRefreshCount(uint32_t FMC_Count)
* @param FMC_Number: specifies the auto Refresh number.
* @retval None
*/
void FMC_SetAutoRefresh_Number(uint32_t FMC_Number)
void FMC_SetAutoRefresh_Number(gU32 FMC_Number)
{
/* check the parameters */
assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_Number));
@ -1036,7 +1036,7 @@ void FMC_SetAutoRefresh_Number(uint32_t FMC_Number)
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewState)
void FMC_SDRAMWriteProtectionConfig(gU32 SDRAM_Bank, FunctionalState NewState)
{
/* Check the parameter */
assert_param(IS_FUNCTIONAL_STATE(NewState));
@ -1088,7 +1088,7 @@ void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewStat
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState)
void FMC_ITConfig(gU32 FMC_Bank, gU32 FMC_IT, FunctionalState NewState)
{
assert_param(IS_FMC_IT_BANK(FMC_Bank));
assert_param(IS_FMC_IT(FMC_IT));
@ -1124,23 +1124,23 @@ void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState)
if(FMC_Bank == FMC_Bank2_NAND)
{
FMC_Bank2->SR2 &= (uint32_t)~FMC_IT;
FMC_Bank2->SR2 &= (gU32)~FMC_IT;
}
/* Disable the selected FMC_Bank3 interrupts */
else if (FMC_Bank == FMC_Bank3_NAND)
{
FMC_Bank3->SR3 &= (uint32_t)~FMC_IT;
FMC_Bank3->SR3 &= (gU32)~FMC_IT;
}
/* Disable the selected FMC_Bank4 interrupts */
else if(FMC_Bank == FMC_Bank4_PCCARD)
{
FMC_Bank4->SR4 &= (uint32_t)~FMC_IT;
FMC_Bank4->SR4 &= (gU32)~FMC_IT;
}
/* Disable the selected FMC_Bank5_6 interrupt */
else
{
/* Disables the interrupt if the refresh error flag is not set */
FMC_Bank5_6->SDRTR &= (uint32_t)~FMC_IT;
FMC_Bank5_6->SDRTR &= (gU32)~FMC_IT;
}
}
}
@ -1165,10 +1165,10 @@ void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState)
* @arg FMC_FLAG_Busy: Busy status Flag.
* @retval The new state of FMC_FLAG (SET or RESET).
*/
FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG)
FlagStatus FMC_GetFlagStatus(gU32 FMC_Bank, gU32 FMC_FLAG)
{
FlagStatus bitstatus = RESET;
uint32_t tmpsr = 0x00000000;
gU32 tmpsr = 0x00000000;
/* Check the parameters */
assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank));
@ -1221,7 +1221,7 @@ FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG)
* @arg FMC_FLAG_Refresh: Refresh error Flag.
* @retval None
*/
void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG)
void FMC_ClearFlag(gU32 FMC_Bank, gU32 FMC_FLAG)
{
/* Check the parameters */
assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank));
@ -1264,13 +1264,13 @@ void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG)
* @arg FMC_IT_Refresh: Refresh error detection interrupt.
* @retval The new state of FMC_IT (SET or RESET).
*/
ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT)
ITStatus FMC_GetITStatus(gU32 FMC_Bank, gU32 FMC_IT)
{
ITStatus bitstatus = RESET;
uint32_t tmpsr = 0x0;
uint32_t tmpsr2 = 0x0;
uint32_t itstatus = 0x0;
uint32_t itenable = 0x0;
gU32 tmpsr = 0x0;
gU32 tmpsr2 = 0x0;
gU32 itstatus = 0x0;
gU32 itenable = 0x0;
/* Check the parameters */
assert_param(IS_FMC_IT_BANK(FMC_Bank));
@ -1308,7 +1308,7 @@ ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT)
itstatus = tmpsr & (FMC_IT >> 3);
}
if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
if ((itstatus != (gU32)RESET) && (itenable != (gU32)RESET))
{
bitstatus = SET;
}
@ -1336,7 +1336,7 @@ ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT)
* @arg FMC_IT_Refresh: Refresh error detection interrupt.
* @retval None
*/
void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT)
void FMC_ClearITPendingBit(gU32 FMC_Bank, gU32 FMC_IT)
{
/* Check the parameters */
assert_param(IS_FMC_IT_BANK(FMC_Bank));

342
boards/base/STM32F429i-Discovery/chibios/stm32f4xx_fmc.h
View file

@ -57,31 +57,31 @@
*/
typedef struct
{
uint32_t FMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
gU32 FMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address setup time.
This parameter can be a value between 0 and 15.
@note This parameter is not used with synchronous NOR Flash memories. */
uint32_t FMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
gU32 FMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address hold time.
This parameter can be a value between 1 and 15.
@note This parameter is not used with synchronous NOR Flash memories.*/
uint32_t FMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
gU32 FMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data setup time.
This parameter can be a value between 1 and 255.
@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
uint32_t FMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
gU32 FMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
the duration of the bus turnaround.
This parameter can be a value between 0 and 15.
@note This parameter is only used for multiplexed NOR Flash memories. */
uint32_t FMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
gU32 FMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
This parameter can be a value between 1 and 15.
@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
uint32_t FMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
gU32 FMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
to the memory before getting the first data.
The parameter value depends on the memory type as shown below:
- It must be set to 0 in case of a CRAM
@ -89,7 +89,7 @@ typedef struct
- It may assume a value between 0 and 15 in NOR Flash memories
with synchronous burst mode enable */
uint32_t FMC_AccessMode; /*!< Specifies the asynchronous access mode.
gU32 FMC_AccessMode; /*!< Specifies the asynchronous access mode.
This parameter can be a value of @ref FMC_Access_Mode */
}FMC_NORSRAMTimingInitTypeDef;
@ -98,55 +98,55 @@ typedef struct
*/
typedef struct
{
uint32_t FMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
gU32 FMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
This parameter can be a value of @ref FMC_NORSRAM_Bank */
uint32_t FMC_DataAddressMux; /*!< Specifies whether the address and data values are
gU32 FMC_DataAddressMux; /*!< Specifies whether the address and data values are
multiplexed on the databus or not.
This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
uint32_t FMC_MemoryType; /*!< Specifies the type of external memory attached to
gU32 FMC_MemoryType; /*!< Specifies the type of external memory attached to
the corresponding memory bank.
This parameter can be a value of @ref FMC_Memory_Type */
uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width.
gU32 FMC_MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
uint32_t FMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
gU32 FMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
valid only with synchronous burst Flash memories.
This parameter can be a value of @ref FMC_Burst_Access_Mode */
uint32_t FMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
gU32 FMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
the Flash memory in burst mode.
This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
uint32_t FMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
gU32 FMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
memory, valid only when accessing Flash memories in burst mode.
This parameter can be a value of @ref FMC_Wrap_Mode */
uint32_t FMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
gU32 FMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
valid only when accessing memories in burst mode.
This parameter can be a value of @ref FMC_Wait_Timing */
uint32_t FMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FMC.
gU32 FMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FMC.
This parameter can be a value of @ref FMC_Write_Operation */
uint32_t FMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait
gU32 FMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait
signal, valid for Flash memory access in burst mode.
This parameter can be a value of @ref FMC_Wait_Signal */
uint32_t FMC_ExtendedMode; /*!< Enables or disables the extended mode.
gU32 FMC_ExtendedMode; /*!< Enables or disables the extended mode.
This parameter can be a value of @ref FMC_Extended_Mode */
uint32_t FMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
gU32 FMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
valid only with asynchronous Flash memories.
This parameter can be a value of @ref FMC_AsynchronousWait */
uint32_t FMC_WriteBurst; /*!< Enables or disables the write burst operation.
gU32 FMC_WriteBurst; /*!< Enables or disables the write burst operation.
This parameter can be a value of @ref FMC_Write_Burst */
uint32_t FMC_ContinousClock; /*!< Enables or disables the FMC clock output to external memory devices.
gU32 FMC_ContinousClock; /*!< Enables or disables the FMC clock output to external memory devices.
This parameter is only enabled through the FMC_BCR1 register, and don't care
through FMC_BCR2..4 registers.
This parameter can be a value of @ref FMC_Continous_Clock */
@ -162,26 +162,26 @@ typedef struct
*/
typedef struct
{
uint32_t FMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
gU32 FMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
the command assertion for NAND-Flash read or write access
to common/Attribute or I/O memory space (depending on
the memory space timing to be configured).
This parameter can be a value between 0 and 255.*/
uint32_t FMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
gU32 FMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
command for NAND-Flash read or write access to
common/Attribute or I/O memory space (depending on the
memory space timing to be configured).
This parameter can be a number between 0 and 255 */
uint32_t FMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
gU32 FMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
(and data for write access) after the command de-assertion
for NAND-Flash read or write access to common/Attribute
or I/O memory space (depending on the memory space timing
to be configured).
This parameter can be a number between 0 and 255 */
uint32_t FMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
gU32 FMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
databus is kept in HiZ after the start of a NAND-Flash
write access to common/Attribute or I/O memory space (depending
on the memory space timing to be configured).
@ -193,26 +193,26 @@ typedef struct
*/
typedef struct
{
uint32_t FMC_Bank; /*!< Specifies the NAND memory bank that will be used.
gU32 FMC_Bank; /*!< Specifies the NAND memory bank that will be used.
This parameter can be a value of @ref FMC_NAND_Bank */
uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
gU32 FMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
This parameter can be any value of @ref FMC_Wait_feature */
uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width.
gU32 FMC_MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be any value of @ref FMC_NAND_Data_Width */
uint32_t FMC_ECC; /*!< Enables or disables the ECC computation.
gU32 FMC_ECC; /*!< Enables or disables the ECC computation.
This parameter can be any value of @ref FMC_ECC */
uint32_t FMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
gU32 FMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
This parameter can be any value of @ref FMC_ECC_Page_Size */
uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
gU32 FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between 0 and 255. */
uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
gU32 FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between 0 and 255 */
@ -227,14 +227,14 @@ typedef struct
typedef struct
{
uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
gU32 FMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
This parameter can be any value of @ref FMC_Wait_feature */
uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
gU32 FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between 0 and 255. */
uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
gU32 FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between 0 and 255 */
@ -252,31 +252,31 @@ typedef struct
typedef struct
{
uint32_t FMC_LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
gU32 FMC_LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
an active or Refresh command in number of memory clock cycles.
This parameter can be a value between 1 and 16. */
uint32_t FMC_ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
gU32 FMC_ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
issuing the Activate command in number of memory clock cycles.
This parameter can be a value between 1 and 16. */
uint32_t FMC_SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
gU32 FMC_SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
cycles.
This parameter can be a value between 1 and 16. */
uint32_t FMC_RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
gU32 FMC_RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
and the delay between two consecutive Refresh commands in number of
memory clock cycles.
This parameter can be a value between 1 and 16. */
uint32_t FMC_WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
gU32 FMC_WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
This parameter can be a value between 1 and 16. */
uint32_t FMC_RPDelay; /*!< Defines the delay between a Precharge Command and an other command
gU32 FMC_RPDelay; /*!< Defines the delay between a Precharge Command and an other command
in number of memory clock cycles.
This parameter can be a value between 1 and 16. */
uint32_t FMC_RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write command
gU32 FMC_RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write command
in number of memory clock cycles.
This parameter can be a value between 1 and 16. */
@ -289,17 +289,17 @@ typedef struct
typedef struct
{
uint32_t FMC_CommandMode; /*!< Defines the command issued to the SDRAM device.
gU32 FMC_CommandMode; /*!< Defines the command issued to the SDRAM device.
This parameter can be a value of @ref FMC_Command_Mode. */
uint32_t FMC_CommandTarget; /*!< Defines which bank (1 or 2) the command will be issued to.
gU32 FMC_CommandTarget; /*!< Defines which bank (1 or 2) the command will be issued to.
This parameter can be a value of @ref FMC_Command_Target. */
uint32_t FMC_AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
gU32 FMC_AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
in auto refresh mode.
This parameter can be a value between 1 and 16. */
uint32_t FMC_ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
gU32 FMC_ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
}FMC_SDRAMCommandTypeDef;
@ -309,36 +309,36 @@ typedef struct
typedef struct
{
uint32_t FMC_Bank; /*!< Specifies the SDRAM memory bank that will be used.
gU32 FMC_Bank; /*!< Specifies the SDRAM memory bank that will be used.
This parameter can be a value of @ref FMC_SDRAM_Bank */
uint32_t FMC_ColumnBitsNumber; /*!< Defines the number of bits of column address.
gU32 FMC_ColumnBitsNumber; /*!< Defines the number of bits of column address.
This parameter can be a value of @ref FMC_ColumnBits_Number. */
uint32_t FMC_RowBitsNumber; /*!< Defines the number of bits of column address..
gU32 FMC_RowBitsNumber; /*!< Defines the number of bits of column address..
This parameter can be a value of @ref FMC_RowBits_Number. */
uint32_t FMC_SDMemoryDataWidth; /*!< Defines the memory device width.
gU32 FMC_SDMemoryDataWidth; /*!< Defines the memory device width.
This parameter can be a value of @ref FMC_SDMemory_Data_Width. */
uint32_t FMC_InternalBankNumber; /*!< Defines the number of bits of column address.
gU32 FMC_InternalBankNumber; /*!< Defines the number of bits of column address.
This parameter can be of @ref FMC_InternalBank_Number. */
uint32_t FMC_CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
gU32 FMC_CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
This parameter can be a value of @ref FMC_CAS_Latency. */
uint32_t FMC_WriteProtection; /*!< Enables the SDRAM bank to be accessed in write mode.
gU32 FMC_WriteProtection; /*!< Enables the SDRAM bank to be accessed in write mode.
This parameter can be a value of @ref FMC_Write_Protection. */
uint32_t FMC_SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM Banks and they allow to disable
gU32 FMC_SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM Banks and they allow to disable
the clock before changing frequency.
This parameter can be a value of @ref FMC_SDClock_Period. */
uint32_t FMC_ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read commands
gU32 FMC_ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read commands
during the CAS latency and stores data in the Read FIFO.
This parameter can be a value of @ref FMC_Read_Burst. */
uint32_t FMC_ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
gU32 FMC_ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
This parameter can be a value of @ref FMC_ReadPipe_Delay. */
FMC_SDRAMTimingInitTypeDef* FMC_SDRAMTimingStruct; /*!< Timing Parameters for write and read access*/
@ -355,10 +355,10 @@ typedef struct
/** @defgroup FMC_NORSRAM_Bank
* @{
*/
#define FMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
#define FMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
#define FMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
#define FMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
#define FMC_Bank1_NORSRAM1 ((gU32)0x00000000)
#define FMC_Bank1_NORSRAM2 ((gU32)0x00000002)
#define FMC_Bank1_NORSRAM3 ((gU32)0x00000004)
#define FMC_Bank1_NORSRAM4 ((gU32)0x00000006)
#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_Bank1_NORSRAM1) || \
((BANK) == FMC_Bank1_NORSRAM2) || \
@ -371,8 +371,8 @@ typedef struct
/** @defgroup FMC_NAND_Bank
* @{
*/
#define FMC_Bank2_NAND ((uint32_t)0x00000010)
#define FMC_Bank3_NAND ((uint32_t)0x00000100)
#define FMC_Bank2_NAND ((gU32)0x00000010)
#define FMC_Bank3_NAND ((gU32)0x00000100)
#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \
((BANK) == FMC_Bank3_NAND))
@ -383,7 +383,7 @@ typedef struct
/** @defgroup FMC_PCCARD_Bank
* @{
*/
#define FMC_Bank4_PCCARD ((uint32_t)0x00001000)
#define FMC_Bank4_PCCARD ((gU32)0x00001000)
/**
* @}
*/
@ -391,8 +391,8 @@ typedef struct
/** @defgroup FMC_SDRAM_Bank
* @{
*/
#define FMC_Bank1_SDRAM ((uint32_t)0x00000000)
#define FMC_Bank2_SDRAM ((uint32_t)0x00000001)
#define FMC_Bank1_SDRAM ((gU32)0x00000000)
#define FMC_Bank2_SDRAM ((gU32)0x00000001)
#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_Bank1_SDRAM) || \
((BANK) == FMC_Bank2_SDRAM))
@ -410,8 +410,8 @@ typedef struct
* @{
*/
#define FMC_DataAddressMux_Disable ((uint32_t)0x00000000)
#define FMC_DataAddressMux_Enable ((uint32_t)0x00000002)
#define FMC_DataAddressMux_Disable ((gU32)0x00000000)
#define FMC_DataAddressMux_Enable ((gU32)0x00000002)
#define IS_FMC_MUX(MUX) (((MUX) == FMC_DataAddressMux_Disable) || \
((MUX) == FMC_DataAddressMux_Enable))
@ -423,9 +423,9 @@ typedef struct
* @{
*/
#define FMC_MemoryType_SRAM ((uint32_t)0x00000000)
#define FMC_MemoryType_PSRAM ((uint32_t)0x00000004)
#define FMC_MemoryType_NOR ((uint32_t)0x00000008)
#define FMC_MemoryType_SRAM ((gU32)0x00000000)
#define FMC_MemoryType_PSRAM ((gU32)0x00000004)
#define FMC_MemoryType_NOR ((gU32)0x00000008)
#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MemoryType_SRAM) || \
((MEMORY) == FMC_MemoryType_PSRAM)|| \
@ -438,9 +438,9 @@ typedef struct
* @{
*/
#define FMC_NORSRAM_MemoryDataWidth_8b ((uint32_t)0x00000000)
#define FMC_NORSRAM_MemoryDataWidth_16b ((uint32_t)0x00000010)
#define FMC_NORSRAM_MemoryDataWidth_32b ((uint32_t)0x00000020)
#define FMC_NORSRAM_MemoryDataWidth_8b ((gU32)0x00000000)
#define FMC_NORSRAM_MemoryDataWidth_16b ((gU32)0x00000010)
#define FMC_NORSRAM_MemoryDataWidth_32b ((gU32)0x00000020)
#define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MemoryDataWidth_8b) || \
((WIDTH) == FMC_NORSRAM_MemoryDataWidth_16b) || \
@ -453,8 +453,8 @@ typedef struct
* @{
*/
#define FMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
#define FMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
#define FMC_BurstAccessMode_Disable ((gU32)0x00000000)
#define FMC_BurstAccessMode_Enable ((gU32)0x00000100)
#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BurstAccessMode_Disable) || \
((STATE) == FMC_BurstAccessMode_Enable))
@ -465,8 +465,8 @@ typedef struct
/** @defgroup FMC_AsynchronousWait
* @{
*/
#define FMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
#define FMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
#define FMC_AsynchronousWait_Disable ((gU32)0x00000000)
#define FMC_AsynchronousWait_Enable ((gU32)0x00008000)
#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_AsynchronousWait_Disable) || \
((STATE) == FMC_AsynchronousWait_Enable))
@ -477,8 +477,8 @@ typedef struct
/** @defgroup FMC_Wait_Signal_Polarity
* @{
*/
#define FMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
#define FMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
#define FMC_WaitSignalPolarity_Low ((gU32)0x00000000)
#define FMC_WaitSignalPolarity_High ((gU32)0x00000200)
#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WaitSignalPolarity_Low) || \
((POLARITY) == FMC_WaitSignalPolarity_High))
@ -489,8 +489,8 @@ typedef struct
/** @defgroup FMC_Wrap_Mode
* @{
*/
#define FMC_WrapMode_Disable ((uint32_t)0x00000000)
#define FMC_WrapMode_Enable ((uint32_t)0x00000400)
#define FMC_WrapMode_Disable ((gU32)0x00000000)
#define FMC_WrapMode_Enable ((gU32)0x00000400)
#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WrapMode_Disable) || \
((MODE) == FMC_WrapMode_Enable))
@ -501,8 +501,8 @@ typedef struct
/** @defgroup FMC_Wait_Timing
* @{
*/
#define FMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
#define FMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
#define FMC_WaitSignalActive_BeforeWaitState ((gU32)0x00000000)
#define FMC_WaitSignalActive_DuringWaitState ((gU32)0x00000800)
#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WaitSignalActive_BeforeWaitState) || \
((ACTIVE) == FMC_WaitSignalActive_DuringWaitState))
@ -513,8 +513,8 @@ typedef struct
/** @defgroup FMC_Write_Operation
* @{
*/
#define FMC_WriteOperation_Disable ((uint32_t)0x00000000)
#define FMC_WriteOperation_Enable ((uint32_t)0x00001000)
#define FMC_WriteOperation_Disable ((gU32)0x00000000)
#define FMC_WriteOperation_Enable ((gU32)0x00001000)
#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WriteOperation_Disable) || \
((OPERATION) == FMC_WriteOperation_Enable))
@ -525,8 +525,8 @@ typedef struct
/** @defgroup FMC_Wait_Signal
* @{
*/
#define FMC_WaitSignal_Disable ((uint32_t)0x00000000)
#define FMC_WaitSignal_Enable ((uint32_t)0x00002000)
#define FMC_WaitSignal_Disable ((gU32)0x00000000)
#define FMC_WaitSignal_Enable ((gU32)0x00002000)
#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WaitSignal_Disable) || \
((SIGNAL) == FMC_WaitSignal_Enable))
@ -537,8 +537,8 @@ typedef struct
/** @defgroup FMC_Extended_Mode
* @{
*/
#define FMC_ExtendedMode_Disable ((uint32_t)0x00000000)
#define FMC_ExtendedMode_Enable ((uint32_t)0x00004000)
#define FMC_ExtendedMode_Disable ((gU32)0x00000000)
#define FMC_ExtendedMode_Enable ((gU32)0x00004000)
#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_ExtendedMode_Disable) || \
((MODE) == FMC_ExtendedMode_Enable))
@ -550,8 +550,8 @@ typedef struct
* @{
*/
#define FMC_WriteBurst_Disable ((uint32_t)0x00000000)
#define FMC_WriteBurst_Enable ((uint32_t)0x00080000)
#define FMC_WriteBurst_Disable ((gU32)0x00000000)
#define FMC_WriteBurst_Enable ((gU32)0x00080000)
#define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WriteBurst_Disable) || \
((BURST) == FMC_WriteBurst_Enable))
@ -563,8 +563,8 @@ typedef struct
* @{
*/
#define FMC_CClock_SyncOnly ((uint32_t)0x00000000)
#define FMC_CClock_SyncAsync ((uint32_t)0x00100000)
#define FMC_CClock_SyncOnly ((gU32)0x00000000)
#define FMC_CClock_SyncAsync ((gU32)0x00100000)
#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CClock_SyncOnly) || \
((CCLOCK) == FMC_CClock_SyncAsync))
@ -623,10 +623,10 @@ typedef struct
/** @defgroup FMC_Access_Mode
* @{
*/
#define FMC_AccessMode_A ((uint32_t)0x00000000)
#define FMC_AccessMode_B ((uint32_t)0x10000000)
#define FMC_AccessMode_C ((uint32_t)0x20000000)
#define FMC_AccessMode_D ((uint32_t)0x30000000)
#define FMC_AccessMode_A ((gU32)0x00000000)
#define FMC_AccessMode_B ((gU32)0x10000000)
#define FMC_AccessMode_C ((gU32)0x20000000)
#define FMC_AccessMode_D ((gU32)0x30000000)
#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_AccessMode_A) || \
((MODE) == FMC_AccessMode_B) || \
@ -647,8 +647,8 @@ typedef struct
/** @defgroup FMC_Wait_feature
* @{
*/
#define FMC_Waitfeature_Disable ((uint32_t)0x00000000)
#define FMC_Waitfeature_Enable ((uint32_t)0x00000002)
#define FMC_Waitfeature_Disable ((gU32)0x00000000)
#define FMC_Waitfeature_Enable ((gU32)0x00000002)
#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_Waitfeature_Disable) || \
((FEATURE) == FMC_Waitfeature_Enable))
@ -659,8 +659,8 @@ typedef struct
/** @defgroup FMC_NAND_Data_Width
* @{
*/
#define FMC_NAND_MemoryDataWidth_8b ((uint32_t)0x00000000)
#define FMC_NAND_MemoryDataWidth_16b ((uint32_t)0x00000010)
#define FMC_NAND_MemoryDataWidth_8b ((gU32)0x00000000)
#define FMC_NAND_MemoryDataWidth_16b ((gU32)0x00000010)
#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MemoryDataWidth_8b) || \
((WIDTH) == FMC_NAND_MemoryDataWidth_16b))
@ -671,8 +671,8 @@ typedef struct
/** @defgroup FMC_ECC
* @{
*/
#define FMC_ECC_Disable ((uint32_t)0x00000000)
#define FMC_ECC_Enable ((uint32_t)0x00000040)
#define FMC_ECC_Disable ((gU32)0x00000000)
#define FMC_ECC_Enable ((gU32)0x00000040)
#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_ECC_Disable) || \
((STATE) == FMC_ECC_Enable))
@ -683,12 +683,12 @@ typedef struct
/** @defgroup FMC_ECC_Page_Size
* @{
*/
#define FMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
#define FMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
#define FMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
#define FMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
#define FMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
#define FMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
#define FMC_ECCPageSize_256Bytes ((gU32)0x00000000)
#define FMC_ECCPageSize_512Bytes ((gU32)0x00020000)
#define FMC_ECCPageSize_1024Bytes ((gU32)0x00040000)
#define FMC_ECCPageSize_2048Bytes ((gU32)0x00060000)
#define FMC_ECCPageSize_4096Bytes ((gU32)0x00080000)
#define FMC_ECCPageSize_8192Bytes ((gU32)0x000A0000)
#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_ECCPageSize_256Bytes) || \
((SIZE) == FMC_ECCPageSize_512Bytes) || \
@ -760,10 +760,10 @@ typedef struct
/** @defgroup FMC_ColumnBits_Number
* @{
*/
#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000)
#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001)
#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002)
#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003)
#define FMC_ColumnBits_Number_8b ((gU32)0x00000000)
#define FMC_ColumnBits_Number_9b ((gU32)0x00000001)
#define FMC_ColumnBits_Number_10b ((gU32)0x00000002)
#define FMC_ColumnBits_Number_11b ((gU32)0x00000003)
#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_ColumnBits_Number_8b) || \
((COLUMN) == FMC_ColumnBits_Number_9b) || \
@ -777,9 +777,9 @@ typedef struct
/** @defgroup FMC_RowBits_Number
* @{
*/
#define FMC_RowBits_Number_11b ((uint32_t)0x00000000)
#define FMC_RowBits_Number_12b ((uint32_t)0x00000004)
#define FMC_RowBits_Number_13b ((uint32_t)0x00000008)
#define FMC_RowBits_Number_11b ((gU32)0x00000000)
#define FMC_RowBits_Number_12b ((gU32)0x00000004)
#define FMC_RowBits_Number_13b ((gU32)0x00000008)
#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_RowBits_Number_11b) || \
((ROW) == FMC_RowBits_Number_12b) || \
@ -792,9 +792,9 @@ typedef struct
/** @defgroup FMC_SDMemory_Data_Width
* @{
*/
#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000)
#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010)
#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020)
#define FMC_SDMemory_Width_8b ((gU32)0x00000000)
#define FMC_SDMemory_Width_16b ((gU32)0x00000010)
#define FMC_SDMemory_Width_32b ((gU32)0x00000020)
#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDMemory_Width_8b) || \
((WIDTH) == FMC_SDMemory_Width_16b) || \
@ -807,8 +807,8 @@ typedef struct
/** @defgroup FMC_InternalBank_Number
* @{
*/
#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000)
#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040)
#define FMC_InternalBank_Number_2 ((gU32)0x00000000)
#define FMC_InternalBank_Number_4 ((gU32)0x00000040)
#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_InternalBank_Number_2) || \
((NUMBER) == FMC_InternalBank_Number_4))
@ -821,9 +821,9 @@ typedef struct
/** @defgroup FMC_CAS_Latency
* @{
*/
#define FMC_CAS_Latency_1 ((uint32_t)0x00000080)
#define FMC_CAS_Latency_2 ((uint32_t)0x00000100)
#define FMC_CAS_Latency_3 ((uint32_t)0x00000180)
#define FMC_CAS_Latency_1 ((gU32)0x00000080)
#define FMC_CAS_Latency_2 ((gU32)0x00000100)
#define FMC_CAS_Latency_3 ((gU32)0x00000180)
#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_CAS_Latency_1) || \
((LATENCY) == FMC_CAS_Latency_2) || \
@ -836,8 +836,8 @@ typedef struct
/** @defgroup FMC_Write_Protection
* @{
*/
#define FMC_Write_Protection_Disable ((uint32_t)0x00000000)
#define FMC_Write_Protection_Enable ((uint32_t)0x00000200)
#define FMC_Write_Protection_Disable ((gU32)0x00000000)
#define FMC_Write_Protection_Enable ((gU32)0x00000200)
#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_Write_Protection_Disable) || \
((WRITE) == FMC_Write_Protection_Enable))
@ -850,9 +850,9 @@ typedef struct
/** @defgroup FMC_SDClock_Period
* @{
*/
#define FMC_SDClock_Disable ((uint32_t)0x00000000)
#define FMC_SDClock_Period_2 ((uint32_t)0x00000800)
#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00)
#define FMC_SDClock_Disable ((gU32)0x00000000)
#define FMC_SDClock_Period_2 ((gU32)0x00000800)
#define FMC_SDClock_Period_3 ((gU32)0x00000C00)
#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDClock_Disable) || \
((PERIOD) == FMC_SDClock_Period_2) || \
@ -865,8 +865,8 @@ typedef struct
/** @defgroup FMC_Read_Burst
* @{
*/
#define FMC_Read_Burst_Disable ((uint32_t)0x00000000)
#define FMC_Read_Burst_Enable ((uint32_t)0x00001000)
#define FMC_Read_Burst_Disable ((gU32)0x00000000)
#define FMC_Read_Burst_Enable ((gU32)0x00001000)
#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_Read_Burst_Disable) || \
((RBURST) == FMC_Read_Burst_Enable))
@ -878,9 +878,9 @@ typedef struct
/** @defgroup FMC_ReadPipe_Delay
* @{
*/
#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000)
#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000)
#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000)
#define FMC_ReadPipe_Delay_0 ((gU32)0x00000000)
#define FMC_ReadPipe_Delay_1 ((gU32)0x00002000)
#define FMC_ReadPipe_Delay_2 ((gU32)0x00004000)
#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_ReadPipe_Delay_0) || \
((DELAY) == FMC_ReadPipe_Delay_1) || \
@ -950,13 +950,13 @@ typedef struct
/** @defgroup FMC_Command_Mode
* @{
*/
#define FMC_Command_Mode_normal ((uint32_t)0x00000000)
#define FMC_Command_Mode_CLK_Enabled ((uint32_t)0x00000001)
#define FMC_Command_Mode_PALL ((uint32_t)0x00000002)
#define FMC_Command_Mode_AutoRefresh ((uint32_t)0x00000003)
#define FMC_Command_Mode_LoadMode ((uint32_t)0x00000004)
#define FMC_Command_Mode_Selfrefresh ((uint32_t)0x00000005)
#define FMC_Command_Mode_PowerDown ((uint32_t)0x00000006)
#define FMC_Command_Mode_normal ((gU32)0x00000000)
#define FMC_Command_Mode_CLK_Enabled ((gU32)0x00000001)
#define FMC_Command_Mode_PALL ((gU32)0x00000002)
#define FMC_Command_Mode_AutoRefresh ((gU32)0x00000003)
#define FMC_Command_Mode_LoadMode ((gU32)0x00000004)
#define FMC_Command_Mode_Selfrefresh ((gU32)0x00000005)
#define FMC_Command_Mode_PowerDown ((gU32)0x00000006)
#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_Command_Mode_normal) || \
((COMMAND) == FMC_Command_Mode_CLK_Enabled) || \
@ -973,9 +973,9 @@ typedef struct
/** @defgroup FMC_Command_Target
* @{
*/
#define FMC_Command_Target_bank2 ((uint32_t)0x00000008)
#define FMC_Command_Target_bank1 ((uint32_t)0x00000010)
#define FMC_Command_Target_bank1_2 ((uint32_t)0x00000018)
#define FMC_Command_Target_bank2 ((gU32)0x00000008)
#define FMC_Command_Target_bank1 ((gU32)0x00000010)
#define FMC_Command_Target_bank1_2 ((gU32)0x00000018)
#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_Command_Target_bank1) || \
((TARGET) == FMC_Command_Target_bank2) || \
@ -1007,7 +1007,7 @@ typedef struct
/** @defgroup FMC_Mode_Status
* @{
*/
#define FMC_NormalMode_Status ((uint32_t)0x00000000)
#define FMC_NormalMode_Status ((gU32)0x00000000)
#define FMC_SelfRefreshMode_Status FMC_SDSR_MODES1_0
#define FMC_PowerDownMode_Status FMC_SDSR_MODES1_1
@ -1027,12 +1027,12 @@ typedef struct
/** @defgroup FMC_Interrupt_sources
* @{
*/
#define FMC_IT_RisingEdge ((uint32_t)0x00000008)
#define FMC_IT_Level ((uint32_t)0x00000010)
#define FMC_IT_FallingEdge ((uint32_t)0x00000020)
#define FMC_IT_Refresh ((uint32_t)0x00004000)
#define FMC_IT_RisingEdge ((gU32)0x00000008)
#define FMC_IT_Level ((gU32)0x00000010)
#define FMC_IT_FallingEdge ((gU32)0x00000020)
#define FMC_IT_Refresh ((gU32)0x00004000)
#define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
#define IS_FMC_IT(IT) ((((IT) & (gU32)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
#define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RisingEdge) || \
((IT) == FMC_IT_Level) || \
((IT) == FMC_IT_FallingEdge) || \
@ -1050,10 +1050,10 @@ typedef struct
/** @defgroup FMC_Flags
* @{
*/
#define FMC_FLAG_RisingEdge ((uint32_t)0x00000001)
#define FMC_FLAG_Level ((uint32_t)0x00000002)
#define FMC_FLAG_FallingEdge ((uint32_t)0x00000004)
#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
#define FMC_FLAG_RisingEdge ((gU32)0x00000001)
#define FMC_FLAG_Level ((gU32)0x00000002)
#define FMC_FLAG_FallingEdge ((gU32)0x00000004)
#define FMC_FLAG_FEMPT ((gU32)0x00000040)
#define FMC_FLAG_Refresh FMC_SDSR_RE
#define FMC_FLAG_Busy FMC_SDSR_BUSY
@ -1071,7 +1071,7 @@ typedef struct
((BANK) == FMC_Bank2_SDRAM) || \
((BANK) == (FMC_Bank1_SDRAM | FMC_Bank2_SDRAM)))
#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (gU32)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
/**
@ -1096,18 +1096,18 @@ typedef struct
/* Exported functions --------------------------------------------------------*/
/* NOR/SRAM Controller functions **********************************************/
void FMC_NORSRAMDeInit(uint32_t FMC_Bank);
void FMC_NORSRAMDeInit(gU32 FMC_Bank);
void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct);
void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct);
void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState);
void FMC_NORSRAMCmd(gU32 FMC_Bank, FunctionalState NewState);
/* NAND Controller functions **************************************************/
void FMC_NANDDeInit(uint32_t FMC_Bank);
void FMC_NANDDeInit(gU32 FMC_Bank);
void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct);
void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct);
void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState);
void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState);
uint32_t FMC_GetECC(uint32_t FMC_Bank);
void FMC_NANDCmd(gU32 FMC_Bank, FunctionalState NewState);
void FMC_NANDECCCmd(gU32 FMC_Bank, FunctionalState NewState);
gU32 FMC_GetECC(gU32 FMC_Bank);
/* PCCARD Controller functions ************************************************/
void FMC_PCCARDDeInit(void);
@ -1116,21 +1116,21 @@ void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct);
void FMC_PCCARDCmd(FunctionalState NewState);
/* SDRAM Controller functions ************************************************/
void FMC_SDRAMDeInit(uint32_t FMC_Bank);
void FMC_SDRAMDeInit(gU32 FMC_Bank);
void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct);
void FMC_SDRAMStructInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct);
void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct);
uint32_t FMC_GetModeStatus(uint32_t SDRAM_Bank);
void FMC_SetRefreshCount(uint32_t FMC_Count);
void FMC_SetAutoRefresh_Number(uint32_t FMC_Number);
void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewState);
gU32 FMC_GetModeStatus(gU32 SDRAM_Bank);
void FMC_SetRefreshCount(gU32 FMC_Count);
void FMC_SetAutoRefresh_Number(gU32 FMC_Number);
void FMC_SDRAMWriteProtectionConfig(gU32 SDRAM_Bank, FunctionalState NewState);
/* Interrupts and flags management functions **********************************/
void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState);
FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG);
void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG);
ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT);
void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT);
void FMC_ITConfig(gU32 FMC_Bank, gU32 FMC_IT, FunctionalState NewState);
FlagStatus FMC_GetFlagStatus(gU32 FMC_Bank, gU32 FMC_FLAG);
void FMC_ClearFlag(gU32 FMC_Bank, gU32 FMC_FLAG);
ITStatus FMC_GetITStatus(gU32 FMC_Bank, gU32 FMC_IT);
void FMC_ClearITPendingBit(gU32 FMC_Bank, gU32 FMC_IT);
#ifdef __cplusplus
}

2
boards/base/STM32F439i-Eval/CubeHal/board_STM32LTDC.h
View file

@ -153,7 +153,7 @@ static GFXINLINE void post_init_board(GDisplay* g)
(void) g;
}
static GFXINLINE void set_backlight(GDisplay* g, uint8_t percent)
static GFXINLINE void set_backlight(GDisplay* g, gU8 percent)
{
(void) g;
(void) percent;

6
boards/base/STM32F439i-Eval/CubeHal/gmouse_lld_EXC7200_board.h
View file

@ -82,12 +82,12 @@ static gBool init_board(GMouse* m, unsigned driverinstance)
return gTrue;
}
static gBool read_bytes(GMouse* m, uint8_t reg, uint8_t* buffer, uint8_t nbrBytes)
static gBool read_bytes(GMouse* m, gU8 reg, gU8* buffer, gU8 nbrBytes)
{
(void)m;
HAL_I2C_Master_Transmit(&_i2cHandle, (uint16_t)EXC7200_SLAVE_ADDR, (uint8_t*)&reg, 1, 10000);
HAL_I2C_Master_Receive(&_i2cHandle, (uint16_t)EXC7200_SLAVE_ADDR, buffer, nbrBytes, 10000);
HAL_I2C_Master_Transmit(&_i2cHandle, (gU16)EXC7200_SLAVE_ADDR, (gU8*)&reg, 1, 10000);
HAL_I2C_Master_Receive(&_i2cHandle, (gU16)EXC7200_SLAVE_ADDR, buffer, nbrBytes, 10000);
return gTrue;
}

28
boards/base/STM32F439i-Eval/CubeHal/stm324x9i_eval_sdram.c
View file

@ -144,9 +144,9 @@ static void SDRAM_MspInit(void);
* @brief Initializes the SDRAM device.
* @retval SDRAM status
*/
uint8_t BSP_SDRAM_Init(void)
gU8 BSP_SDRAM_Init(void)
{
static uint8_t sdramstatus = SDRAM_ERROR;
static gU8 sdramstatus = SDRAM_ERROR;
/* SDRAM device configuration */
sdramHandle.Instance = FMC_SDRAM_DEVICE;
@ -191,9 +191,9 @@ uint8_t BSP_SDRAM_Init(void)
* @brief Programs the SDRAM device.
* @param RefreshCount: SDRAM refresh counter value
*/
void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
void BSP_SDRAM_Initialization_sequence(gU32 RefreshCount)
{
__IO uint32_t tmpmrd = 0;
__IO gU32 tmpmrd = 0;
/* Step 1: Configure a clock configuration enable command */
Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
@ -227,7 +227,7 @@ void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
/* Step 5: Program the external memory mode register */
tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\
tmpmrd = (gU32)SDRAM_MODEREG_BURST_LENGTH_1 |\
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
SDRAM_MODEREG_CAS_LATENCY_3 |\
SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
@ -253,9 +253,9 @@ void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
* @param uwDataSize: Size of read data from the memory
* @retval SDRAM status
*/
uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
gU8 BSP_SDRAM_ReadData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
{
if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
if(HAL_SDRAM_Read_32b(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
{
return SDRAM_ERROR;
}
@ -272,9 +272,9 @@ uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uw
* @param uwDataSize: Size of read data from the memory
* @retval SDRAM status
*/
uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
gU8 BSP_SDRAM_ReadData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
{
if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
if(HAL_SDRAM_Read_DMA(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
{
return SDRAM_ERROR;
}
@ -291,9 +291,9 @@ uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_
* @param uwDataSize: Size of written data from the memory
* @retval SDRAM status
*/
uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
gU8 BSP_SDRAM_WriteData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
{
if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
if(HAL_SDRAM_Write_32b(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
{
return SDRAM_ERROR;
}
@ -310,9 +310,9 @@ uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t u
* @param uwDataSize: Size of written data from the memory
* @retval SDRAM status
*/
uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
gU8 BSP_SDRAM_WriteData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
{
if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
if(HAL_SDRAM_Write_DMA(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
{
return SDRAM_ERROR;
}
@ -327,7 +327,7 @@ uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32
* @param SdramCmd: Pointer to SDRAM command structure
* @retval HAL status
*/
uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
gU8 BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
{
if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK)
{

44
boards/base/STM32F439i-Eval/CubeHal/stm324x9i_eval_sdram.h
View file

@ -82,8 +82,8 @@
/** @defgroup STM324x9I_EVAL_SDRAM_Exported_Constants STM324x9I EVAL SDRAM Exported Constants
* @{
*/
#define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000)
#define SDRAM_DEVICE_SIZE ((uint32_t)0x800000) /* SDRAM device size in MBytes */
#define SDRAM_DEVICE_ADDR ((gU32)0xC0000000)
#define SDRAM_DEVICE_SIZE ((gU32)0x800000) /* SDRAM device size in MBytes */
/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */
/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16 */
@ -92,9 +92,9 @@
#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2
/* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */
#define REFRESH_COUNT ((uint32_t)0x0569) /* SDRAM refresh counter (90Mhz SD clock) */
#define REFRESH_COUNT ((gU32)0x0569) /* SDRAM refresh counter (90Mhz SD clock) */
#define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
#define SDRAM_TIMEOUT ((gU32)0xFFFF)
/* DMA definitions for SDRAM DMA transfer */
#define __DMAx_CLK_ENABLE __DMA2_CLK_ENABLE
@ -106,17 +106,17 @@
/**
* @brief FMC SDRAM Mode definition register defines
*/
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
#define SDRAM_MODEREG_BURST_LENGTH_1 ((gU16)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((gU16)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((gU16)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((gU16)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((gU16)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((gU16)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((gU16)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((gU16)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((gU16)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((gU16)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((gU16)0x0200)
/**
* @}
*/
@ -131,13 +131,13 @@
/** @defgroup STM324x9I_EVAL_SDRAM_Exported_Functions STM324x9I EVAL SDRAM Exported Functions
* @{
*/
uint8_t BSP_SDRAM_Init(void);
void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount);
uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
gU8 BSP_SDRAM_Init(void);
void BSP_SDRAM_Initialization_sequence(gU32 RefreshCount);
gU8 BSP_SDRAM_ReadData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
gU8 BSP_SDRAM_ReadData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
gU8 BSP_SDRAM_WriteData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
gU8 BSP_SDRAM_WriteData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
gU8 BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
void BSP_SDRAM_DMA_IRQHandler(void);
/**

26
boards/base/STM32F439i-Eval/CubeHal/stm32f439i_raw32_system.c
View file

@ -71,11 +71,11 @@
#include "stm32f4xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
#define HSE_VALUE ((gU32)8000000) /*!< Default value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE ((gU32)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
@ -135,8 +135,8 @@
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 16000000;
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
gU32 SystemCoreClock = 16000000;
__I gU8 AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
@ -173,19 +173,19 @@ void SystemInit(void)
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
RCC->CR |= (gU32)0x00000001;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
RCC->CR &= (gU32)0xFEF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
RCC->CR &= (gU32)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
@ -240,7 +240,7 @@ void SystemInit(void)
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
gU32 tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
@ -299,10 +299,10 @@ void SystemCoreClockUpdate(void)
*/
void SystemInit_ExtMemCtl(void)
{
__IO uint32_t tmp = 0x00;
__IO gU32 tmp = 0x00;
register uint32_t tmpreg = 0, timeout = 0xFFFF;
register __IO uint32_t index;
register gU32 tmpreg = 0, timeout = 0xFFFF;
register __IO gU32 index;
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
RCC->AHB1ENR |= 0x000001F8;
@ -464,8 +464,8 @@ void SystemInit_ExtMemCtl(void)
{
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
#if defined (DATA_IN_ExtSDRAM)
register uint32_t tmpreg = 0, timeout = 0xFFFF;
register __IO uint32_t index;
register gU32 tmpreg = 0, timeout = 0xFFFF;
register __IO gU32 index;
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
clock */

8
boards/base/STM32F469i-Discovery/CubeHAL/board_STM32LTDC.h
View file

@ -118,7 +118,7 @@ static GFXINLINE void init_board(GDisplay *g) {
dsiHandle.Instance = DSI; // There is only one DSI interface
dsiHandle.Init.AutomaticClockLaneControl = DSI_AUTO_CLK_LANE_CTRL_ENABLE; // Automatic clock lane control: powers down the clock lane when not in use
/* Highest speed = 500MHz. */
uint16_t laneByteClk_kHz = 62500; /* 500 MHz / 8 = 62.5 MHz = 62500 kHz */
gU16 laneByteClk_kHz = 62500; /* 500 MHz / 8 = 62.5 MHz = 62500 kHz */
/* TXEscapeCkdiv = f(LaneByteClk)/15.62 = 4 -> 500MHz/4 = 25MHz datasheet says around 20MHz */
dsiHandle.Init.TXEscapeCkdiv = laneByteClk_kHz/15620; // Low power clock relative to the laneByteClock
dsiHandle.Init.NumberOfLanes = DSI_TWO_DATA_LANES; // Two data lines for the fastest transfer speed
@ -201,7 +201,7 @@ static GFXINLINE void init_board(GDisplay *g) {
BSP_SDRAM_Init();
}
static GFXINLINE void set_backlight(GDisplay* g, uint8_t percent)
static GFXINLINE void set_backlight(GDisplay* g, gU8 percent)
{
(void)g;
(void)percent;
@ -287,7 +287,7 @@ static GFXINLINE void post_init_board(GDisplay* g)
* @param pParams: Pointer to parameter values table.
* @retval HAL status
*/
void DSI_IO_WriteCmd(uint32_t NbrParams, uint8_t *pParams)
void DSI_IO_WriteCmd(gU32 NbrParams, gU8 *pParams)
{
if(NbrParams <= 1)
{
@ -304,7 +304,7 @@ void DSI_IO_WriteCmd(uint32_t NbrParams, uint8_t *pParams)
*
* @param Delay: The requested delay in ms.
*/
void OTM8009A_IO_Delay(uint32_t Delay)
void OTM8009A_IO_Delay(gU32 Delay)
{
gfxSleepMilliseconds(Delay);
}

16
boards/base/STM32F469i-Discovery/CubeHAL/gmouse_lld_FT6x06_board.h
View file

@ -82,26 +82,26 @@ static GFXINLINE void release_bus(GMouse* m) {
(void)m;
}
static void write_reg(GMouse* m, uint8_t reg, uint8_t val) {
static void write_reg(GMouse* m, gU8 reg, gU8 val) {
(void)m;
HAL_I2C_Mem_Write(&i2cHandle, FT6x06_SLAVE_ADDR, (uint16_t)reg, I2C_MEMADD_SIZE_8BIT, &val, 1, 1000);
HAL_I2C_Mem_Write(&i2cHandle, FT6x06_SLAVE_ADDR, (gU16)reg, I2C_MEMADD_SIZE_8BIT, &val, 1, 1000);
}
static uint8_t read_byte(GMouse* m, uint8_t reg) {
static gU8 read_byte(GMouse* m, gU8 reg) {
(void)m;
uint8_t result;
gU8 result;
HAL_I2C_Mem_Read(&i2cHandle, FT6x06_SLAVE_ADDR, (uint16_t)reg, I2C_MEMADD_SIZE_8BIT, &result, 1, 1000);
HAL_I2C_Mem_Read(&i2cHandle, FT6x06_SLAVE_ADDR, (gU16)reg, I2C_MEMADD_SIZE_8BIT, &result, 1, 1000);
return result;
}
static uint16_t read_word(GMouse* m, uint8_t reg) {
static gU16 read_word(GMouse* m, gU8 reg) {
(void)m;
uint8_t result[2];
gU8 result[2];
HAL_I2C_Mem_Read(&i2cHandle, FT6x06_SLAVE_ADDR, (uint16_t)reg, I2C_MEMADD_SIZE_8BIT, result, 2, 1000);
HAL_I2C_Mem_Read(&i2cHandle, FT6x06_SLAVE_ADDR, (gU16)reg, I2C_MEMADD_SIZE_8BIT, result, 2, 1000);
return (result[0]<<8 | result[1]);

364
boards/base/STM32F469i-Discovery/otm8009a.c
View file

@ -64,31 +64,31 @@
* @brief Constant tables of register settings used to transmit DSI
* command packets as power up initialization sequence of the KoD LCD (OTM8009A LCD Driver)
*/
const uint8_t lcdRegData1[] = {0x80,0x09,0x01,0xFF};
const uint8_t lcdRegData2[] = {0x80,0x09,0xFF};
const uint8_t lcdRegData3[] = {0x00,0x09,0x0F,0x0E,0x07,0x10,0x0B,0x0A,0x04,0x07,0x0B,0x08,0x0F,0x10,0x0A,0x01,0xE1};
const uint8_t lcdRegData4[] = {0x00,0x09,0x0F,0x0E,0x07,0x10,0x0B,0x0A,0x04,0x07,0x0B,0x08,0x0F,0x10,0x0A,0x01,0xE2};
const uint8_t lcdRegData5[] = {0x79,0x79,0xD8};
const uint8_t lcdRegData6[] = {0x00,0x01,0xB3};
const uint8_t lcdRegData7[] = {0x85,0x01,0x00,0x84,0x01,0x00,0xCE};
const uint8_t lcdRegData8[] = {0x18,0x04,0x03,0x39,0x00,0x00,0x00,0x18,0x03,0x03,0x3A,0x00,0x00,0x00,0xCE};
const uint8_t lcdRegData9[] = {0x18,0x02,0x03,0x3B,0x00,0x00,0x00,0x18,0x01,0x03,0x3C,0x00,0x00,0x00,0xCE};
const uint8_t lcdRegData10[] = {0x01,0x01,0x20,0x20,0x00,0x00,0x01,0x02,0x00,0x00,0xCF};
const uint8_t lcdRegData11[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const uint8_t lcdRegData12[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const uint8_t lcdRegData13[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const uint8_t lcdRegData14[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const uint8_t lcdRegData15[] = {0x00,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const uint8_t lcdRegData16[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00,0xCB};
const uint8_t lcdRegData17[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const uint8_t lcdRegData18[] = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xCB};
const uint8_t lcdRegData19[] = {0x00,0x26,0x09,0x0B,0x01,0x25,0x00,0x00,0x00,0x00,0xCC};
const uint8_t lcdRegData20[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x26,0x0A,0x0C,0x02,0xCC};
const uint8_t lcdRegData21[] = {0x25,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCC};
const uint8_t lcdRegData22[] = {0x00,0x25,0x0C,0x0A,0x02,0x26,0x00,0x00,0x00,0x00,0xCC};
const uint8_t lcdRegData23[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x25,0x0B,0x09,0x01,0xCC};
const uint8_t lcdRegData24[] = {0x26,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCC};
const uint8_t lcdRegData25[] = {0xFF,0xFF,0xFF,0xFF};
const gU8 lcdRegData1[] = {0x80,0x09,0x01,0xFF};
const gU8 lcdRegData2[] = {0x80,0x09,0xFF};
const gU8 lcdRegData3[] = {0x00,0x09,0x0F,0x0E,0x07,0x10,0x0B,0x0A,0x04,0x07,0x0B,0x08,0x0F,0x10,0x0A,0x01,0xE1};
const gU8 lcdRegData4[] = {0x00,0x09,0x0F,0x0E,0x07,0x10,0x0B,0x0A,0x04,0x07,0x0B,0x08,0x0F,0x10,0x0A,0x01,0xE2};
const gU8 lcdRegData5[] = {0x79,0x79,0xD8};
const gU8 lcdRegData6[] = {0x00,0x01,0xB3};
const gU8 lcdRegData7[] = {0x85,0x01,0x00,0x84,0x01,0x00,0xCE};
const gU8 lcdRegData8[] = {0x18,0x04,0x03,0x39,0x00,0x00,0x00,0x18,0x03,0x03,0x3A,0x00,0x00,0x00,0xCE};
const gU8 lcdRegData9[] = {0x18,0x02,0x03,0x3B,0x00,0x00,0x00,0x18,0x01,0x03,0x3C,0x00,0x00,0x00,0xCE};
const gU8 lcdRegData10[] = {0x01,0x01,0x20,0x20,0x00,0x00,0x01,0x02,0x00,0x00,0xCF};
const gU8 lcdRegData11[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const gU8 lcdRegData12[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const gU8 lcdRegData13[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const gU8 lcdRegData14[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const gU8 lcdRegData15[] = {0x00,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const gU8 lcdRegData16[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00,0xCB};
const gU8 lcdRegData17[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const gU8 lcdRegData18[] = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xCB};
const gU8 lcdRegData19[] = {0x00,0x26,0x09,0x0B,0x01,0x25,0x00,0x00,0x00,0x00,0xCC};
const gU8 lcdRegData20[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x26,0x0A,0x0C,0x02,0xCC};
const gU8 lcdRegData21[] = {0x25,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCC};
const gU8 lcdRegData22[] = {0x00,0x25,0x0C,0x0A,0x02,0x26,0x00,0x00,0x00,0x00,0xCC};
const gU8 lcdRegData23[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x25,0x0B,0x09,0x01,0xCC};
const gU8 lcdRegData24[] = {0x26,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCC};
const gU8 lcdRegData25[] = {0xFF,0xFF,0xFF,0xFF};
/*
* CASET value (Column Address Set) : X direction LCD GRAM boundaries
* depending on LCD orientation mode and PASET value (Page Address Set) : Y direction
@ -96,65 +96,65 @@ const uint8_t lcdRegData25[] = {0xFF,0xFF,0xFF,0xFF};
* XS[15:0] = 0x000 = 0, XE[15:0] = 0x31F = 799 for landscape mode : apply to CASET
* YS[15:0] = 0x000 = 0, YE[15:0] = 0x31F = 799 for portrait mode : : apply to PASET
*/
const uint8_t lcdRegData27[] = {0x00, 0x00, 0x03, 0x1F, OTM8009A_CMD_CASET};
const gU8 lcdRegData27[] = {0x00, 0x00, 0x03, 0x1F, OTM8009A_CMD_CASET};
/*
* XS[15:0] = 0x000 = 0, XE[15:0] = 0x1DF = 479 for portrait mode : apply to CASET
* YS[15:0] = 0x000 = 0, YE[15:0] = 0x1DF = 479 for landscape mode : apply to PASET
*/
const uint8_t lcdRegData28[] = {0x00, 0x00, 0x01, 0xDF, OTM8009A_CMD_PASET};
const gU8 lcdRegData28[] = {0x00, 0x00, 0x01, 0xDF, OTM8009A_CMD_PASET};
const uint8_t ShortRegData1[] = {OTM8009A_CMD_NOP, 0x00};
const uint8_t ShortRegData2[] = {OTM8009A_CMD_NOP, 0x80};
const uint8_t ShortRegData3[] = {0xC4, 0x30};
const uint8_t ShortRegData4[] = {OTM8009A_CMD_NOP, 0x8A};
const uint8_t ShortRegData5[] = {0xC4, 0x40};
const uint8_t ShortRegData6[] = {OTM8009A_CMD_NOP, 0xB1};
const uint8_t ShortRegData7[] = {0xC5, 0xA9};
const uint8_t ShortRegData8[] = {OTM8009A_CMD_NOP, 0x91};
const uint8_t ShortRegData9[] = {0xC5, 0x34};
const uint8_t ShortRegData10[] = {OTM8009A_CMD_NOP, 0xB4};
const uint8_t ShortRegData11[] = {0xC0, 0x50};
const uint8_t ShortRegData12[] = {0xD9, 0x4E};
const uint8_t ShortRegData13[] = {OTM8009A_CMD_NOP, 0x81};
const uint8_t ShortRegData14[] = {0xC1, 0x66};
const uint8_t ShortRegData15[] = {OTM8009A_CMD_NOP, 0xA1};
const uint8_t ShortRegData16[] = {0xC1, 0x08};
const uint8_t ShortRegData17[] = {OTM8009A_CMD_NOP, 0x92};
const uint8_t ShortRegData18[] = {0xC5, 0x01};
const uint8_t ShortRegData19[] = {OTM8009A_CMD_NOP, 0x95};
const uint8_t ShortRegData20[] = {OTM8009A_CMD_NOP, 0x94};
const uint8_t ShortRegData21[] = {0xC5, 0x33};
const uint8_t ShortRegData22[] = {OTM8009A_CMD_NOP, 0xA3};
const uint8_t ShortRegData23[] = {0xC0, 0x1B};
const uint8_t ShortRegData24[] = {OTM8009A_CMD_NOP, 0x82};
const uint8_t ShortRegData25[] = {0xC5, 0x83};
const uint8_t ShortRegData26[] = {0xC4, 0x83};
const uint8_t ShortRegData27[] = {0xC1, 0x0E};
const uint8_t ShortRegData28[] = {OTM8009A_CMD_NOP, 0xA6};
const uint8_t ShortRegData29[] = {OTM8009A_CMD_NOP, 0xA0};
const uint8_t ShortRegData30[] = {OTM8009A_CMD_NOP, 0xB0};
const uint8_t ShortRegData31[] = {OTM8009A_CMD_NOP, 0xC0};
const uint8_t ShortRegData32[] = {OTM8009A_CMD_NOP, 0xD0};
const uint8_t ShortRegData33[] = {OTM8009A_CMD_NOP, 0x90};
const uint8_t ShortRegData34[] = {OTM8009A_CMD_NOP, 0xE0};
const uint8_t ShortRegData35[] = {OTM8009A_CMD_NOP, 0xF0};
const uint8_t ShortRegData36[] = {OTM8009A_CMD_SLPOUT, 0x00};
const uint8_t ShortRegData37[] = {OTM8009A_CMD_COLMOD, OTM8009A_COLMOD_RGB565};
const uint8_t ShortRegData38[] = {OTM8009A_CMD_COLMOD, OTM8009A_COLMOD_RGB888};
const uint8_t ShortRegData39[] = {OTM8009A_CMD_MADCTR, OTM8009A_MADCTR_MODE_LANDSCAPE};
const uint8_t ShortRegData40[] = {OTM8009A_CMD_WRDISBV, 0x7F};
const uint8_t ShortRegData41[] = {OTM8009A_CMD_WRCTRLD, 0x2C};
const uint8_t ShortRegData42[] = {OTM8009A_CMD_WRCABC, 0x02};
const uint8_t ShortRegData43[] = {OTM8009A_CMD_WRCABCMB, 0xFF};
const uint8_t ShortRegData44[] = {OTM8009A_CMD_DISPON, 0x00};
const uint8_t ShortRegData45[] = {OTM8009A_CMD_RAMWR, 0x00};
const uint8_t ShortRegData46[] = {0xCF, 0x00};
const uint8_t ShortRegData47[] = {0xC5, 0x66};
const uint8_t ShortRegData48[] = {OTM8009A_CMD_NOP, 0xB6};
const uint8_t ShortRegData49[] = {0xF5, 0x06};
const uint8_t ShortRegData50[] = {OTM8009A_CMD_NOP, 0xB1};
const uint8_t ShortRegData51[] = {0xC6, 0x06};
const gU8 ShortRegData1[] = {OTM8009A_CMD_NOP, 0x00};
const gU8 ShortRegData2[] = {OTM8009A_CMD_NOP, 0x80};
const gU8 ShortRegData3[] = {0xC4, 0x30};
const gU8 ShortRegData4[] = {OTM8009A_CMD_NOP, 0x8A};
const gU8 ShortRegData5[] = {0xC4, 0x40};
const gU8 ShortRegData6[] = {OTM8009A_CMD_NOP, 0xB1};
const gU8 ShortRegData7[] = {0xC5, 0xA9};
const gU8 ShortRegData8[] = {OTM8009A_CMD_NOP, 0x91};
const gU8 ShortRegData9[] = {0xC5, 0x34};
const gU8 ShortRegData10[] = {OTM8009A_CMD_NOP, 0xB4};
const gU8 ShortRegData11[] = {0xC0, 0x50};
const gU8 ShortRegData12[] = {0xD9, 0x4E};
const gU8 ShortRegData13[] = {OTM8009A_CMD_NOP, 0x81};
const gU8 ShortRegData14[] = {0xC1, 0x66};
const gU8 ShortRegData15[] = {OTM8009A_CMD_NOP, 0xA1};
const gU8 ShortRegData16[] = {0xC1, 0x08};
const gU8 ShortRegData17[] = {OTM8009A_CMD_NOP, 0x92};
const gU8 ShortRegData18[] = {0xC5, 0x01};
const gU8 ShortRegData19[] = {OTM8009A_CMD_NOP, 0x95};
const gU8 ShortRegData20[] = {OTM8009A_CMD_NOP, 0x94};
const gU8 ShortRegData21[] = {0xC5, 0x33};
const gU8 ShortRegData22[] = {OTM8009A_CMD_NOP, 0xA3};
const gU8 ShortRegData23[] = {0xC0, 0x1B};
const gU8 ShortRegData24[] = {OTM8009A_CMD_NOP, 0x82};
const gU8 ShortRegData25[] = {0xC5, 0x83};
const gU8 ShortRegData26[] = {0xC4, 0x83};
const gU8 ShortRegData27[] = {0xC1, 0x0E};
const gU8 ShortRegData28[] = {OTM8009A_CMD_NOP, 0xA6};
const gU8 ShortRegData29[] = {OTM8009A_CMD_NOP, 0xA0};
const gU8 ShortRegData30[] = {OTM8009A_CMD_NOP, 0xB0};
const gU8 ShortRegData31[] = {OTM8009A_CMD_NOP, 0xC0};
const gU8 ShortRegData32[] = {OTM8009A_CMD_NOP, 0xD0};
const gU8 ShortRegData33[] = {OTM8009A_CMD_NOP, 0x90};
const gU8 ShortRegData34[] = {OTM8009A_CMD_NOP, 0xE0};
const gU8 ShortRegData35[] = {OTM8009A_CMD_NOP, 0xF0};
const gU8 ShortRegData36[] = {OTM8009A_CMD_SLPOUT, 0x00};
const gU8 ShortRegData37[] = {OTM8009A_CMD_COLMOD, OTM8009A_COLMOD_RGB565};
const gU8 ShortRegData38[] = {OTM8009A_CMD_COLMOD, OTM8009A_COLMOD_RGB888};
const gU8 ShortRegData39[] = {OTM8009A_CMD_MADCTR, OTM8009A_MADCTR_MODE_LANDSCAPE};
const gU8 ShortRegData40[] = {OTM8009A_CMD_WRDISBV, 0x7F};
const gU8 ShortRegData41[] = {OTM8009A_CMD_WRCTRLD, 0x2C};
const gU8 ShortRegData42[] = {OTM8009A_CMD_WRCABC, 0x02};
const gU8 ShortRegData43[] = {OTM8009A_CMD_WRCABCMB, 0xFF};
const gU8 ShortRegData44[] = {OTM8009A_CMD_DISPON, 0x00};
const gU8 ShortRegData45[] = {OTM8009A_CMD_RAMWR, 0x00};
const gU8 ShortRegData46[] = {0xCF, 0x00};
const gU8 ShortRegData47[] = {0xC5, 0x66};
const gU8 ShortRegData48[] = {OTM8009A_CMD_NOP, 0xB6};
const gU8 ShortRegData49[] = {0xF5, 0x06};
const gU8 ShortRegData50[] = {OTM8009A_CMD_NOP, 0xB1};
const gU8 ShortRegData51[] = {0xC6, 0x06};
/**
* @}
*/
@ -178,7 +178,7 @@ const uint8_t ShortRegData51[] = {0xC6, 0x06};
* @brief DSI IO write short/long command.
* @note : Can be surcharged by application code implementation of the function.
*/
__weak void DSI_IO_WriteCmd(uint32_t NbrParams, uint8_t *pParams)
__weak void DSI_IO_WriteCmd(gU32 NbrParams, gU8 *pParams)
{
/* NOTE : This function Should not be modified, when it is needed,
the DSI_IO_WriteCmd could be implemented in the user file
@ -192,194 +192,194 @@ __weak void DSI_IO_WriteCmd(uint32_t NbrParams, uint8_t *pParams)
* @param hdsivideo_handle : pointer on DSI video mode configuration structure
* @retval Status
*/
uint8_t OTM8009A_Init(uint32_t ColorCoding, uint32_t orientation)
gU8 OTM8009A_Init(gU32 ColorCoding, gU32 orientation)
{
/* Enable CMD2 to access vendor specific commands */
/* Enter in command 2 mode and set EXTC to enable address shift function (0x00) */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
DSI_IO_WriteCmd( 3, (uint8_t *)lcdRegData1);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
DSI_IO_WriteCmd( 3, (gU8 *)lcdRegData1);
/* Enter ORISE Command 2 */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData2); /* Shift address to 0x80 */
DSI_IO_WriteCmd( 2, (uint8_t *)lcdRegData2);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2); /* Shift address to 0x80 */
DSI_IO_WriteCmd( 2, (gU8 *)lcdRegData2);
/////////////////////////////////////////////////////////////////////
/* SD_PCH_CTRL - 0xC480h - 129th parameter - Default 0x00 */
/* Set SD_PT */
/* -> Source output level during porch and non-display area to GND */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData2);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData3);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData3);
OTM8009A_IO_Delay(10);
/* Not documented */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData4);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData5);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData4);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData5);
OTM8009A_IO_Delay(10);
/////////////////////////////////////////////////////////////////////
/* PWR_CTRL4 - 0xC4B0h - 178th parameter - Default 0xA8 */
/* Set gvdd_en_test */
/* -> enable GVDD test mode !!! */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData6);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData7);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData6);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData7);
/* PWR_CTRL2 - 0xC590h - 146th parameter - Default 0x79 */
/* Set pump 4 vgh voltage */
/* -> from 15.0v down to 13.0v */
/* Set pump 5 vgh voltage */
/* -> from -12.0v downto -9.0v */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData8);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData9);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData8);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData9);
/* P_DRV_M - 0xC0B4h - 181th parameter - Default 0x00 */
/* -> Column inversion */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData10);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData11);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData10);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData11);
/* VCOMDC - 0xD900h - 1st parameter - Default 0x39h */
/* VCOM Voltage settings */
/* -> from -1.0000v downto -1.2625v */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData12);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData12);
/* Oscillator adjustment for Idle/Normal mode (LPDT only) set to 65Hz (default is 60Hz) */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData13);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData14);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData13);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData14);
/* Video mode internal */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData15);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData16);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData15);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData16);
/* PWR_CTRL2 - 0xC590h - 147h parameter - Default 0x00 */
/* Set pump 4&5 x6 */
/* -> ONLY VALID when PUMP4_EN_ASDM_HV = "0" */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData17);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData18);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData17);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData18);
/* PWR_CTRL2 - 0xC590h - 150th parameter - Default 0x33h */
/* Change pump4 clock ratio */
/* -> from 1 line to 1/2 line */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData19);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData9);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData19);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData9);
/* GVDD/NGVDD settings */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
DSI_IO_WriteCmd( 2, (uint8_t *)lcdRegData5);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
DSI_IO_WriteCmd( 2, (gU8 *)lcdRegData5);
/* PWR_CTRL2 - 0xC590h - 149th parameter - Default 0x33h */
/* Rewrite the default value ! */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData20);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData21);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData20);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData21);
/* Panel display timing Setting 3 */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData22);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData23);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData22);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData23);
/* Power control 1 */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData24);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData25);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData24);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData25);
/* Source driver precharge */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData13);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData26);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData13);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData26);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData15);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData27);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData15);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData27);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData28);
DSI_IO_WriteCmd( 2, (uint8_t *)lcdRegData6);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData28);
DSI_IO_WriteCmd( 2, (gU8 *)lcdRegData6);
/* GOAVST */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData2);
DSI_IO_WriteCmd( 6, (uint8_t *)lcdRegData7);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
DSI_IO_WriteCmd( 6, (gU8 *)lcdRegData7);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData29);
DSI_IO_WriteCmd( 14, (uint8_t *)lcdRegData8);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData29);
DSI_IO_WriteCmd( 14, (gU8 *)lcdRegData8);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData30);
DSI_IO_WriteCmd( 14, (uint8_t *)lcdRegData9);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData30);
DSI_IO_WriteCmd( 14, (gU8 *)lcdRegData9);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData31);
DSI_IO_WriteCmd( 10, (uint8_t *)lcdRegData10);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData31);
DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData10);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData32);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData46);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData32);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData46);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData2);
DSI_IO_WriteCmd( 10, (uint8_t *)lcdRegData11);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData11);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData33);
DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData12);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData33);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData12);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData29);
DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData13);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData29);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData13);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData30);
DSI_IO_WriteCmd( 10, (uint8_t *)lcdRegData14);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData30);
DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData14);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData31);
DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData15);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData31);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData15);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData32);
DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData16);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData32);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData16);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData34);
DSI_IO_WriteCmd( 10, (uint8_t *)lcdRegData17);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData34);
DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData17);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData35);
DSI_IO_WriteCmd( 10, (uint8_t *)lcdRegData18);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData35);
DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData18);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData2);
DSI_IO_WriteCmd( 10, (uint8_t *)lcdRegData19);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData19);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData33);
DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData20);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData33);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData20);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData29);
DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData21);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData29);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData21);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData30);
DSI_IO_WriteCmd( 10, (uint8_t *)lcdRegData22);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData30);
DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData22);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData31);
DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData23);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData31);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData23);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData32);
DSI_IO_WriteCmd( 15, (uint8_t *)lcdRegData24);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData32);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData24);
/////////////////////////////////////////////////////////////////////////////
/* PWR_CTRL1 - 0xc580h - 130th parameter - default 0x00 */
/* Pump 1 min and max DM */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData13);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData47);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData48);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData49);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData13);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData47);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData48);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData49);
/////////////////////////////////////////////////////////////////////////////
/* CABC LEDPWM frequency adjusted to 19,5kHz */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData50);
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData51);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData50);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData51);
/* Exit CMD2 mode */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
DSI_IO_WriteCmd( 3, (uint8_t *)lcdRegData25);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
DSI_IO_WriteCmd( 3, (gU8 *)lcdRegData25);
/*************************************************************************** */
/* Standard DCS Initialization TO KEEP CAN BE DONE IN HSDT */
/*************************************************************************** */
/* NOP - goes back to DCS std command ? */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
/* Gamma correction 2.2+ table (HSDT possible) */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
DSI_IO_WriteCmd( 16, (uint8_t *)lcdRegData3);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
DSI_IO_WriteCmd( 16, (gU8 *)lcdRegData3);
/* Gamma correction 2.2- table (HSDT possible) */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
DSI_IO_WriteCmd( 16, (uint8_t *)lcdRegData4);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
DSI_IO_WriteCmd( 16, (gU8 *)lcdRegData4);
/* Send Sleep Out command to display : no parameter */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData36);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData36);
/* Wait for sleep out exit */
OTM8009A_IO_Delay(120);
@ -388,11 +388,11 @@ uint8_t OTM8009A_Init(uint32_t ColorCoding, uint32_t orientation)
{
case OTM8009A_FORMAT_RBG565 :
/* Set Pixel color format to RGB565 */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData37);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData37);
break;
case OTM8009A_FORMAT_RGB888 :
/* Set Pixel color format to RGB888 */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData38);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData38);
break;
default :
break;
@ -402,35 +402,35 @@ uint8_t OTM8009A_Init(uint32_t ColorCoding, uint32_t orientation)
the orientation mode is portrait */
if(orientation == OTM8009A_ORIENTATION_LANDSCAPE)
{
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData39);
DSI_IO_WriteCmd( 4, (uint8_t *)lcdRegData27);
DSI_IO_WriteCmd( 4, (uint8_t *)lcdRegData28);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData39);
DSI_IO_WriteCmd( 4, (gU8 *)lcdRegData27);
DSI_IO_WriteCmd( 4, (gU8 *)lcdRegData28);
}
/** CABC : Content Adaptive Backlight Control section start >> */
/* Note : defaut is 0 (lowest Brightness), 0xFF is highest Brightness, try 0x7F : intermediate value */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData40);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData40);
/* defaut is 0, try 0x2C - Brightness Control Block, Display Dimming & BackLight on */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData41);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData41);
/* defaut is 0, try 0x02 - image Content based Adaptive Brightness [Still Picture] */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData42);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData42);
/* defaut is 0 (lowest Brightness), 0xFF is highest Brightness */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData43);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData43);
/** CABC : Content Adaptive Backlight Control section end << */
/* Send Command Display On */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData44);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData44);
/* NOP command */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData1);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
/* Send Command GRAM memory write (no parameters) : this initiates frame write via other DSI commands sent by */
/* DSI host from LTDC incoming pixels in video mode */
DSI_IO_WriteCmd(0, (uint8_t *)ShortRegData45);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData45);
return 0;
}

34
boards/base/STM32F469i-Discovery/otm8009a.h
View file

@ -73,37 +73,37 @@
* @brief LCD_OrientationTypeDef
* Possible values of Display Orientation
*/
#define OTM8009A_ORIENTATION_PORTRAIT ((uint32_t)0x00) /* Portrait orientation choice of LCD screen */
#define OTM8009A_ORIENTATION_LANDSCAPE ((uint32_t)0x01) /* Landscape orientation choice of LCD screen */
#define OTM8009A_ORIENTATION_PORTRAIT ((gU32)0x00) /* Portrait orientation choice of LCD screen */
#define OTM8009A_ORIENTATION_LANDSCAPE ((gU32)0x01) /* Landscape orientation choice of LCD screen */
/**
* @brief Possible values of
* pixel data format (ie color coding) transmitted on DSI Data lane in DSI packets
*/
#define OTM8009A_FORMAT_RGB888 ((uint32_t)0x00) /* Pixel format chosen is RGB888 : 24 bpp */
#define OTM8009A_FORMAT_RBG565 ((uint32_t)0x02) /* Pixel format chosen is RGB565 : 16 bpp */
#define OTM8009A_FORMAT_RGB888 ((gU32)0x00) /* Pixel format chosen is RGB888 : 24 bpp */
#define OTM8009A_FORMAT_RBG565 ((gU32)0x02) /* Pixel format chosen is RGB565 : 16 bpp */
/**
* @brief otm8009a_480x800 Size
*/
/* Width and Height in Portrait mode */
#define OTM8009A_480X800_WIDTH ((uint16_t)480) /* LCD PIXEL WIDTH */
#define OTM8009A_480X800_HEIGHT ((uint16_t)800) /* LCD PIXEL HEIGHT */
#define OTM8009A_480X800_WIDTH ((gU16)480) /* LCD PIXEL WIDTH */
#define OTM8009A_480X800_HEIGHT ((gU16)800) /* LCD PIXEL HEIGHT */
/* Width and Height in Landscape mode */
#define OTM8009A_800X480_WIDTH ((uint16_t)800) /* LCD PIXEL WIDTH */
#define OTM8009A_800X480_HEIGHT ((uint16_t)480) /* LCD PIXEL HEIGHT */
#define OTM8009A_800X480_WIDTH ((gU16)800) /* LCD PIXEL WIDTH */
#define OTM8009A_800X480_HEIGHT ((gU16)480) /* LCD PIXEL HEIGHT */
/**
* @brief OTM8009A_480X800 Timing parameters for Portrait orientation mode
*/
#define OTM8009A_480X800_HSYNC ((uint16_t)2) /* Horizontal synchronization */
#define OTM8009A_480X800_HBP ((uint16_t)34) /* Horizontal back porch */
#define OTM8009A_480X800_HFP ((uint16_t)34) /* Horizontal front porch */
#define OTM8009A_480X800_VSYNC ((uint16_t)1) /* Vertical synchronization */
#define OTM8009A_480X800_VBP ((uint16_t)15) /* Vertical back porch */
#define OTM8009A_480X800_VFP ((uint16_t)16) /* Vertical front porch */
#define OTM8009A_480X800_HSYNC ((gU16)2) /* Horizontal synchronization */
#define OTM8009A_480X800_HBP ((gU16)34) /* Horizontal back porch */
#define OTM8009A_480X800_HFP ((gU16)34) /* Horizontal front porch */
#define OTM8009A_480X800_VSYNC ((gU16)1) /* Vertical synchronization */
#define OTM8009A_480X800_VBP ((gU16)15) /* Vertical back porch */
#define OTM8009A_480X800_VFP ((gU16)16) /* Vertical front porch */
/**
* @brief OTM8009A_800X480 Timing parameters for Landscape orientation mode
@ -198,9 +198,9 @@
/** @addtogroup OTM8009A_Exported_Functions
* @{
*/
void DSI_IO_WriteCmd(uint32_t NbrParams, uint8_t *pParams);
uint8_t OTM8009A_Init(uint32_t ColorCoding, uint32_t orientation);
void OTM8009A_IO_Delay(uint32_t Delay);
void DSI_IO_WriteCmd(gU32 NbrParams, gU8 *pParams);
gU8 OTM8009A_Init(gU32 ColorCoding, gU32 orientation);
void OTM8009A_IO_Delay(gU32 Delay);
/**
* @}
*/

32
boards/base/STM32F469i-Discovery/stm32f469i_discovery_sdram.c
View file

@ -147,9 +147,9 @@ static FMC_SDRAM_CommandTypeDef Command;
* @brief Initializes the SDRAM device.
* @retval SDRAM status
*/
uint8_t BSP_SDRAM_Init(void)
gU8 BSP_SDRAM_Init(void)
{
static uint8_t sdramstatus = SDRAM_ERROR;
static gU8 sdramstatus = SDRAM_ERROR;
/* SDRAM device configuration */
sdramHandle.Instance = FMC_SDRAM_DEVICE;
@ -196,9 +196,9 @@ uint8_t BSP_SDRAM_Init(void)
* @brief DeInitializes the SDRAM device.
* @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
*/
uint8_t BSP_SDRAM_DeInit(void)
gU8 BSP_SDRAM_DeInit(void)
{
static uint8_t sdramstatus = SDRAM_ERROR;
static gU8 sdramstatus = SDRAM_ERROR;
/* SDRAM device configuration */
sdramHandle.Instance = FMC_SDRAM_DEVICE;
@ -219,9 +219,9 @@ uint8_t BSP_SDRAM_DeInit(void)
* @brief Programs the SDRAM device.
* @param RefreshCount: SDRAM refresh counter value
*/
void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
void BSP_SDRAM_Initialization_sequence(gU32 RefreshCount)
{
__IO uint32_t tmpmrd = 0;
__IO gU32 tmpmrd = 0;
/* Step 1: Configure a clock configuration enable command */
Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
@ -255,7 +255,7 @@ void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
/* Step 5: Program the external memory mode register */
tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\
tmpmrd = (gU32)SDRAM_MODEREG_BURST_LENGTH_1 |\
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
SDRAM_MODEREG_CAS_LATENCY_3 |\
SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
@ -281,9 +281,9 @@ void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
* @param uwDataSize: Size of read data from the memory
* @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
*/
uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
gU8 BSP_SDRAM_ReadData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
{
if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
if(HAL_SDRAM_Read_32b(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
{
return SDRAM_ERROR;
}
@ -300,9 +300,9 @@ uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uw
* @param uwDataSize: Size of read data from the memory
* @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
*/
uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
gU8 BSP_SDRAM_ReadData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
{
if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
if(HAL_SDRAM_Read_DMA(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
{
return SDRAM_ERROR;
}
@ -319,9 +319,9 @@ uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_
* @param uwDataSize: Size of written data from the memory
* @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
*/
uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
gU8 BSP_SDRAM_WriteData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
{
if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
if(HAL_SDRAM_Write_32b(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
{
return SDRAM_ERROR;
}
@ -338,9 +338,9 @@ uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t u
* @param uwDataSize: Size of written data from the memory
* @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
*/
uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
gU8 BSP_SDRAM_WriteData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize)
{
if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
if(HAL_SDRAM_Write_DMA(&sdramHandle, (gU32 *)uwStartAddress, pData, uwDataSize) != HAL_OK)
{
return SDRAM_ERROR;
}
@ -355,7 +355,7 @@ uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32
* @param SdramCmd: Pointer to SDRAM command structure
* @retval HAL status : SDRAM_OK or SDRAM_ERROR.
*/
uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
gU8 BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
{
if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK)
{

50
boards/base/STM32F469i-Discovery/stm32f469i_discovery_sdram.h
View file

@ -66,8 +66,8 @@
/**
* @brief SDRAM status structure definition
*/
#define SDRAM_OK ((uint8_t)0x00)
#define SDRAM_ERROR ((uint8_t)0x01)
#define SDRAM_OK ((gU8)0x00)
#define SDRAM_ERROR ((gU8)0x01)
/**
* @}
@ -76,17 +76,17 @@
/** @defgroup STM32469I-Discovery_SDRAM_Exported_Constants STM32469I Discovery SDRAM Exported Constants
* @{
*/
#define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000)
#define SDRAM_DEVICE_ADDR ((gU32)0xC0000000)
/* SDRAM device size in Bytes */
#define SDRAM_DEVICE_SIZE ((uint32_t)0x1000000)
#define SDRAM_DEVICE_SIZE ((gU32)0x1000000)
#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_32
#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2
/* SDRAM refresh counter (90 MHz SD clock) */
#define REFRESH_COUNT ((uint32_t)0x0569)
#define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
#define REFRESH_COUNT ((gU32)0x0569)
#define SDRAM_TIMEOUT ((gU32)0xFFFF)
/* DMA definitions for SDRAM DMA transfer */
#define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
@ -100,17 +100,17 @@
/**
* @brief FMC SDRAM Mode definition register defines
*/
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
#define SDRAM_MODEREG_BURST_LENGTH_1 ((gU16)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((gU16)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((gU16)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((gU16)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((gU16)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((gU16)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((gU16)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((gU16)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((gU16)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((gU16)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((gU16)0x0200)
/**
* @}
*/
@ -125,14 +125,14 @@
/** @addtogroup STM32469I_Discovery_SDRAM_Exported_Functions
* @{
*/
uint8_t BSP_SDRAM_Init(void);
uint8_t BSP_SDRAM_DeInit(void);
void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount);
uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
gU8 BSP_SDRAM_Init(void);
gU8 BSP_SDRAM_DeInit(void);
void BSP_SDRAM_Initialization_sequence(gU32 RefreshCount);
gU8 BSP_SDRAM_ReadData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
gU8 BSP_SDRAM_ReadData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
gU8 BSP_SDRAM_WriteData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
gU8 BSP_SDRAM_WriteData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
gU8 BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
void BSP_SDRAM_DMA_IRQHandler(void);
/* These function can be modified in case the current settings (e.g. DMA stream)

24
boards/base/STM32F469i-Discovery/stm32f469i_raw32_system.c
View file

@ -68,14 +68,14 @@
#if !defined (HSE_VALUE)
#if defined(USE_STM32469I_DISCO_REVA)
#define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
#define HSE_VALUE ((gU32)25000000) /*!< Default value of the External oscillator in Hz */
#else
#define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
#define HSE_VALUE ((gU32)8000000) /*!< Default value of the External oscillator in Hz */
#endif /* USE_STM32469I_DISCO_REVA */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE ((gU32)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
@ -129,9 +129,9 @@
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 16000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
gU32 SystemCoreClock = 16000000;
const gU8 AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const gU8 APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
@ -167,19 +167,19 @@ void SystemInit(void)
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
RCC->CR |= (gU32)0x00000001;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
RCC->CR &= (gU32)0xFEF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
RCC->CR &= (gU32)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
@ -234,7 +234,7 @@ void SystemInit(void)
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
gU32 tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
@ -291,8 +291,8 @@ void SystemCoreClockUpdate(void)
*/
void SystemInit_ExtMemCtl(void)
{
register uint32_t tmpreg = 0, timeout = 0xFFFF;
register __IO uint32_t index;
register gU32 tmpreg = 0, timeout = 0xFFFF;
register __IO gU32 index;
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH, and GPIOI interface
clock */

2
boards/base/STM32F746-Discovery/board_STM32LTDC.h
View file

@ -461,7 +461,7 @@ static GFXINLINE void post_init_board(GDisplay* g) {
(void) g;
}
static GFXINLINE void set_backlight(GDisplay* g, uint8_t percent) {
static GFXINLINE void set_backlight(GDisplay* g, gU8 percent) {
(void) g;
// ST was stupid enought not to hook this up to a pin that

54
boards/base/STM32F746-Discovery/example_chibios3/stm32f7xx_hal_conf.h
View file

@ -202,39 +202,39 @@
/* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */
#define PHY_BCR ((gU16)0x00U) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((gU16)0x01U) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */
#define PHY_RESET ((gU16)0x8000U) /*!< PHY Reset */
#define PHY_LOOPBACK ((gU16)0x4000U) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((gU16)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((gU16)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((gU16)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((gU16)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((gU16)0x1000U) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((gU16)0x0200U) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((gU16)0x0800U) /*!< Select the power down mode */
#define PHY_ISOLATE ((gU16)0x0400U) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */
#define PHY_AUTONEGO_COMPLETE ((gU16)0x0020U) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((gU16)0x0004U) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((gU16)0x0002U) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */
#define PHY_MICR ((uint16_t)0x11U) /*!< MII Interrupt Control Register */
#define PHY_MISR ((uint16_t)0x12U) /*!< MII Interrupt Status and Misc. Control Register */
#define PHY_SR ((gU16)0x10U) /*!< PHY status register Offset */
#define PHY_MICR ((gU16)0x11U) /*!< MII Interrupt Control Register */
#define PHY_MISR ((gU16)0x12U) /*!< MII Interrupt Status and Misc. Control Register */
#define PHY_LINK_STATUS ((uint16_t)0x0001U) /*!< PHY Link mask */
#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */
#define PHY_LINK_STATUS ((gU16)0x0001U) /*!< PHY Link mask */
#define PHY_SPEED_STATUS ((gU16)0x0002U) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((gU16)0x0004U) /*!< PHY Duplex mask */
#define PHY_MICR_INT_EN ((uint16_t)0x0002U) /*!< PHY Enable interrupts */
#define PHY_MICR_INT_OE ((uint16_t)0x0001U) /*!< PHY Enable output interrupt events */
#define PHY_MICR_INT_EN ((gU16)0x0002U) /*!< PHY Enable interrupts */
#define PHY_MICR_INT_OE ((gU16)0x0001U) /*!< PHY Enable output interrupt events */
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */
#define PHY_MISR_LINK_INT_EN ((gU16)0x0020U) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((gU16)0x2000U) /*!< PHY link status interrupt mask */
/* ################## SPI peripheral configuration ########################## */
@ -436,9 +436,9 @@
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((gU8 *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
void assert_failed(gU8* file, gU32 line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */

74
boards/base/STM32F746-Discovery/example_raw32/stm32f7xx_hal_conf.h
View file

@ -100,11 +100,11 @@
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */
#define HSE_VALUE ((gU32)25000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
#define HSE_STARTUP_TIMEOUT ((gU32)100U) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
@ -113,14 +113,14 @@
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE ((gU32)16000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/
#define LSI_VALUE ((gU32)32000U) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
@ -128,11 +128,11 @@
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */
#define LSE_VALUE ((gU32)32768U) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
#define LSE_STARTUP_TIMEOUT ((gU32)5000U) /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/**
@ -141,7 +141,7 @@
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
#define EXTERNAL_CLOCK_VALUE ((gU32)12288000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
@ -151,8 +151,8 @@
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
#define VDD_VALUE ((gU32)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((gU32)0x0F) /*!< tick interrupt priority */
#define USE_RTOS 0
#define ART_ACCLERATOR_ENABLE 1 /* To enable instruction cache and prefetch */
@ -178,50 +178,50 @@
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB ((uint32_t)5U) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB ((uint32_t)5U) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
#define ETH_RXBUFNB ((gU32)5U) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB ((gU32)5U) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* LAN8742A PHY Address*/
#define LAN8742A_PHY_ADDRESS 0x00U
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x00000FFFU)
#define PHY_RESET_DELAY ((gU32)0x00000FFFU)
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU)
#define PHY_CONFIG_DELAY ((gU32)0x00000FFFU)
#define PHY_READ_TO ((uint32_t)0x0000FFFFU)
#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU)
#define PHY_READ_TO ((gU32)0x0000FFFFU)
#define PHY_WRITE_TO ((gU32)0x0000FFFFU)
/* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */
#define PHY_BCR ((gU16)0x00U) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((gU16)0x01U) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */
#define PHY_RESET ((gU16)0x8000U) /*!< PHY Reset */
#define PHY_LOOPBACK ((gU16)0x4000U) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((gU16)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((gU16)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((gU16)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((gU16)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((gU16)0x1000U) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((gU16)0x0200U) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((gU16)0x0800U) /*!< Select the power down mode */
#define PHY_ISOLATE ((gU16)0x0400U) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */
#define PHY_AUTONEGO_COMPLETE ((gU16)0x0020U) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((gU16)0x0004U) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((gU16)0x0002U) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x1FU) /*!< PHY special control/ status register Offset */
#define PHY_SR ((gU16)0x1FU) /*!< PHY special control/ status register Offset */
#define PHY_SPEED_STATUS ((uint16_t)0x0004U) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0010U) /*!< PHY Duplex mask */
#define PHY_SPEED_STATUS ((gU16)0x0004U) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((gU16)0x0010U) /*!< PHY Duplex mask */
#define PHY_ISFR ((uint16_t)0x1DU) /*!< PHY Interrupt Source Flag register Offset */
#define PHY_ISFR_INT4 ((uint16_t)0x0010U) /*!< PHY Link down inturrupt */
#define PHY_ISFR ((gU16)0x1DU) /*!< PHY Interrupt Source Flag register Offset */
#define PHY_ISFR_INT4 ((gU16)0x0010U) /*!< PHY Link down inturrupt */
/* ################## SPI peripheral configuration ########################## */
@ -407,9 +407,9 @@
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((gU8 *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
void assert_failed(gU8* file, gU32 line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */

10
boards/base/STM32F746-Discovery/gmouse_lld_FT5336_board.h
View file

@ -40,14 +40,14 @@ static gBool init_board(GMouse* m, unsigned instance)
GPIOH->MODER |= GPIO_MODER_MODER7_1; // Alternate function
GPIOH->OTYPER |= GPIO_OTYPER_OT_7; // OpenDrain
GPIOH->OSPEEDR &= ~GPIO_OSPEEDER_OSPEEDR7; // LowSpeed
GPIOH->AFRL |= ((uint32_t)0x04 << 4*7); // AF4
GPIOH->AFRL |= ((gU32)0x04 << 4*7); // AF4
// I2C3_SDA GPIOH8, alternate, opendrain, highspeed
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOHEN; // Enable clock
GPIOH->MODER |= GPIO_MODER_MODER8_1; // Alternate function
GPIOH->OTYPER |= GPIO_OTYPER_OT_8; // OpenDrain
GPIOH->OSPEEDR &= ~GPIO_OSPEEDER_OSPEEDR8; // LowSpeed
GPIOH->AFRH |= ((uint32_t)0x04 << 4*0); // AF4
GPIOH->AFRH |= ((gU32)0x04 << 4*0); // AF4
// Initialize the I2C3 peripheral
if (!(i2cInit(I2C3))) {
@ -57,21 +57,21 @@ static gBool init_board(GMouse* m, unsigned instance)
return gTrue;
}
static void write_reg(GMouse* m, uint8_t reg, uint8_t val)
static void write_reg(GMouse* m, gU8 reg, gU8 val)
{
(void)m;
i2cWriteReg(I2C3, FT5336_SLAVE_ADDR, reg, val);
}
static uint8_t read_byte(GMouse* m, uint8_t reg)
static gU8 read_byte(GMouse* m, gU8 reg)
{
(void)m;
return i2cReadByte(I2C3, FT5336_SLAVE_ADDR, reg);
}
static uint16_t read_word(GMouse* m, uint8_t reg)
static gU16 read_word(GMouse* m, gU8 reg)
{
(void)m;

92
boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c
View file

@ -16,8 +16,8 @@
#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16
#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2
#define REFRESH_COUNT ((uint32_t)0x0603) /* SDRAM refresh counter (100Mhz SD clock) */
#define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
#define REFRESH_COUNT ((gU32)0x0603) /* SDRAM refresh counter (100Mhz SD clock) */
#define SDRAM_TIMEOUT ((gU32)0xFFFF)
/* DMA definitions for SDRAM DMA transfer */
#define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
@ -26,25 +26,25 @@
#define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn
/* FMC SDRAM Mode definition register defines */
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
#define SDRAM_MODEREG_BURST_LENGTH_1 ((gU16)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((gU16)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((gU16)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((gU16)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((gU16)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((gU16)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((gU16)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((gU16)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((gU16)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((gU16)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((gU16)0x0200)
static void BSP_SDRAM_Initialization_sequence(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshCount);
static void BSP_SDRAM_Initialization_sequence(SDRAM_HandleTypeDef *hsdram, gU32 RefreshCount);
static void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
static void _HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
static HAL_StatusTypeDef _FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
static HAL_StatusTypeDef _FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
static HAL_StatusTypeDef _FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
static HAL_StatusTypeDef _FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
static HAL_StatusTypeDef _FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, gU32 Bank);
static HAL_StatusTypeDef _FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, gU32 Timeout);
static HAL_StatusTypeDef _FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, gU32 RefreshRate);
static void _HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
{
@ -73,8 +73,8 @@ static void _HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef
static HAL_StatusTypeDef _FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
{
uint32_t tmpr1 = 0;
uint32_t tmpr2 = 0;
gU32 tmpr1 = 0;
gU32 tmpr2 = 0;
/* Set SDRAM bank configuration parameters */
if (Init->SDBank != FMC_SDRAM_BANK2)
@ -82,11 +82,11 @@ static HAL_StatusTypeDef _FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_In
tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
tmpr1 &= ((gU32)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
tmpr1 |= (gU32)(Init->ColumnBitsNumber |\
Init->RowBitsNumber |\
Init->MemoryDataWidth |\
Init->InternalBankNumber |\
@ -103,22 +103,22 @@ static HAL_StatusTypeDef _FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_In
tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
tmpr1 &= ((gU32)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
tmpr1 |= (gU32)(Init->SDClockPeriod |\
Init->ReadBurst |\
Init->ReadPipeDelay);
tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
/* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
tmpr2 &= ((gU32)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
tmpr2 |= (gU32)(Init->ColumnBitsNumber |\
Init->RowBitsNumber |\
Init->MemoryDataWidth |\
Init->InternalBankNumber |\
@ -132,10 +132,10 @@ static HAL_StatusTypeDef _FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_In
return HAL_OK;
}
static HAL_StatusTypeDef _FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
static HAL_StatusTypeDef _FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, gU32 Bank)
{
uint32_t tmpr1 = 0;
uint32_t tmpr2 = 0;
gU32 tmpr1 = 0;
gU32 tmpr2 = 0;
/* Set SDRAM device timing parameters */
if (Bank != FMC_SDRAM_BANK2)
@ -143,11 +143,11 @@ static HAL_StatusTypeDef _FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_S
tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
tmpr1 &= ((gU32)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
FMC_SDTR1_TRCD));
tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
tmpr1 |= (gU32)(((Timing->LoadToActiveDelay)-1) |\
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
(((Timing->SelfRefreshTime)-1) << 8) |\
(((Timing->RowCycleDelay)-1) << 12) |\
@ -161,11 +161,11 @@ static HAL_StatusTypeDef _FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_S
tmpr1 = Device->SDTR[FMC_SDRAM_BANK2];
/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
tmpr1 &= ((gU32)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
FMC_SDTR1_TRCD));
tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
tmpr1 |= (gU32)(((Timing->LoadToActiveDelay)-1) |\
(((Timing->ExitSelfRefreshDelay)-1) << 4) |\
(((Timing->SelfRefreshTime)-1) << 8) |\
(((Timing->WriteRecoveryTime)-1) <<16) |\
@ -174,10 +174,10 @@ static HAL_StatusTypeDef _FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_S
tmpr2 = Device->SDTR[FMC_SDRAM_BANK1];
/* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
tmpr2 &= ((gU32)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
FMC_SDTR1_TRCD));
tmpr2 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
tmpr2 |= (gU32)((((Timing->RowCycleDelay)-1) << 12) |\
(((Timing->RPDelay)-1) << 20));
Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;
@ -229,7 +229,7 @@ void BSP_SDRAM_Init(void)
BSP_SDRAM_Initialization_sequence(&sdramHandle, REFRESH_COUNT);
}
static HAL_StatusTypeDef _HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
static HAL_StatusTypeDef _HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, gU32 Timeout)
{
/* Check the SDRAM controller state */
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
@ -256,13 +256,13 @@ static HAL_StatusTypeDef _HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC
return HAL_OK;
}
static HAL_StatusTypeDef _FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
static HAL_StatusTypeDef _FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, gU32 Timeout)
{
__IO uint32_t tmpr = 0;
__IO gU32 tmpr = 0;
gTicks tickstart = 0;
/* Set command register */
tmpr = (uint32_t)((Command->CommandMode) |\
tmpr = (gU32)((Command->CommandMode) |\
(Command->CommandTarget) |\
(((Command->AutoRefreshNumber)-1) << 5) |\
((Command->ModeRegisterDefinition) << 9)
@ -291,7 +291,7 @@ static HAL_StatusTypeDef _FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_S
return HAL_OK;
}
static HAL_StatusTypeDef _HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
static HAL_StatusTypeDef _HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, gU32 RefreshRate)
{
/* Check the SDRAM controller state */
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
@ -311,7 +311,7 @@ static HAL_StatusTypeDef _HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdr
return HAL_OK;
}
static HAL_StatusTypeDef _FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
static HAL_StatusTypeDef _FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, gU32 RefreshRate)
{
/* Set the refresh rate in command register */
Device->SDRTR |= (RefreshRate<<1);
@ -321,7 +321,7 @@ static HAL_StatusTypeDef _FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device
static HAL_StatusTypeDef _HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
uint32_t tmp = 0;
gU32 tmp = 0;
/* Check the DMA peripheral state */
if(hdma == NULL)
@ -336,7 +336,7 @@ static HAL_StatusTypeDef _HAL_DMA_Init(DMA_HandleTypeDef *hdma)
tmp = hdma->Instance->CR;
/* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
tmp &= ((gU32)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
@ -361,7 +361,7 @@ static HAL_StatusTypeDef _HAL_DMA_Init(DMA_HandleTypeDef *hdma)
tmp = hdma->Instance->FCR;
/* Clear Direct mode and FIFO threshold bits */
tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
tmp &= (gU32)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
/* Prepare the DMA Stream FIFO configuration */
tmp |= hdma->Init.FIFOMode;
@ -424,7 +424,7 @@ static HAL_StatusTypeDef _HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
hdma->Instance->M1AR = 0;
/* Reset DMA Streamx FIFO control register */
hdma->Instance->FCR = (uint32_t)0x00000021;
hdma->Instance->FCR = (gU32)0x00000021;
/* Clear all flags */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
@ -450,7 +450,7 @@ static HAL_StatusTypeDef _HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
* @param RefreshCount: SDRAM refresh counter value
* @retval None
*/
static void BSP_SDRAM_Initialization_sequence(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshCount)
static void BSP_SDRAM_Initialization_sequence(SDRAM_HandleTypeDef *hsdram, gU32 RefreshCount)
{
FMC_SDRAM_CommandTypeDef Command;
@ -489,7 +489,7 @@ static void BSP_SDRAM_Initialization_sequence(SDRAM_HandleTypeDef *hsdram, uint3
Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
Command.AutoRefreshNumber = 1;
Command.ModeRegisterDefinition = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\
Command.ModeRegisterDefinition = (gU32)SDRAM_MODEREG_BURST_LENGTH_1 |\
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
SDRAM_MODEREG_CAS_LATENCY_2 |\
SDRAM_MODEREG_OPERATING_MODE_STANDARD |\

4
boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h
View file

@ -44,8 +44,8 @@
extern "C" {
#endif
#define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000)
#define SDRAM_DEVICE_SIZE ((uint32_t)0x800000) /* SDRAM device size in MBytes */
#define SDRAM_DEVICE_ADDR ((gU32)0xC0000000)
#define SDRAM_DEVICE_SIZE ((gU32)0x800000) /* SDRAM device size in MBytes */
void BSP_SDRAM_Init(void);

22
boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c
View file

@ -66,11 +66,11 @@
#include "stm32f7xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
#define HSE_VALUE ((gU32)25000000) /*!< Default value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE ((gU32)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
@ -125,9 +125,9 @@
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 16000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
gU32 SystemCoreClock = 16000000;
const gU8 AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const gU8 APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
@ -163,19 +163,19 @@ void SystemInit(void)
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
RCC->CR |= (gU32)0x00000001;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
RCC->CR &= (gU32)0xFEF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
RCC->CR &= (gU32)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
@ -230,7 +230,7 @@ void SystemInit(void)
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
gU32 tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
@ -287,8 +287,8 @@ void SystemCoreClockUpdate(void)
*/
void SystemInit_ExtMemCtl(void)
{
register uint32_t tmpreg = 0, timeout = 0xFFFF;
register __IO uint32_t index;
register gU32 tmpreg = 0, timeout = 0xFFFF;
register __IO gU32 index;
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG and GPIOH interface
clock */

30
boards/base/STM32F746-Discovery/stm32f7_i2c.c
View file

@ -9,18 +9,18 @@
/*
* The CR2 register needs atomic access. Hence always use this function to setup a transfer configuration.
*/
static void _i2cConfigTransfer(I2C_TypeDef* i2c, uint16_t slaveAddr, uint8_t numBytes, uint32_t mode, uint32_t request)
static void _i2cConfigTransfer(I2C_TypeDef* i2c, gU16 slaveAddr, gU8 numBytes, gU32 mode, gU32 request)
{
uint32_t tmpreg = 0;
gU32 tmpreg = 0;
// Get the current CR2 register value
tmpreg = i2c->CR2;
// Clear tmpreg specific bits
tmpreg &= (uint32_t) ~((uint32_t) (I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
tmpreg &= (gU32) ~((gU32) (I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
// update tmpreg
tmpreg |= (uint32_t) (((uint32_t) slaveAddr & I2C_CR2_SADD) | (((uint32_t) numBytes << 16) & I2C_CR2_NBYTES) | (uint32_t) mode | (uint32_t) request);
tmpreg |= (gU32) (((gU32) slaveAddr & I2C_CR2_SADD) | (((gU32) numBytes << 16) & I2C_CR2_NBYTES) | (gU32) mode | (gU32) request);
// Update the actual CR2 contents
i2c->CR2 = tmpreg;
@ -31,7 +31,7 @@ static void _i2cConfigTransfer(I2C_TypeDef* i2c, uint16_t slaveAddr, uint8_t num
*/
static void _i2cResetCr2(I2C_TypeDef* i2c)
{
i2c->CR2 &= (uint32_t) ~((uint32_t) (I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN));
i2c->CR2 &= (gU32) ~((gU32) (I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN));
}
gBool i2cInit(I2C_TypeDef* i2c)
@ -79,7 +79,7 @@ gBool i2cInit(I2C_TypeDef* i2c)
return gTrue;
}
void i2cSend(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t* data, uint16_t length)
void i2cSend(I2C_TypeDef* i2c, gU8 slaveAddr, gU8* data, gU16 length)
{
// We are currently not able to send more than 255 bytes at once
if (length > 255) {
@ -109,21 +109,21 @@ void i2cSend(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t* data, uint16_t length
_i2cResetCr2(i2c);
}
void i2cSendByte(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t data)
void i2cSendByte(I2C_TypeDef* i2c, gU8 slaveAddr, gU8 data)
{
i2cSend(i2c, slaveAddr, &data, 1);
}
void i2cWriteReg(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t regAddr, uint8_t value)
void i2cWriteReg(I2C_TypeDef* i2c, gU8 slaveAddr, gU8 regAddr, gU8 value)
{
uint8_t txbuf[2];
gU8 txbuf[2];
txbuf[0] = regAddr;
txbuf[1] = value;
i2cSend(i2c, slaveAddr, txbuf, 2);
}
void i2cRead(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t* data, uint16_t length)
void i2cRead(I2C_TypeDef* i2c, gU8 slaveAddr, gU8* data, gU16 length)
{
int i;
@ -151,9 +151,9 @@ void i2cRead(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t* data, uint16_t length
_i2cResetCr2(i2c);
}
uint8_t i2cReadByte(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t regAddr)
gU8 i2cReadByte(I2C_TypeDef* i2c, gU8 slaveAddr, gU8 regAddr)
{
uint8_t ret = 0xAA;
gU8 ret = 0xAA;
i2cSend(i2c, slaveAddr, &regAddr, 1);
i2cRead(i2c, slaveAddr, &ret, 1);
@ -161,12 +161,12 @@ uint8_t i2cReadByte(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t regAddr)
return ret;
}
uint16_t i2cReadWord(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t regAddr)
gU16 i2cReadWord(I2C_TypeDef* i2c, gU8 slaveAddr, gU8 regAddr)
{
uint8_t ret[2] = { 0xAA, 0xAA };
gU8 ret[2] = { 0xAA, 0xAA };
i2cSend(i2c, slaveAddr, &regAddr, 1);
i2cRead(i2c, slaveAddr, ret, 2);
return (uint16_t)((ret[0] << 8) | (ret[1] & 0x00FF));
return (gU16)((ret[0] << 8) | (ret[1] & 0x00FF));
}

12
boards/base/STM32F746-Discovery/stm32f7_i2c.h
View file

@ -5,10 +5,10 @@
gBool i2cInit(I2C_TypeDef* i2c);
void i2cSend(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t* data, uint16_t length);
void i2cSendByte(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t data);
void i2cWriteReg(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t regAddr, uint8_t value);
void i2cSend(I2C_TypeDef* i2c, gU8 slaveAddr, gU8* data, gU16 length);
void i2cSendByte(I2C_TypeDef* i2c, gU8 slaveAddr, gU8 data);
void i2cWriteReg(I2C_TypeDef* i2c, gU8 slaveAddr, gU8 regAddr, gU8 value);
void i2cRead(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t* data, uint16_t length);
uint8_t i2cReadByte(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t regAddr);
uint16_t i2cReadWord(I2C_TypeDef* i2c, uint8_t slaveAddr, uint8_t regAddr);
void i2cRead(I2C_TypeDef* i2c, gU8 slaveAddr, gU8* data, gU16 length);
gU8 i2cReadByte(I2C_TypeDef* i2c, gU8 slaveAddr, gU8 regAddr);
gU16 i2cReadWord(I2C_TypeDef* i2c, gU8 slaveAddr, gU8 regAddr);

6
boards/base/eCos-Synthetic-Framebuffer/board_framebuffer.h
View file

@ -63,7 +63,7 @@
#endif
#if GDISP_NEED_CONTROL
static void board_backlight(GDisplay *g, uint8_t percent) {
static void board_backlight(GDisplay *g, gU8 percent) {
(void) g;
#if (CYG_FB_FLAGS0(FRAMEBUF) & CYG_FB_FLAGS0_BACKLIGHT)
cyg_fb_ioctl_backlight backlight;
@ -74,12 +74,12 @@
if (backlight.fbbl_max == 1)
backlight.fbbl_current = percent ? 1 : 0;
else
backlight.fbbl_current = (((uint32_t)percent)*backlight.fbbl_max)/100;
backlight.fbbl_current = (((gU32)percent)*backlight.fbbl_max)/100;
CYG_FB_IOCTL(FRAMEBUF, CYG_FB_IOCTL_BACKLIGHT_SET, &backlight, &len);
#endif
}
static void board_contrast(GDisplay *g, uint8_t percent) {
static void board_contrast(GDisplay *g, gU8 percent) {
(void) g;
(void) percent;
}

4
changelog.txt
View file

@ -32,7 +32,9 @@ CHANGE: Added type gJustify to replace V2.x justify_t, and values gJ
CHANGE: Added type gFontmetric to replace V2.x fontmetric_t, and values gFontXXX replace fontXXX
CHANGE: Added type gOrientation to replace V2.x orientation_t, and values gOrientationX replace GDISP_ROTATE_X
CHANGE: Added macros JUSTIFYMASK_HORIZONTAL, JUSTIFYMASK_VERTICAL to replace macros JUSTIFYMASK_LEFTRIGHT, JUSTIFYMASK_TOPBOTTOM
FEATURE: Added types gPtr and gPtrDiff
FEATURE: Added types gPtr, gPtrDiff and gAny
FEATURE: Added type gMemSize and config macro GFX_MEM_LT64K
FEATURE: Added type gFileSize
FEATURE: Added gI64 and gU64 when the compiler supports it. GFX_TYPE_64 macro is defined as GFXON if it does.
FEATURE: Fixed headers to ensure size_t, NULL are always defined. size_t is not used as it may be 64bit.
FIX: Added gfxRealloc() to Qt port

50
demos/3rdparty/bubbles/main.c vendored
View file

@ -25,14 +25,14 @@
#define background RGB2COLOR(0,0,0)
uint16_t width, height;
int16_t sine[SCALE+(SCALE/4)];
int16_t *cosi = &sine[SCALE/4]; /* cos(x) = sin(x+90d)... */
gU16 width, height;
gI16 sine[SCALE+(SCALE/4)];
gI16 *cosi = &sine[SCALE/4]; /* cos(x) = sin(x+90d)... */
void initialize (void)
{
uint16_t i;
gU16 i;
/* if you change the SCALE*1.25 back to SCALE, the program will
* occassionally overrun the cosi array -- however this actually
@ -44,12 +44,12 @@ void initialize (void)
}
void matrix (int16_t xyz[3][N], gColor col[N])
void matrix (gI16 xyz[3][N], gColor col[N])
{
static uint32_t t = 0;
int16_t x = -SCALE, y = -SCALE;
uint16_t i, s, d;
uint8_t red,grn,blu;
static gU32 t = 0;
gI16 x = -SCALE, y = -SCALE;
gU16 i, s, d;
gU8 red,grn,blu;
#define RED_COLORS (32)
#define GREEN_COLORS (64)
@ -81,13 +81,13 @@ void matrix (int16_t xyz[3][N], gColor col[N])
}
void rotate (int16_t xyz[3][N], uint16_t angleX, uint16_t angleY, uint16_t angleZ)
void rotate (gI16 xyz[3][N], gU16 angleX, gU16 angleY, gU16 angleZ)
{
uint16_t i;
int16_t tmpX, tmpY;
int16_t sinx = sine[angleX], cosx = cosi[angleX];
int16_t siny = sine[angleY], cosy = cosi[angleY];
int16_t sinz = sine[angleZ], cosz = cosi[angleZ];
gU16 i;
gI16 tmpX, tmpY;
gI16 sinx = sine[angleX], cosx = cosi[angleX];
gI16 siny = sine[angleY], cosy = cosi[angleY];
gI16 sinz = sine[angleZ], cosz = cosi[angleZ];
for (i = 0; i < N; i++)
{
@ -106,12 +106,12 @@ void rotate (int16_t xyz[3][N], uint16_t angleX, uint16_t angleY, uint16_t angle
}
void draw(int16_t xyz[3][N], gColor col[N])
void draw(gI16 xyz[3][N], gColor col[N])
{
static uint16_t oldProjX[N] = {0};
static uint16_t oldProjY[N] = {0};
static uint8_t oldDotSize[N] = {0};
uint16_t i, projX, projY, projZ, dotSize;
static gU16 oldProjX[N] = {0};
static gU16 oldProjY[N] = {0};
static gU8 oldDotSize[N] = {0};
gU16 i, projX, projY, projZ, dotSize;
for (i = 0; i < N; i++)
{
@ -138,10 +138,10 @@ void draw(int16_t xyz[3][N], gColor col[N])
/* ---------------------------------------------------------------------- */
int16_t angleX = 0, angleY = 0, angleZ = 0;
int16_t speedX = 0, speedY = 0, speedZ = 0;
gI16 angleX = 0, angleY = 0, angleZ = 0;
gI16 speedX = 0, speedY = 0, speedZ = 0;
int16_t xyz[3][N];
gI16 xyz[3][N];
gColor col[N];
@ -158,8 +158,8 @@ int main (void)
gfxSleepMilliseconds (10);
gdispClear (background); /* glitches.. */
width = (uint16_t)gdispGetWidth();
height = (uint16_t)gdispGetHeight();
width = (gU16)gdispGetWidth();
height = (gU16)gdispGetHeight();
initialize();

2
demos/3rdparty/notepad-2/main.c vendored
View file

@ -66,7 +66,7 @@ const NColorScheme schemeDefault2 = {
.statusBarText = HTML2COLOR(0x000000)
};
const char *tsCalibRead(uint16_t instance) {
const char *tsCalibRead(gU16 instance) {
// This will perform a on-spot calibration
// Unless you read and add the co-efficients here
(void) instance;

2
demos/3rdparty/notepad-2/notepadApp.c vendored
View file

@ -96,7 +96,7 @@ static void nbtnColorBarDraw(GHandle gh, gBool enabled, gBool isdown, const char
// Update selection - this is like lazy release.
if (k >= 0 && k <= 7) {
selPenWidth = k + 1;
ncoreSetPenWidth((uint8_t) selPenWidth);
ncoreSetPenWidth((gU8) selPenWidth);
}
gdispFillArea(gh->x + NPAD_TOOLBAR_BTN_WIDTH * i, gh->y,

18
demos/3rdparty/notepad-2/notepadCore.c vendored
View file

@ -45,8 +45,8 @@
/* This is the drawing core */
static DECLARE_THREAD_STACK(waDrawThread, NCORE_THD_STACK_SIZE);
static uint8_t nPenWidth = 1;
static uint8_t nMode = NCORE_MODE_DRAW;
static gU8 nPenWidth = 1;
static gU8 nMode = NCORE_MODE_DRAW;
static gThread nThd;
@ -72,9 +72,9 @@ static void draw_point(gCoord x, gCoord y) {
/* Bresenham's Line Drawing Algorithm
Modified version to draw line of variable thickness */
static void draw_line(gCoord x0, gCoord y0, gCoord x1, gCoord y1) {
int16_t dy, dx;
int16_t addx, addy;
int16_t P, diff, i;
gI16 dy, dx;
gI16 addx, addy;
gI16 P, diff, i;
if (x1 >= x0) {
dx = x1 - x0;
@ -223,13 +223,13 @@ void ncoreTerminateDrawThread(void) {
/* Get and set the pen width
* Brush is cicular, width is pixel radius */
void ncoreSetPenWidth(uint8_t penWidth) { nPenWidth = penWidth; }
uint8_t ncoreGetPenWidth(void) { return nPenWidth; }
void ncoreSetPenWidth(gU8 penWidth) { nPenWidth = penWidth; }
gU8 ncoreGetPenWidth(void) { return nPenWidth; }
/* Get and set the drawing color */
void ncoreSetPenColor(gColor penColor) { gwinSetColor(ncoreDrawingArea, penColor); }
gColor ncoreGetPenColor(void) { return ncoreDrawingArea->color; }
/* Set mode */
void ncoreSetMode(uint8_t mode) { nMode = mode; }
uint8_t ncoreGetMode(void) { return nMode; }
void ncoreSetMode(gU8 mode) { nMode = mode; }
gU8 ncoreGetMode(void) { return nMode; }

8
demos/3rdparty/notepad-2/notepadCore.h vendored
View file

@ -54,15 +54,15 @@ void ncoreTerminateDrawThread(void);
/* Get and set the pen width
* Brush is cicular, width is pixel radius */
void ncoreSetPenWidth(uint8_t penWidth);
uint8_t ncoreGetPenWidth(void);
void ncoreSetPenWidth(gU8 penWidth);
gU8 ncoreGetPenWidth(void);
/* Get and set the drawing color */
void ncoreSetPenColor(gColor penColor);
gColor ncoreGetPenColor(void);
/* Get and set the pen mode */
void ncoreSetMode(uint8_t mode);
uint8_t ncoreGetMode(void);
void ncoreSetMode(gU8 mode);
gU8 ncoreGetMode(void);
#endif /* NOTEPADCORE_H_ */

2
demos/applications/combo/mandelbrot.c
View file

@ -36,7 +36,7 @@ static gThread thread;
static void mandelbrot(float x1, float y1, float x2, float y2) {
unsigned int i,j, width, height;
uint16_t iter;
gU16 iter;
float fwidth, fheight;
float sy = y2 - y1;

2
demos/applications/mandelbrot/main.c
View file

@ -31,7 +31,7 @@
void mandelbrot(float x1, float y1, float x2, float y2) {
unsigned int i,j, width, height;
uint16_t iter;
gU16 iter;
gColor color;
float fwidth, fheight;

2
demos/applications/notepad/main.c
View file

@ -75,7 +75,7 @@ GEventMouse ev;
int main(void) {
gColor color = GFX_BLACK;
uint16_t pen = 0;
gU16 pen = 0;
gfxInit();
ginputGetMouse(0);

2
demos/benchmarks/main.c
View file

@ -86,7 +86,7 @@ static int uitoa(unsigned int value, char * buf, int max) {
}
void benchmark(void) {
uint32_t i, pixels, ms, pps;
gU32 i, pixels, ms, pps;
char pps_str[25];
gCoord height, width, rx, ry, rcx, rcy;
gColor random_color;

54
demos/games/justget10/jg10.c
View file

@ -16,7 +16,7 @@ GHandle jg10SelectionWidgetGCreate(GDisplay* g, jg10WidgetObject* wo, GWidgetIni
typedef struct { // Node properties
uint8_t num; // Node number
gU8 num; // Node number
gBool check; // Node needs to be checked or not
gBool sel; // Node selected or not
} nodeProps;
@ -29,7 +29,7 @@ gdispImage jg10Image[JG10_MAX_COUNT];
#define JG10_ANIM_DELAY 60
const char *jg10GraphAnim[] = {"a1.bmp","a2.bmp","a3.bmp","a4.bmp","background.bmp"}; // 5 elements (0-4)
gdispImage jg10ImageAnim[JG10_ANIM_IMAGES];
uint8_t jg10MaxVal=4; // Max value in field...
gU8 jg10MaxVal=4; // Max value in field...
gFont font;
#if JG10_SHOW_SPLASH
GTimer jg10SplashBlink;
@ -42,7 +42,7 @@ static void initRng(void) {
srand(gfxSystemTicks());
}
static uint32_t randomInt(uint32_t max) {
static gU32 randomInt(gU32 max) {
return rand() % max;
}
@ -86,12 +86,12 @@ static int uitoa(unsigned int value, char * buf, int max) {
return n;
}
static gBool inRange(int16_t x, int16_t y) {
static gBool inRange(gI16 x, gI16 y) {
if ((x >= 0) && (x < JG10_FIELD_WIDTH) && (y >= 0) && (y < JG10_FIELD_HEIGHT)) return gTrue; else return gFalse;
}
static void clean_SelCheck(void) {
uint16_t i ,j;
gU16 i ,j;
for (i = 0; i < JG10_FIELD_WIDTH; i++) {
for (j = 0; j < JG10_FIELD_HEIGHT; j++) {
jg10Field[i][j].check = gFalse;
@ -101,7 +101,7 @@ static void clean_SelCheck(void) {
}
static void remove_Selected(void) {
uint16_t i ,j, step;
gU16 i ,j, step;
gTicks delay_start = 0;
gTicks delay=0;
for (step = 0; step < JG10_ANIM_IMAGES; step++) {
@ -129,12 +129,12 @@ static void remove_Selected(void) {
// gwinRedraw(mainWin);
}
static uint8_t jg10_randomer(uint8_t max, uint8_t th) {
uint32_t r = randomInt((1<<max)-1);
static gU8 jg10_randomer(gU8 max, gU8 th) {
gU32 r = randomInt((1<<max)-1);
if (r != 0) {
for (int8_t i = max; i >= 0; i--) {
if (r >= (uint32_t)(1<<i)) {
for (gI8 i = max; i >= 0; i--) {
if (r >= (gU32)(1<<i)) {
if ((max-i) >= th) {
return randomInt(max-i)+1;
} else {
@ -147,20 +147,20 @@ static uint8_t jg10_randomer(uint8_t max, uint8_t th) {
}
static void movePiecesDown(void) {
uint8_t tmp = 0;
gU8 tmp = 0;
gBool needToCheck = gTrue;
while (needToCheck) {
needToCheck = gFalse;
for (int8_t y = (JG10_FIELD_HEIGHT-1); y >= 0; y--) {
for (uint8_t x = 0; x < JG10_FIELD_WIDTH; x++) {
for (gI8 y = (JG10_FIELD_HEIGHT-1); y >= 0; y--) {
for (gU8 x = 0; x < JG10_FIELD_WIDTH; x++) {
if (jg10Field[x][y].num == 0) {
// check if there is at least single none empty piece
tmp = 0;
for (int8_t tmpy = y; tmpy >= 0; tmpy--) {
for (gI8 tmpy = y; tmpy >= 0; tmpy--) {
if (jg10Field[x][tmpy].num != 0) tmp++;
}
if (tmp != 0) {
for (int8_t tmpy = y; tmpy > 0; tmpy--) {
for (gI8 tmpy = y; tmpy > 0; tmpy--) {
jg10Field[x][tmpy].num = jg10Field[x][tmpy-1].num;
}
jg10Field[x][0].num = 0;
@ -175,10 +175,10 @@ static void movePiecesDown(void) {
needToCheck = gTrue;
while (needToCheck) {
needToCheck = gFalse;
for (int8_t y = (JG10_FIELD_HEIGHT-1); y >= 0; y--) {
for (uint8_t x = 0; x < JG10_FIELD_WIDTH; x++) {
for (gI8 y = (JG10_FIELD_HEIGHT-1); y >= 0; y--) {
for (gU8 x = 0; x < JG10_FIELD_WIDTH; x++) {
if (jg10Field[x][y].num == 0) {
for (int8_t tmpy = y; tmpy > 0; tmpy--) {
for (gI8 tmpy = y; tmpy > 0; tmpy--) {
jg10Field[x][tmpy].num = jg10Field[x][tmpy-1].num;
}
jg10Field[x][0].num = jg10_randomer(jg10MaxVal, 3);
@ -193,7 +193,7 @@ static void movePiecesDown(void) {
static gBool checkForPossibleMove(void) {
gBool canMove = gFalse;
uint16_t i ,j;
gU16 i ,j;
for (i = 0; i < JG10_FIELD_WIDTH; i++) {
for (j = 0; j < JG10_FIELD_HEIGHT; j++) {
if ((inRange(i,j-1) && jg10Field[i][j-1].num == jg10Field[i][j].num) ||
@ -225,7 +225,7 @@ static void printCongrats(void) {
static DECLARE_THREAD_FUNCTION(thdJg10, msg) {
(void)msg;
uint16_t x,y;
gU16 x,y;
while (!jg10GameOver) {
srand(gfxSystemTicks());
ginputGetMouseStatus(0, &ev);
@ -278,8 +278,8 @@ static DECLARE_THREAD_FUNCTION(thdJg10, msg) {
static void initField(void) {
jg10MaxVal = 4;
for (uint8_t x = 0; x < JG10_FIELD_WIDTH; x++) {
for (uint8_t y = 0; y < JG10_FIELD_HEIGHT; y++) {
for (gU8 x = 0; x < JG10_FIELD_WIDTH; x++) {
for (gU8 y = 0; y < JG10_FIELD_HEIGHT; y++) {
jg10Field[x][y].num = randomInt(jg10MaxVal)+1;
//jg10Field[x][y].num = 1; // good for animation testing
//jg10Field[x][y].num = x+x+5; // good to get high score fast
@ -295,15 +295,15 @@ static void initField(void) {
static void mainWinDraw(GWidgetObject* gw, void* param) {
(void)param;
for (uint8_t x = 0; x < JG10_FIELD_WIDTH; x++) {
for (uint8_t y = 0; y < JG10_FIELD_HEIGHT; y++) {
for (gU8 x = 0; x < JG10_FIELD_WIDTH; x++) {
for (gU8 y = 0; y < JG10_FIELD_HEIGHT; y++) {
gdispGImageDraw(gw->g.display, &jg10Image[jg10Field[x][y].num], (x*JG10_CELL_HEIGHT)+1, (y*JG10_CELL_WIDTH)+1, JG10_CELL_WIDTH, JG10_CELL_HEIGHT, 0, 0);
}
}
}
static void jg10SelectionWidget_Draw(GWidgetObject* gw, void* param) {
int16_t x, y;
gI16 x, y;
gBool needToCheck = gTrue;
(void)param;
@ -468,11 +468,11 @@ void jg10Start(void) {
void jg10Init(void) {
initRng();
for (uint8_t i = 0; i < JG10_MAX_COUNT; i++) {
for (gU8 i = 0; i < JG10_MAX_COUNT; i++) {
gdispImageOpenFile(&jg10Image[i], jg10Graph[i]);
gdispImageCache(&jg10Image[i]);
}
for (uint8_t i = 0; i < JG10_ANIM_IMAGES; i++) {
for (gU8 i = 0; i < JG10_ANIM_IMAGES; i++) {
gdispImageOpenFile(&jg10ImageAnim[i], jg10GraphAnim[i]);
gdispImageCache(&jg10ImageAnim[i]);
}

28
demos/games/minesweeper/mines.c
View file

@ -3,25 +3,25 @@
#include "mines.h"
typedef struct { // Node properties
uint8_t num; // Node number, how many mines around
gU8 num; // Node number, how many mines around
gBool open; // Node shown or hidden
gBool check; // Node needs to be checked or not, used for opening up empty nodes
gBool flag; // Node is marked with flag by player
uint16_t fieldNum; // Node number, used to randomize gamestart "animation"
gU16 fieldNum; // Node number, used to randomize gamestart "animation"
} nodeProps;
static GEventMouse ev;
static nodeProps minesField[MINES_FIELD_WIDTH][MINES_FIELD_HEIGHT]; // Mines field array
static gBool minesGameOver = gFalse;
static gBool minesGameWinner = gFalse;
static int16_t minesEmptyNodes; // Empty node counter
static int16_t minesFlags; // Flag counter
static int16_t minesTime; // Time counter
static gI16 minesEmptyNodes; // Empty node counter
static gI16 minesFlags; // Flag counter
static gI16 minesTime; // Time counter
static GTimer minesTimeCounterTimer;
static const char* minesGraph[] = {"1.bmp","2.bmp","3.bmp","4.bmp","5.bmp","6.bmp","7.bmp","8.bmp", "closed.bmp", "empty.bmp", "explode.bmp", "flag.bmp", "mine.bmp", "wrong.bmp"}; // 14 elements (0-13)
static gdispImage minesImage;
static uint8_t minesStatusIconWidth = 0;
static uint8_t minesStatusIconHeight = 0;
static gU8 minesStatusIconWidth = 0;
static gU8 minesStatusIconHeight = 0;
static gBool minesFirstGame = gTrue; // Just don't clear field for the first time, as we have black screen already... :/
static gBool minesSplashTxtVisible = gFalse;
#if MINES_SHOW_SPLASH
@ -84,7 +84,7 @@ static void initRng(void)
srand(gfxSystemTicks());
}
static uint32_t randomInt(uint32_t max)
static gU32 randomInt(gU32 max)
{
return rand() % max;
}
@ -125,7 +125,7 @@ static void minesTimeCounter(void* arg)
minesUpdateTime();
}
static gBool inRange(int16_t x, int16_t y)
static gBool inRange(gI16 x, gI16 y)
{
if ((x >= 0) && (x < MINES_FIELD_WIDTH) && (y >= 0) && (y < MINES_FIELD_HEIGHT))
return gTrue;
@ -133,7 +133,7 @@ static gBool inRange(int16_t x, int16_t y)
return gFalse;
}
static void showOne(int16_t x, int16_t y)
static void showOne(gI16 x, gI16 y)
{
minesField[x][y].open = gTrue;
if (minesField[x][y].flag) {
@ -167,7 +167,7 @@ static void showOne(int16_t x, int16_t y)
static void openEmptyNodes(void)
{
int16_t x, y, i, j;
gI16 x, y, i, j;
gBool needToCheck = gTrue;
while (needToCheck) {
@ -195,7 +195,7 @@ static void openEmptyNodes(void)
static DECLARE_THREAD_FUNCTION(thdMines, msg)
{
(void)msg;
uint16_t x,y, delay;
gU16 x,y, delay;
gBool delayed = gFalse;
while (!minesGameOver) {
if (minesEmptyNodes == 0) {
@ -265,7 +265,7 @@ static void printGameOver(void)
static void initField(void)
{
int16_t x, y, mines, i, j;
gI16 x, y, mines, i, j;
minesFlags = 0;
minesGameOver = gFalse;
@ -374,7 +374,7 @@ static void initField(void)
void minesStart(void)
{
int16_t x, y;
gI16 x, y;
#if MINES_SHOW_SPLASH
gtimerStop(&minesSplashBlink);

8
demos/games/minesweeper/resources/romfs/userfonts.h
View file

@ -11,25 +11,25 @@
#error The font file is not compatible with this version of mcufont.
#endif
static const uint8_t mf_rlefont_digital_7__mono_20_dictionary_data[39] = {
static const gU8 mf_rlefont_digital_7__mono_20_dictionary_data[39] = {
0x81, 0x05, 0x81, 0x05, 0x81, 0x05, 0x81, 0x05, 0x81, 0x06, 0x80, 0x01, 0x07, 0x80, 0x05, 0x85,
0x05, 0x80, 0x81, 0x03, 0x03, 0x85, 0x0f, 0x44, 0x84, 0x85, 0x86, 0x88, 0x44, 0x44, 0x44, 0x44,
0x24, 0x84, 0x44, 0x44, 0x18, 0xc4, 0x83,
};
static const uint16_t mf_rlefont_digital_7__mono_20_dictionary_offsets[13] = {
static const gU16 mf_rlefont_digital_7__mono_20_dictionary_offsets[13] = {
0x0000, 0x0009, 0x000c, 0x000f, 0x0010, 0x0012, 0x0013, 0x0014,
0x0016, 0x001c, 0x0020, 0x0024, 0x0027,
};
static const uint8_t mf_rlefont_digital_7__mono_20_glyph_data_0[63] = {
static const gU8 mf_rlefont_digital_7__mono_20_glyph_data_0[63] = {
0x09, 0x1b, 0x18, 0x1c, 0x1a, 0x18, 0x1b, 0x09, 0x21, 0x19, 0x22, 0x21, 0x09, 0x83, 0x44, 0x21,
0x83, 0x20, 0x1f, 0x10, 0x09, 0x83, 0x44, 0x21, 0x82, 0x44, 0x21, 0x83, 0x09, 0x84, 0x23, 0x20,
0xec, 0x44, 0x09, 0x43, 0x20, 0x1f, 0x20, 0xec, 0x83, 0x09, 0x43, 0x20, 0x1f, 0x23, 0x0f, 0x09,
0x1b, 0x18, 0x22, 0x21, 0x09, 0x1b, 0x23, 0x23, 0x0f, 0x09, 0x1b, 0x23, 0x20, 0xec, 0x83,
};
static const uint16_t mf_rlefont_digital_7__mono_20_glyph_offsets_0[10] = {
static const gU16 mf_rlefont_digital_7__mono_20_glyph_offsets_0[10] = {
0x0000, 0x0007, 0x000c, 0x0014, 0x001c, 0x0022, 0x0029, 0x002f,
0x0034, 0x0039,
};

12
demos/games/tetris/Example_Makefiles/stm32f4/board_SSD1289.h
View file

@ -18,8 +18,8 @@
// For a multiple display configuration we would put all this in a structure and then
// set g->board to that structure.
#define GDISP_REG ((volatile uint16_t *) 0x60000000)[0] /* RS = 0 */
#define GDISP_RAM ((volatile uint16_t *) 0x60020000)[0] /* RS = 1 */
#define GDISP_REG ((volatile gU16 *) 0x60000000)[0] /* RS = 0 */
#define GDISP_RAM ((volatile gU16 *) 0x60020000)[0] /* RS = 1 */
#define GDISP_DMA_STREAM STM32_DMA2_STREAM6
#define FSMC_BANK 0
@ -116,7 +116,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
(void) state;
}
static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
pwmEnableChannel(&PWMD3, 2, percent);
}
@ -129,12 +129,12 @@ static GFXINLINE void release_bus(GDisplay *g) {
(void) g;
}
static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
static GFXINLINE void write_index(GDisplay *g, gU16 index) {
(void) g;
GDISP_REG = index;
}
static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
static GFXINLINE void write_data(GDisplay *g, gU16 data) {
(void) g;
GDISP_RAM = data;
}
@ -149,7 +149,7 @@ static GFXINLINE void setwritemode(GDisplay *g) {
FSMC_Bank1->BTCR[FSMC_BANK+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0; /* FSMC timing */
}
static GFXINLINE uint16_t read_data(GDisplay *g) {
static GFXINLINE gU16 read_data(GDisplay *g) {
(void) g;
return GDISP_RAM;
}

8
demos/games/tetris/Example_Makefiles/stm32f4/ginput_lld_mouse_board.h
View file

@ -43,11 +43,11 @@ static GFXINLINE void release_bus(void)
spiReleaseBus(&SPID1);
}
static GFXINLINE uint16_t read_value(uint16_t port)
static GFXINLINE gU16 read_value(gU16 port)
{
static uint8_t txbuf[3] = {0};
static uint8_t rxbuf[3] = {0};
uint16_t ret;
static gU8 txbuf[3] = {0};
static gU8 rxbuf[3] = {0};
gU16 ret;
txbuf[0] = port;

8
demos/games/tetris/Example_Makefiles/stm32f4/gmouse_lld_ADS7843_board.h
View file

@ -85,15 +85,15 @@ static GFXINLINE void release_bus(GMouse* m) {
spiReleaseBus(&SPID1);
}
static GFXINLINE uint16_t read_value(GMouse* m, uint16_t port) {
static uint8_t txbuf[3] = {0};
static uint8_t rxbuf[3] = {0};
static GFXINLINE gU16 read_value(GMouse* m, gU16 port) {
static gU8 txbuf[3] = {0};
static gU8 rxbuf[3] = {0};
(void) m;
txbuf[0] = port;
spiExchange(&SPID1, 3, txbuf, rxbuf);
return ((uint16_t)rxbuf[1] << 5) | (rxbuf[2] >> 3);
return ((gU16)rxbuf[1] << 5) | (rxbuf[2] >> 3);
}
#endif /* _GINPUT_LLD_MOUSE_BOARD_H */

8
demos/games/tetris/Example_Makefiles/stm32f4/gmouse_lld_ADS7843_board.h.old
View file

@ -57,10 +57,10 @@ static GFXINLINE void release_bus(void) {
spiReleaseBus(&SPID1);
}
static GFXINLINE uint16_t read_value(uint16_t port) {
static uint8_t txbuf[3] = {0};
static uint8_t rxbuf[3] = {0};
uint16_t ret;
static GFXINLINE gU16 read_value(gU16 port) {
static gU8 txbuf[3] = {0};
static gU8 rxbuf[3] = {0};
gU16 ret;
txbuf[0] = port;

12
demos/games/tetris/Example_Makefiles/stm32f4_chibios_3.x/board_SSD1289.h
View file

@ -18,8 +18,8 @@
// For a multiple display configuration we would put all this in a structure and then
// set g->board to that structure.
#define GDISP_REG ((volatile uint16_t *) 0x60000000)[0] /* RS = 0 */
#define GDISP_RAM ((volatile uint16_t *) 0x60020000)[0] /* RS = 1 */
#define GDISP_REG ((volatile gU16 *) 0x60000000)[0] /* RS = 0 */
#define GDISP_RAM ((volatile gU16 *) 0x60020000)[0] /* RS = 1 */
#define GDISP_DMA_STREAM STM32_DMA2_STREAM6
#define FSMC_BANK 0
@ -114,7 +114,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
(void) state;
}
static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
pwmEnableChannel(&PWMD3, 2, percent);
}
@ -127,12 +127,12 @@ static GFXINLINE void release_bus(GDisplay *g) {
(void) g;
}
static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
static GFXINLINE void write_index(GDisplay *g, gU16 index) {
(void) g;
GDISP_REG = index;
}
static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
static GFXINLINE void write_data(GDisplay *g, gU16 data) {
(void) g;
GDISP_RAM = data;
}
@ -147,7 +147,7 @@ static GFXINLINE void setwritemode(GDisplay *g) {
FSMC_Bank1->BTCR[FSMC_BANK+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0; /* FSMC timing */
}
static GFXINLINE uint16_t read_data(GDisplay *g) {
static GFXINLINE gU16 read_data(GDisplay *g) {
(void) g;
return GDISP_RAM;
}

8
demos/games/tetris/Example_Makefiles/stm32f4_chibios_3.x/ginput_lld_mouse_board.h
View file

@ -43,11 +43,11 @@ static GFXINLINE void release_bus(void)
spiReleaseBus(&SPID1);
}
static GFXINLINE uint16_t read_value(uint16_t port)
static GFXINLINE gU16 read_value(gU16 port)
{
static uint8_t txbuf[3] = {0};
static uint8_t rxbuf[3] = {0};
uint16_t ret;
static gU8 txbuf[3] = {0};
static gU8 rxbuf[3] = {0};
gU16 ret;
txbuf[0] = port;

8
demos/games/tetris/Example_Makefiles/stm32f4_chibios_3.x/gmouse_lld_ADS7843_board.h
View file

@ -57,10 +57,10 @@ static GFXINLINE void release_bus(void) {
spiReleaseBus(&SPID1);
}
static GFXINLINE uint16_t read_value(uint16_t port) {
static uint8_t txbuf[3] = {0};
static uint8_t rxbuf[3] = {0};
uint16_t ret;
static GFXINLINE gU16 read_value(gU16 port) {
static gU8 txbuf[3] = {0};
static gU8 rxbuf[3] = {0};
gU16 ret;
txbuf[0] = port;

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