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This commit is contained in:
Joel Bodenmann 2013-11-10 22:40:20 +01:00
parent 16c021e5b3
commit 83482a3b8a
6 changed files with 660 additions and 0 deletions
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168
boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h Normal file
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/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.org/license.html
*/
#ifndef _GDISP_LLD_BOARD_H
#define _GDISP_LLD_BOARD_H
// For a multiple display configuration we would put all this in a structure and then
// set g->board to that structure.
/* Using FSMC A19 (PE3) as DC */
#define GDISP_REG (*((volatile uint16_t *) 0x60000000)) /* DC = 0 */
#define GDISP_RAM (*((volatile uint16_t *) 0x60100000)) /* DC = 1 */
#define GDISP_DMA_STREAM STM32_DMA2_STREAM6
#define SET_RST palSetPad(GPIOD, 3);
#define CLR_RST palClearPad(GPIOD, 3);
/*
* PWM configuration structure. We use timer 4 channel 2 (orange LED on board).
* The reason for so high clock is that with any lower, onboard coil is squeaking.
* The major disadvantage of this clock is a lack of linearity between PWM duty
* cycle width and brightness. In fact only with low preset one sees any change
* (eg. duty cycle between 1-20). Feel free to adjust this, maybe only my board
* behaves like this. According to the G5126 datesheet (backlight LED driver)
* the PWM frequency should be somewhere between 200 Hz to 200 kHz.
*/
static const PWMConfig pwmcfg = {
1000000, /* 1 MHz PWM clock frequency. */
100, /* PWM period is 100 cycles. */
NULL,
{
{PWM_OUTPUT_ACTIVE_HIGH, NULL},
{PWM_OUTPUT_ACTIVE_HIGH, NULL},
{PWM_OUTPUT_ACTIVE_HIGH, NULL},
{PWM_OUTPUT_ACTIVE_HIGH, NULL}
},
0
};
static inline void init_board(GDisplay *g) {
// As we are not using multiple displays we set g->board to NULL as we don't use it.
g->board = 0;
switch(g->controllerdisplay) {
case 0: // Set up for Display 0
#if defined(STM32F4XX) || defined(STM32F2XX)
/* STM32F4 FSMC init */
rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0);
#if defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM)
if (dmaStreamAllocate(GDISP_DMA_STREAM, 0, NULL, NULL))
gfxExit();
dmaStreamSetMemory0(GDISP_DMA_STREAM, &GDISP_RAM);
dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
#endif
#else
#error "FSMC not implemented for this device"
#endif
/* Group pins */
IOBus busD = {GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) | (1 << 7) | (1 << 8) |
(1 << 9) | (1 << 10) | (1 << 14) | (1 << 15), 0};
IOBus busE = {GPIOE, (1 << 3) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) |
(1 << 13) | (1 << 14) | (1 << 15), 0};
/* FSMC is an alternate function 12 (AF12) */
palSetBusMode(&busD, PAL_MODE_ALTERNATE(12));
palSetBusMode(&busE, PAL_MODE_ALTERNATE(12));
/* FSMC timing register configuration */
FSMC_Bank1->BTCR[0 + 1] = (FSMC_BTR1_ADDSET_2 | FSMC_BTR1_ADDSET_1) \
| (FSMC_BTR1_DATAST_2 | FSMC_BTR1_DATAST_1) \
| FSMC_BTR1_BUSTURN_0;
/* Bank1 NOR/PSRAM control register configuration
* Write enable, memory databus width set to 16 bit, memory bank enable */
FSMC_Bank1->BTCR[0] = FSMC_BCR1_WREN | FSMC_BCR1_MWID_0 | FSMC_BCR1_MBKEN;
/* Display backlight control */
/* TIM4 is an alternate function 2 (AF2) */
pwmStart(&PWMD4, &pwmcfg);
palSetPadMode(GPIOD, 13, PAL_MODE_ALTERNATE(2));
pwmEnableChannel(&PWMD4, 1, 100);
break;
}
}
static inline void post_init_board(GDisplay *g) {
(void) g;
}
static inline void setpin_reset(GDisplay *g, bool_t state) {
(void) g;
if (state) {
CLR_RST;
} else {
SET_RST;
}
}
static inline void set_backlight(GDisplay *g, uint8_t percent) {
(void) g;
pwmEnableChannel(&PWMD4, 1, percent);
}
static inline void acquire_bus(GDisplay *g) {
(void) g;
}
static inline void release_bus(GDisplay *g) {
(void) g;
}
static inline void write_index(GDisplay *g, uint16_t index) {
(void) g;
GDISP_REG = index;
}
static inline void write_data(GDisplay *g, uint16_t data) {
(void) g;
GDISP_RAM = data;
}
static inline void setreadmode(GDisplay *g) {
(void) g;
}
static inline void setwritemode(GDisplay *g) {
(void) g;
}
static inline uint16_t read_data(GDisplay *g) {
(void) g;
return GDISP_RAM;
}
#if defined(GDISP_USE_DMA)
static inline void dma_with_noinc(GDisplay *g, color_t *buffer, int area) {
(void) g;
dmaStreamSetPeripheral(GDISP_DMA_STREAM, buffer);
dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
for (; area > 0; area -= 65535) {
dmaStreamSetTransactionSize(GDISP_DMA_STREAM, area > 65535 ? 65535 : area);
dmaStreamEnable(GDISP_DMA_STREAM);
dmaWaitCompletion(GDISP_DMA_STREAM);
}
}
static inline void dma_with_inc(GDisplay *g, color_t *buffer, int area) {
(void) g;
dmaStreamSetPeripheral(GDISP_DMA_STREAM, buffer);
dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PINC | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
for (; area > 0; area -= 65535) {
dmaStreamSetTransactionSize(GDISP_DMA_STREAM, area > 65535 ? 65535 : area);
dmaStreamEnable(GDISP_DMA_STREAM);
dmaWaitCompletion(GDISP_DMA_STREAM);
}
}
#endif
#endif /* _GDISP_LLD_BOARD_H */

88
boards/base/Embest-STM32-DMSTF4BB/ginput_lld_mouse_board.h Normal file
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/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.org/license.html
*/
#ifndef _GINPUT_LLD_MOUSE_BOARD_H
#define _GINPUT_LLD_MOUSE_BOARD_H
static const I2CConfig i2ccfg = {
OPMODE_I2C,
400000,
FAST_DUTY_CYCLE_2,
};
static void init_board(void)
{
palSetPadMode(GPIOC, 13, PAL_MODE_INPUT | PAL_STM32_PUDR_FLOATING); /* TP IRQ */
palSetPadMode(GPIOB, 8, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN); /* SCL */
palSetPadMode(GPIOB, 9, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN); /* SDA */
i2cStart(&I2CD1, &i2ccfg);
}
static inline bool_t getpin_irq(void)
{
return (!(palReadPad(GPIOC, 13)));
}
static void write_reg(uint8_t reg, uint8_t n, uint16_t val)
{
uint8_t txbuf[3];
i2cAcquireBus(&I2CD1);
txbuf[0] = reg;
if (n == 1) {
txbuf[1] = val;
i2cMasterTransmitTimeout(&I2CD1, STMPE811_ADDR, txbuf, 2, NULL, 0, MS2ST(STMPE811_TIMEOUT));
} else if (n == 2) {
txbuf[1] = ((val & 0xFF00) >> 8);
txbuf[2] = (val & 0x00FF);
i2cMasterTransmitTimeout(&I2CD1, STMPE811_ADDR, txbuf, 3, NULL, 0, MS2ST(STMPE811_TIMEOUT));
}
i2cReleaseBus(&I2CD1);
}
static uint16_t read_reg(uint8_t reg, uint8_t n)
{
uint8_t txbuf[1], rxbuf[2];
uint16_t ret;
rxbuf[0] = 0;
rxbuf[1] = 0;
i2cAcquireBus(&I2CD1);
txbuf[0] = reg;
i2cMasterTransmitTimeout(&I2CD1, STMPE811_ADDR, txbuf, 1, rxbuf, n, MS2ST(STMPE811_TIMEOUT));
if (n == 1) {
ret = rxbuf[0];
} else if (n == 2) {
ret = ((rxbuf[0] << 8) | (rxbuf[1] & 0xFF));
}
i2cReleaseBus(&I2CD1);
return ret;
}
static void read_reg_n(uint8_t reg, uint8_t n, uint8_t *rxbuf)
{
uint8_t txbuf[1];
i2cAcquireBus(&I2CD1);
txbuf[0] = reg;
i2cMasterTransmitTimeout(&I2CD1, STMPE811_ADDR, txbuf, 1, rxbuf, n, MS2ST(STMPE811_TIMEOUT));
i2cReleaseBus(&I2CD1);
}
#endif /* _GINPUT_LLD_MOUSE_BOARD_H */

124
boards/base/FireBull-STM32F103-FB/board_SSD1289.h Normal file
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/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.org/license.html
*/
#ifndef _GDISP_LLD_BOARD_H
#define _GDISP_LLD_BOARD_H
// For a multiple display configuration we would put all this in a structure and then
// set g->board to that structure.
#define SET_CS palSetPad(GPIOD, 12);
#define CLR_CS palClearPad(GPIOD, 12);
#define SET_RS palSetPad(GPIOD, 13);
#define CLR_RS palClearPad(GPIOD, 13);
#define SET_WR palSetPad(GPIOD, 14);
#define CLR_WR palClearPad(GPIOD, 14);
#define SET_RD palSetPad(GPIOD, 15);
#define CLR_RD palClearPad(GPIOD, 15);
static inline void init_board(GDisplay *g)
{
// As we are not using multiple displays we set g->board to NULL as we don't use it.
g->board = 0;
switch(g->controllerdisplay) {
case 0: // Set up for Display 0
palSetGroupMode(GPIOE, PAL_WHOLE_PORT, 0, PAL_MODE_OUTPUT_PUSHPULL);
palSetPadMode(GPIOD, 12, PAL_MODE_OUTPUT_PUSHPULL);
palSetPadMode(GPIOD, 13, PAL_MODE_OUTPUT_PUSHPULL);
palSetPadMode(GPIOD, 14, PAL_MODE_OUTPUT_PUSHPULL);
palSetPadMode(GPIOD, 15, PAL_MODE_OUTPUT_PUSHPULL);
// Configure the pins to a well know state
SET_RS;
SET_RD;
SET_WR;
CLR_CS;
break;
}
}
static inline void post_init_board(GDisplay *g)
{
(void) g;
}
static inline void setpin_reset(GDisplay *g, bool_t state)
{
(void) g;
(void) state;
/* Nothing to do here - reset pin tied to Vcc */
}
static inline void set_backlight(GDisplay *g, uint8_t percent)
{
(void) g;
(void) percent;
/* Nothing to do here - Backlight always on */
}
static inline void acquire_bus(GDisplay *g)
{
(void) g;
}
static inline void release_bus(GDisplay *g)
{
(void) g;
}
static inline void write_index(GDisplay *g, uint16_t index)
{
(void) g;
palWritePort(GPIOE, index);
CLR_RS;
CLR_WR;
SET_WR;
SET_RS;
}
static inline void write_data(GDisplay *g, uint16_t data)
{
(void) g;
palWritePort(GPIOE, data);
CLR_WR;
SET_WR;
}
static inline void setreadmode(GDisplay *g)
{
(void) g;
// change pin mode to digital input
palSetGroupMode(GPIOE, PAL_WHOLE_PORT, 0, PAL_MODE_INPUT);
CLR_RD;
}
static inline void setwritemode(GDisplay *g)
{
(void) g;
// change pin mode back to digital output
SET_RD;
palSetGroupMode(GPIOE, PAL_WHOLE_PORT, 0, PAL_MODE_OUTPUT_PUSHPULL);
}
static inline uint16_t read_data(GDisplay *g) {
return palReadPort(GPIOE);
}
#if defined(GDISP_USE_DMA)
#error "GDISP - SSD1289: The GPIO interface does not support DMA"
#endif
#endif /* _GDISP_LLD_BOARD_H */

56
boards/base/FireBull-STM32F103-FB/ginput_lld_mouse_board.h Normal file
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/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.org/license.html
*/
#ifndef _GINPUT_LLD_MOUSE_BOARD_H
#define _GINPUT_LLD_MOUSE_BOARD_H
static const SPIConfig spicfg = {
NULL,
GPIOC,
6,
/* SPI_CR1_BR_2 |*/ SPI_CR1_BR_1 | SPI_CR1_BR_0,
};
static inline void init_board(void)
{
spiStart(&SPID1, &spicfg);
}
static inline bool_t getpin_pressed(void)
{
return (!palReadPad(GPIOC, 4));
}
static inline void aquire_bus(void)
{
spiAcquireBus(&SPID1);
palClearPad(GPIOC, 6);
}
static inline void release_bus(void)
{
palSetPad(GPIOC, 6);
spiReleaseBus(&SPID1);
}
static inline uint16_t read_value(uint16_t port)
{
static uint8_t txbuf[3] = {0};
static uint8_t rxbuf[3] = {0};
uint16_t ret;
txbuf[0] = port;
spiExchange(&SPID1, 3, txbuf, rxbuf);
ret = (rxbuf[1] << 5) | (rxbuf[2] >> 3);
return ret;
}
#endif /* _GINPUT_LLD_MOUSE_BOARD_H */

113
boards/base/Marlin/board_RA8875.h Normal file
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/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.org/license.html
*/
/**
* @file drivers/gdisp/RA8875/board_RA8875_marlin.h
* @brief GDISP Graphic Driver subsystem board interface for the RA8875 display.
*/
#ifndef _BOARD_RA8875_H
#define _BOARD_RA8875_H
// For a multiple display configuration we would put all this in a structure and then
// set g->board to that structure.
#define GDISP_RAM (*((volatile uint16_t *) 0x68000000)) /* RS = 0 */
#define GDISP_REG (*((volatile uint16_t *) 0x68020000)) /* RS = 1 */
#define FSMC_BANK 4
static inline void init_board(GDisplay *g) {
// As we are not using multiple displays we set g->board to NULL as we don't use it.
g->board = 0;
switch(g->controllerdisplay) {
// setup for display 0
case 0: {
// enable the FSMC peripheral
rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0);
// setup the pin modes for FSMC
IOBus busD = {GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) | (1 << 8) |
(1 << 9) | (1 << 10) | (1 << 11) | (1 << 14) | (1 << 15), 0};
IOBus busE = {GPIOE, (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) |
(1 << 13) | (1 << 14) | (1 << 15), 0};
IOBus busG = {GPIOG, (1 << 10), 0};
palSetBusMode(&busD, PAL_MODE_ALTERNATE(12));
palSetBusMode(&busE, PAL_MODE_ALTERNATE(12));
palSetBusMode(&busG, PAL_MODE_ALTERNATE(12));
// FSMC timing
FSMC_Bank1->BTCR[FSMC_BANK+1] = (FSMC_BTR1_ADDSET_1 | FSMC_BTR1_ADDSET_3) \
| (FSMC_BTR1_DATAST_1 | FSMC_BTR1_DATAST_3) \
| (FSMC_BTR1_BUSTURN_1 | FSMC_BTR1_BUSTURN_3) ;
// Bank1 NOR/SRAM control register configuration
// This is actually not needed as already set by default after reset
FSMC_Bank1->BTCR[FSMC_BANK] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
break;
}
// marlin does not have any secondary display so far
default:
break;
}
}
static inline void post_init_board(GDisplay *g) {
(void) g;
// FSMC delay reduced as the controller now runs at full speed
FSMC_Bank1->BTCR[2+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0 ;
FSMC_Bank1->BTCR[2] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
}
static inline void setpin_reset(GDisplay *g, bool_t state) {
(void) g;
(void) state;
}
static inline void acquire_bus(GDisplay *g) {
(void) g;
}
static inline void release_bus(GDisplay *g) {
(void) g;
}
static inline void write_index(GDisplay *g, uint16_t index) {
(void) g;
GDISP_REG = index;
}
static inline void write_data(GDisplay *g, uint16_t data) {
(void) g;
GDISP_RAM = data;
}
static inline void setreadmode(GDisplay *g) {
(void) g;
}
static inline void setwritemode(GDisplay *g) {
(void) g;
}
static inline uint16_t read_data(GDisplay *g) {
(void) g;
return GDISP_RAM;
}
#endif /* _BOARD_RA8875_H */

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boards/base/Marlin/ginput_lld_mouse_board.h Normal file
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/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.org/license.html
*/
/**
* @file drivers/ginput/touch/FT5x06/ginput_lld_mouse_board_marlin.h
* @brief GINPUT Touch low level driver source for the FT5x06.
*
* @defgroup Mouse Mouse
* @ingroup GINPUT
* @{
*/
#ifndef _GINPUT_LLD_MOUSE_BOARD_H
#define _GINPUT_LLD_MOUSE_BOARD_H
/* I2C interface #2 - Touchscreen controller */
static const I2CConfig i2ccfg2 = {
OPMODE_I2C,
400000,
FAST_DUTY_CYCLE_2,
};
/**
* @brief Initialise the board for the touch.
*
* @notapi
*/
static void init_board(void) {
}
/**
* @brief Write a value into a certain register
*
* @param[in] reg The register address
* @param[in] n The amount of bytes (one or two)
* @param[in] val The value
*
* @notapi
*/
static void write_reg(uint8_t reg, uint8_t n, uint16_t val) {
uint8_t txbuf[3];
i2cAcquireBus(&I2CD2);
txbuf[0] = reg;
if (n == 1) {
txbuf[1] = val;
i2cMasterTransmitTimeout(&I2CD2, FT5x06_ADDR, txbuf, 2, NULL, 0, MS2ST(FT5x06_TIMEOUT));
} else if (n == 2) {
txbuf[1] = ((val & 0xFF00) >> 8);
txbuf[2] = (val & 0x00FF);
i2cMasterTransmitTimeout(&I2CD2, FT5x06_ADDR, txbuf, 3, NULL, 0, MS2ST(FT5x06_TIMEOUT));
}
i2cReleaseBus(&I2CD2);
}
/**
* @brief Read the value of a certain register
*
* @param[in] reg The register address
* @param[in] n The amount of bytes (one or two)
*
* @return Data read from device (one byte or two depending on n param)
*
* @notapi
*/
static uint16_t read_reg(uint8_t reg, uint8_t n) {
uint8_t txbuf[1], rxbuf[2];
uint16_t ret;
rxbuf[0] = 0;
rxbuf[1] = 0;
i2cAcquireBus(&I2CD2);
txbuf[0] = reg;
i2cMasterTransmitTimeout(&I2CD2, FT5x06_ADDR, txbuf, 1, rxbuf, n, MS2ST(FT5x06_TIMEOUT));
if (n == 1) {
ret = rxbuf[0];
} else if (n == 2) {
ret = ((rxbuf[0] << 8) | (rxbuf[1] & 0xFF));
}
i2cReleaseBus(&I2CD2);
return ret;
}
static void read_reg_n(uint8_t reg, uint8_t n, uint8_t *rxbuf) {
uint8_t txbuf[1];
i2cAcquireBus(&I2CD2);
txbuf[0] = reg;
i2cMasterTransmitTimeout(&I2CD2, FT5x06_ADDR, txbuf, 1, rxbuf, n, MS2ST(FT5x06_TIMEOUT));
i2cReleaseBus(&I2CD2);
}
#endif /* _GINPUT_LLD_MOUSE_BOARD_H */
/** @} */