Fixes to allow STM32F749-Discovery to work with ChibiOS
This commit is contained in:
inmarket
parent
76ce1dd0e3
commit
864210b764
7 changed files with 551 additions and 355 deletions
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@ -1,4 +1,6 @@
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GFXINC += $(GFXLIB)/boards/base/STM32F746-Discovery
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GFXINC += $(GFXLIB)/boards/base/STM32F746-Discovery \
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$(STMHAL)/Inc
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GFXSRC += $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c \
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$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f7_i2c.c
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@ -17,8 +19,7 @@ ifeq ($(OPT_OS),raw32)
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$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_interrupts.c
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GFXDEFS += GFX_OS_PRE_INIT_FUNCTION=Raw32OSInit GFX_OS_INIT_NO_WARNING=TRUE
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GFXINC += $(CMSIS)/Device/ST/STM32F7xx/Include \
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$(CMSIS)/Include \
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$(STMHAL)/Inc
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$(CMSIS)/Include
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LDSCRIPT = $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746nghx_flash.ld
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endif
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@ -9,8 +9,26 @@
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#define _GDISP_LLD_BOARD_H
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#include "stm32f746g_discovery_sdram.h"
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#include "stm32f7xx_hal_rcc.h"
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#include "stm32f7xx_hal_gpio.h"
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#ifndef GFX_LTDC_USE_DIRECTIO
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#define GFX_LTDC_USE_DIRECTIO TRUE
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#endif
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#ifndef GFX_LTDC_TIMING_SET
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/* Options are:
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* 0 - don't initialise the display VCO and LTDC clocks - something else will do it
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* 1 - uGFX preferred timings (default)
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* 2 - Alternate timings
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*/
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#define GFX_LTDC_TIMING_SET 1
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#endif
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#if GFX_USE_OS_CHIBIOS && !GFX_USE_DIRECTIO
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#include "hal.h"
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#include "ch.h"
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#else
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#include "stm32f7xx_hal_rcc.h"
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#include "stm32f7xx_hal_gpio.h"
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#endif
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#include <string.h>
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#if !GFX_USE_OS_CHIBIOS
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@ -45,207 +63,314 @@ static const ltdcConfig driverCfg = {
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LTDC_UNUSED_LAYER_CONFIG // Foreground layer config
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};
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/* Display timing */
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#define RK043FN48H_FREQUENCY_DIVIDER 5
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static void configureLcdPins(void) {
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#if GFX_USE_OS_CHIBIOS && !GFX_LTDC_USE_DIRECTIO
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palSetPadMode(GPIOI, GPIOI_LCD_R0, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PI15: LCD_R0
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palSetPadMode(GPIOJ, GPIOJ_LCD_R1, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ0 : LCD_R1
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palSetPadMode(GPIOJ, GPIOJ_LCD_R2, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ1 : LCD_R2
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palSetPadMode(GPIOJ, GPIOJ_LCD_R3, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ2 : LCD_R3
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palSetPadMode(GPIOJ, GPIOJ_LCD_R4, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ3 : LCD_R4
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palSetPadMode(GPIOJ, GPIOJ_LCD_R5, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ4 : LCD_R5
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palSetPadMode(GPIOJ, GPIOJ_LCD_R6, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ5 : LCD_R6
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palSetPadMode(GPIOJ, GPIOJ_LCD_R7, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ6 : LCD_R7
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palSetPadMode(GPIOJ, GPIOJ_LCD_G0, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ7 : LCD_G0
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palSetPadMode(GPIOJ, GPIOJ_LCD_G1, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ8 : LCD_G1
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palSetPadMode(GPIOJ, GPIOJ_LCD_G2, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ9 : LCD_G2
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palSetPadMode(GPIOJ, GPIOJ_LCD_G3, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ10: LCD_G3
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palSetPadMode(GPIOJ, GPIOJ_LCD_G4, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ11: LCD_G4
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palSetPadMode(GPIOK, GPIOK_LCD_G5, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PK0 : LCD_G5
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palSetPadMode(GPIOK, GPIOK_LCD_G6, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PK1 : LCD_G6
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palSetPadMode(GPIOK, GPIOK_LCD_G7, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PK2 : LCD_G7
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palSetPadMode(GPIOE, GPIOE_LCD_B0, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PE4 : LCD_B0
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palSetPadMode(GPIOJ, GPIOJ_LCD_B1, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ13: LCD_B1
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palSetPadMode(GPIOJ, GPIOJ_LCD_B2, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ14: LCD_B2
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palSetPadMode(GPIOJ, GPIOJ_LCD_B3, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ15: LCD_B3
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palSetPadMode(GPIOG, GPIOG_LCD_B4, PAL_MODE_ALTERNATE(9) | PAL_STM32_OSPEED_HIGHEST); // PG12: LCD_B4
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palSetPadMode(GPIOK, GPIOK_LCD_B5, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PK4 : LCD_B5
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palSetPadMode(GPIOK, GPIOK_LCD_B6, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PK5 : LCD_B6
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palSetPadMode(GPIOK, GPIOK_LCD_B7, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PK6 : LCD_B7
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palSetPadMode(GPIOK, GPIOK_LCD_DE, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PK7 : LCD_DE
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palSetPadMode(GPIOI, GPIOI_LCD_VSYNC, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PI9 : LCD_VSYNC
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palSetPadMode(GPIOI, GPIOI_LCD_HSYNC, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PI10: LCD_HSYNC
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palSetPadMode(GPIOI, GPIOI_LCD_INT, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PI13: LCD_INT
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palSetPadMode(GPIOI, GPIOI_LCD_CLK, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PI14: LCD_CLK
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palSetPadMode(GPIOI, GPIOI_LCD_DISP, PAL_MODE_OUTPUT_PUSHPULL | PAL_STM32_OSPEED_HIGHEST); // PI12: LCD_DISP_PIN
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palSetPadMode(GPIOK, GPIOK_LCD_BL_CTRL, PAL_MODE_OUTPUT_PUSHPULL | PAL_STM32_OSPEED_HIGHEST); // PK3 : LCD_BL_CTRL
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#else
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//-------------------------------------------
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// Initialise port PE
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN;
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GPIOE->MODER |= (
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GPIO_MODER_MODER4_1 // PE4: LCD_B0 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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);
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GPIOE->MODER &=~ (
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GPIO_MODER_MODER4_0
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);
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GPIOE->OTYPER &=~ (
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GPIO_OTYPER_OT_4
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);
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GPIOE->OSPEEDR |= (
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GPIO_OSPEEDER_OSPEEDR4_0 | GPIO_OSPEEDER_OSPEEDR4_1
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);
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GPIOE->PUPDR &=~ (
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GPIO_PUPDR_PUPDR4_0 | GPIO_PUPDR_PUPDR4_1
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);
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GPIOE->AFRL |= (
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(14U << 4*4)
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);
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static void configureLcdPins(void)
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{
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// Enable GPIOs clock
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN; // GPIOE
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOGEN; // GPIOG
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOIEN; // GPIOI
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOJEN; // GPIOJ
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOKEN; // GPIOK
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//-------------------------------------------
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// Initialise port PG
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOGEN;
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GPIOG->MODER |= (
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GPIO_MODER_MODER12_1 // PG12: LCD_B4 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(9)
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);
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GPIOG->MODER &=~ (
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GPIO_MODER_MODER12_0
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);
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GPIOG->OTYPER &=~ (
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GPIO_OTYPER_OT_12
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);
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GPIOG->OSPEEDR |= (
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GPIO_OSPEEDER_OSPEEDR12_0 | GPIO_OSPEEDER_OSPEEDR12_1
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);
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GPIOG->PUPDR &=~ (
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GPIO_PUPDR_PUPDR12_0 | GPIO_PUPDR_PUPDR12_1
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);
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GPIOG->AFRH |= (
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( 9U << 4*(12-8))
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);
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//-------------------------------------------
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// Initialise port PI
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOIEN;
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GPIOI->MODER |= (
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GPIO_MODER_MODER9_1 // PI9: LCD_VSYNC - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER10_1 // PI10: LCD_HSYNC - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER12_0 // PI12: LCD_DISP_PIN - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_OUTPUT_PUSHPULL
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| GPIO_MODER_MODER13_1 // PI13: LCD_INT - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER14_1 // PI14: LCD_CLK - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER15_1 // PI15: LCD_R0 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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);
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GPIOI->MODER &=~ (
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GPIO_MODER_MODER9_0
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| GPIO_MODER_MODER10_0
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| GPIO_MODER_MODER12_1
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| GPIO_MODER_MODER13_0
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| GPIO_MODER_MODER14_0
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| GPIO_MODER_MODER15_0
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);
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GPIOI->OTYPER &=~ (
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GPIO_OTYPER_OT_9
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| GPIO_OTYPER_OT_10
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| GPIO_OTYPER_OT_12
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| GPIO_OTYPER_OT_13
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| GPIO_OTYPER_OT_14
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| GPIO_OTYPER_OT_15
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);
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GPIOI->OSPEEDR |= (
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GPIO_OSPEEDER_OSPEEDR9_0 | GPIO_OSPEEDER_OSPEEDR9_1
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| GPIO_OSPEEDER_OSPEEDR10_0 | GPIO_OSPEEDER_OSPEEDR10_1
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| GPIO_OSPEEDER_OSPEEDR12_0 | GPIO_OSPEEDER_OSPEEDR12_1
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| GPIO_OSPEEDER_OSPEEDR13_0 | GPIO_OSPEEDER_OSPEEDR13_1
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| GPIO_OSPEEDER_OSPEEDR14_0 | GPIO_OSPEEDER_OSPEEDR14_1
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| GPIO_OSPEEDER_OSPEEDR15_0 | GPIO_OSPEEDER_OSPEEDR15_1
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);
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GPIOI->PUPDR &=~ (
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GPIO_PUPDR_PUPDR9_0 | GPIO_PUPDR_PUPDR9_1
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| GPIO_PUPDR_PUPDR10_0 | GPIO_PUPDR_PUPDR10_1
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| GPIO_PUPDR_PUPDR12_0 | GPIO_PUPDR_PUPDR12_1
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| GPIO_PUPDR_PUPDR13_0 | GPIO_PUPDR_PUPDR13_1
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| GPIO_PUPDR_PUPDR14_0 | GPIO_PUPDR_PUPDR14_1
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| GPIO_PUPDR_PUPDR15_0 | GPIO_PUPDR_PUPDR15_1
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);
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GPIOI->AFRH |= (
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(14U << 4*(9-8))
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| (14U << 4*(10-8))
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| ( 0U << 4*(12-8))
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| (14U << 4*(13-8))
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| (14U << 4*(14-8))
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| (14U << 4*(15-8))
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);
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// PI15: LCD_R0
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GPIOI->MODER |= GPIO_MODER_MODER15_1;
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GPIOI->OTYPER &=~ GPIO_OTYPER_OT_15;
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GPIOI->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR15_0 | GPIO_OSPEEDER_OSPEEDR15_1;
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GPIOI->AFRH |= ((uint32_t)0xE << 4*7);
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//-------------------------------------------
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// Initialise port PJ
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// PJ0: LCD_R1
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GPIOJ->MODER |= GPIO_MODER_MODER0_1;
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GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_0;
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GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR0_0 | GPIO_OSPEEDER_OSPEEDR0_1;
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GPIOJ->AFRL |= ((uint32_t)0xE << 4*0);
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOJEN;
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GPIOJ->MODER |= (
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GPIO_MODER_MODER0_1 // PJ0: LCD_R1 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER1_1 // PJ1: LCD_R2 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER2_1 // PJ2: LCD_R3 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER3_1 // PJ3: LCD_R4 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER4_1 // PJ4: LCD_R5 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER5_1 // PJ5: LCD_R6 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER6_1 // PJ6: LCD_R7 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER7_1 // PJ7: LCD_G0 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER8_1 // PJ8: LCD_G1 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER9_1 // PJ9: LCD_G2 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER10_1 // PJ10: LCD_G3 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER11_1 // PJ11: LCD_G4 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER13_1 // PJ13: LCD_B1 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER14_1 // PJ14: LCD_B2 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER15_1 // PJ15: LCD_B3 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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);
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GPIOJ->MODER &=~ (
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GPIO_MODER_MODER0_0
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| GPIO_MODER_MODER1_0
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| GPIO_MODER_MODER2_0
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| GPIO_MODER_MODER3_0
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| GPIO_MODER_MODER4_0
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| GPIO_MODER_MODER5_0
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| GPIO_MODER_MODER6_0
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| GPIO_MODER_MODER7_0
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| GPIO_MODER_MODER8_0
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| GPIO_MODER_MODER9_0
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| GPIO_MODER_MODER10_0
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| GPIO_MODER_MODER11_0
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| GPIO_MODER_MODER13_0
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| GPIO_MODER_MODER14_0
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| GPIO_MODER_MODER15_0
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);
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GPIOJ->OTYPER &=~ (
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GPIO_OTYPER_OT_0
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| GPIO_OTYPER_OT_1
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| GPIO_OTYPER_OT_2
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| GPIO_OTYPER_OT_3
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| GPIO_OTYPER_OT_4
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| GPIO_OTYPER_OT_5
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| GPIO_OTYPER_OT_6
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| GPIO_OTYPER_OT_7
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| GPIO_OTYPER_OT_8
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| GPIO_OTYPER_OT_9
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| GPIO_OTYPER_OT_10
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| GPIO_OTYPER_OT_11
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| GPIO_OTYPER_OT_13
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| GPIO_OTYPER_OT_14
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| GPIO_OTYPER_OT_15
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);
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GPIOJ->OSPEEDR |= (
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GPIO_OSPEEDER_OSPEEDR0_0 | GPIO_OSPEEDER_OSPEEDR0_1
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| GPIO_OSPEEDER_OSPEEDR1_0 | GPIO_OSPEEDER_OSPEEDR1_1
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| GPIO_OSPEEDER_OSPEEDR2_0 | GPIO_OSPEEDER_OSPEEDR2_1
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| GPIO_OSPEEDER_OSPEEDR3_0 | GPIO_OSPEEDER_OSPEEDR3_1
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| GPIO_OSPEEDER_OSPEEDR4_0 | GPIO_OSPEEDER_OSPEEDR4_1
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| GPIO_OSPEEDER_OSPEEDR5_0 | GPIO_OSPEEDER_OSPEEDR5_1
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| GPIO_OSPEEDER_OSPEEDR6_0 | GPIO_OSPEEDER_OSPEEDR6_1
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| GPIO_OSPEEDER_OSPEEDR7_0 | GPIO_OSPEEDER_OSPEEDR7_1
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| GPIO_OSPEEDER_OSPEEDR8_0 | GPIO_OSPEEDER_OSPEEDR8_1
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| GPIO_OSPEEDER_OSPEEDR9_0 | GPIO_OSPEEDER_OSPEEDR9_1
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| GPIO_OSPEEDER_OSPEEDR10_0 | GPIO_OSPEEDER_OSPEEDR10_1
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| GPIO_OSPEEDER_OSPEEDR11_0 | GPIO_OSPEEDER_OSPEEDR11_1
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| GPIO_OSPEEDER_OSPEEDR13_0 | GPIO_OSPEEDER_OSPEEDR13_1
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| GPIO_OSPEEDER_OSPEEDR14_0 | GPIO_OSPEEDER_OSPEEDR14_1
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| GPIO_OSPEEDER_OSPEEDR15_0 | GPIO_OSPEEDER_OSPEEDR15_1
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);
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GPIOJ->PUPDR &=~ (
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GPIO_PUPDR_PUPDR0_0 | GPIO_PUPDR_PUPDR0_1
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| GPIO_PUPDR_PUPDR1_0 | GPIO_PUPDR_PUPDR1_1
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| GPIO_PUPDR_PUPDR2_0 | GPIO_PUPDR_PUPDR2_1
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| GPIO_PUPDR_PUPDR3_0 | GPIO_PUPDR_PUPDR3_1
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| GPIO_PUPDR_PUPDR4_0 | GPIO_PUPDR_PUPDR4_1
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| GPIO_PUPDR_PUPDR5_0 | GPIO_PUPDR_PUPDR5_1
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| GPIO_PUPDR_PUPDR6_0 | GPIO_PUPDR_PUPDR6_1
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| GPIO_PUPDR_PUPDR7_0 | GPIO_PUPDR_PUPDR7_1
|
||||
| GPIO_PUPDR_PUPDR8_0 | GPIO_PUPDR_PUPDR8_1
|
||||
| GPIO_PUPDR_PUPDR9_0 | GPIO_PUPDR_PUPDR9_1
|
||||
| GPIO_PUPDR_PUPDR10_0 | GPIO_PUPDR_PUPDR10_1
|
||||
| GPIO_PUPDR_PUPDR11_0 | GPIO_PUPDR_PUPDR11_1
|
||||
| GPIO_PUPDR_PUPDR13_0 | GPIO_PUPDR_PUPDR13_1
|
||||
| GPIO_PUPDR_PUPDR14_0 | GPIO_PUPDR_PUPDR14_1
|
||||
| GPIO_PUPDR_PUPDR15_0 | GPIO_PUPDR_PUPDR15_1
|
||||
);
|
||||
GPIOJ->AFRL |= (
|
||||
(14U << 4*0)
|
||||
| (14U << 4*1)
|
||||
| (14U << 4*2)
|
||||
| (14U << 4*3)
|
||||
| (14U << 4*4)
|
||||
| (14U << 4*5)
|
||||
| (14U << 4*6)
|
||||
| (14U << 4*7)
|
||||
);
|
||||
GPIOJ->AFRH |= (
|
||||
(14U << 4*(8-8))
|
||||
| (14U << 4*(9-8))
|
||||
| (14U << 4*(10-8))
|
||||
| (14U << 4*(11-8))
|
||||
| (14U << 4*(13-8))
|
||||
| (14U << 4*(14-8))
|
||||
| (14U << 4*(15-8))
|
||||
);
|
||||
|
||||
// PJ1: LCD_R2
|
||||
GPIOJ->MODER |= GPIO_MODER_MODER1_1;
|
||||
GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_1;
|
||||
GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR1_0 | GPIO_OSPEEDER_OSPEEDR1_1;
|
||||
GPIOJ->AFRL |= ((uint32_t)0xE << 4*1);
|
||||
//-------------------------------------------
|
||||
// Initialise port PK
|
||||
|
||||
// PJ2: LCD_R3
|
||||
GPIOJ->MODER |= GPIO_MODER_MODER2_1;
|
||||
GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_2;
|
||||
GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR2_0 | GPIO_OSPEEDER_OSPEEDR2_1;
|
||||
GPIOJ->AFRL |= ((uint32_t)0xE << 4*2);
|
||||
|
||||
// PJ3: LCD_R4
|
||||
GPIOJ->MODER |= GPIO_MODER_MODER3_1;
|
||||
GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_3;
|
||||
GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR3_0 | GPIO_OSPEEDER_OSPEEDR3_1;
|
||||
GPIOJ->AFRL |= ((uint32_t)0xE << 4*3);
|
||||
|
||||
// PJ4: LCD_R5
|
||||
GPIOJ->MODER |= GPIO_MODER_MODER4_1;
|
||||
GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_4;
|
||||
GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR4_0 | GPIO_OSPEEDER_OSPEEDR4_1;
|
||||
GPIOJ->AFRL |= ((uint32_t)0xE << 4*4);
|
||||
|
||||
// PJ5: LCD_R6
|
||||
GPIOJ->MODER |= GPIO_MODER_MODER5_1;
|
||||
GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_5;
|
||||
GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR5_0 | GPIO_OSPEEDER_OSPEEDR5_1;
|
||||
GPIOJ->AFRL |= ((uint32_t)0xE << 4*5);
|
||||
|
||||
// PJ6: LCD_R7
|
||||
GPIOJ->MODER |= GPIO_MODER_MODER6_1;
|
||||
GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_6;
|
||||
GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR6_0 | GPIO_OSPEEDER_OSPEEDR6_1;
|
||||
GPIOJ->AFRL |= ((uint32_t)0xE << 4*6);
|
||||
|
||||
// PJ7: LCD_G0
|
||||
GPIOJ->MODER |= GPIO_MODER_MODER7_1;
|
||||
GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_7;
|
||||
GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR7_0 | GPIO_OSPEEDER_OSPEEDR7_1;
|
||||
GPIOJ->AFRL |= ((uint32_t)0xE << 4*7);
|
||||
|
||||
// PJ8: LCD_G1
|
||||
GPIOJ->MODER |= GPIO_MODER_MODER8_1;
|
||||
GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_8;
|
||||
GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR8_0 | GPIO_OSPEEDER_OSPEEDR8_1;
|
||||
GPIOJ->AFRH |= ((uint32_t)0xE << 4*0);
|
||||
|
||||
// PJ9: LCD_G2
|
||||
GPIOJ->MODER |= GPIO_MODER_MODER9_1;
|
||||
GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_9;
|
||||
GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR9_0 | GPIO_OSPEEDER_OSPEEDR9_1;
|
||||
GPIOJ->AFRH |= ((uint32_t)0xE << 4*1);
|
||||
|
||||
// PJ10: LCD_G3
|
||||
GPIOJ->MODER |= GPIO_MODER_MODER10_1;
|
||||
GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_10;
|
||||
GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR10_0 | GPIO_OSPEEDER_OSPEEDR10_1;
|
||||
GPIOJ->AFRH |= ((uint32_t)0xE << 4*2);
|
||||
|
||||
// PJ11: LCD_G4
|
||||
GPIOJ->MODER |= GPIO_MODER_MODER11_1;
|
||||
GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_11;
|
||||
GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR11_0 | GPIO_OSPEEDER_OSPEEDR11_1;
|
||||
GPIOJ->AFRH |= ((uint32_t)0xE << 4*3);
|
||||
|
||||
// PK0: LCD_G5
|
||||
GPIOK->MODER |= GPIO_MODER_MODER0_1;
|
||||
GPIOK->OTYPER &=~ GPIO_OTYPER_OT_0;
|
||||
GPIOK->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR0_0 | GPIO_OSPEEDER_OSPEEDR0_1;
|
||||
GPIOK->AFRL |= ((uint32_t)0xE << 4*0);
|
||||
|
||||
// PK1: LCD_G6
|
||||
GPIOK->MODER |= GPIO_MODER_MODER1_1;
|
||||
GPIOK->OTYPER &=~ GPIO_OTYPER_OT_1;
|
||||
GPIOK->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR1_0 | GPIO_OSPEEDER_OSPEEDR1_1;
|
||||
GPIOK->AFRL |= ((uint32_t)0xE << 4*1);
|
||||
|
||||
// PK2: LCD_G7
|
||||
GPIOK->MODER |= GPIO_MODER_MODER2_1;
|
||||
GPIOK->OTYPER &=~ GPIO_OTYPER_OT_2;
|
||||
GPIOK->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR2_0 | GPIO_OSPEEDER_OSPEEDR2_1;
|
||||
GPIOK->AFRL |= ((uint32_t)0xE << 4*2);
|
||||
|
||||
// PE4: LCD_B0
|
||||
GPIOE->MODER |= GPIO_MODER_MODER4_1;
|
||||
GPIOE->OTYPER &=~ GPIO_OTYPER_OT_4;
|
||||
GPIOE->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR4_0 | GPIO_OSPEEDER_OSPEEDR4_1;
|
||||
GPIOE->AFRL |= ((uint32_t)0xE << 4*4);
|
||||
|
||||
// PJ13: LCD_B1
|
||||
GPIOJ->MODER |= GPIO_MODER_MODER13_1;
|
||||
GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_13;
|
||||
GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR13_0 | GPIO_OSPEEDER_OSPEEDR13_1;
|
||||
GPIOJ->AFRH |= ((uint32_t)0xE << 4*5);
|
||||
|
||||
// PJ14: LCD_B2
|
||||
GPIOJ->MODER |= GPIO_MODER_MODER14_1;
|
||||
GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_14;
|
||||
GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR14_0 | GPIO_OSPEEDER_OSPEEDR14_1;
|
||||
GPIOJ->AFRH |= ((uint32_t)0xE << 4*6);
|
||||
|
||||
// PJ15: LCD_B3
|
||||
GPIOJ->MODER |= GPIO_MODER_MODER15_1;
|
||||
GPIOJ->OTYPER &=~ GPIO_OTYPER_OT_15;
|
||||
GPIOJ->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR15_0 | GPIO_OSPEEDER_OSPEEDR15_1;
|
||||
GPIOJ->AFRH |= ((uint32_t)0xE << 4*7);
|
||||
|
||||
// PG12: LCD_B4
|
||||
GPIOG->MODER |= GPIO_MODER_MODER12_1;
|
||||
GPIOG->OTYPER &=~ GPIO_OTYPER_OT_12;
|
||||
GPIOG->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR12_0 | GPIO_OSPEEDER_OSPEEDR12_1;
|
||||
GPIOG->AFRH |= ((uint32_t)0x9 << 4*4);
|
||||
|
||||
// PK4: LCD_B5
|
||||
GPIOK->MODER |= GPIO_MODER_MODER4_1;
|
||||
GPIOK->OTYPER &=~ GPIO_OTYPER_OT_4;
|
||||
GPIOK->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR4_0 | GPIO_OSPEEDER_OSPEEDR4_1;
|
||||
GPIOK->AFRL |= ((uint32_t)0xE << 4*4);
|
||||
|
||||
// PK5: LCD_B6
|
||||
GPIOK->MODER |= GPIO_MODER_MODER5_1;
|
||||
GPIOK->OTYPER &=~ GPIO_OTYPER_OT_5;
|
||||
GPIOK->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR5_0 | GPIO_OSPEEDER_OSPEEDR5_1;
|
||||
GPIOK->AFRL |= ((uint32_t)0xE << 4*5);
|
||||
|
||||
// PK6: LCD_B7
|
||||
GPIOK->MODER |= GPIO_MODER_MODER6_1;
|
||||
GPIOK->OTYPER &=~ GPIO_OTYPER_OT_6;
|
||||
GPIOK->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR6_0 | GPIO_OSPEEDER_OSPEEDR6_1;
|
||||
GPIOK->AFRL |= ((uint32_t)0xE << 4*6);
|
||||
|
||||
// PK7: LCD_DE
|
||||
GPIOK->MODER |= GPIO_MODER_MODER7_1;
|
||||
GPIOK->OTYPER &=~ GPIO_OTYPER_OT_7;
|
||||
GPIOK->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR7_0 | GPIO_OSPEEDER_OSPEEDR7_1;
|
||||
GPIOK->AFRL |= ((uint32_t)0xE << 4*7);
|
||||
|
||||
// PI9: LCD_VSYNC
|
||||
GPIOI->MODER |= GPIO_MODER_MODER9_1;
|
||||
GPIOI->OTYPER &=~ GPIO_OTYPER_OT_9;
|
||||
GPIOI->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR9_0 | GPIO_OSPEEDER_OSPEEDR9_1;
|
||||
GPIOI->AFRH |= ((uint32_t)0xE << 4*1);
|
||||
|
||||
// PI10: LCD_VSYNC
|
||||
GPIOI->MODER |= GPIO_MODER_MODER10_1;
|
||||
GPIOI->OTYPER &=~ GPIO_OTYPER_OT_10;
|
||||
GPIOI->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR10_0 | GPIO_OSPEEDER_OSPEEDR10_1;
|
||||
GPIOI->AFRH |= ((uint32_t)0xE << 4*2);
|
||||
|
||||
// PI13: LCD_INT
|
||||
GPIOI->MODER |= GPIO_MODER_MODER13_1;
|
||||
GPIOI->OTYPER &=~ GPIO_OTYPER_OT_13;
|
||||
GPIOI->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR13_0 | GPIO_OSPEEDER_OSPEEDR13_1;
|
||||
GPIOI->AFRH |= ((uint32_t)0xE << 4*5);
|
||||
|
||||
// PI14: LCD_CLK
|
||||
GPIOI->MODER |= GPIO_MODER_MODER14_1;
|
||||
GPIOI->OTYPER &=~ GPIO_OTYPER_OT_14;
|
||||
GPIOI->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR14_0 | GPIO_OSPEEDER_OSPEEDR14_1;
|
||||
GPIOI->AFRH |= ((uint32_t)0xE << 4*6);
|
||||
|
||||
// PI8: ???
|
||||
GPIOI->MODER |= GPIO_MODER_MODER8_1;
|
||||
GPIOI->OTYPER &=~ GPIO_OTYPER_OT_8;
|
||||
GPIOI->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR8_0 | GPIO_OSPEEDER_OSPEEDR8_1;
|
||||
GPIOI->AFRH |= ((uint32_t)0xE << 4*0);
|
||||
|
||||
// PI12: LCD_DISP_PIN
|
||||
GPIOI->MODER |= GPIO_MODER_MODER12_0;
|
||||
GPIOI->OTYPER &=~ GPIO_OTYPER_OT_12;
|
||||
GPIOI->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR12_0 | GPIO_OSPEEDER_OSPEEDR12_1;
|
||||
|
||||
// PK3: LCD_BL_CTRL
|
||||
GPIOK->MODER |= GPIO_MODER_MODER3_0;
|
||||
GPIOK->OTYPER &=~ GPIO_OTYPER_OT_3;
|
||||
GPIOK->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR3_0 | GPIO_OSPEEDER_OSPEEDR3_1;
|
||||
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOKEN;
|
||||
GPIOK->MODER |= (
|
||||
GPIO_MODER_MODER0_1 // PK0: LCD_G5 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
|
||||
| GPIO_MODER_MODER1_1 // PK1: LCD_G6 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
|
||||
| GPIO_MODER_MODER2_1 // PK2: LCD_G7 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
|
||||
| GPIO_MODER_MODER3_0 // PK3: LCD_BL_CTRL - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_OUTPUT_PUSHPULL
|
||||
| GPIO_MODER_MODER4_1 // PK4: LCD_B5 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
|
||||
| GPIO_MODER_MODER5_1 // PK5: LCD_B6 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
|
||||
| GPIO_MODER_MODER6_1 // PK6: LCD_B7 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
|
||||
| GPIO_MODER_MODER7_1 // PK7: LCD_DE - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
|
||||
);
|
||||
GPIOK->MODER &=~ (
|
||||
GPIO_MODER_MODER0_0
|
||||
| GPIO_MODER_MODER1_0
|
||||
| GPIO_MODER_MODER2_0
|
||||
| GPIO_MODER_MODER3_1
|
||||
| GPIO_MODER_MODER4_0
|
||||
| GPIO_MODER_MODER5_0
|
||||
| GPIO_MODER_MODER6_0
|
||||
| GPIO_MODER_MODER7_0
|
||||
);
|
||||
GPIOK->OTYPER &=~ (
|
||||
GPIO_OTYPER_OT_0
|
||||
| GPIO_OTYPER_OT_1
|
||||
| GPIO_OTYPER_OT_2
|
||||
| GPIO_OTYPER_OT_3
|
||||
| GPIO_OTYPER_OT_4
|
||||
| GPIO_OTYPER_OT_5
|
||||
| GPIO_OTYPER_OT_6
|
||||
| GPIO_OTYPER_OT_7
|
||||
);
|
||||
GPIOK->OSPEEDR |= (
|
||||
GPIO_OSPEEDER_OSPEEDR0_0 | GPIO_OSPEEDER_OSPEEDR0_1
|
||||
| GPIO_OSPEEDER_OSPEEDR1_0 | GPIO_OSPEEDER_OSPEEDR1_1
|
||||
| GPIO_OSPEEDER_OSPEEDR2_0 | GPIO_OSPEEDER_OSPEEDR2_1
|
||||
| GPIO_OSPEEDER_OSPEEDR3_0 | GPIO_OSPEEDER_OSPEEDR3_1
|
||||
| GPIO_OSPEEDER_OSPEEDR4_0 | GPIO_OSPEEDER_OSPEEDR4_1
|
||||
| GPIO_OSPEEDER_OSPEEDR5_0 | GPIO_OSPEEDER_OSPEEDR5_1
|
||||
| GPIO_OSPEEDER_OSPEEDR6_0 | GPIO_OSPEEDER_OSPEEDR6_1
|
||||
| GPIO_OSPEEDER_OSPEEDR7_0 | GPIO_OSPEEDER_OSPEEDR7_1
|
||||
);
|
||||
GPIOK->PUPDR &=~ (
|
||||
GPIO_PUPDR_PUPDR0_0 | GPIO_PUPDR_PUPDR0_1
|
||||
| GPIO_PUPDR_PUPDR1_0 | GPIO_PUPDR_PUPDR1_1
|
||||
| GPIO_PUPDR_PUPDR2_0 | GPIO_PUPDR_PUPDR2_1
|
||||
| GPIO_PUPDR_PUPDR3_0 | GPIO_PUPDR_PUPDR3_1
|
||||
| GPIO_PUPDR_PUPDR4_0 | GPIO_PUPDR_PUPDR4_1
|
||||
| GPIO_PUPDR_PUPDR5_0 | GPIO_PUPDR_PUPDR5_1
|
||||
| GPIO_PUPDR_PUPDR6_0 | GPIO_PUPDR_PUPDR6_1
|
||||
| GPIO_PUPDR_PUPDR7_0 | GPIO_PUPDR_PUPDR7_1
|
||||
);
|
||||
GPIOK->AFRL |= (
|
||||
(14U << 4*0)
|
||||
| (14U << 4*1)
|
||||
| (14U << 4*2)
|
||||
| ( 0U << 4*3)
|
||||
| (14U << 4*4)
|
||||
| (14U << 4*5)
|
||||
| (14U << 4*6)
|
||||
| (14U << 4*7)
|
||||
);
|
||||
#endif
|
||||
}
|
||||
|
||||
static GFXINLINE void init_board(GDisplay *g) {
|
||||
|
|
@ -260,30 +385,57 @@ static GFXINLINE void init_board(GDisplay *g) {
|
|||
configureLcdPins();
|
||||
|
||||
// Enable the display and turn on the backlight
|
||||
GPIOI->ODR |= (1 << 12); // PowerOn
|
||||
GPIOK->ODR |= (1 << 3); // Backlight on
|
||||
#if GFX_USE_OS_CHIBIOS && !GFX_LTDC_USE_DIRECTIO
|
||||
palSetPad(GPIOI, GPIOI_LCD_DISP);
|
||||
palSetPad(GPIOK, GPIOK_LCD_BL_CTRL);
|
||||
#else
|
||||
GPIOI->ODR |= (1 << 12); // PowerOn
|
||||
GPIOK->ODR |= (1 << 3); // Backlight on
|
||||
#endif
|
||||
|
||||
#define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */
|
||||
#define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */
|
||||
#define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */
|
||||
#define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */
|
||||
#define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */
|
||||
#define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */
|
||||
#if GFX_LTDC_TIMING_SET != 0
|
||||
#define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */
|
||||
#define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */
|
||||
#define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */
|
||||
#define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */
|
||||
#define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */
|
||||
#define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */
|
||||
|
||||
// RK043FN48H LCD clock configuration
|
||||
// PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 Mhz
|
||||
// PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 192 Mhz
|
||||
// PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 192/5 = 38.4 Mhz
|
||||
// LTDC clock frequency = PLLLCDCLK / LTDC_PLLSAI_DIVR_4 = 38.4/4 = 9.6Mhz
|
||||
#define STM32_PLLSAIN_VALUE 192
|
||||
#undef STM32_PLLSAIQ_VALUE
|
||||
#define STM32_PLLSAIQ_VALUE 7
|
||||
#undef STM32_PLLSAIR_VALUE
|
||||
#define STM32_PLLSAIR_VALUE RK043FN48H_FREQUENCY_DIVIDER
|
||||
#define STM32_PLLSAIR_POST STM32_SAIR_DIV4
|
||||
RCC->PLLSAICFGR = (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24);
|
||||
RCC->DCKCFGR1 = (RCC->DCKCFGR1 & ~RCC_DCKCFGR1_PLLSAIDIVR) | STM32_PLLSAIR_POST;
|
||||
RCC->CR |= RCC_CR_PLLSAION;
|
||||
// Some operating systems get these wrong eg ChibiOS - define our own values
|
||||
#undef STM32_PLLSAIN_VALUE
|
||||
#undef STM32_PLLSAIQ_VALUE
|
||||
#undef STM32_PLLSAIP_VALUE
|
||||
#undef STM32_PLLSAIR_VALUE
|
||||
|
||||
/* Display timing */
|
||||
// RK043FN48H LCD clock configuration
|
||||
// PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 Mhz
|
||||
// PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 192 Mhz
|
||||
// PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 192/5 = 38.4 Mhz
|
||||
// LTDC clock frequency = PLLLCDCLK / STM32_PLLSAIR_POST = 38.4/4 = 9.6Mhz
|
||||
#if GFX_LTDC_TIMING_SET == 1
|
||||
#define RK043FN48H_FREQUENCY_DIVIDER 5
|
||||
#define STM32_PLLSAIN_VALUE 192
|
||||
#define STM32_PLLSAIQ_VALUE 4
|
||||
#define STM32_PLLSAIP_VALUE 4
|
||||
#define STM32_PLLSAIR_VALUE RK043FN48H_FREQUENCY_DIVIDER
|
||||
#define STM32_PLLSAIR_POST STM32_SAIR_DIV4
|
||||
#elif GFX_LTDC_TIMING_SET == 2
|
||||
#define RK043FN48H_FREQUENCY_DIVIDER 4
|
||||
#define STM32_PLLSAIN_VALUE 192
|
||||
#define STM32_PLLSAIQ_VALUE 4
|
||||
#define STM32_PLLSAIP_VALUE 4
|
||||
#define STM32_PLLSAIR_VALUE RK043FN48H_FREQUENCY_DIVIDER
|
||||
#define STM32_PLLSAIR_POST STM32_SAIR_DIV4
|
||||
#else
|
||||
#error "LTDC: - Unknown timing set for the STM32F746-Discovery board"
|
||||
#endif
|
||||
|
||||
RCC->CR &= ~RCC_CR_PLLSAION;
|
||||
RCC->PLLSAICFGR = ((STM32_PLLSAIP_VALUE/2-1)<<16) | (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24);
|
||||
RCC->DCKCFGR1 = (RCC->DCKCFGR1 & ~RCC_DCKCFGR1_PLLSAIDIVR) | STM32_PLLSAIR_POST;
|
||||
RCC->CR |= RCC_CR_PLLSAION;
|
||||
#endif
|
||||
|
||||
// Initialise the SDRAM
|
||||
BSP_SDRAM_Init();
|
||||
|
|
@ -304,11 +456,19 @@ static GFXINLINE void set_backlight(GDisplay* g, uint8_t percent) {
|
|||
|
||||
// ST was stupid enought not to hook this up to a pin that
|
||||
// is able to act as PWM output...
|
||||
if (percent <= 0) {
|
||||
GPIOK->ODR &=~ (1 << 3); // Backlight off
|
||||
} else {
|
||||
GPIOK->ODR |= (1 << 3); // Backlight on
|
||||
}
|
||||
#if GFX_USE_OS_CHIBIOS && !GFX_LTDC_USE_DIRECTIO
|
||||
if (percent <= 0) {
|
||||
palClearPad(GPIOK, GPIOK_LCD_BL_CTRL); // Backlight off
|
||||
} else {
|
||||
palSetPad(GPIOK, GPIOK_LCD_BL_CTRL); // Backlight on
|
||||
}
|
||||
#else
|
||||
if (percent <= 0) {
|
||||
GPIOK->ODR &=~ (1 << 3); // Backlight off
|
||||
} else {
|
||||
GPIOK->ODR |= (1 << 3); // Backlight on
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* _GDISP_LLD_BOARD_H */
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
|
||||
# uGFX settings
|
||||
# See $(GFXLIB)/tools/gmake_scripts/library_ugfx.mk for the list of variables
|
||||
GFXLIB = ../ugfx
|
||||
GFXLIB = ../ugfx2
|
||||
GFXBOARD = STM32F746-Discovery
|
||||
GFXDEMO = applications/combo
|
||||
#GFXDRIVERS =
|
||||
|
|
@ -22,8 +22,8 @@
|
|||
# ChibiOS settings
|
||||
ifeq ($(OPT_OS),chibios)
|
||||
# See $(GFXLIB)/tools/gmake_scripts/os_chibios_3.mk for the list of variables
|
||||
CHIBIOS = ../ChibiOS-Master
|
||||
CHIBIOS_VERSION = 3
|
||||
CHIBIOS = ../ChibiOS16
|
||||
CHIBIOS_VERSION = 16
|
||||
CHIBIOS_CPUCLASS = ARMCMx
|
||||
CHIBIOS_PLATFORM = STM32
|
||||
CHIBIOS_DEVICE_FAMILY = STM32F7xx
|
||||
|
|
@ -35,11 +35,14 @@ ifeq ($(OPT_OS),chibios)
|
|||
#CHIBIOS_EXCEPTIONS_STACKSIZE = 0x400
|
||||
endif
|
||||
|
||||
#Special - Required for the drivers for this discovery board.
|
||||
STMHAL = ../STM32/STM32F7xx_HAL_Driver
|
||||
# Raw32 settings
|
||||
ifeq ($(OPT_OS),raw32)
|
||||
CMSIS = ../STM32F7_Drivers/CMSIS
|
||||
endif
|
||||
|
||||
#Special - Required for the drivers for this discovery board.
|
||||
STMHAL = ../STM32F7_Drivers/STM32F7xx_HAL_Driver
|
||||
|
||||
#Special - Required for Raw32
|
||||
CMSIS = ../STM32/CMSIS
|
||||
|
||||
##############################################################################################
|
||||
# Set these for your project
|
||||
|
|
@ -55,8 +58,8 @@ LDFLAGS =
|
|||
SRC =
|
||||
|
||||
OBJS =
|
||||
DEFS =
|
||||
#DEFS = GFX_OS_HEAP_SIZE=40960
|
||||
DEFS =
|
||||
LIBS =
|
||||
INCPATH =
|
||||
|
||||
|
|
|
|||
|
|
@ -67,9 +67,9 @@
|
|||
#define STM32_PLLI2SR_VALUE 4
|
||||
#define STM32_PLLSAIN_VALUE 192
|
||||
#define STM32_PLLSAIP_VALUE 4
|
||||
#define STM32_PLLSAIQ_VALUE 7
|
||||
#define STM32_PLLSAIQ_VALUE 4
|
||||
#define STM32_PLLSAIR_VALUE 4
|
||||
#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
|
||||
#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_DIV4
|
||||
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
|
||||
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
|
||||
#define STM32_USART1SEL STM32_USART1SEL_PCLK2
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
#
|
||||
# To program your device:
|
||||
#
|
||||
# openocd -f openocd.cfg -c "Burn yourfile.bin" -c shutdown
|
||||
# openocd -f openocd.cfg -c "Burn yourfile.elf" -c shutdown
|
||||
#
|
||||
# To debug your device:
|
||||
#
|
||||
|
|
|
|||
|
|
@ -1,14 +1,16 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_conf.h
|
||||
* @file stm32f7xx_hal_conf_template.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 25-June-2015
|
||||
* @brief HAL configuration file.
|
||||
* @version V1.1.0
|
||||
* @date 22-April-2016
|
||||
* @brief HAL configuration template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32f7xx_hal_conf.h.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -33,7 +35,7 @@
|
|||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_CONF_H
|
||||
|
|
@ -48,79 +50,83 @@
|
|||
|
||||
/* ########################## Module Selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
#define HAL_MODULE_ENABLED
|
||||
/* #define HAL_ADC_MODULE_ENABLED */
|
||||
/* #define HAL_CAN_MODULE_ENABLED */
|
||||
/* #define HAL_CEC_MODULE_ENABLED */
|
||||
/* #define HAL_CRC_MODULE_ENABLED */
|
||||
/* #define HAL_CRYP_MODULE_ENABLED */
|
||||
/* #define HAL_DAC_MODULE_ENABLED */
|
||||
/* #define HAL_DCMI_MODULE_ENABLED */
|
||||
#define HAL_MODULE_ENABLED
|
||||
#define HAL_ADC_MODULE_ENABLED
|
||||
#define HAL_CAN_MODULE_ENABLED
|
||||
#define HAL_CEC_MODULE_ENABLED
|
||||
#define HAL_CRC_MODULE_ENABLED
|
||||
#define HAL_CRYP_MODULE_ENABLED
|
||||
#define HAL_DAC_MODULE_ENABLED
|
||||
#define HAL_DCMI_MODULE_ENABLED
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
/* #define HAL_DMA2D_MODULE_ENABLED */
|
||||
/* #define HAL_ETH_MODULE_ENABLED */
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
/* #define HAL_NAND_MODULE_ENABLED */
|
||||
/* #define HAL_NOR_MODULE_ENABLED */
|
||||
/* #define HAL_SRAM_MODULE_ENABLED */
|
||||
//#define HAL_SDRAM_MODULE_ENABLED
|
||||
/* #define HAL_HASH_MODULE_ENABLED */
|
||||
#define HAL_DMA2D_MODULE_ENABLED
|
||||
#define HAL_ETH_MODULE_ENABLED
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
#define HAL_NAND_MODULE_ENABLED
|
||||
#define HAL_NOR_MODULE_ENABLED
|
||||
#define HAL_SRAM_MODULE_ENABLED
|
||||
#define HAL_SDRAM_MODULE_ENABLED
|
||||
#define HAL_HASH_MODULE_ENABLED
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
/* #define HAL_I2C_MODULE_ENABLED */
|
||||
/* #define HAL_I2S_MODULE_ENABLED */
|
||||
/* #define HAL_IWDG_MODULE_ENABLED */
|
||||
/* #define HAL_LPTIM_MODULE_ENABLED */
|
||||
/* #define HAL_LTDC_MODULE_ENABLED */
|
||||
#define HAL_I2C_MODULE_ENABLED
|
||||
#define HAL_I2S_MODULE_ENABLED
|
||||
#define HAL_IWDG_MODULE_ENABLED
|
||||
#define HAL_LPTIM_MODULE_ENABLED
|
||||
#define HAL_LTDC_MODULE_ENABLED
|
||||
#define HAL_PWR_MODULE_ENABLED
|
||||
/* #define HAL_QSPI_MODULE_ENABLED */
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
/* #define HAL_RNG_MODULE_ENABLED */
|
||||
/* #define HAL_RTC_MODULE_ENABLED */
|
||||
/* #define HAL_SAI_MODULE_ENABLED */
|
||||
/* #define HAL_SD_MODULE_ENABLED */
|
||||
/* #define HAL_SPDIFRX_MODULE_ENABLED */
|
||||
/* #define HAL_SPI_MODULE_ENABLED */
|
||||
/* #define HAL_TIM_MODULE_ENABLED */
|
||||
/* #define HAL_UART_MODULE_ENABLED */
|
||||
/* #define HAL_USART_MODULE_ENABLED */
|
||||
/* #define HAL_IRDA_MODULE_ENABLED */
|
||||
/* #define HAL_SMARTCARD_MODULE_ENABLED */
|
||||
/* #define HAL_WWDG_MODULE_ENABLED */
|
||||
#define HAL_QSPI_MODULE_ENABLED
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
#define HAL_RNG_MODULE_ENABLED
|
||||
#define HAL_RTC_MODULE_ENABLED
|
||||
#define HAL_SAI_MODULE_ENABLED
|
||||
#define HAL_SD_MODULE_ENABLED
|
||||
#define HAL_SPDIFRX_MODULE_ENABLED
|
||||
#define HAL_SPI_MODULE_ENABLED
|
||||
#define HAL_TIM_MODULE_ENABLED
|
||||
#define HAL_UART_MODULE_ENABLED
|
||||
#define HAL_USART_MODULE_ENABLED
|
||||
#define HAL_IRDA_MODULE_ENABLED
|
||||
#define HAL_SMARTCARD_MODULE_ENABLED
|
||||
#define HAL_WWDG_MODULE_ENABLED
|
||||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
/* #define HAL_PCD_MODULE_ENABLED */
|
||||
/* #define HAL_HCD_MODULE_ENABLED */
|
||||
#define HAL_PCD_MODULE_ENABLED
|
||||
#define HAL_HCD_MODULE_ENABLED
|
||||
#define HAL_DFSDM_MODULE_ENABLED
|
||||
#define HAL_DSI_MODULE_ENABLED
|
||||
#define HAL_JPEG_MODULE_ENABLED
|
||||
#define HAL_MDIOS_MODULE_ENABLED
|
||||
|
||||
|
||||
/* ########################## HSE/HSI Values adaptation ##################### */
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
|
||||
#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI) value.
|
||||
*/
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE ((uint32_t)40000)
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/
|
||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature. */
|
||||
|
|
@ -128,16 +134,20 @@
|
|||
* @brief External Low Speed oscillator (LSE) value.
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
|
||||
#define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||
#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
|
||||
#endif /* LSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief External clock source for I2S peripheral
|
||||
* This value is used by the I2S HAL module to compute the I2S clock source
|
||||
* frequency, this source is inserted directly through I2S_CKIN pad.
|
||||
* This value is used by the I2S HAL module to compute the I2S clock source
|
||||
* frequency, this source is inserted directly through I2S_CKIN pad.
|
||||
*/
|
||||
#if !defined (EXTERNAL_CLOCK_VALUE)
|
||||
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* EXTERNAL_CLOCK_VALUE */
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
|
|
@ -146,15 +156,16 @@
|
|||
/* ########################### System Configuration ######################### */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
|
||||
#define USE_RTOS 0
|
||||
#define ART_ACCLERATOR_ENABLE 1 /* To enable instruction cache and prefetch */
|
||||
*/
|
||||
#define VDD_VALUE 3300U /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */
|
||||
#define USE_RTOS 0U
|
||||
#define PREFETCH_ENABLE 1U
|
||||
#define ART_ACCLERATOR_ENABLE 1U /* To enable instruction cache and prefetch */
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/* #define USE_FULL_ASSERT 1 */
|
||||
|
|
@ -164,70 +175,79 @@
|
|||
/* Section 1 : Ethernet peripheral configuration */
|
||||
|
||||
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
|
||||
#define MAC_ADDR0 2
|
||||
#define MAC_ADDR1 0
|
||||
#define MAC_ADDR2 0
|
||||
#define MAC_ADDR3 0
|
||||
#define MAC_ADDR4 0
|
||||
#define MAC_ADDR5 0
|
||||
#define MAC_ADDR0 2U
|
||||
#define MAC_ADDR1 0U
|
||||
#define MAC_ADDR2 0U
|
||||
#define MAC_ADDR3 0U
|
||||
#define MAC_ADDR4 0U
|
||||
#define MAC_ADDR5 0U
|
||||
|
||||
/* Definition of the Ethernet driver buffers size and count */
|
||||
/* Definition of the Ethernet driver buffers size and count */
|
||||
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
|
||||
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
|
||||
#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
|
||||
#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
|
||||
#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
|
||||
#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
|
||||
|
||||
/* Section 2: PHY configuration section */
|
||||
|
||||
/* DP83848 PHY Address*/
|
||||
#define DP83848_PHY_ADDRESS 0x01
|
||||
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
|
||||
#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
|
||||
/* DP83848 PHY Address*/
|
||||
#define DP83848_PHY_ADDRESS 0x01U
|
||||
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
|
||||
#define PHY_RESET_DELAY 0x000000FFU
|
||||
/* PHY Configuration delay */
|
||||
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
|
||||
#define PHY_CONFIG_DELAY 0x00000FFFU
|
||||
|
||||
#define PHY_READ_TO ((uint32_t)0x0000FFFF)
|
||||
#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
|
||||
#define PHY_READ_TO 0x0000FFFFU
|
||||
#define PHY_WRITE_TO 0x0000FFFFU
|
||||
|
||||
/* Section 3: Common PHY Registers */
|
||||
|
||||
#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
|
||||
#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
|
||||
|
||||
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
|
||||
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
|
||||
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
|
||||
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
|
||||
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
|
||||
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
|
||||
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
|
||||
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
|
||||
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
|
||||
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
|
||||
|
||||
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
|
||||
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
|
||||
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
|
||||
#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */
|
||||
#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */
|
||||
|
||||
#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
|
||||
#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */
|
||||
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
|
||||
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
|
||||
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
|
||||
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
|
||||
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
|
||||
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */
|
||||
#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */
|
||||
#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */
|
||||
|
||||
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
|
||||
#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
|
||||
#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */
|
||||
|
||||
/* Section 4: Extended PHY Registers */
|
||||
|
||||
#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
|
||||
#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
|
||||
#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
|
||||
#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */
|
||||
#define PHY_MICR ((uint16_t)0x11U) /*!< MII Interrupt Control Register */
|
||||
#define PHY_MISR ((uint16_t)0x12U) /*!< MII Interrupt Status and Misc. Control Register */
|
||||
|
||||
#define PHY_LINK_STATUS ((uint16_t)0x0001U) /*!< PHY Link mask */
|
||||
#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */
|
||||
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */
|
||||
|
||||
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
|
||||
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
|
||||
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
|
||||
#define PHY_MICR_INT_EN ((uint16_t)0x0002U) /*!< PHY Enable interrupts */
|
||||
#define PHY_MICR_INT_OE ((uint16_t)0x0001U) /*!< PHY Enable output interrupt events */
|
||||
|
||||
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
|
||||
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
|
||||
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */
|
||||
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */
|
||||
|
||||
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
|
||||
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
|
||||
/* ################## SPI peripheral configuration ########################## */
|
||||
|
||||
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
|
||||
* Activated: CRC code is present inside driver
|
||||
* Deactivated: CRC code cleaned from driver
|
||||
*/
|
||||
|
||||
#define USE_SPI_CRC 1U
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
|
|
@ -241,7 +261,7 @@
|
|||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
|
@ -263,7 +283,7 @@
|
|||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRYP_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_cryp.h"
|
||||
#include "stm32f7xx_hal_cryp.h"
|
||||
#endif /* HAL_CRYP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA2D_MODULE_ENABLED
|
||||
|
|
@ -285,7 +305,7 @@
|
|||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_flash.h"
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
|
||||
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_sram.h"
|
||||
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||
|
|
@ -300,7 +320,7 @@
|
|||
|
||||
#ifdef HAL_SDRAM_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_sdram.h"
|
||||
#endif /* HAL_SDRAM_MODULE_ENABLED */
|
||||
#endif /* HAL_SDRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HASH_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_hash.h"
|
||||
|
|
@ -390,13 +410,29 @@
|
|||
#include "stm32f7xx_hal_hcd.h"
|
||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DFSDM_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_dfsdm.h"
|
||||
#endif /* HAL_DFSDM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DSI_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_dsi.h"
|
||||
#endif /* HAL_DSI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_JPEG_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_jpeg.h"
|
||||
#endif /* HAL_JPEG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MDIOS_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_mdios.h"
|
||||
#endif /* HAL_MDIOS_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
|
|
@ -413,6 +449,6 @@
|
|||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_CONF_H */
|
||||
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -510,9 +510,7 @@ static void BSP_SDRAM_Initialization_sequence(SDRAM_HandleTypeDef *hsdram, uint3
|
|||
static void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
|
||||
{
|
||||
static DMA_HandleTypeDef dma_handle;
|
||||
#if !GFX_USE_OS_CHIBIOS
|
||||
GPIO_InitTypeDef gpio_init_structure;
|
||||
#endif
|
||||
|
||||
/* Enable FMC clock */
|
||||
__HAL_RCC_FMC_CLK_ENABLE();
|
||||
|
|
@ -529,7 +527,6 @@ static void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
|
|||
__HAL_RCC_GPIOH_CLK_ENABLE();
|
||||
|
||||
/* Common GPIO configuration - some are already setup by ChibiOS Init */
|
||||
#if !GFX_USE_OS_CHIBIOS
|
||||
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
|
||||
gpio_init_structure.Pull = GPIO_PULLUP;
|
||||
gpio_init_structure.Speed = GPIO_SPEED_FAST;
|
||||
|
|
@ -564,7 +561,6 @@ static void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
|
|||
/* GPIOH configuration */
|
||||
gpio_init_structure.Pin = GPIO_PIN_3 | GPIO_PIN_5;
|
||||
HAL_GPIO_Init(GPIOH, &gpio_init_structure);
|
||||
#endif
|
||||
|
||||
/* Configure common DMA parameters */
|
||||
dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue