From 932f4881bca348ecb769f1977088cf9df1d29652 Mon Sep 17 00:00:00 2001 From: Joel Bodenmann Date: Sun, 10 Nov 2013 21:52:55 +0100 Subject: [PATCH] added Embest-STM32-DMSTF4BB base board --- .../ChibiOS_Board/EMBEST_DMSTF4BB.zip | Bin 0 -> 10132 bytes .../ChibiOS_Board/EMBEST_DMSTF4BB/board.c | 108 ++ .../ChibiOS_Board/EMBEST_DMSTF4BB/board.h | 1297 +++++++++++++++++ .../ChibiOS_Board/EMBEST_DMSTF4BB/board.mk | 5 + .../EMBEST_DMSTF4BB/cfg/board.chcfg | 1186 +++++++++++++++ boards/base/Embest-STM32-DMSTF4BB/board.mk | 7 + .../board_SSD2119_embest_dmstf4bb.h | 5 - .../ginput_lld_mouse_board_embest_dmstf4bb.h | 44 +- .../ginput_lld_mouse_config.h | 22 + 9 files changed, 2628 insertions(+), 46 deletions(-) create mode 100644 boards/base/Embest-STM32-DMSTF4BB/ChibiOS_Board/EMBEST_DMSTF4BB.zip create mode 100644 boards/base/Embest-STM32-DMSTF4BB/ChibiOS_Board/EMBEST_DMSTF4BB/board.c create mode 100644 boards/base/Embest-STM32-DMSTF4BB/ChibiOS_Board/EMBEST_DMSTF4BB/board.h create mode 100644 boards/base/Embest-STM32-DMSTF4BB/ChibiOS_Board/EMBEST_DMSTF4BB/board.mk create mode 100644 boards/base/Embest-STM32-DMSTF4BB/ChibiOS_Board/EMBEST_DMSTF4BB/cfg/board.chcfg create mode 100644 boards/base/Embest-STM32-DMSTF4BB/board.mk rename boards/{addons/gdisp => base/Embest-STM32-DMSTF4BB}/board_SSD2119_embest_dmstf4bb.h (96%) rename boards/{addons/ginput/touch/STMPE811 => base/Embest-STM32-DMSTF4BB}/ginput_lld_mouse_board_embest_dmstf4bb.h (67%) create mode 100644 boards/base/Embest-STM32-DMSTF4BB/ginput_lld_mouse_config.h diff --git a/boards/base/Embest-STM32-DMSTF4BB/ChibiOS_Board/EMBEST_DMSTF4BB.zip b/boards/base/Embest-STM32-DMSTF4BB/ChibiOS_Board/EMBEST_DMSTF4BB.zip new file mode 100644 index 0000000000000000000000000000000000000000..47e0cc8a1e89d4dda132f9f44940fbe16e4173ea GIT binary patch literal 10132 zcmc(FcUV))w>Cu}2n0~7gx*`I0-^UVMG%x;q=P_c0tzajNtLd2rHM*MN+<$SLsLLd zdI`NFy?q-!_ndQoN6-E4UpIO7tgJn=*UVn;tanzP866GmOP4V&J|E)w6@L8qqaeY6 zU?|;?SJKlrSG=L8uPiJt&v#279|IdCD0-6+xV-KYU|?Qa#Kyq5bQgF=2e3p2NDu}> zhhL%m2`%S)Y77hoRZI-ZUs$qowS?b=+W#=b{Q8S2Z67CVhwXGesO=F3F zroy;=)$8PJe^PO8_Mt{&PRrI-kKzN8iS4CfuG1qIW^kRtr+bxJG8M+`w4}MHjq+9| z@&K;3B`(vmGh^z9&nH+Tyx@Epl>43P&JC0P>H~Fy70()ywHRLaSke22 zr%U70GV0IFQFdEm$E*~nsQYH@&(&)wh?gWuJNuAx4$Pl}tBs|ldj`JFKuKjj_f*ZO zC-%1AL>H^u9NGw>ux#&i=@A@E#i>;NYz1a&({i@0(VbBiJ>JuBcRal>APlYE-B1*_>Y8dZ zu|@yJGalMN7rwh~xnuoaT|N8Qv;I!5d4_1Ef7P0;$k{3G*YQ-|kI1vz9a|Cti!tbf zf`mgJ_N`5CCh2|Gdq=}psUurAmG8GWnQP5$iXRv2d@nw~avnE)_Dr=*BH5Jl@UWsw z<(b#@o()I1`FOK?++gii2@kR|Kz;pl=yxd1)Xd7xsuNQKw2}Rdk_dDw;Vs>Omvqa@ z+xY$5e#wWLqUATXG+aEtwocG5h<=ax&Uic;lmZSpr3t*IU2bl3o(_#WH9tKYbjp-*mHxN z{Z6a+D2_WWG|qe`W}?;CF3olhHeSP2dyon->Q1LN<`PlvJ#atJ{fo$ zI)NV76R$Rz%-uP3E;o56^EPhPyo~2Id#Yso7p3IZUAHSIoX~c;tr5wb)Ei|qF5cFy zlPJ1LdNR`#TcUbYAZ>!19y9pOo?w^H2aLPAZq7*N%ro1=|I5Z*~#G+jc-lK@kZbVJ}UdZ`c6BeKTiXc zu3X>vjpZj*@bN&?+Fijq1OKl#Q={f~!=+QMzPw}X`i1R)KnRwSXy1b7R3w#aV575f?Aj{IF$sH%qE$K&1ESqe*-bNF?qwLngCy+5spSIzf zsdv!ncF8_>gw7pbB&+Ubg0uJhCVahp4TU9!Qqv22iVE0`dnAghTaK{(wXP4ij^PYN zc3gG2w(YH$VZRew$sCeBpKkZuC&OmK_e;RS=wZ5RvQL1(1oyi-`>T${jlD+$sTPoe z&e!O48QOp@I_izRdA8~ar*UTJk>A9j_r)WopH}5vz2(Nu9$p))+u=R!%{0T6-uhVR zYgoa|Cf|d6NxNnL=0aI7&G3<%U%$$fZKNpF+@UpSYY;%GS?_L;;9#R4s^dStfhEyM zu(}N`K_LMbVj=4Ycy^#A-N+ByULqymksm&9U^z7sterqBc98wh4SAsT+BUQT^+N$# z|DgzO$fN2Acz2)`-N=4GS*eQvjFzF09ncLX%FO z9d&!Y`(Uv<3caa|0PMdy-Encj)l<1DKB#qiViRmsHIsQxhIi;X8L>CbNSfsP{+f^5w%_e@_?0n}efB1e zIk{1$)!IN<Joa>7Rs(^|c^<4|*x!=Znb(n|5ar+h5o0@($$s{WXK(wfFrd!a@(>NgLdB1~CuLS%_bm zm+v)aWGw6~f;@bf7Iz335&G42)#7aMQ=zD?!#Mm>CK z%}OhR3O?CI1pd=dj+LE2D(c+pl$&~9i1p`OSS-!%b6R@+}aT!sD3p zHCthBw%kZLu(zF3Fo$|?V{=y&KRmc}ZJkaQy5O3I)>m0tqh#TuGbD?<9xuUg`DWL` z#AoK4Me81*8WDpc>;#W}v75c)v-U8%7@>|DzcdG~-pBhuwKL2o#wpHYvs$^P${!+C z-b-f}>#-~L>Q%~vqWexYuAX?y5?TrZ`*~&#a3g{Cq>FLN*3@>^bnbdPdd1A5h9toZ z?1%8(*J5~D!3N!1bIWX@ac?xiY@*E_LpQ(-RjzR78r*p9q&&wfcps0bs#4y(OZ^0G z|MA9>F!V$XrAJPhzkmt~M(KeI8@7thc)pSHVb)U4%2IOwiNwHYT5P@=2hE^kfnIP!(m}oWgC-_6DcPR9@?#Gm$ z_L6DFo{1@S+Ti-I_(cxt%$+bAXwAd(G$U5F6!XwYxOIn#xkKdRXzwKN1lQ~0b(xIl z6YjTTAZEkcFT^P!HQk@x;K8|QI9DBi|5UKtn{O2C7|4^*F$((XECOswPfMLFg6}HV zA{eYjef!@*72SO233dw^{N8*c(Jv#Iv!hR(@bVF`8wv(J>U+RQdEe4a_vV$sP?o5A z?hc%ztMT&$*i(K&)Pe|51az%CoV}aqAHhYs?vbXw{-9mx;~=RPa1sh?AGCX1(3GTniOH`} z`@TeDTO52HDVvja3?<5HUu?ZDQfL+$+pd}9_D!d4ktOp=qg8oXV2zrl z!W~*9srLxnWkUOPG<~@&uDH=#64WX{=qT5oH1JgXOmDhw=>`hs>Nf!IO`WJPp=95G z`sq5H(0>$BJ5cIP>yPbyI>KJwaaD(*u6=VEdEn3Cdn>f_f*y07IxYX+i#*W8snJ}k#phSRXnvTMKlO!yNsog>hKP*eKbkt=Uk-(kS>JZeyvGBgeHo;@mM5wFArRe$G z9$V09cQXkdafH}?+bd)K*b^UiVK>Xxy+AO?OqL(*OCPb1a=YS)F;1P{@dZ_wPo_{; z69ZOsA2r&71hai1vX7_4hnZ!jf7Q$TKKAIMu++Pkz;rplefiRQAKWfVLQZSEPR8Mr z8((HMbJt+a1 z%#xrrUr%7qXNmAvQt7HO^i+mbJ?-UKF!)4`9&==iPqS9CyKigxAZXna1Ewcs*Ce7t z*FF-SW3W&S7kmHMD1CMh+%BT?#>1pWFDuOewKZ2^6wQbC3NP$W!Jc2-TZ*=DR(REN z$BpPkQ(|g-k#QVdlGA31NlWh(f9BeLiAhi>`kHzWc9$u6W~-th3QE1*bh14NxK-K)X&XmX%A8^LQ3O-y@o--7_ehCH{o1(mp zeVSXM)bA8;Kmz`r-1@E62X+5y$F}2x;z-e+0Bgy|vIj|_k_RISbPq0J>Q1hV2Q0wZ zj;b2nk!`2mPo=zbj`nPaDXHH197pRuh2x=G>B(SY_{7pP2t1{AthAQ(;=CNl4kFZO z0xc4nXgxz*n0A~;%&B5fe@3&3H#C<*lUUeUiuT6ETcKSa<24en@02bVD?%MyO0M#HuUjW^~RiFz(nD-i}QGk z)`aI7^_>kjwaNPWvgDIDF7t-0^FVCxp{BiNN(?TIb4OS12}N(ZQL zZFJtiU6YZJ0FfbgXV_ZyRHwrxSi5)1m7+f=Myk81U7pz3AA4;#X%BbR)Y7$}exkO1 zP5(|%s~mB_fF-zr==+p4u?Gh&QCiKn_z&?xwDUSf*W5~KaxKwr)mjb?WIH7G-3mJV z#M^$KBl!xBkDJuUzdX1SL}BamD2T!!mU!a6IGvi{YU1hQhjn4RwKDGon7yUDg3fjqhr%yq2$L8nNG}RT;$8kH?jRoO(345_YHRAtu(47? z%$bDHdfovGBk8^9A%Y=^F-~I4y@XJV2-v0D-Hacsz?c*sppq1YM;{>iuo22TmqzsH zuvR&VA3tX%o_GW+kZvD~*MAtzD=MF{ne`3w(x-adc4&bFF4iTt3qwGn;W`)azk=vz z26Z&`W&#=$p2T$a*M(Jnyq77n&gxfM0m9~jroNS#YK%(FU!L1?&oum zhzsNe>=J@#rJ6YBBjF{l*u`4YbbIx?@3?^n%OKV&$wo=mol7V<5A0nWz*s(Y*p)m0 z`0f|AhTwLX4hn7pgDlAMq5zTz)do~&*vJ+*3T!7Qo`8!tn!`f`<`9*q+bFp%)^B+A z(#R|=*6J1*GszS5LN)Y5h$pBdN8u4GEf&ubiG^Bd*FXvIHnd#YEnUyrB@ow^Nxso; zWUX(6c;iXhTiz>Bu=nW*qL^0}L)=3sEdCFIp_#FQ1tO0{ZMUita!If^u?6!gQSpj1?l!GfiTJA4;MjhPd6#`0)yuG06>7`e)UPN%de?1^^!Gb(KOOL|aI~g?)^3 zZit{|4}krrvyLG0U=^_fX*@M+stZjKtbCz83nB&gNZYB1k+eeWWa56H)%+8*e~JSK zLT1Ph?EVzjZuDlj{Xh`H4}hWxua0@^@e~#hiT>m6^oNVPV$F~Bx`9;&feql=)da%R z0&o-}_n<&rAT$z_lLRD{KqI51*{*32p5vWp?oeh(feow(FqD;q9=YflP~Sr$f2eT& z=Il??JfP6eQx?Y`ZG1|AhqHyn-U6-va7r^9;7`Wiy3L*q!W88eHUbUqL^Y5 zLIJ@FVFEC*#192&h$#Y?G+zOeCb@-`{JyH&HTR_`2>^`1KJ%?ig%03Nf5cex&lq$2 z5o633F_t3`d7%L->(7V-h1zD8|8ROay&4(tR{}B(Q0p%Rz_+AefNzrlWd9IRY1sBPW;F5{^9XNj=XPplW`T{Ee8~{jbR1+vv zIkcSNw{98)94YcI-a;t6B?Y_7i4nF>=$q-ygq)5a+@%qzORr<>1~3~3g^v9H2|0v< zvzpk)fo(=F(-tOlS*VY83~PR4;tVj=La8*wJ_6viT>%RK-~j;@$qKOoaJ9z&TUF`d zJN*;f3z+5ua+W=uYe?h%0_&GJ{th`w*t--Ur2+w@`AabicmqJ6U2(<_wKW8mUBb|c}ld%)uvA~jDzr&l*LpfY_vqD&s++uJ4n*wlQ=l^Y(trK2^ z(jTC(089pik{Uq2f5o6OjOv0JBQHFD!Hk-%X~4e(UX;Kd^XorZ@7I**eXZpOL-GP4 z`UfT2djdcK{5K-){+0HE1pm8(ZXkjHD*TP#UXy_DG~^P`Y}oXU(`&Y*P7hVcG`ygr z2V?mZ<3Q5bRt81 zE~jxasbO-c?S5ibXHq?~{O;6&e|7R;p!x)Lj(xEW^m9Y0>pwP>$bPX6WNmBrb5n^1 z*iaJww@oE?>|ptC`01fTmoP9m?J+Rue`D?E#*(!?VEM=9(ycR7-R1ZH*j!pmclCHF z26;5O(H(#nz5n$5+lu$c^vffH`9q{G8)gDL$~Itp6^qKrGc0>b>rgM14|C9mtZE=) z{L@o9rpWPPWEA%UJWO~Ndqj_)0@)+Gmf+cUcip9F2G>6p*Y{=CHV!#H5um9w4(h$f z{vgPpgv8cj7HI%N81deVBMUfV0aa@dk8i{>N38IF-(Yn>j(@3I6DKsd`R0?odSG-& zNIfpioB8`36_PYzozWdN`%~qWm>pHlu_Dy+qnEGNYTE66JDitI_#Q^go}KeLfq?-( zIMv%JT&^c4t3iRFl#)KnNx^mL?MsHGPl^nLTj4Krz{4TOSLO3ugICNjNFuRl7#xDz z@7BbfV9fAd!uEu-EIphoQuHj}fGB6v2RrE2Pb8L&;-@BHCxeTYrn8r(9o$wiuqa0? zF{Ij+L!ZBX4K8EM=&347_{uo&xcmb$^>{w7kf!TEDfP_DKKhMNRPr;sc8&s{f^*%t z=sbe8#%G&%?Sn8*u1?GO#kV4rx7piTPemu?RVk8_A|7!N#$20W<16HfSgS5g*jsF2 zc#s+09xfd);`-4mdRWXE^dx$Jwa>16tNh@V+ul6(ois&zsc;ifJ%LM;kGUhXdmYm` zuRp+`C=)C5?q&OSmn#ng#({Xu12(a59f*AmX~K~XTc7@lN|3H*1W8J+bcU;`jPzKq z-h4b8Fn^|0&HLVM)Op%F+C5Yc9kXK6v=K`mG#NJ~+CJ5$Sd)^jiWh;XSpD}Pb(axR}T-F@UugNCbDHx{0Y)!Q`_)xohv z&0Z6+zQ(TDL8R?9*|LQ^;F;>$MBHD+)+XX$sm@iUU#DxgpLYov<;*DQ4~?C7NhwN?X0I?E#_-2#F**xwOT(9n31ey?dCSu)?;bOeX^^T`NyanL%oM~=YD(53%$6+k!YJU;>+QC> z*vCcNy>%p0T(@e0!sepzx+sEc6YL798H#QeMljk!7jD&FHYF7BSStFQxJVGL7x<;@ zOtSi$k+6p=JKWV4E2Re1tb;M#+#UR!K!|c)DEzsGw@FG3f9B;K2JY?{lN4?oTWAPB zrF=>R10fCxwELpc!%{jvrRHus@XXF@ei_@~L(ctiIR(z+@mawNSR3>>{r!1_RK7M_ zWwnCgbqi3khMLMWJwNRo}5}ZgyLa$z1Shf|q?dpE%IOgwPU-;HQ+My3Fvi zgZbtMYyuvg(HDc#v(%!k;ie4;u{lTb9Sk)7wFO@da4#Q!fQ%KumV<;C|FQ*d{evY> z1b#`s?~-*rW<*FHO$x=Im-N(=gvh=~T~crr_h=KD;>5&_N6vRLJ7X?WqY~%b9H8g* z+yqx*(|S$w12DfJ-?;kZntpQ1%*2#F3*r4Lyxv3Uh9k{Kk7MjgR&k;|5+E+aMHRGvQ(?>o2B zKri>hCNbYRa_3HFG7~vgPCv^l20Zz)jd>ONA1>lm(Z;zpJD zENn8NQ0`B~x&68fTmyG^5>7VA zDI31cy2GvZWQl&i#Vw8{dBLv!{lq7igKDzKA`*Egjl#k*r#b4@sAn2uElvm&f^xlrtUb!wt;(J>)dCMAKLrd|?IF&13pSWJq`V&%wnq| z6|%(D1ggDfUpNO`g-zI~Y)kh-4?hg$eug);J&K#d$BN}L3}+0Q?Cs0&e3B_`DIZd9 zzsy=Sz>qe}=ufIixi6$~rLUP^jI?LnmZQMQD<|J88fU^n+MDIoLNC7jr1GK!=pkkH zB%;5H^aw29h~HF2`T(!VhxCN)(xmbx?WIP1#u8F2JVrOtCv1oh${+|L3!kxqR34Af zleC!)(XR}mMU>!MS}+qr5RW7H?d7RPK-hSe{RsXF(hzWSzY>)QBcTf-JBZ&|p6V-z z8P9T#De?u0vPg4>9MyG3MG^Tq21Tg+AcEv8=vfd6HDagS4zjpm|Ex4|eN0OM9Ns~1 zZk+8<&e>Nml(mxN_}YcrIa;Hzok%N}_x*@WCE_g^m~wS;iE>~?J5>nGA}o)cc7kJu zyS(MIeApjAFNR`JE3nn9P}k6aPIpEIyneso8YjH4M7d*NZkDlzNsf0$Ovv#reMVF6 zq0)eL3hRRJOIcfoxP?2-cVF(hS*qcffsE{_2V1be73ekST(jjpvbcoh!F2fmKeRI~ z&RMz4U|d$Z|THUu87U`Urmw7~7=MK3hTwaIeAUXev(q!!?Bs#!c4+IVc6aJ>bgJG`?b7B^*X2;}QR7j& zp{t7OR^$CLi-vFe5W?}naD$RtI+~H3^ zE37;4EjTClrCf?6TMEpmu5OK9&KqjCR57>XG`1rI^&+z8{fd|2PZv)9UYzSN*h#3E0bdto{qDe;&31jQ`@G)!&Ew z&!qkDL)N|a&msRz;Q`ARDg3_-`=1H?--n&~8_WMKod-I(Naz2hlYg#zfA6G+{-4AD vqk~)efbok}@L!DobB6xi_#>9z8NZmXzZ*IZ?!`2~1-`sk7#O;&7ux>=+j=_T literal 0 HcmV?d00001 diff --git a/boards/base/Embest-STM32-DMSTF4BB/ChibiOS_Board/EMBEST_DMSTF4BB/board.c b/boards/base/Embest-STM32-DMSTF4BB/ChibiOS_Board/EMBEST_DMSTF4BB/board.c new file mode 100644 index 00000000..c892481a --- /dev/null +++ b/boards/base/Embest-STM32-DMSTF4BB/ChibiOS_Board/EMBEST_DMSTF4BB/board.c @@ -0,0 +1,108 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = +{ + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + + return !palReadPad(GPIOB, GPIOB_SD_DETECT); +} + +/** + * @brief SDC card write protection detection. + */ +bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + + return FALSE; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + + return !palReadPad(GPIOB, GPIOB_SD_DETECT); +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + + return FALSE; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} diff --git a/boards/base/Embest-STM32-DMSTF4BB/ChibiOS_Board/EMBEST_DMSTF4BB/board.h b/boards/base/Embest-STM32-DMSTF4BB/ChibiOS_Board/EMBEST_DMSTF4BB/board.h new file mode 100644 index 00000000..f68d0609 --- /dev/null +++ b/boards/base/Embest-STM32-DMSTF4BB/ChibiOS_Board/EMBEST_DMSTF4BB/board.h @@ -0,0 +1,1297 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for STMicroelectronics STM32F4-Discovery board. + */ + +/* + * Board identifier. + */ +#define BOARD_EMBEST_DMSTF4BB +#define BOARD_NAME "STMicroelectronics STM32F4-Discovery with Embest add-on" + + +/* + * Board oscillators-related settings. + * NOTE: LSE not fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768 +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 8000000 +#endif + + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300 + +/* + * MCU type as defined in the ST header file stm32f4xx.h. + */ +#define STM32F4XX + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON 0 +#define GPIOA_PIN1 1 +#define GPIOA_PIN2 2 +#define GPIOA_PIN3 3 +#define GPIOA_LRCK 4 +#define GPIOA_SPC 5 +#define GPIOA_SDO 6 +#define GPIOA_SDI 7 +#define GPIOA_PIN8 8 +#define GPIOA_VBUS_FS 9 +#define GPIOA_OTG_FS_ID 10 +#define GPIOA_OTG_FS_DM 11 +#define GPIOA_OTG_FS_DP 12 +#define GPIOA_SWDIO 13 +#define GPIOA_SWCLK 14 +#define GPIOA_PIN15 15 + +#define GPIOB_PIN0 0 +#define GPIOB_PIN1 1 +#define GPIOB_PIN2 2 +#define GPIOB_SWO 3 +#define GPIOB_PIN4 4 +#define GPIOB_PIN5 5 +#define GPIOB_SCL 6 +#define GPIOB_PIN7 7 +#define GPIOB_PIN8 8 +#define GPIOB_SDA 9 +#define GPIOB_CLK_IN 10 +#define GPIOB_PIN11 11 +#define GPIOB_PIN12 12 +#define GPIOB_PIN13 13 +#define GPIOB_PIN14 14 +#define GPIOB_SD_DETECT 15 + +#define GPIOC_OTG_FS_POWER_ON 0 +#define GPIOC_PIN1 1 +#define GPIOC_PIN2 2 +#define GPIOC_PDM_OUT 3 +#define GPIOC_PIN4 4 +#define GPIOC_PIN5 5 +#define GPIOC_PIN6 6 +#define GPIOC_MCLK 7 +#define GPIOC_SD_D0 8 +#define GPIOC_SD_D1 9 +#define GPIOC_SD_D2 10 +#define GPIOC_SD_D3 11 +#define GPIOC_SD_CLK 12 +#define GPIOC_PIN13 13 +#define GPIOC_PIN14 14 +#define GPIOC_PIN15 15 + +#define GPIOD_PIN0 0 +#define GPIOD_PIN1 1 +#define GPIOD_SD_CMD 2 +#define GPIOD_PIN3 3 +#define GPIOD_RESET 4 +#define GPIOD_OVER_CURRENT 5 +#define GPIOD_PIN6 6 +#define GPIOD_PIN7 7 +#define GPIOD_PIN8 8 +#define GPIOD_PIN9 9 +#define GPIOD_PIN10 10 +#define GPIOD_PIN11 11 +#define GPIOD_LED4 12 +#define GPIOD_LED3 13 +#define GPIOD_LED5 14 +#define GPIOD_LED6 15 + +#define GPIOE_INT1 0 +#define GPIOE_INT2 1 +#define GPIOE_PIN2 2 +#define GPIOE_CS_SPI 3 +#define GPIOE_PIN4 4 +#define GPIOE_PIN5 5 +#define GPIOE_PIN6 6 +#define GPIOE_PIN7 7 +#define GPIOE_PIN8 8 +#define GPIOE_PIN9 9 +#define GPIOE_PIN10 10 +#define GPIOE_PIN11 11 +#define GPIOE_PIN12 12 +#define GPIOE_PIN13 13 +#define GPIOE_PIN14 14 +#define GPIOE_PIN15 15 + +#define GPIOF_PIN0 0 +#define GPIOF_PIN1 1 +#define GPIOF_PIN2 2 +#define GPIOF_PIN3 3 +#define GPIOF_PIN4 4 +#define GPIOF_PIN5 5 +#define GPIOF_PIN6 6 +#define GPIOF_PIN7 7 +#define GPIOF_PIN8 8 +#define GPIOF_PIN9 9 +#define GPIOF_PIN10 10 +#define GPIOF_PIN11 11 +#define GPIOF_PIN12 12 +#define GPIOF_PIN13 13 +#define GPIOF_PIN14 14 +#define GPIOF_PIN15 15 + +#define GPIOG_PIN0 0 +#define GPIOG_PIN1 1 +#define GPIOG_PIN2 2 +#define GPIOG_PIN3 3 +#define GPIOG_PIN4 4 +#define GPIOG_PIN5 5 +#define GPIOG_PIN6 6 +#define GPIOG_PIN7 7 +#define GPIOG_PIN8 8 +#define GPIOG_PIN9 9 +#define GPIOG_PIN10 10 +#define GPIOG_PIN11 11 +#define GPIOG_PIN12 12 +#define GPIOG_PIN13 13 +#define GPIOG_PIN14 14 +#define GPIOG_PIN15 15 + +#define GPIOH_OSC_IN 0 +#define GPIOH_OSC_OUT 1 +#define GPIOH_PIN2 2 +#define GPIOH_PIN3 3 +#define GPIOH_PIN4 4 +#define GPIOH_PIN5 5 +#define GPIOH_PIN6 6 +#define GPIOH_PIN7 7 +#define GPIOH_PIN8 8 +#define GPIOH_PIN9 9 +#define GPIOH_PIN10 10 +#define GPIOH_PIN11 11 +#define GPIOH_PIN12 12 +#define GPIOH_PIN13 13 +#define GPIOH_PIN14 14 +#define GPIOH_PIN15 15 + +#define GPIOI_PIN0 0 +#define GPIOI_PIN1 1 +#define GPIOI_PIN2 2 +#define GPIOI_PIN3 3 +#define GPIOI_PIN4 4 +#define GPIOI_PIN5 5 +#define GPIOI_PIN6 6 +#define GPIOI_PIN7 7 +#define GPIOI_PIN8 8 +#define GPIOI_PIN9 9 +#define GPIOI_PIN10 10 +#define GPIOI_PIN11 11 +#define GPIOI_PIN12 12 +#define GPIOI_PIN13 13 +#define GPIOI_PIN14 14 +#define GPIOI_PIN15 15 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_2M(n) (0U << ((n) * 2)) +#define PIN_OSPEED_25M(n) (1U << ((n) * 2)) +#define PIN_OSPEED_50M(n) (2U << ((n) * 2)) +#define PIN_OSPEED_100M(n) (3U << ((n) * 2)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2)) +#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4)) + +/* + * GPIOA setup: + * + * PA0 - BUTTON (input floating). + * PA1 - PIN1 (input pullup). + * PA2 - PIN2 (input pullup). + * PA3 - PIN3 (input pullup). + * PA4 - LRCK (alternate 6). + * PA5 - SPC (alternate 5). + * PA6 - SDO (alternate 5). + * PA7 - SDI (alternate 5). + * PA8 - PIN8 (input pullup). + * PA9 - VBUS_FS (input floating). + * PA10 - OTG_FS_ID (alternate 10). + * PA11 - OTG_FS_DM (alternate 10). + * PA12 - OTG_FS_DP (alternate 10). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - PIN15 (input pullup). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON) | \ + PIN_MODE_INPUT(GPIOA_PIN1) | \ + PIN_MODE_INPUT(GPIOA_PIN2) | \ + PIN_MODE_INPUT(GPIOA_PIN3) | \ + PIN_MODE_ALTERNATE(GPIOA_LRCK) | \ + PIN_MODE_ALTERNATE(GPIOA_SPC) | \ + PIN_MODE_ALTERNATE(GPIOA_SDO) | \ + PIN_MODE_ALTERNATE(GPIOA_SDI) | \ + PIN_MODE_INPUT(GPIOA_PIN8) | \ + PIN_MODE_INPUT(GPIOA_VBUS_FS) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_INPUT(GPIOA_PIN15)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LRCK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SPC) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SDO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SDI) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOA_VBUS_FS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_100M(GPIOA_BUTTON) | \ + PIN_OSPEED_100M(GPIOA_PIN1) | \ + PIN_OSPEED_100M(GPIOA_PIN2) | \ + PIN_OSPEED_100M(GPIOA_PIN3) | \ + PIN_OSPEED_100M(GPIOA_LRCK) | \ + PIN_OSPEED_50M(GPIOA_SPC) | \ + PIN_OSPEED_50M(GPIOA_SDO) | \ + PIN_OSPEED_50M(GPIOA_SDI) | \ + PIN_OSPEED_100M(GPIOA_PIN8) | \ + PIN_OSPEED_100M(GPIOA_VBUS_FS) | \ + PIN_OSPEED_100M(GPIOA_OTG_FS_ID) | \ + PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \ + PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \ + PIN_OSPEED_100M(GPIOA_SWDIO) | \ + PIN_OSPEED_100M(GPIOA_SWCLK) | \ + PIN_OSPEED_100M(GPIOA_PIN15)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOA_LRCK) | \ + PIN_PUPDR_FLOATING(GPIOA_SPC) | \ + PIN_PUPDR_FLOATING(GPIOA_SDO) | \ + PIN_PUPDR_FLOATING(GPIOA_SDI) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOA_VBUS_FS) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ + PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ + PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN15)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON) | \ + PIN_ODR_HIGH(GPIOA_PIN1) | \ + PIN_ODR_HIGH(GPIOA_PIN2) | \ + PIN_ODR_HIGH(GPIOA_PIN3) | \ + PIN_ODR_HIGH(GPIOA_LRCK) | \ + PIN_ODR_HIGH(GPIOA_SPC) | \ + PIN_ODR_HIGH(GPIOA_SDO) | \ + PIN_ODR_HIGH(GPIOA_SDI) | \ + PIN_ODR_HIGH(GPIOA_PIN8) | \ + PIN_ODR_HIGH(GPIOA_VBUS_FS) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_ID) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0) | \ + PIN_AFIO_AF(GPIOA_PIN1, 0) | \ + PIN_AFIO_AF(GPIOA_PIN2, 0) | \ + PIN_AFIO_AF(GPIOA_PIN3, 0) | \ + PIN_AFIO_AF(GPIOA_LRCK, 6) | \ + PIN_AFIO_AF(GPIOA_SPC, 5) | \ + PIN_AFIO_AF(GPIOA_SDO, 5) | \ + PIN_AFIO_AF(GPIOA_SDI, 5)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \ + PIN_AFIO_AF(GPIOA_VBUS_FS, 0) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0) | \ + PIN_AFIO_AF(GPIOA_PIN15, 0)) + +/* + * GPIOB setup: + * + * PB0 - PIN0 (input pullup). + * PB1 - PIN1 (input pullup). + * PB2 - PIN2 (input pullup). + * PB3 - SWO (alternate 0). + * PB4 - PIN4 (input pullup). + * PB5 - PIN5 (input pullup). + * PB6 - SCL (alternate 4). + * PB7 - PIN7 (input pullup). + * PB8 - PIN8 (input pullup). + * PB9 - SDA (alternate 4). + * PB10 - CLK_IN (input pullup). + * PB11 - PIN11 (input pullup). + * PB12 - PIN12 (input pullup). + * PB13 - PIN13 (input pullup). + * PB14 - PIN14 (input pullup). + * PB15 - SD_DETECT (input pullup). + */ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \ + PIN_MODE_INPUT(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_PIN2) | \ + PIN_MODE_ALTERNATE(GPIOB_SWO) | \ + PIN_MODE_INPUT(GPIOB_PIN4) | \ + PIN_MODE_INPUT(GPIOB_PIN5) | \ + PIN_MODE_ALTERNATE(GPIOB_SCL) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_INPUT(GPIOB_PIN8) | \ + PIN_MODE_ALTERNATE(GPIOB_SDA) | \ + PIN_MODE_INPUT(GPIOB_CLK_IN) | \ + PIN_MODE_INPUT(GPIOB_PIN11) | \ + PIN_MODE_INPUT(GPIOB_PIN12) | \ + PIN_MODE_INPUT(GPIOB_PIN13) | \ + PIN_MODE_INPUT(GPIOB_PIN14) | \ + PIN_MODE_INPUT(GPIOB_SD_DETECT)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_SCL) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOB_CLK_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SD_DETECT)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_PIN0) | \ + PIN_OSPEED_100M(GPIOB_PIN1) | \ + PIN_OSPEED_100M(GPIOB_PIN2) | \ + PIN_OSPEED_100M(GPIOB_SWO) | \ + PIN_OSPEED_100M(GPIOB_PIN4) | \ + PIN_OSPEED_100M(GPIOB_PIN5) | \ + PIN_OSPEED_100M(GPIOB_SCL) | \ + PIN_OSPEED_100M(GPIOB_PIN7) | \ + PIN_OSPEED_100M(GPIOB_PIN8) | \ + PIN_OSPEED_100M(GPIOB_SDA) | \ + PIN_OSPEED_100M(GPIOB_CLK_IN) | \ + PIN_OSPEED_100M(GPIOB_PIN11) | \ + PIN_OSPEED_100M(GPIOB_PIN12) | \ + PIN_OSPEED_100M(GPIOB_PIN13) | \ + PIN_OSPEED_100M(GPIOB_PIN14) | \ + PIN_OSPEED_100M(GPIOB_SD_DETECT)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOB_SWO) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOB_SCL) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOB_SDA) | \ + PIN_PUPDR_PULLUP(GPIOB_CLK_IN) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOB_SD_DETECT)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ + PIN_ODR_HIGH(GPIOB_PIN1) | \ + PIN_ODR_HIGH(GPIOB_PIN2) | \ + PIN_ODR_HIGH(GPIOB_SWO) | \ + PIN_ODR_HIGH(GPIOB_PIN4) | \ + PIN_ODR_HIGH(GPIOB_PIN5) | \ + PIN_ODR_HIGH(GPIOB_SCL) | \ + PIN_ODR_HIGH(GPIOB_PIN7) | \ + PIN_ODR_HIGH(GPIOB_PIN8) | \ + PIN_ODR_HIGH(GPIOB_SDA) | \ + PIN_ODR_HIGH(GPIOB_CLK_IN) | \ + PIN_ODR_HIGH(GPIOB_PIN11) | \ + PIN_ODR_HIGH(GPIOB_PIN12) | \ + PIN_ODR_HIGH(GPIOB_PIN13) | \ + PIN_ODR_HIGH(GPIOB_PIN14) | \ + PIN_ODR_HIGH(GPIOB_SD_DETECT)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \ + PIN_AFIO_AF(GPIOB_PIN1, 0) | \ + PIN_AFIO_AF(GPIOB_PIN2, 0) | \ + PIN_AFIO_AF(GPIOB_SWO, 0) | \ + PIN_AFIO_AF(GPIOB_PIN4, 0) | \ + PIN_AFIO_AF(GPIOB_PIN5, 0) | \ + PIN_AFIO_AF(GPIOB_SCL, 4) | \ + PIN_AFIO_AF(GPIOB_PIN7, 0)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \ + PIN_AFIO_AF(GPIOB_SDA, 4) | \ + PIN_AFIO_AF(GPIOB_CLK_IN, 0) | \ + PIN_AFIO_AF(GPIOB_PIN11, 0) | \ + PIN_AFIO_AF(GPIOB_PIN12, 0) | \ + PIN_AFIO_AF(GPIOB_PIN13, 0) | \ + PIN_AFIO_AF(GPIOB_PIN14, 0) | \ + PIN_AFIO_AF(GPIOB_SD_DETECT, 0)) + +/* + * GPIOC setup: + * + * PC0 - OTG_FS_POWER_ON (output pushpull maximum). + * PC1 - PIN1 (input pullup). + * PC2 - PIN2 (input pullup). + * PC3 - PDM_OUT (input pullup). + * PC4 - PIN4 (input pullup). + * PC5 - PIN5 (input pullup). + * PC6 - PIN6 (input pullup). + * PC7 - MCLK (alternate 6). + * PC8 - SD_D0 (alternate 12). + * PC9 - SD_D1 (alternate 12). + * PC10 - SD_D2 (alternate 12). + * PC11 - SD_D3 (alternate 12). + * PC12 - SD_CLK (alternate 12). + * PC13 - PIN13 (input pullup). + * PC14 - PIN14 (input pullup). + * PC15 - PIN15 (input pullup). + */ +#define VAL_GPIOC_MODER (PIN_MODE_OUTPUT(GPIOC_OTG_FS_POWER_ON) |\ + PIN_MODE_INPUT(GPIOC_PIN1) | \ + PIN_MODE_INPUT(GPIOC_PIN2) | \ + PIN_MODE_INPUT(GPIOC_PDM_OUT) | \ + PIN_MODE_INPUT(GPIOC_PIN4) | \ + PIN_MODE_INPUT(GPIOC_PIN5) | \ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_ALTERNATE(GPIOC_MCLK) | \ + PIN_MODE_ALTERNATE(GPIOC_SD_D0) | \ + PIN_MODE_ALTERNATE(GPIOC_SD_D1) | \ + PIN_MODE_ALTERNATE(GPIOC_SD_D2) | \ + PIN_MODE_ALTERNATE(GPIOC_SD_D3) | \ + PIN_MODE_ALTERNATE(GPIOC_SD_CLK) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_PIN14) | \ + PIN_MODE_INPUT(GPIOC_PIN15)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_OTG_FS_POWER_ON) |\ + PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PDM_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_MCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SD_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SD_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SD_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SD_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SD_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(GPIOC_OTG_FS_POWER_ON) |\ + PIN_OSPEED_100M(GPIOC_PIN1) | \ + PIN_OSPEED_100M(GPIOC_PIN2) | \ + PIN_OSPEED_100M(GPIOC_PDM_OUT) | \ + PIN_OSPEED_100M(GPIOC_PIN4) | \ + PIN_OSPEED_100M(GPIOC_PIN5) | \ + PIN_OSPEED_100M(GPIOC_PIN6) | \ + PIN_OSPEED_100M(GPIOC_MCLK) | \ + PIN_OSPEED_100M(GPIOC_SD_D0) | \ + PIN_OSPEED_100M(GPIOC_SD_D1) | \ + PIN_OSPEED_100M(GPIOC_SD_D2) | \ + PIN_OSPEED_100M(GPIOC_SD_D3) | \ + PIN_OSPEED_100M(GPIOC_SD_CLK) | \ + PIN_OSPEED_100M(GPIOC_PIN13) | \ + PIN_OSPEED_100M(GPIOC_PIN14) | \ + PIN_OSPEED_100M(GPIOC_PIN15)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_OTG_FS_POWER_ON) |\ + PIN_PUPDR_PULLUP(GPIOC_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOC_PDM_OUT) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOC_MCLK) | \ + PIN_PUPDR_FLOATING(GPIOC_SD_D0) | \ + PIN_PUPDR_FLOATING(GPIOC_SD_D1) | \ + PIN_PUPDR_FLOATING(GPIOC_SD_D2) | \ + PIN_PUPDR_FLOATING(GPIOC_SD_D3) | \ + PIN_PUPDR_FLOATING(GPIOC_SD_CLK) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN15)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_OTG_FS_POWER_ON) | \ + PIN_ODR_HIGH(GPIOC_PIN1) | \ + PIN_ODR_HIGH(GPIOC_PIN2) | \ + PIN_ODR_HIGH(GPIOC_PDM_OUT) | \ + PIN_ODR_HIGH(GPIOC_PIN4) | \ + PIN_ODR_HIGH(GPIOC_PIN5) | \ + PIN_ODR_HIGH(GPIOC_PIN6) | \ + PIN_ODR_HIGH(GPIOC_MCLK) | \ + PIN_ODR_HIGH(GPIOC_SD_D0) | \ + PIN_ODR_HIGH(GPIOC_SD_D1) | \ + PIN_ODR_HIGH(GPIOC_SD_D2) | \ + PIN_ODR_HIGH(GPIOC_SD_D3) | \ + PIN_ODR_HIGH(GPIOC_SD_CLK) | \ + PIN_ODR_HIGH(GPIOC_PIN13) | \ + PIN_ODR_HIGH(GPIOC_PIN14) | \ + PIN_ODR_HIGH(GPIOC_PIN15)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_OTG_FS_POWER_ON, 0) |\ + PIN_AFIO_AF(GPIOC_PIN1, 0) | \ + PIN_AFIO_AF(GPIOC_PIN2, 0) | \ + PIN_AFIO_AF(GPIOC_PDM_OUT, 0) | \ + PIN_AFIO_AF(GPIOC_PIN4, 0) | \ + PIN_AFIO_AF(GPIOC_PIN5, 0) | \ + PIN_AFIO_AF(GPIOC_PIN6, 0) | \ + PIN_AFIO_AF(GPIOC_MCLK, 6)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SD_D0, 12) | \ + PIN_AFIO_AF(GPIOC_SD_D1, 12) | \ + PIN_AFIO_AF(GPIOC_SD_D2, 12) | \ + PIN_AFIO_AF(GPIOC_SD_D3, 12) | \ + PIN_AFIO_AF(GPIOC_SD_CLK, 12) | \ + PIN_AFIO_AF(GPIOC_PIN13, 0) | \ + PIN_AFIO_AF(GPIOC_PIN14, 0) | \ + PIN_AFIO_AF(GPIOC_PIN15, 0)) + +/* + * GPIOD setup: + * + * PD0 - PIN0 (input pullup). + * PD1 - PIN1 (input pullup). + * PD2 - SD_CMD (alternate 12). + * PD3 - PIN3 (input pullup). + * PD4 - RESET (output pushpull maximum). + * PD5 - OVER_CURRENT (input floating). + * PD6 - PIN6 (input pullup). + * PD7 - PIN7 (input pullup). + * PD8 - PIN8 (input pullup). + * PD9 - PIN9 (input pullup). + * PD10 - PIN10 (input pullup). + * PD11 - PIN11 (input pullup). + * PD12 - LED4 (output pushpull maximum). + * PD13 - LED3 (output pushpull maximum). + * PD14 - LED5 (output pushpull maximum). + * PD15 - LED6 (output pushpull maximum). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ + PIN_MODE_INPUT(GPIOD_PIN1) | \ + PIN_MODE_ALTERNATE(GPIOD_SD_CMD) | \ + PIN_MODE_INPUT(GPIOD_PIN3) | \ + PIN_MODE_OUTPUT(GPIOD_RESET) | \ + PIN_MODE_INPUT(GPIOD_OVER_CURRENT) | \ + PIN_MODE_INPUT(GPIOD_PIN6) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_INPUT(GPIOD_PIN8) | \ + PIN_MODE_INPUT(GPIOD_PIN9) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_PIN11) | \ + PIN_MODE_OUTPUT(GPIOD_LED4) | \ + PIN_MODE_OUTPUT(GPIOD_LED3) | \ + PIN_MODE_OUTPUT(GPIOD_LED5) | \ + PIN_MODE_OUTPUT(GPIOD_LED6)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SD_CMD) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_RESET) | \ + PIN_OTYPE_PUSHPULL(GPIOD_OVER_CURRENT) |\ + PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED6)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_PIN0) | \ + PIN_OSPEED_100M(GPIOD_PIN1) | \ + PIN_OSPEED_100M(GPIOD_SD_CMD) | \ + PIN_OSPEED_100M(GPIOD_PIN3) | \ + PIN_OSPEED_100M(GPIOD_RESET) | \ + PIN_OSPEED_100M(GPIOD_OVER_CURRENT) | \ + PIN_OSPEED_100M(GPIOD_PIN6) | \ + PIN_OSPEED_100M(GPIOD_PIN7) | \ + PIN_OSPEED_100M(GPIOD_PIN8) | \ + PIN_OSPEED_100M(GPIOD_PIN9) | \ + PIN_OSPEED_100M(GPIOD_PIN10) | \ + PIN_OSPEED_100M(GPIOD_PIN11) | \ + PIN_OSPEED_100M(GPIOD_LED4) | \ + PIN_OSPEED_100M(GPIOD_LED3) | \ + PIN_OSPEED_100M(GPIOD_LED5) | \ + PIN_OSPEED_100M(GPIOD_LED6)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOD_SD_CMD) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOD_RESET) | \ + PIN_PUPDR_FLOATING(GPIOD_OVER_CURRENT) |\ + PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOD_LED4) | \ + PIN_PUPDR_FLOATING(GPIOD_LED3) | \ + PIN_PUPDR_FLOATING(GPIOD_LED5) | \ + PIN_PUPDR_FLOATING(GPIOD_LED6)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ + PIN_ODR_HIGH(GPIOD_PIN1) | \ + PIN_ODR_HIGH(GPIOD_SD_CMD) | \ + PIN_ODR_HIGH(GPIOD_PIN3) | \ + PIN_ODR_HIGH(GPIOD_RESET) | \ + PIN_ODR_HIGH(GPIOD_OVER_CURRENT) | \ + PIN_ODR_HIGH(GPIOD_PIN6) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_PIN8) | \ + PIN_ODR_HIGH(GPIOD_PIN9) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_PIN11) | \ + PIN_ODR_LOW(GPIOD_LED4) | \ + PIN_ODR_LOW(GPIOD_LED3) | \ + PIN_ODR_LOW(GPIOD_LED5) | \ + PIN_ODR_LOW(GPIOD_LED6)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \ + PIN_AFIO_AF(GPIOD_PIN1, 0) | \ + PIN_AFIO_AF(GPIOD_SD_CMD, 12) | \ + PIN_AFIO_AF(GPIOD_PIN3, 0) | \ + PIN_AFIO_AF(GPIOD_RESET, 0) | \ + PIN_AFIO_AF(GPIOD_OVER_CURRENT, 0) | \ + PIN_AFIO_AF(GPIOD_PIN6, 0) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \ + PIN_AFIO_AF(GPIOD_PIN9, 0) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0) | \ + PIN_AFIO_AF(GPIOD_PIN11, 0) | \ + PIN_AFIO_AF(GPIOD_LED4, 0) | \ + PIN_AFIO_AF(GPIOD_LED3, 0) | \ + PIN_AFIO_AF(GPIOD_LED5, 0) | \ + PIN_AFIO_AF(GPIOD_LED6, 0)) + +/* + * GPIOE setup: + * + * PE0 - INT1 (input floating). + * PE1 - INT2 (input floating). + * PE2 - PIN2 (input floating). + * PE3 - CS_SPI (output pushpull maximum). + * PE4 - PIN4 (input floating). + * PE5 - PIN5 (input floating). + * PE6 - PIN6 (input floating). + * PE7 - PIN7 (input floating). + * PE8 - PIN8 (input floating). + * PE9 - PIN9 (input floating). + * PE10 - PIN10 (input floating). + * PE11 - PIN11 (input floating). + * PE12 - PIN12 (input floating). + * PE13 - PIN13 (input floating). + * PE14 - PIN14 (input floating). + * PE15 - PIN15 (input floating). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_INT1) | \ + PIN_MODE_INPUT(GPIOE_INT2) | \ + PIN_MODE_INPUT(GPIOE_PIN2) | \ + PIN_MODE_OUTPUT(GPIOE_CS_SPI) | \ + PIN_MODE_INPUT(GPIOE_PIN4) | \ + PIN_MODE_INPUT(GPIOE_PIN5) | \ + PIN_MODE_INPUT(GPIOE_PIN6) | \ + PIN_MODE_INPUT(GPIOE_PIN7) | \ + PIN_MODE_INPUT(GPIOE_PIN8) | \ + PIN_MODE_INPUT(GPIOE_PIN9) | \ + PIN_MODE_INPUT(GPIOE_PIN10) | \ + PIN_MODE_INPUT(GPIOE_PIN11) | \ + PIN_MODE_INPUT(GPIOE_PIN12) | \ + PIN_MODE_INPUT(GPIOE_PIN13) | \ + PIN_MODE_INPUT(GPIOE_PIN14) | \ + PIN_MODE_INPUT(GPIOE_PIN15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_INT1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_INT2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_CS_SPI) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_INT1) | \ + PIN_OSPEED_100M(GPIOE_INT2) | \ + PIN_OSPEED_100M(GPIOE_PIN2) | \ + PIN_OSPEED_100M(GPIOE_CS_SPI) | \ + PIN_OSPEED_100M(GPIOE_PIN4) | \ + PIN_OSPEED_100M(GPIOE_PIN5) | \ + PIN_OSPEED_100M(GPIOE_PIN6) | \ + PIN_OSPEED_100M(GPIOE_PIN7) | \ + PIN_OSPEED_100M(GPIOE_PIN8) | \ + PIN_OSPEED_100M(GPIOE_PIN9) | \ + PIN_OSPEED_100M(GPIOE_PIN10) | \ + PIN_OSPEED_100M(GPIOE_PIN11) | \ + PIN_OSPEED_100M(GPIOE_PIN12) | \ + PIN_OSPEED_100M(GPIOE_PIN13) | \ + PIN_OSPEED_100M(GPIOE_PIN14) | \ + PIN_OSPEED_100M(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_INT1) | \ + PIN_PUPDR_FLOATING(GPIOE_INT2) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOE_CS_SPI) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_INT1) | \ + PIN_ODR_HIGH(GPIOE_INT2) | \ + PIN_ODR_HIGH(GPIOE_PIN2) | \ + PIN_ODR_HIGH(GPIOE_CS_SPI) | \ + PIN_ODR_HIGH(GPIOE_PIN4) | \ + PIN_ODR_HIGH(GPIOE_PIN5) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_PIN7) | \ + PIN_ODR_HIGH(GPIOE_PIN8) | \ + PIN_ODR_HIGH(GPIOE_PIN9) | \ + PIN_ODR_HIGH(GPIOE_PIN10) | \ + PIN_ODR_HIGH(GPIOE_PIN11) | \ + PIN_ODR_HIGH(GPIOE_PIN12) | \ + PIN_ODR_HIGH(GPIOE_PIN13) | \ + PIN_ODR_HIGH(GPIOE_PIN14) | \ + PIN_ODR_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_INT1, 0) | \ + PIN_AFIO_AF(GPIOE_INT2, 0) | \ + PIN_AFIO_AF(GPIOE_PIN2, 0) | \ + PIN_AFIO_AF(GPIOE_CS_SPI, 0) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0) | \ + PIN_AFIO_AF(GPIOE_PIN7, 0)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \ + PIN_AFIO_AF(GPIOE_PIN9, 0) | \ + PIN_AFIO_AF(GPIOE_PIN10, 0) | \ + PIN_AFIO_AF(GPIOE_PIN11, 0) | \ + PIN_AFIO_AF(GPIOE_PIN12, 0) | \ + PIN_AFIO_AF(GPIOE_PIN13, 0) | \ + PIN_AFIO_AF(GPIOE_PIN14, 0) | \ + PIN_AFIO_AF(GPIOE_PIN15, 0)) + +/* + * GPIOF setup: + * + * PF0 - PIN0 (input floating). + * PF1 - PIN1 (input floating). + * PF2 - PIN2 (input floating). + * PF3 - PIN3 (input floating). + * PF4 - PIN4 (input floating). + * PF5 - PIN5 (input floating). + * PF6 - PIN6 (input floating). + * PF7 - PIN7 (input floating). + * PF8 - PIN8 (input floating). + * PF9 - PIN9 (input floating). + * PF10 - PIN10 (input floating). + * PF11 - PIN11 (input floating). + * PF12 - PIN12 (input floating). + * PF13 - PIN13 (input floating). + * PF14 - PIN14 (input floating). + * PF15 - PIN15 (input floating). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ + PIN_MODE_INPUT(GPIOF_PIN1) | \ + PIN_MODE_INPUT(GPIOF_PIN2) | \ + PIN_MODE_INPUT(GPIOF_PIN3) | \ + PIN_MODE_INPUT(GPIOF_PIN4) | \ + PIN_MODE_INPUT(GPIOF_PIN5) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_INPUT(GPIOF_PIN7) | \ + PIN_MODE_INPUT(GPIOF_PIN8) | \ + PIN_MODE_INPUT(GPIOF_PIN9) | \ + PIN_MODE_INPUT(GPIOF_PIN10) | \ + PIN_MODE_INPUT(GPIOF_PIN11) | \ + PIN_MODE_INPUT(GPIOF_PIN12) | \ + PIN_MODE_INPUT(GPIOF_PIN13) | \ + PIN_MODE_INPUT(GPIOF_PIN14) | \ + PIN_MODE_INPUT(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_PIN0) | \ + PIN_OSPEED_100M(GPIOF_PIN1) | \ + PIN_OSPEED_100M(GPIOF_PIN2) | \ + PIN_OSPEED_100M(GPIOF_PIN3) | \ + PIN_OSPEED_100M(GPIOF_PIN4) | \ + PIN_OSPEED_100M(GPIOF_PIN5) | \ + PIN_OSPEED_100M(GPIOF_PIN6) | \ + PIN_OSPEED_100M(GPIOF_PIN7) | \ + PIN_OSPEED_100M(GPIOF_PIN8) | \ + PIN_OSPEED_100M(GPIOF_PIN9) | \ + PIN_OSPEED_100M(GPIOF_PIN10) | \ + PIN_OSPEED_100M(GPIOF_PIN11) | \ + PIN_OSPEED_100M(GPIOF_PIN12) | \ + PIN_OSPEED_100M(GPIOF_PIN13) | \ + PIN_OSPEED_100M(GPIOF_PIN14) | \ + PIN_OSPEED_100M(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ + PIN_ODR_HIGH(GPIOF_PIN1) | \ + PIN_ODR_HIGH(GPIOF_PIN2) | \ + PIN_ODR_HIGH(GPIOF_PIN3) | \ + PIN_ODR_HIGH(GPIOF_PIN4) | \ + PIN_ODR_HIGH(GPIOF_PIN5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_PIN7) | \ + PIN_ODR_HIGH(GPIOF_PIN8) | \ + PIN_ODR_HIGH(GPIOF_PIN9) | \ + PIN_ODR_HIGH(GPIOF_PIN10) | \ + PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_PIN12) | \ + PIN_ODR_HIGH(GPIOF_PIN13) | \ + PIN_ODR_HIGH(GPIOF_PIN14) | \ + PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \ + PIN_AFIO_AF(GPIOF_PIN1, 0) | \ + PIN_AFIO_AF(GPIOF_PIN2, 0) | \ + PIN_AFIO_AF(GPIOF_PIN3, 0) | \ + PIN_AFIO_AF(GPIOF_PIN4, 0) | \ + PIN_AFIO_AF(GPIOF_PIN5, 0) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0) | \ + PIN_AFIO_AF(GPIOF_PIN7, 0)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \ + PIN_AFIO_AF(GPIOF_PIN9, 0) | \ + PIN_AFIO_AF(GPIOF_PIN10, 0) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0) | \ + PIN_AFIO_AF(GPIOF_PIN12, 0) | \ + PIN_AFIO_AF(GPIOF_PIN13, 0) | \ + PIN_AFIO_AF(GPIOF_PIN14, 0) | \ + PIN_AFIO_AF(GPIOF_PIN15, 0)) + +/* + * GPIOG setup: + * + * PG0 - PIN0 (input floating). + * PG1 - PIN1 (input floating). + * PG2 - PIN2 (input floating). + * PG3 - PIN3 (input floating). + * PG4 - PIN4 (input floating). + * PG5 - PIN5 (input floating). + * PG6 - PIN6 (input floating). + * PG7 - PIN7 (input floating). + * PG8 - PIN8 (input floating). + * PG9 - PIN9 (input floating). + * PG10 - PIN10 (input floating). + * PG11 - PIN11 (input floating). + * PG12 - PIN12 (input floating). + * PG13 - PIN13 (input floating). + * PG14 - PIN14 (input floating). + * PG15 - PIN15 (input floating). + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ + PIN_MODE_INPUT(GPIOG_PIN1) | \ + PIN_MODE_INPUT(GPIOG_PIN2) | \ + PIN_MODE_INPUT(GPIOG_PIN3) | \ + PIN_MODE_INPUT(GPIOG_PIN4) | \ + PIN_MODE_INPUT(GPIOG_PIN5) | \ + PIN_MODE_INPUT(GPIOG_PIN6) | \ + PIN_MODE_INPUT(GPIOG_PIN7) | \ + PIN_MODE_INPUT(GPIOG_PIN8) | \ + PIN_MODE_INPUT(GPIOG_PIN9) | \ + PIN_MODE_INPUT(GPIOG_PIN10) | \ + PIN_MODE_INPUT(GPIOG_PIN11) | \ + PIN_MODE_INPUT(GPIOG_PIN12) | \ + PIN_MODE_INPUT(GPIOG_PIN13) | \ + PIN_MODE_INPUT(GPIOG_PIN14) | \ + PIN_MODE_INPUT(GPIOG_PIN15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(GPIOG_PIN0) | \ + PIN_OSPEED_100M(GPIOG_PIN1) | \ + PIN_OSPEED_100M(GPIOG_PIN2) | \ + PIN_OSPEED_100M(GPIOG_PIN3) | \ + PIN_OSPEED_100M(GPIOG_PIN4) | \ + PIN_OSPEED_100M(GPIOG_PIN5) | \ + PIN_OSPEED_100M(GPIOG_PIN6) | \ + PIN_OSPEED_100M(GPIOG_PIN7) | \ + PIN_OSPEED_100M(GPIOG_PIN8) | \ + PIN_OSPEED_100M(GPIOG_PIN9) | \ + PIN_OSPEED_100M(GPIOG_PIN10) | \ + PIN_OSPEED_100M(GPIOG_PIN11) | \ + PIN_OSPEED_100M(GPIOG_PIN12) | \ + PIN_OSPEED_100M(GPIOG_PIN13) | \ + PIN_OSPEED_100M(GPIOG_PIN14) | \ + PIN_OSPEED_100M(GPIOG_PIN15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ + PIN_ODR_HIGH(GPIOG_PIN1) | \ + PIN_ODR_HIGH(GPIOG_PIN2) | \ + PIN_ODR_HIGH(GPIOG_PIN3) | \ + PIN_ODR_HIGH(GPIOG_PIN4) | \ + PIN_ODR_HIGH(GPIOG_PIN5) | \ + PIN_ODR_HIGH(GPIOG_PIN6) | \ + PIN_ODR_HIGH(GPIOG_PIN7) | \ + PIN_ODR_HIGH(GPIOG_PIN8) | \ + PIN_ODR_HIGH(GPIOG_PIN9) | \ + PIN_ODR_HIGH(GPIOG_PIN10) | \ + PIN_ODR_HIGH(GPIOG_PIN11) | \ + PIN_ODR_HIGH(GPIOG_PIN12) | \ + PIN_ODR_HIGH(GPIOG_PIN13) | \ + PIN_ODR_HIGH(GPIOG_PIN14) | \ + PIN_ODR_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | \ + PIN_AFIO_AF(GPIOG_PIN1, 0) | \ + PIN_AFIO_AF(GPIOG_PIN2, 0) | \ + PIN_AFIO_AF(GPIOG_PIN3, 0) | \ + PIN_AFIO_AF(GPIOG_PIN4, 0) | \ + PIN_AFIO_AF(GPIOG_PIN5, 0) | \ + PIN_AFIO_AF(GPIOG_PIN6, 0) | \ + PIN_AFIO_AF(GPIOG_PIN7, 0)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \ + PIN_AFIO_AF(GPIOG_PIN9, 0) | \ + PIN_AFIO_AF(GPIOG_PIN10, 0) | \ + PIN_AFIO_AF(GPIOG_PIN11, 0) | \ + PIN_AFIO_AF(GPIOG_PIN12, 0) | \ + PIN_AFIO_AF(GPIOG_PIN13, 0) | \ + PIN_AFIO_AF(GPIOG_PIN14, 0) | \ + PIN_AFIO_AF(GPIOG_PIN15, 0)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (input floating). + * PH3 - PIN3 (input floating). + * PH4 - PIN4 (input floating). + * PH5 - PIN5 (input floating). + * PH6 - PIN6 (input floating). + * PH7 - PIN7 (input floating). + * PH8 - PIN8 (input floating). + * PH9 - PIN9 (input floating). + * PH10 - PIN10 (input floating). + * PH11 - PIN11 (input floating). + * PH12 - PIN12 (input floating). + * PH13 - PIN13 (input floating). + * PH14 - PIN14 (input floating). + * PH15 - PIN15 (input floating). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(GPIOH_OSC_IN) | \ + PIN_OSPEED_100M(GPIOH_OSC_OUT) | \ + PIN_OSPEED_100M(GPIOH_PIN2) | \ + PIN_OSPEED_100M(GPIOH_PIN3) | \ + PIN_OSPEED_100M(GPIOH_PIN4) | \ + PIN_OSPEED_100M(GPIOH_PIN5) | \ + PIN_OSPEED_100M(GPIOH_PIN6) | \ + PIN_OSPEED_100M(GPIOH_PIN7) | \ + PIN_OSPEED_100M(GPIOH_PIN8) | \ + PIN_OSPEED_100M(GPIOH_PIN9) | \ + PIN_OSPEED_100M(GPIOH_PIN10) | \ + PIN_OSPEED_100M(GPIOH_PIN11) | \ + PIN_OSPEED_100M(GPIOH_PIN12) | \ + PIN_OSPEED_100M(GPIOH_PIN13) | \ + PIN_OSPEED_100M(GPIOH_PIN14) | \ + PIN_OSPEED_100M(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0)) + +/* + * GPIOI setup: + * + * PI0 - PIN0 (input floating). + * PI1 - PIN1 (input floating). + * PI2 - PIN2 (input floating). + * PI3 - PIN3 (input floating). + * PI4 - PIN4 (input floating). + * PI5 - PIN5 (input floating). + * PI6 - PIN6 (input floating). + * PI7 - PIN7 (input floating). + * PI8 - PIN8 (input floating). + * PI9 - PIN9 (input floating). + * PI10 - PIN10 (input floating). + * PI11 - PIN11 (input floating). + * PI12 - PIN12 (input floating). + * PI13 - PIN13 (input floating). + * PI14 - PIN14 (input floating). + * PI15 - PIN15 (input floating). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ + PIN_MODE_INPUT(GPIOI_PIN1) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_INPUT(GPIOI_PIN4) | \ + PIN_MODE_INPUT(GPIOI_PIN5) | \ + PIN_MODE_INPUT(GPIOI_PIN6) | \ + PIN_MODE_INPUT(GPIOI_PIN7) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_INPUT(GPIOI_PIN9) | \ + PIN_MODE_INPUT(GPIOI_PIN10) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_INPUT(GPIOI_PIN13) | \ + PIN_MODE_INPUT(GPIOI_PIN14) | \ + PIN_MODE_INPUT(GPIOI_PIN15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_100M(GPIOI_PIN0) | \ + PIN_OSPEED_100M(GPIOI_PIN1) | \ + PIN_OSPEED_100M(GPIOI_PIN2) | \ + PIN_OSPEED_100M(GPIOI_PIN3) | \ + PIN_OSPEED_100M(GPIOI_PIN4) | \ + PIN_OSPEED_100M(GPIOI_PIN5) | \ + PIN_OSPEED_100M(GPIOI_PIN6) | \ + PIN_OSPEED_100M(GPIOI_PIN7) | \ + PIN_OSPEED_100M(GPIOI_PIN8) | \ + PIN_OSPEED_100M(GPIOI_PIN9) | \ + PIN_OSPEED_100M(GPIOI_PIN10) | \ + PIN_OSPEED_100M(GPIOI_PIN11) | \ + PIN_OSPEED_100M(GPIOI_PIN12) | \ + PIN_OSPEED_100M(GPIOI_PIN13) | \ + PIN_OSPEED_100M(GPIOI_PIN14) | \ + PIN_OSPEED_100M(GPIOI_PIN15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ + PIN_ODR_HIGH(GPIOI_PIN1) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_PIN4) | \ + PIN_ODR_HIGH(GPIOI_PIN5) | \ + PIN_ODR_HIGH(GPIOI_PIN6) | \ + PIN_ODR_HIGH(GPIOI_PIN7) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_PIN9) | \ + PIN_ODR_HIGH(GPIOI_PIN10) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_PIN13) | \ + PIN_ODR_HIGH(GPIOI_PIN14) | \ + PIN_ODR_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0) | \ + PIN_AFIO_AF(GPIOI_PIN4, 0) | \ + PIN_AFIO_AF(GPIOI_PIN5, 0) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0) | \ + PIN_AFIO_AF(GPIOI_PIN13, 0) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0)) + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/base/Embest-STM32-DMSTF4BB/ChibiOS_Board/EMBEST_DMSTF4BB/board.mk b/boards/base/Embest-STM32-DMSTF4BB/ChibiOS_Board/EMBEST_DMSTF4BB/board.mk new file mode 100644 index 00000000..f39f85f1 --- /dev/null +++ b/boards/base/Embest-STM32-DMSTF4BB/ChibiOS_Board/EMBEST_DMSTF4BB/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/EMBEST_DMSTF4BB/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/EMBEST_DMSTF4BB diff --git a/boards/base/Embest-STM32-DMSTF4BB/ChibiOS_Board/EMBEST_DMSTF4BB/cfg/board.chcfg b/boards/base/Embest-STM32-DMSTF4BB/ChibiOS_Board/EMBEST_DMSTF4BB/cfg/board.chcfg new file mode 100644 index 00000000..e30de70e --- /dev/null +++ b/boards/base/Embest-STM32-DMSTF4BB/ChibiOS_Board/EMBEST_DMSTF4BB/cfg/board.chcfg @@ -0,0 +1,1186 @@ + + + + + resources/gencfg/processors/boards/stm32f4xx/templates + .. + + STMicroelectronics STM32F4-Discovery + ST_STM32F4_DISCOVERY + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/boards/base/Embest-STM32-DMSTF4BB/board.mk b/boards/base/Embest-STM32-DMSTF4BB/board.mk new file mode 100644 index 00000000..4b8448c2 --- /dev/null +++ b/boards/base/Embest-STM32-DMSTF4BB/board.mk @@ -0,0 +1,7 @@ +GFXINC += $(GFXLIB)/boards/base/Embest-STM32-DMSTF4BB +GFXSRC += +GFXDEFS += -DGFX_USE_CHIBIOS=TRUE + +include $(GFXLIB)/drivers/gdisp/SSD2119/gdisp_lld.mk +include $(GFXLIB)/drivers/ginput/touch/STMPE811/ginput_lld.mk + diff --git a/boards/addons/gdisp/board_SSD2119_embest_dmstf4bb.h b/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119_embest_dmstf4bb.h similarity index 96% rename from boards/addons/gdisp/board_SSD2119_embest_dmstf4bb.h rename to boards/base/Embest-STM32-DMSTF4BB/board_SSD2119_embest_dmstf4bb.h index 927e93a4..c6d3d040 100644 --- a/boards/addons/gdisp/board_SSD2119_embest_dmstf4bb.h +++ b/boards/base/Embest-STM32-DMSTF4BB/board_SSD2119_embest_dmstf4bb.h @@ -5,11 +5,6 @@ * http://ugfx.org/license.html */ -/** - * @file drivers/gdisp/SSD2119/board_SSD2119_embest_dmstf4bb.h - * @brief GDISP Graphic Driver subsystem board FSMC interface for the SSD2119 display. - */ - #ifndef _GDISP_LLD_BOARD_H #define _GDISP_LLD_BOARD_H diff --git a/boards/addons/ginput/touch/STMPE811/ginput_lld_mouse_board_embest_dmstf4bb.h b/boards/base/Embest-STM32-DMSTF4BB/ginput_lld_mouse_board_embest_dmstf4bb.h similarity index 67% rename from boards/addons/ginput/touch/STMPE811/ginput_lld_mouse_board_embest_dmstf4bb.h rename to boards/base/Embest-STM32-DMSTF4BB/ginput_lld_mouse_board_embest_dmstf4bb.h index a2d38d34..6eff87c9 100644 --- a/boards/addons/ginput/touch/STMPE811/ginput_lld_mouse_board_embest_dmstf4bb.h +++ b/boards/base/Embest-STM32-DMSTF4BB/ginput_lld_mouse_board_embest_dmstf4bb.h @@ -5,15 +5,6 @@ * http://ugfx.org/license.html */ -/** - * @file drivers/ginput/touch/STMPE811/ginput_lld_mouse_board_embest_dmstf4bb.h - * @brief GINPUT Touch low level driver source for the STMPE811 on the Embest DM-STF4BB board. - * - * @defgroup Mouse Mouse - * @ingroup GINPUT - * @{ - */ - #ifndef _GINPUT_LLD_MOUSE_BOARD_H #define _GINPUT_LLD_MOUSE_BOARD_H @@ -23,11 +14,6 @@ static const I2CConfig i2ccfg = { FAST_DUTY_CYCLE_2, }; -/** - * @brief Initialise the board for the touch. - * - * @notapi - */ static void init_board(void) { palSetPadMode(GPIOC, 13, PAL_MODE_INPUT | PAL_STM32_PUDR_FLOATING); /* TP IRQ */ @@ -37,25 +23,11 @@ static void init_board(void) i2cStart(&I2CD1, &i2ccfg); } -/** - * @brief Check whether an interrupt is raised - * @return TRUE if there is an interrupt signal present - * - * @notapi - */ -static inline bool_t getpin_irq(void) { +static inline bool_t getpin_irq(void) +{ return (!(palReadPad(GPIOC, 13))); } -/** - * @brief Write a value into a certain register - * - * @param[in] reg The register address - * @param[in] n The amount of bytes (one or two) - * @param[in] val The value - * - * @notapi - */ static void write_reg(uint8_t reg, uint8_t n, uint16_t val) { uint8_t txbuf[3]; @@ -76,16 +48,6 @@ static void write_reg(uint8_t reg, uint8_t n, uint16_t val) i2cReleaseBus(&I2CD1); } -/** - * @brief Read the value of a certain register - * - * @param[in] reg The register address - * @param[in] n The amount of bytes (one or two) - * - * @return Data read from device (one byte or two depending on n param) - * - * @notapi - */ static uint16_t read_reg(uint8_t reg, uint8_t n) { uint8_t txbuf[1], rxbuf[2]; @@ -123,4 +85,4 @@ static void read_reg_n(uint8_t reg, uint8_t n, uint8_t *rxbuf) } #endif /* _GINPUT_LLD_MOUSE_BOARD_H */ -/** @} */ + diff --git a/boards/base/Embest-STM32-DMSTF4BB/ginput_lld_mouse_config.h b/boards/base/Embest-STM32-DMSTF4BB/ginput_lld_mouse_config.h new file mode 100644 index 00000000..f3a89208 --- /dev/null +++ b/boards/base/Embest-STM32-DMSTF4BB/ginput_lld_mouse_config.h @@ -0,0 +1,22 @@ +/* + * This file is subject to the terms of the GFX License. If a copy of + * the license was not distributed with this file, you can obtain one at: + * + * http://ugfx.org/license.html + */ + +#ifndef _LLD_GINPUT_MOUSE_CONFIG_H +#define _LLD_GINPUT_MOUSE_CONFIG_H + +#define GINPUT_MOUSE_EVENT_TYPE GEVENT_TOUCH +#define GINPUT_MOUSE_NEED_CALIBRATION TRUE +#define GINPUT_MOUSE_LLD_CALIBRATION_LOADSAVE FALSE +#define GINPUT_MOUSE_MAX_CALIBRATION_ERROR 12 +#define GINPUT_MOUSE_READ_CYCLES 4 +#define GINPUT_MOUSE_POLL_PERIOD 3 +#define GINPUT_MOUSE_MAX_CLICK_JITTER 2 +#define GINPUT_MOUSE_MAX_MOVE_JITTER 2 +#define GINPUT_MOUSE_CLICK_TIME 500 + +#endif /* _LLD_GINPUT_MOUSE_CONFIG_H */ +