Improving STM32F746G-Discovery board files
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025bc66666
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2 changed files with 68 additions and 112 deletions
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@ -1,112 +1,67 @@
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#include "../../../gfx.h"
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#undef Red
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#undef Green
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#undef Blue
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#include "stm32f7xx_hal.h"
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#if GFX_USE_OS_CHIBIOS
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#define HAL_GPIO_Init(port, ptr) palSetGroupMode(port, (ptr)->Pin, 0, (ptr)->Mode|((ptr)->Speed<<3)|((ptr)->Pull<<5)|((ptr)->Alternate<<7))
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#else
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systemticks_t gfxSystemTicks(void)
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{
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return HAL_GetTick();
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}
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systemticks_t gfxMillisecondsToTicks(delaytime_t ms)
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{
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return ms;
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}
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#endif
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static void SystemClock_Config(void);
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void Raw32OSInit(void) {
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/* Enable the CPU Cache's */
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SCB_EnableICache(); // Enable I-Cache
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SCB_EnableDCache(); // Enable D-Cache
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/* STM32F7xx HAL library initialization:
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- Configure the Flash ART accelerator on ITCM interface
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- Configure the Systick to generate an interrupt each 1 msec
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- Set NVIC Group Priority to 4
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- Global MSP (MCU Support Package) initialization
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*/
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HAL_Init();
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/* Configure the system clock to 216 MHz */
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SystemClock_Config();
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#if !GFX_USE_OS_CHIBIOS
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// LED - for testing
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GPIO_InitTypeDef GPIO_InitStruct;
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GPIO_InitStruct.Pin = GPIO_PIN_1;
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GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
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__GPIOI_CLK_ENABLE();
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HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
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#endif
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}
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/**
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* @brief System Clock Configuration
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* The system Clock is configured as follow :
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* System Clock source = PLL (HSE)
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* SYSCLK(Hz) = 200000000 / 216000000
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* HCLK(Hz) = 200000000 / 216000000
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* AHB Prescaler = 1
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* APB1 Prescaler = 4
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* APB2 Prescaler = 2
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* HSE Frequency(Hz) = 25000000
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* PLL_M = 25
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* PLL_N = 400 / 432
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* PLL_P = 2
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* PLL_Q = 8 / 9
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* VDD(V) = 3.3
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* Main regulator output voltage = Scale1 mode
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* Flash Latency(WS) = 6 / 7
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* @param None
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* @retval None
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*/
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void SystemClock_Config(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct;
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
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__PWR_CLK_ENABLE();
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSICalibrationValue = 16;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 12;
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RCC_OscInitStruct.PLL.PLLN = 192;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = 2;
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HAL_RCC_OscConfig(&RCC_OscInitStruct);
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HAL_PWREx_ActivateOverDrive();
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
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HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6);
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C1;
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PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
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HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
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HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
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HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
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}
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#include "../../../gfx.h"
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#undef Red
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#undef Green
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#undef Blue
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#include "stm32f7xx_hal.h"
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#if GFX_USE_OS_CHIBIOS
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#define HAL_GPIO_Init(port, ptr) palSetGroupMode(port, (ptr)->Pin, 0, (ptr)->Mode|((ptr)->Speed<<3)|((ptr)->Pull<<5)|((ptr)->Alternate<<7))
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#else
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systemticks_t gfxSystemTicks(void)
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{
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return HAL_GetTick();
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}
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systemticks_t gfxMillisecondsToTicks(delaytime_t ms)
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{
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return ms;
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}
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#endif
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void SystemClock_Config(void)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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RCC_OscInitTypeDef RCC_OscInitStruct;
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/* Enable HSE Oscillator and activate PLL with HSE as source */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 25;
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RCC_OscInitStruct.PLL.PLLN = 432;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = 9;
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HAL_RCC_OscConfig(&RCC_OscInitStruct);
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/* Activate the OverDrive to reach the 216 MHz Frequency */
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HAL_PWREx_EnableOverDrive();
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/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
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HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
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}
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void Raw32OSInit(void)
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{
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/* Enable the CPU Cache's */
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SCB_EnableICache(); // Enable I-Cache
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SCB_EnableDCache(); // Enable D-Cache
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/* STM32F7xx HAL library initialization:
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- Configure the Flash ART accelerator on ITCM interface
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- Configure the Systick to generate an interrupt each 1 msec
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- Set NVIC Group Priority to 4
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- Global MSP (MCU Support Package) initialization
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*/
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HAL_Init();
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/* Configure the system clock to 216 MHz */
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SystemClock_Config();
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}
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@ -64,6 +64,7 @@ FEATURE: Added nullpointer checks to GDISP image functions (with new error co
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FIX: Add cache flushing to the ChibiOS FATFS/PETITFS block drivers. Needed for STM32F7 chips. This should really be in the ChibiOS DMA routines.
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FIX: Add cache flushing to enable DMA2D accelerated bitblits in the STM32LTDC driver on the STM32F7 cpu.
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FIX: Improved STM32F469i-Discovery board support.
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FIX: Improved STM32F746G-Discovery board support.
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*** Release 2.7 ***
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