uGFX
/
ugfx
2
0
Fork 0
Code Issues 2 Pull Requests Projects Releases Wiki Activity

Improving STM32F746G-Discovery board files

release/v2.9
Joel Bodenmann 2017-10-28 15:28:31 +02:00
parent 025bc66666
commit a5c1e29d21
2 changed files with 68 additions and 112 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

179
boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c
View File

@ -1,112 +1,67 @@
#include "../../../gfx.h" #include "../../../gfx.h"
#undef Red #undef Red
#undef Green #undef Green
#undef Blue #undef Blue
#include "stm32f7xx_hal.h" #include "stm32f7xx_hal.h"
#if GFX_USE_OS_CHIBIOS #if GFX_USE_OS_CHIBIOS
#define HAL_GPIO_Init(port, ptr) palSetGroupMode(port, (ptr)->Pin, 0, (ptr)->Mode|((ptr)->Speed<<3)|((ptr)->Pull<<5)|((ptr)->Alternate<<7)) #define HAL_GPIO_Init(port, ptr) palSetGroupMode(port, (ptr)->Pin, 0, (ptr)->Mode|((ptr)->Speed<<3)|((ptr)->Pull<<5)|((ptr)->Alternate<<7))
#else #else
systemticks_t gfxSystemTicks(void) systemticks_t gfxSystemTicks(void)
{ {
return HAL_GetTick(); return HAL_GetTick();
} }
systemticks_t gfxMillisecondsToTicks(delaytime_t ms) systemticks_t gfxMillisecondsToTicks(delaytime_t ms)
{ {
return ms; return ms;
} }
#endif #endif
static void SystemClock_Config(void); void SystemClock_Config(void)
{
void Raw32OSInit(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct;
/* Enable the CPU Cache's */ RCC_OscInitTypeDef RCC_OscInitStruct;
SCB_EnableICache(); // Enable I-Cache
SCB_EnableDCache(); // Enable D-Cache /* Enable HSE Oscillator and activate PLL with HSE as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
/* STM32F7xx HAL library initialization: RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
- Configure the Flash ART accelerator on ITCM interface RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
- Configure the Systick to generate an interrupt each 1 msec RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
- Set NVIC Group Priority to 4 RCC_OscInitStruct.PLL.PLLM = 25;
- Global MSP (MCU Support Package) initialization RCC_OscInitStruct.PLL.PLLN = 432;
*/ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
HAL_Init(); RCC_OscInitStruct.PLL.PLLQ = 9;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
/* Configure the system clock to 216 MHz */
SystemClock_Config(); /* Activate the OverDrive to reach the 216 MHz Frequency */
HAL_PWREx_EnableOverDrive();
#if !GFX_USE_OS_CHIBIOS
// LED - for testing /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
GPIO_InitTypeDef GPIO_InitStruct; RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
GPIO_InitStruct.Pin = GPIO_PIN_1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
GPIO_InitStruct.Pull = GPIO_NOPULL; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
GPIO_InitStruct.Speed = GPIO_SPEED_FAST; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
__GPIOI_CLK_ENABLE(); HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); }
#endif
void Raw32OSInit(void)
} {
/* Enable the CPU Cache's */
/** SCB_EnableICache(); // Enable I-Cache
* @brief System Clock Configuration SCB_EnableDCache(); // Enable D-Cache
* The system Clock is configured as follow :
* System Clock source = PLL (HSE)
* SYSCLK(Hz) = 200000000 / 216000000 /* STM32F7xx HAL library initialization:
* HCLK(Hz) = 200000000 / 216000000 - Configure the Flash ART accelerator on ITCM interface
* AHB Prescaler = 1 - Configure the Systick to generate an interrupt each 1 msec
* APB1 Prescaler = 4 - Set NVIC Group Priority to 4
* APB2 Prescaler = 2 - Global MSP (MCU Support Package) initialization
* HSE Frequency(Hz) = 25000000 */
* PLL_M = 25 HAL_Init();
* PLL_N = 400 / 432
* PLL_P = 2 /* Configure the system clock to 216 MHz */
* PLL_Q = 8 / 9 SystemClock_Config();
* VDD(V) = 3.3 }
* Main regulator output voltage = Scale1 mode
* Flash Latency(WS) = 6 / 7
* @param None
* @retval None
*/
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
__PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSICalibrationValue = 16;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 12;
RCC_OscInitStruct.PLL.PLLN = 192;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 2;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
HAL_PWREx_ActivateOverDrive();
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6);
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C1;
PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
}

1
changelog.txt
View File

@ -64,6 +64,7 @@ FEATURE: Added nullpointer checks to GDISP image functions (with new error co
FIX: Add cache flushing to the ChibiOS FATFS/PETITFS block drivers. Needed for STM32F7 chips. This should really be in the ChibiOS DMA routines. FIX: Add cache flushing to the ChibiOS FATFS/PETITFS block drivers. Needed for STM32F7 chips. This should really be in the ChibiOS DMA routines.
FIX: Add cache flushing to enable DMA2D accelerated bitblits in the STM32LTDC driver on the STM32F7 cpu. FIX: Add cache flushing to enable DMA2D accelerated bitblits in the STM32LTDC driver on the STM32F7 cpu.
FIX: Improved STM32F469i-Discovery board support. FIX: Improved STM32F469i-Discovery board support.
FIX: Improved STM32F746G-Discovery board support.
*** Release 2.7 *** *** Release 2.7 ***