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Updates to standard STM32LTDC based boards to ensure the LTDC clock is fully operational before continuing

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This commit is contained in:
inmarket 2018-02-24 11:49:30 +10:00
parent 891b78a62c
commit aeef03a83e
4 changed files with 16 additions and 12 deletions
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1
boards/base/STM32F429i-Discovery/chibios/board_STM32LTDC.h
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@ -189,6 +189,7 @@ static void init_board(GDisplay *g) {
RCC->PLLSAICFGR = (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24);
RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST;
RCC->CR |= RCC_CR_PLLSAION;
while(!(RCC->CR & RCC_CR_PLLSAIRDY)); // wait for PLLSAI to lock
// Initialise the SDRAM
SDRAM_Init();

1
boards/base/STM32F439i-Eval/CubeHal/board_STM32LTDC.h
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@ -89,6 +89,7 @@ static void configureLcdClock(void)
RCC->PLLSAICFGR = (LCD_PLLSAIN_VALUE << 6) | (LCD_PLLSAIR_VALUE << 28) | (LCD_PLLSAIQ_VALUE << 24);
RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | LCD_PLLSAIDIVR_VALUE;
RCC->CR |= RCC_CR_PLLSAION;
while(!(RCC->CR & RCC_CR_PLLSAIRDY)); // wait for PLLSAI to lock
#endif
}

1
boards/base/STM32F469i-Discovery/CubeHAL/board_STM32LTDC.h
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@ -104,6 +104,7 @@ static GFXINLINE void init_board(GDisplay *g) {
RCC->PLLSAICFGR = (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24);
RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST;
RCC->CR |= RCC_CR_PLLSAION;
while(!(RCC->CR & RCC_CR_PLLSAIRDY)); // wait for PLLSAI to lock
#endif
__HAL_RCC_DSI_CLK_ENABLE();

1
boards/base/STM32F746-Discovery/board_STM32LTDC.h
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@ -450,6 +450,7 @@ static GFXINLINE void init_board(GDisplay *g) {
RCC->PLLSAICFGR = ((STM32_PLLSAIP_VALUE/2-1)<<16) | (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24);
RCC->DCKCFGR1 = (RCC->DCKCFGR1 & ~RCC_DCKCFGR1_PLLSAIDIVR) | STM32_PLLSAIR_POST;
RCC->CR |= RCC_CR_PLLSAION;
while(!(RCC->CR & RCC_CR_PLLSAIRDY)); // wait for PLLSAI to lock
#endif
// Initialise the SDRAM