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Board STM32F746-Discovery: Fix rouge-ly replaced types

develop
Joel Bodenmann 2021-08-12 20:08:02 +02:00
parent 346375c001
commit beb815e109
1 changed files with 11 additions and 11 deletions
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22
boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c
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@ -66,11 +66,11 @@
#include "stm32f7xx.h" #include "stm32f7xx.h"
#if !defined (HSE_VALUE) #if !defined (HSE_VALUE)
#define HSE_VALUE ((gU32)25000000) /*!< Default value of the External oscillator in Hz */ #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
#endif /* HSE_VALUE */ #endif /* HSE_VALUE */
#if !defined (HSI_VALUE) #if !defined (HSI_VALUE)
#define HSI_VALUE ((gU32)16000000) /*!< Value of the Internal oscillator in Hz*/ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */ #endif /* HSI_VALUE */
/** /**
@ -125,9 +125,9 @@
is no need to call the 2 first functions listed above, since SystemCoreClock is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically. variable is updated automatically.
*/ */
gU32 SystemCoreClock = 16000000; uint32_t SystemCoreClock = 16000000;
const gU8 AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const gU8 APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/** /**
* @} * @}
@ -163,19 +163,19 @@ void SystemInit(void)
#endif #endif
/* Reset the RCC clock configuration to the default reset state ------------*/ /* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */ /* Set HSION bit */
RCC->CR |= (gU32)0x00000001; RCC->CR |= (uint32_t)0x00000001;
/* Reset CFGR register */ /* Reset CFGR register */
RCC->CFGR = 0x00000000; RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */ /* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (gU32)0xFEF6FFFF; RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset PLLCFGR register */ /* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010; RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */ /* Reset HSEBYP bit */
RCC->CR &= (gU32)0xFFFBFFFF; RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Disable all interrupts */ /* Disable all interrupts */
RCC->CIR = 0x00000000; RCC->CIR = 0x00000000;
@ -230,7 +230,7 @@ void SystemInit(void)
*/ */
void SystemCoreClockUpdate(void) void SystemCoreClockUpdate(void)
{ {
gU32 tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/ /* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS; tmp = RCC->CFGR & RCC_CFGR_SWS;
@ -287,8 +287,8 @@ void SystemCoreClockUpdate(void)
*/ */
void SystemInit_ExtMemCtl(void) void SystemInit_ExtMemCtl(void)
{ {
register gU32 tmpreg = 0, timeout = 0xFFFF; register uint32_t tmpreg = 0, timeout = 0xFFFF;
register __IO gU32 index; register __IO uint32_t index;
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG and GPIOH interface /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG and GPIOH interface
clock */ clock */