Some more work on the F7 discovery
Joel Bodenmann
parent
c58dabc9c9
commit
d4f2cb0d72
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@ -1,5 +1,5 @@
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GFXINC += $(GFXLIB)/boards/base/STM32F746-Discovery
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GFXSRC += $(GFXLIB)/boards/base/STM32F746-Discovery/STM32F746_discovery_sdram.c \
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$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f4xx_fmc.c
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GFXSRC += $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c \
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$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c
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include $(GFXLIB)/drivers/gdisp/STM32LTDC/driver.mk
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@ -8,8 +8,8 @@
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#ifndef _GDISP_LLD_BOARD_H
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#define _GDISP_LLD_BOARD_H
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#include "stm32f4xx_fmc.h"
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#include "stm32f429i_discovery_sdram.h"
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#include "stm32f7xx_ll_fmc.h"
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#include "stm32f746g_discovery_sdram.h"
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#include <string.h>
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static const ltdcConfig driverCfg = {
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@ -1,333 +0,0 @@
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#include "ch.h"
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#include "hal.h"
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#include "stm32f429i_discovery_sdram.h"
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#include "stm32f4xx_fmc.h"
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/**
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* @brief Configures the FMC and GPIOs to interface with the SDRAM memory.
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* This function must be called before any read/write operation
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* on the SDRAM.
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* @param None
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* @retval None
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*/
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void SDRAM_Init(void)
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{
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FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure;
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FMC_SDRAMTimingInitTypeDef FMC_SDRAMTimingInitStructure;
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/* Enable FMC clock */
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rccEnableAHB3(RCC_AHB3ENR_FMCEN, FALSE);
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/* FMC Configuration ---------------------------------------------------------*/
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/* FMC SDRAM Bank configuration */
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/* Timing configuration for 84 Mhz of SD clock frequency (168Mhz/2) */
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/* TMRD: 2 Clock cycles */
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FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;
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/* TXSR: min=70ns (6x11.90ns) */
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FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 7;
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/* TRAS: min=42ns (4x11.90ns) max=120k (ns) */
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FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;
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/* TRC: min=63 (6x11.90ns) */
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FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 7;
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/* TWR: 2 Clock cycles */
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FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;
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/* TRP: 15ns => 2x11.90ns */
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FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;
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/* TRCD: 15ns => 2x11.90ns */
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FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;
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/* FMC SDRAM control configuration */
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FMC_SDRAMInitStructure.FMC_Bank = FMC_Bank2_SDRAM;
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/* Row addressing: [7:0] */
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FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
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/* Column addressing: [11:0] */
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FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_12b;
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FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = SDRAM_MEMORY_WIDTH;
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FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
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FMC_SDRAMInitStructure.FMC_CASLatency = SDRAM_CAS_LATENCY;
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FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
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FMC_SDRAMInitStructure.FMC_SDClockPeriod = SDCLOCK_PERIOD;
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FMC_SDRAMInitStructure.FMC_ReadBurst = SDRAM_READBURST;
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FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;
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FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
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/* FMC SDRAM bank initialization */
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FMC_SDRAMInit(&FMC_SDRAMInitStructure);
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/* FMC SDRAM device initialization sequence */
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SDRAM_InitSequence();
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}
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/*-- GPIOs Configuration -----------------------------------------------------*/
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/*
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+-------------------+--------------------+--------------------+--------------------+
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+ SDRAM pins assignment +
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+-------------------+--------------------+--------------------+--------------------+
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| PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 |
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| PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 |
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| PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF2 <-> FMC_A2 | PG8 <-> FMC_SDCLK |
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| PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF3 <-> FMC_A3 | PG15 <-> FMC_NCAS |
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| PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF4 <-> FMC_A4 |--------------------+
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| PD14 <-> FMC_D0 | PE10 <-> FMC_D7 | PF5 <-> FMC_A5 |
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| PD15 <-> FMC_D1 | PE11 <-> FMC_D8 | PF11 <-> FMC_NRAS |
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+-------------------| PE12 <-> FMC_D9 | PF12 <-> FMC_A6 |
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| PE13 <-> FMC_D10 | PF13 <-> FMC_A7 |
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| PE14 <-> FMC_D11 | PF14 <-> FMC_A8 |
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| PE15 <-> FMC_D12 | PF15 <-> FMC_A9 |
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+-------------------+--------------------+--------------------+
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| PB5 <-> FMC_SDCKE1|
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| PB6 <-> FMC_SDNE1 |
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| PC0 <-> FMC_SDNWE |
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+-------------------+
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*/
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// /* Common GPIO configuration */
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// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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// GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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// GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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//
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// /* GPIOB configuration */
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// GPIO_PinAFConfig(GPIOB, GPIO_PinSource5 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOB, GPIO_PinSource6 , GPIO_AF_FMC);
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//
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// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6;
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//
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// GPIO_Init(GPIOB, &GPIO_InitStructure);
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//
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// /* GPIOC configuration */
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// GPIO_PinAFConfig(GPIOC, GPIO_PinSource0 , GPIO_AF_FMC);
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//
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// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
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//
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// GPIO_Init(GPIOC, &GPIO_InitStructure);
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//
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// /* GPIOD configuration */
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// GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FMC);
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//
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// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 |
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// GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 |
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// GPIO_Pin_15;
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//
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// GPIO_Init(GPIOD, &GPIO_InitStructure);
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//
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// /* GPIOE configuration */
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// GPIO_PinAFConfig(GPIOE, GPIO_PinSource0 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOE, GPIO_PinSource1 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FMC);
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//
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// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_7 |
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// GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
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// GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
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// GPIO_Pin_14 | GPIO_Pin_15;
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//
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// GPIO_Init(GPIOE, &GPIO_InitStructure);
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//
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// /* GPIOF configuration */
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// GPIO_PinAFConfig(GPIOF, GPIO_PinSource0 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOF, GPIO_PinSource1 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOF, GPIO_PinSource2 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOF, GPIO_PinSource3 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOF, GPIO_PinSource4 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOF, GPIO_PinSource5 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOF, GPIO_PinSource11 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOF, GPIO_PinSource12 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOF, GPIO_PinSource13 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOF, GPIO_PinSource14 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOF, GPIO_PinSource15 , GPIO_AF_FMC);
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//
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// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 |
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// GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 |
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// GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
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// GPIO_Pin_14 | GPIO_Pin_15;
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//
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// GPIO_Init(GPIOF, &GPIO_InitStructure);
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//
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// /* GPIOG configuration */
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// GPIO_PinAFConfig(GPIOG, GPIO_PinSource0 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOG, GPIO_PinSource1 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOG, GPIO_PinSource4 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOG, GPIO_PinSource5 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOG, GPIO_PinSource8 , GPIO_AF_FMC);
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// GPIO_PinAFConfig(GPIOG, GPIO_PinSource15 , GPIO_AF_FMC);
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//
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//
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// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 |
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// GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_15;
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//
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// GPIO_Init(GPIOG, &GPIO_InitStructure);
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/**
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* @brief Executes the SDRAM memory initialization sequence.
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* @param None.
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* @retval None.
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*/
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void SDRAM_InitSequence(void)
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{
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FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
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uint32_t tmpr = 0;
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/* Step 3 --------------------------------------------------------------------*/
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/* Configure a clock configuration enable command */
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FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled;
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FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
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FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
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FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
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/* Wait until the SDRAM controller is ready */
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while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
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{
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}
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/* Send the command */
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FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
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//In the ST example, this is 100ms, but the 429 RM says 100us is typical, and
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//the ISSI datasheet confirms this. 1ms seems plenty, and is much shorter than
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//refresh interval, meaning we won't risk losing contents if the SDRAM is in self-refresh
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//mode
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/* Step 4 --------------------------------------------------------------------*/
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/* Insert 1 ms delay */
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chThdSleepMilliseconds(1);
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/* Step 5 --------------------------------------------------------------------*/
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/* Configure a PALL (precharge all) command */
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FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL;
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FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
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FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
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FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
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/* Wait until the SDRAM controller is ready */
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while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
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{
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}
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/* Send the command */
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FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
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/* Step 6 --------------------------------------------------------------------*/
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/* Configure a Auto-Refresh command */
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FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh;
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FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
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FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 4;
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FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
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/* Wait until the SDRAM controller is ready */
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while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
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{
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}
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/* Send the first command */
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FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
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/* Wait until the SDRAM controller is ready */
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while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
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{
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}
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/* Send the second command */
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FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
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/* Step 7 --------------------------------------------------------------------*/
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/* Program the external memory mode register */
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tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 |
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SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
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SDRAM_MODEREG_CAS_LATENCY_3 |
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SDRAM_MODEREG_OPERATING_MODE_STANDARD |
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SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
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/* Configure a load Mode register command*/
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FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode;
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FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
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FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
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FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr;
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/* Wait until the SDRAM controller is ready */
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while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
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{
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}
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/* Send the command */
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FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
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/* Step 8 --------------------------------------------------------------------*/
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/* Set the refresh rate counter */
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/* (7.81 us x Freq) - 20 */
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/* Set the device refresh counter */
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FMC_SetRefreshCount(683);
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/* Wait until the SDRAM controller is ready */
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while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
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{
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}
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}
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/**
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* @brief Writes a Entire-word buffer to the SDRAM memory.
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* @param pBuffer: pointer to buffer.
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* @param uwWriteAddress: SDRAM memory internal address from which the data will be
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* written.
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* @param uwBufferSize: number of words to write.
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* @retval None.
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*/
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void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize)
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{
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__IO uint32_t write_pointer = (uint32_t)uwWriteAddress;
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/* Disable write protection */
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FMC_SDRAMWriteProtectionConfig(FMC_Bank2_SDRAM, DISABLE);
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/* Wait until the SDRAM controller is ready */
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while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
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{
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}
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/* While there is data to write */
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for (; uwBufferSize != 0; uwBufferSize--)
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{
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/* Transfer data to the memory */
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*(uint32_t *) (SDRAM_BANK_ADDR + write_pointer) = *pBuffer++;
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/* Increment the address*/
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write_pointer += 4;
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}
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}
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/**
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* @brief Reads data buffer from the SDRAM memory.
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* @param pBuffer: pointer to buffer.
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* @param ReadAddress: SDRAM memory internal address from which the data will be
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* read.
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* @param uwBufferSize: number of words to write.
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* @retval None.
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*/
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void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize)
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{
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__IO uint32_t write_pointer = (uint32_t)uwReadAddress;
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/* Wait until the SDRAM controller is ready */
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while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
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{
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}
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/* Read data */
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for(; uwBufferSize != 0x00; uwBufferSize--)
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{
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*pBuffer++ = *(__IO uint32_t *)(SDRAM_BANK_ADDR + write_pointer );
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/* Increment the address*/
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write_pointer += 4;
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}
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}
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@ -1,96 +0,0 @@
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/**
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******************************************************************************
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* @file stm32f429i_discovery_sdram.h
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* @author MCD Application Team
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* @version V1.0.0
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* @date 20-September-2013
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* @brief This file contains all the functions prototypes for the
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* stm324x9i_disco_sdram.c driver.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
|
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
|
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32429I_DISCO_SDRAM_H
|
||||
#define __STM32429I_DISCO_SDRAM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
//FIXME this should not be needed
|
||||
#define STM32F429_439xx
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/**
|
||||
* @brief FMC SDRAM Bank address
|
||||
*/
|
||||
#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000)
|
||||
|
||||
/**
|
||||
* @brief FMC SDRAM Memory Width
|
||||
*/
|
||||
/* #define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_8b */
|
||||
#define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_16b
|
||||
|
||||
/**
|
||||
* @brief FMC SDRAM CAS Latency
|
||||
*/
|
||||
/* #define SDRAM_CAS_LATENCY FMC_CAS_Latency_2 */
|
||||
#define SDRAM_CAS_LATENCY FMC_CAS_Latency_3
|
||||
|
||||
/**
|
||||
* @brief FMC SDRAM Memory clock period
|
||||
*/
|
||||
#define SDCLOCK_PERIOD FMC_SDClock_Period_2 /* Default configuration used with LCD */
|
||||
/* #define SDCLOCK_PERIOD FMC_SDClock_Period_3 */
|
||||
|
||||
/**
|
||||
* @brief FMC SDRAM Memory Read Burst feature
|
||||
*/
|
||||
#define SDRAM_READBURST FMC_Read_Burst_Disable /* Default configuration used with LCD */
|
||||
/* #define SDRAM_READBURST FMC_Read_Burst_Enable */
|
||||
|
||||
/**
|
||||
* @brief FMC SDRAM Mode definition register defines
|
||||
*/
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
|
||||
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
|
||||
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
|
||||
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
|
||||
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
|
||||
|
||||
void SDRAM_Init(void);
|
||||
void SDRAM_InitSequence(void);
|
||||
void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize);
|
||||
void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -76,7 +76,7 @@
|
|||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32746g_discovery_sdram.h"
|
||||
#include "stm32f746g_discovery_sdram.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
|
|
@ -34,44 +34,46 @@
|
|||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32746G_DISCOVERY_SDRAM_H
|
||||
#define __STM32746G_DISCOVERY_SDRAM_H
|
||||
#ifndef __STM32F746G_DISCOVERY_SDRAM_H
|
||||
#define __STM32F746G_DISCOVERY_SDRAM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal.h"
|
||||
#include "stm32f7xx_hal_sdram.h"
|
||||
#include "stm32f7xx_hal_dma.h"
|
||||
#include "stm32f7xx_ll_fmc.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32746G_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup STM32746G_DISCOVERY_SDRAM
|
||||
* @{
|
||||
*/
|
||||
*/
|
||||
|
||||
/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Types STM32746G_DISCOVERY_SDRAM Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SDRAM status structure definition
|
||||
*/
|
||||
/**
|
||||
* @brief SDRAM status structure definition
|
||||
*/
|
||||
#define SDRAM_OK ((uint8_t)0x00)
|
||||
#define SDRAM_ERROR ((uint8_t)0x01)
|
||||
|
||||
/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Constants STM32746G_DISCOVERY_SDRAM Exported Constants
|
||||
* @{
|
||||
*/
|
||||
*/
|
||||
#define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000)
|
||||
#define SDRAM_DEVICE_SIZE ((uint32_t)0x800000) /* SDRAM device size in MBytes */
|
||||
|
||||
|
|
@ -79,23 +81,23 @@
|
|||
#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16
|
||||
|
||||
#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2
|
||||
/* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */
|
||||
/* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */
|
||||
|
||||
#define REFRESH_COUNT ((uint32_t)0x0603) /* SDRAM refresh counter (100Mhz SD clock) */
|
||||
|
||||
|
||||
#define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
|
||||
|
||||
/* DMA definitions for SDRAM DMA transfer */
|
||||
#define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
|
||||
#define __DMAx_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
|
||||
#define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0
|
||||
#define SDRAM_DMAx_STREAM DMA2_Stream0
|
||||
#define SDRAM_DMAx_STREAM DMA2_Stream0
|
||||
#define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn
|
||||
#define SDRAM_DMAx_IRQHandler DMA2_Stream0_IRQHandler
|
||||
#define SDRAM_DMAx_IRQHandler DMA2_Stream0_IRQHandler
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FMC SDRAM Mode definition register defines
|
||||
*/
|
||||
|
|
@ -108,22 +110,22 @@
|
|||
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
|
||||
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
|
||||
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
*/
|
||||
|
||||
/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Macro STM32746G_DISCOVERY_SDRAM Exported Macro
|
||||
* @{
|
||||
*/
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32746G_DISCOVERY_SDRAM_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
*/
|
||||
uint8_t BSP_SDRAM_Init(void);
|
||||
uint8_t BSP_SDRAM_DeInit(void);
|
||||
void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount);
|
||||
|
|
@ -132,8 +134,8 @@ uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_
|
|||
uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
|
||||
uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
|
||||
uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
|
||||
void BSP_SDRAM_DMA_IRQHandler(void);
|
||||
|
||||
void BSP_SDRAM_DMA_IRQHandler(void);
|
||||
|
||||
/* These functions can be modified in case the current settings (e.g. DMA stream)
|
||||
need to be changed for specific application needs */
|
||||
void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params);
|
||||
|
|
@ -142,19 +144,19 @@ void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params);
|
|||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
Loading…
Reference in New Issue