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ssd1289 GPIO interface abstraction

ugfx_release_2.6
Tectu 2012-06-24 17:37:33 +02:00
parent 73e0021db2
commit ed70b3acc4
2 changed files with 16 additions and 6 deletions
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6
drivers/lcd/ssd1289_lld.c
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@ -9,8 +9,10 @@ extern uint16_t lcd_width, lcd_height;
#ifdef LCD_USE_GPIO
static __inline lld_lcdWriteGPIO(uint16_t d) {
LCD_DATA_PORT_1->BSRR = (((~d >> 8) << 16) | (d >> 8) << LCD_DATA_PORT_1_BASE);
LCD_DATA_PORT_2->BSRR = (((~d & 0xFF) << 16) | (d & 0xFF) << LCD_DATA_PORT_2_BASE);
LCD_DATA_PORT_1->BSRR = ((((~d >> 12 & 0xF) << 16) | (d >> 12 & 0xF)) << LCD_DATA_PORT_1_BASE);
LCD_DATA_PORT_2->BSRR = ((((~d >> 8 & 0xF) << 16) | (d >> 8 & 0xF)) << LCD_DATA_PORT_2_BASE);
LCD_DATA_PORT_3->BSRR = ((((~d >> 4 & 0xF) << 16) | (d >> 4 & 0xF)) << LCD_DATA_PORT_3_BASE);
LCD_DATA_PORT_4->BSRR = ((((~d >> 0 & 0xF) << 16) | (d >> 0 & 0xF)) << LCD_DATA_PORT_4_BASE);
}
static __inline void lld_lcdWriteIndex(uint16_t index) {

16
readme
View File

@ -11,16 +11,24 @@ add the following to your board.h file, matching to your pinconfig:
#define TP_CS 6
#define LCD_DATA_PORT_1 GPIOB
#define LCD_DATA_PORT_2 GPIOC
#define LCD_DATA_PORT_1_BASE 8
#define LCD_DATA_PORT_2_BASE 0
#define LCD_DATA_PORT_2 GPIOB
#define LCD_DATA_PORT_3 GPIOC
#define LCD_DATA_PORT_4 GPIOE
#define LCD_DATA_PORT_1_BASE 12
#define LCD_DATA_PORT_2_BASE 8
#define LCD_DATA_PORT_3_BASE 4
#define LCD_DATA_PORT_4_BASE 0
#define LCD_CMD_PORT GPIOD
#define LCD_CS 12
#define LCD_RS 13
#define LCD_WR 14
#define LCD_RD 15
in this example, we use GPIOC[0:7] for DB[0:7] and GPIOB[8:15] for DB[8:15]
in this example we use the following pin config for 16-bit GPIO interfacing:
GPIOB 8-15
GPIOC 4-7
GPIOE 0-3
### Edit Makefile:
include lcd.mk: