Updating STM32F746-Discovery board files to be compatible with newer STM32F7CubeHAL
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@ -2,13 +2,13 @@
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******************************************************************************
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* @file stm32f7xx_hal_conf.h
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* @author MCD Application Team
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* @version V1.0.0
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* @date 25-June-2015
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* @version V1.0.3
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* @date 22-April-2016
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* @brief HAL configuration file.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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@ -51,46 +51,46 @@
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* @brief This is the list of modules to be used in the HAL driver
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*/
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#define HAL_MODULE_ENABLED
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/* #define HAL_ADC_MODULE_ENABLED */
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/* #define HAL_CAN_MODULE_ENABLED */
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/* #define HAL_CEC_MODULE_ENABLED */
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/* #define HAL_CRC_MODULE_ENABLED */
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/* #define HAL_CRYP_MODULE_ENABLED */
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/* #define HAL_DAC_MODULE_ENABLED */
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/* #define HAL_DCMI_MODULE_ENABLED */
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//#define HAL_ADC_MODULE_ENABLED
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//#define HAL_CAN_MODULE_ENABLED
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//#define HAL_CEC_MODULE_ENABLED
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//#define HAL_CRC_MODULE_ENABLED
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//#define HAL_CRYP_MODULE_ENABLED
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//#define HAL_DAC_MODULE_ENABLED
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//#define HAL_DCMI_MODULE_ENABLED
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#define HAL_DMA_MODULE_ENABLED
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/* #define HAL_DMA2D_MODULE_ENABLED */
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/* #define HAL_ETH_MODULE_ENABLED */
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//#define HAL_DMA2D_MODULE_ENABLED
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//#define HAL_ETH_MODULE_ENABLED
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#define HAL_FLASH_MODULE_ENABLED
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/* #define HAL_NAND_MODULE_ENABLED */
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/* #define HAL_NOR_MODULE_ENABLED */
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/* #define HAL_SRAM_MODULE_ENABLED */
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//#define HAL_NAND_MODULE_ENABLED
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//#define HAL_NOR_MODULE_ENABLED
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//#define HAL_SRAM_MODULE_ENABLED
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//#define HAL_SDRAM_MODULE_ENABLED
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/* #define HAL_HASH_MODULE_ENABLED */
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//#define HAL_HASH_MODULE_ENABLED
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#define HAL_GPIO_MODULE_ENABLED
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/* #define HAL_I2C_MODULE_ENABLED */
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/* #define HAL_I2S_MODULE_ENABLED */
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/* #define HAL_IWDG_MODULE_ENABLED */
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/* #define HAL_LPTIM_MODULE_ENABLED */
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/* #define HAL_LTDC_MODULE_ENABLED */
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//#define HAL_I2C_MODULE_ENABLED
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//#define HAL_I2S_MODULE_ENABLED
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//#define HAL_IWDG_MODULE_ENABLED
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//#define HAL_LPTIM_MODULE_ENABLED
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//#define HAL_LTDC_MODULE_ENABLED
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#define HAL_PWR_MODULE_ENABLED
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/* #define HAL_QSPI_MODULE_ENABLED */
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//#define HAL_QSPI_MODULE_ENABLED
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#define HAL_RCC_MODULE_ENABLED
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/* #define HAL_RNG_MODULE_ENABLED */
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/* #define HAL_RTC_MODULE_ENABLED */
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/* #define HAL_SAI_MODULE_ENABLED */
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/* #define HAL_SD_MODULE_ENABLED */
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/* #define HAL_SPDIFRX_MODULE_ENABLED */
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/* #define HAL_SPI_MODULE_ENABLED */
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/* #define HAL_TIM_MODULE_ENABLED */
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/* #define HAL_UART_MODULE_ENABLED */
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/* #define HAL_USART_MODULE_ENABLED */
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/* #define HAL_IRDA_MODULE_ENABLED */
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/* #define HAL_SMARTCARD_MODULE_ENABLED */
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/* #define HAL_WWDG_MODULE_ENABLED */
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//#define HAL_RNG_MODULE_ENABLED
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//#define HAL_RTC_MODULE_ENABLED
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//#define HAL_SAI_MODULE_ENABLED
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//#define HAL_SD_MODULE_ENABLED
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//#define HAL_SPDIFRX_MODULE_ENABLED
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//#define HAL_SPI_MODULE_ENABLED
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//#define HAL_TIM_MODULE_ENABLED
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//#define HAL_UART_MODULE_ENABLED
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//#define HAL_USART_MODULE_ENABLED
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//#define HAL_IRDA_MODULE_ENABLED
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//#define HAL_SMARTCARD_MODULE_ENABLED
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//#define HAL_WWDG_MODULE_ENABLED
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#define HAL_CORTEX_MODULE_ENABLED
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/* #define HAL_PCD_MODULE_ENABLED */
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/* #define HAL_HCD_MODULE_ENABLED */
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//#define HAL_PCD_MODULE_ENABLED
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//#define HAL_HCD_MODULE_ENABLED
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/* ########################## HSE/HSI Values adaptation ##################### */
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@ -100,11 +100,11 @@
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* (when HSE is used as system clock source, directly or through the PLL).
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*/
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#if !defined (HSE_VALUE)
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#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
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#define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined (HSE_STARTUP_TIMEOUT)
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#define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
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#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
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#endif /* HSE_STARTUP_TIMEOUT */
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/**
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@ -113,14 +113,14 @@
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* (when HSI is used as system clock source, directly or through the PLL).
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*/
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#if !defined (HSI_VALUE)
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#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
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#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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/**
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* @brief Internal Low Speed oscillator (LSI) value.
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*/
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#if !defined (LSI_VALUE)
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#define LSI_VALUE ((uint32_t)40000)
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#define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/
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#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
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The real value may vary depending on the variations
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in voltage and temperature. */
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@ -128,16 +128,20 @@
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* @brief External Low Speed oscillator (LSE) value.
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*/
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#if !defined (LSE_VALUE)
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#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
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#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */
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#endif /* LSE_VALUE */
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#if !defined (LSE_STARTUP_TIMEOUT)
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#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
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#endif /* LSE_STARTUP_TIMEOUT */
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/**
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* @brief External clock source for I2S peripheral
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* This value is used by the I2S HAL module to compute the I2S clock source
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* frequency, this source is inserted directly through I2S_CKIN pad.
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*/
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#if !defined (EXTERNAL_CLOCK_VALUE)
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#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
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#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
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#endif /* EXTERNAL_CLOCK_VALUE */
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/* Tip: To avoid modifying this file each time you need to use different HSE,
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@ -164,66 +168,69 @@
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/* Section 1 : Ethernet peripheral configuration */
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/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
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#define MAC_ADDR0 2
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#define MAC_ADDR1 0
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#define MAC_ADDR2 0
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#define MAC_ADDR3 0
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#define MAC_ADDR4 0
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#define MAC_ADDR5 0
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#define MAC_ADDR0 2U
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#define MAC_ADDR1 0U
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#define MAC_ADDR2 0U
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#define MAC_ADDR3 0U
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#define MAC_ADDR4 0U
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#define MAC_ADDR5 0U
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/* Definition of the Ethernet driver buffers size and count */
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#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
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#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
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#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
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#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
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#define ETH_RXBUFNB ((uint32_t)5U) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
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#define ETH_TXBUFNB ((uint32_t)5U) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
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/* Section 2: PHY configuration section */
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/* DP83848 PHY Address*/
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#define DP83848_PHY_ADDRESS 0x01
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/* LAN8742A PHY Address*/
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#define LAN8742A_PHY_ADDRESS 0x00U
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/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
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#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
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#define PHY_RESET_DELAY ((uint32_t)0x00000FFFU)
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/* PHY Configuration delay */
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#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
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#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU)
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#define PHY_READ_TO ((uint32_t)0x0000FFFF)
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#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
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#define PHY_READ_TO ((uint32_t)0x0000FFFFU)
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#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU)
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/* Section 3: Common PHY Registers */
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#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
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#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
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#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */
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#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */
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#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
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#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
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#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
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#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
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#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
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#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
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#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
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#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
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#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
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#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
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#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
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#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */
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#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
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#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
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#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
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#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
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#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
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#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */
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#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */
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#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */
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#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
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#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
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#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
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#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
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#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
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#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */
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/* Section 4: Extended PHY Registers */
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#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
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#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
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#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
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#define PHY_SR ((uint16_t)0x1FU) /*!< PHY special control/ status register Offset */
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#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
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#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
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#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
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#define PHY_SPEED_STATUS ((uint16_t)0x0004U) /*!< PHY Speed mask */
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#define PHY_DUPLEX_STATUS ((uint16_t)0x0010U) /*!< PHY Duplex mask */
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#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
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#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
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#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
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#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
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#define PHY_ISFR ((uint16_t)0x1DU) /*!< PHY Interrupt Source Flag register Offset */
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#define PHY_ISFR_INT4 ((uint16_t)0x0010U) /*!< PHY Link down inturrupt */
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/* ################## SPI peripheral configuration ########################## */
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/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
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* Activated: CRC code is present inside driver
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* Deactivated: CRC code cleaned from driver
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*/
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#define USE_SPI_CRC 1U
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/* Includes ------------------------------------------------------------------*/
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/**
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@ -1,7 +1,68 @@
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#include "../../../gfx.h"
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#undef Red
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#undef Green
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#undef Blue
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/**
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******************************************************************************
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* @file Templates/system_stm32f7xx.c
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* @author MCD Application Team
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* @version V1.0.3
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* @date 22-April-2016
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* @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
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*
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* This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32f7xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32f7xx_system
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* @{
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*/
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/** @addtogroup STM32F7xx_System_Private_Includes
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* @{
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*/
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#include "stm32f7xx.h"
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#if !defined (HSE_VALUE)
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@ -12,17 +73,80 @@
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#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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/**
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* @}
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*/
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/** @addtogroup STM32F7xx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F7xx_System_Private_Defines
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* @{
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*/
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/************************* Miscellaneous Configuration ************************/
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/*!< Uncomment the following line if you need to use external SDRAM mounted
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on DK as data memory */
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/* #define DATA_IN_ExtSDRAM */
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/******************************************************************************/
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#if !GFX_USE_OS_CHIBIOS
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uint32_t SystemCoreClock = HSI_VALUE;
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#endif
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/**
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* @}
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*/
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__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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/** @addtogroup STM32F7xx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F7xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* This variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 16000000;
|
||||
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
#if defined (DATA_IN_ExtSDRAM)
|
||||
static void SystemInit_ExtMemCtl(void);
|
||||
#endif /* DATA_IN_ExtSDRAM */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F7xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system
|
||||
@ -48,9 +172,7 @@ void SystemInit(void)
|
||||
RCC->CR &= (uint32_t)0xFEF6FFFF;
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
//RCC->PLLCFGR = 0x24003010; // From discovery example
|
||||
// M = 12 = 0b1100, N = 192 = 0b11000000, P = 2 = 0b10, Q = 2 = 0b10
|
||||
RCC->PLLCFGR = 0x00C0980C;
|
||||
RCC->PLLCFGR = 0x24003010;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
@ -58,6 +180,10 @@ void SystemInit(void)
|
||||
/* Disable all interrupts */
|
||||
RCC->CIR = 0x00000000;
|
||||
|
||||
#if defined (DATA_IN_ExtSDRAM)
|
||||
SystemInit_ExtMemCtl();
|
||||
#endif /* DATA_IN_ExtSDRAM */
|
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
@ -150,3 +276,165 @@ void SystemCoreClockUpdate(void)
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
#if defined (DATA_IN_ExtSDRAM)
|
||||
/**
|
||||
* @brief Setup the external memory controller.
|
||||
* Called in startup_stm32f7xx.s before jump to main.
|
||||
* This function configures the external memories (SDRAM)
|
||||
* This SDRAM will be used as program data memory (including heap and stack).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit_ExtMemCtl(void)
|
||||
{
|
||||
register uint32_t tmpreg = 0, timeout = 0xFFFF;
|
||||
register __IO uint32_t index;
|
||||
|
||||
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG and GPIOH interface
|
||||
clock */
|
||||
RCC->AHB1ENR |= 0x000000FC;
|
||||
|
||||
/* Connect PCx pins to FMC Alternate function */
|
||||
GPIOC->AFR[0] = 0x0000C000;
|
||||
GPIOC->AFR[1] = 0x00000000;
|
||||
/* Configure PCx pins in Alternate function mode */
|
||||
GPIOC->MODER = 0x00000080;
|
||||
/* Configure PCx pins speed to 50 MHz */
|
||||
GPIOC->OSPEEDR = 0x00000080;
|
||||
/* Configure PCx pins Output type to push-pull */
|
||||
GPIOC->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PCx pins */
|
||||
GPIOC->PUPDR = 0x00000040;
|
||||
|
||||
/* Connect PDx pins to FMC Alternate function */
|
||||
GPIOD->AFR[0] = 0x000000CC;
|
||||
GPIOD->AFR[1] = 0xCC000CCC;
|
||||
/* Configure PDx pins in Alternate function mode */
|
||||
GPIOD->MODER = 0xA02A000A;
|
||||
/* Configure PDx pins speed to 50 MHz */
|
||||
GPIOD->OSPEEDR = 0xA02A000A;
|
||||
/* Configure PDx pins Output type to push-pull */
|
||||
GPIOD->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PDx pins */
|
||||
GPIOD->PUPDR = 0x50150005;
|
||||
|
||||
/* Connect PEx pins to FMC Alternate function */
|
||||
GPIOE->AFR[0] = 0xC00000CC;
|
||||
GPIOE->AFR[1] = 0xCCCCCCCC;
|
||||
/* Configure PEx pins in Alternate function mode */
|
||||
GPIOE->MODER = 0xAAAA800A;
|
||||
/* Configure PEx pins speed to 50 MHz */
|
||||
GPIOE->OSPEEDR = 0xAAAA800A;
|
||||
/* Configure PEx pins Output type to push-pull */
|
||||
GPIOE->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PEx pins */
|
||||
GPIOE->PUPDR = 0x55554005;
|
||||
|
||||
/* Connect PFx pins to FMC Alternate function */
|
||||
GPIOF->AFR[0] = 0x00CCCCCC;
|
||||
GPIOF->AFR[1] = 0xCCCCC000;
|
||||
/* Configure PFx pins in Alternate function mode */
|
||||
GPIOF->MODER = 0xAA800AAA;
|
||||
/* Configure PFx pins speed to 50 MHz */
|
||||
GPIOF->OSPEEDR = 0xAA800AAA;
|
||||
/* Configure PFx pins Output type to push-pull */
|
||||
GPIOF->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PFx pins */
|
||||
GPIOF->PUPDR = 0x55400555;
|
||||
|
||||
/* Connect PGx pins to FMC Alternate function */
|
||||
GPIOG->AFR[0] = 0x00CC00CC;
|
||||
GPIOG->AFR[1] = 0xC000000C;
|
||||
/* Configure PGx pins in Alternate function mode */
|
||||
GPIOG->MODER = 0x80020A0A;
|
||||
/* Configure PGx pins speed to 50 MHz */
|
||||
GPIOG->OSPEEDR = 0x80020A0A;
|
||||
/* Configure PGx pins Output type to push-pull */
|
||||
GPIOG->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PGx pins */
|
||||
GPIOG->PUPDR = 0x40010505;
|
||||
|
||||
/* Connect PHx pins to FMC Alternate function */
|
||||
GPIOH->AFR[0] = 0x00C0C000;
|
||||
GPIOH->AFR[1] = 0x00000000;
|
||||
/* Configure PHx pins in Alternate function mode */
|
||||
GPIOH->MODER = 0x00000880;
|
||||
/* Configure PHx pins speed to 50 MHz */
|
||||
GPIOH->OSPEEDR = 0x00000880;
|
||||
/* Configure PHx pins Output type to push-pull */
|
||||
GPIOH->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PHx pins */
|
||||
GPIOH->PUPDR = 0x00000440;
|
||||
|
||||
/* Enable the FMC interface clock */
|
||||
RCC->AHB3ENR |= 0x00000001;
|
||||
|
||||
/* Configure and enable SDRAM bank1 */
|
||||
FMC_Bank5_6->SDCR[0] = 0x00001954;
|
||||
FMC_Bank5_6->SDTR[0] = 0x01115351;
|
||||
|
||||
/* SDRAM initialization sequence */
|
||||
/* Clock enable command */
|
||||
FMC_Bank5_6->SDCMR = 0x00000011;
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
while((tmpreg != 0) && (timeout-- > 0))
|
||||
{
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
}
|
||||
|
||||
/* Delay */
|
||||
for (index = 0; index<1000; index++);
|
||||
|
||||
/* PALL command */
|
||||
FMC_Bank5_6->SDCMR = 0x00000012;
|
||||
timeout = 0xFFFF;
|
||||
while((tmpreg != 0) && (timeout-- > 0))
|
||||
{
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
}
|
||||
|
||||
/* Auto refresh command */
|
||||
FMC_Bank5_6->SDCMR = 0x000000F3;
|
||||
timeout = 0xFFFF;
|
||||
while((tmpreg != 0) && (timeout-- > 0))
|
||||
{
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
}
|
||||
|
||||
/* MRD register program */
|
||||
FMC_Bank5_6->SDCMR = 0x00044014;
|
||||
timeout = 0xFFFF;
|
||||
while((tmpreg != 0) && (timeout-- > 0))
|
||||
{
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
}
|
||||
|
||||
/* Set refresh count */
|
||||
tmpreg = FMC_Bank5_6->SDRTR;
|
||||
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
|
||||
|
||||
/* Disable write protection */
|
||||
tmpreg = FMC_Bank5_6->SDCR[0];
|
||||
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
|
||||
|
||||
/*
|
||||
* Disable the FMC bank1 (enabled after reset).
|
||||
* This, prevents CPU speculation access on this bank which blocks the use of FMC during
|
||||
* 24us. During this time the others FMC master (such as LTDC) cannot use it!
|
||||
*/
|
||||
FMC_Bank1->BTCR[0] = 0x000030d2;
|
||||
}
|
||||
#endif /* DATA_IN_ExtSDRAM */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user