179 lines
6.1 KiB
C
179 lines
6.1 KiB
C
/*
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* This file is subject to the terms of the GFX License. If a copy of
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* the license was not distributed with this file, you can obtain one at:
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*
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* http://ugfx.org/license.html
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*/
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/**
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* @file boards/addons/gdisp/board_SSD1289_stm32f4discovery.h
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* @brief GDISP Graphic Driver subsystem board interface for the SSD1289 display.
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*
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* @note This file contains a mix of hardware specific and operating system specific
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* code. You will need to change it for your CPU and/or operating system.
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*/
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#ifndef _GDISP_LLD_BOARD_H
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#define _GDISP_LLD_BOARD_H
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// For a multiple display configuration we would put all this in a structure and then
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// set g->board to that structure.
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#define GDISP_REG ((volatile uint16_t *) 0x60000000)[0] /* RS = 0 */
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#define GDISP_RAM ((volatile uint16_t *) 0x60020000)[0] /* RS = 1 */
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#define GDISP_DMA_STREAM STM32_DMA2_STREAM6
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#define FSMC_BANK 0
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/* PWM configuration structure. We use timer 3 channel 3 */
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static const PWMConfig pwmcfg = {
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100000, /* 100 kHz PWM clock frequency. */
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100, /* PWM period is 100 cycles. */
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0,
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{
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{PWM_OUTPUT_DISABLED, 0},
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{PWM_OUTPUT_DISABLED, 0},
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{PWM_OUTPUT_ACTIVE_HIGH, 0},
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{PWM_OUTPUT_DISABLED, 0}
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},
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0,
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0
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};
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static GFXINLINE void init_board(GDisplay *g) {
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// As we are not using multiple displays we set g->board to NULL as we don't use it.
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g->board = 0;
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switch(g->controllerdisplay) {
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case 0: // Set up for Display 0
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/**
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* Performs the following functions:
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* 1. initialise the io port used by the display
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* 2. initialise the reset pin (initial state not-in-reset)
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* 3. initialise the chip select pin (initial state not-active)
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* 4. initialise the backlight pin (initial state back-light off)
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*/
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#if defined(STM32F1XX) || defined(STM32F3XX)
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/* FSMC setup for F1/F3 */
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rccEnableAHB(RCC_AHBENR_FSMCEN, 0);
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#if defined(GDISP_USE_DMA)
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#error "GDISP: SSD1289 - DMA not implemented for F1/F3 Devices"
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#endif
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#elif defined(STM32F4XX) || defined(STM32F2XX)
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/* STM32F2-F4 FSMC init */
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rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0);
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#if defined(GDISP_USE_DMA)
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if (dmaStreamAllocate(GDISP_DMA_STREAM, 0, 0, 0)) gfxExit();
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dmaStreamSetMemory0(GDISP_DMA_STREAM, &GDISP_RAM);
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dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
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#else
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#warning "GDISP: SSD1289 - DMA is supported for F2/F4 Devices. Define GDISP_USE_DMA in your gfxconf.h to turn this on for better performance."
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#endif
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#else
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#error "GDISP: SSD1289 - FSMC not implemented for this device"
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#endif
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/* set pins to FSMC mode */
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IOBus busD = {GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) | (1 << 7) | (1 << 8) |
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(1 << 9) | (1 << 10) | (1 << 11) | (1 << 14) | (1 << 15), 0};
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IOBus busE = {GPIOE, (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) |
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(1 << 13) | (1 << 14) | (1 << 15), 0};
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palSetBusMode(&busD, PAL_MODE_ALTERNATE(12));
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palSetBusMode(&busE, PAL_MODE_ALTERNATE(12));
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/* FSMC timing */
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// FSMC_Bank1->BTCR[FSMC_BANK+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0 ;
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//FSMC_Bank1->BTCR[FSMC_BANK+1] = FSMC_BTR1_ADDSET_2 | FSMC_BTR1_ADDSET_1 | FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_DATAST_1 | FSMC_BTR1_DATAST_0 | FSMC_BTR1_BUSTURN_2 | FSMC_BTR1_BUSTURN_1 | FSMC_BTR1_BUSTURN_0;
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//this works// FSMC_Bank1->BTCR[FSMC_BANK+1] = FSMC_BTR1_ADDSET_2 | FSMC_BTR1_ADDSET_1 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_DATAST_1 | FSMC_BTR1_BUSTURN_2;
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FSMC_Bank1->BTCR[FSMC_BANK+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_DATAST_0 | FSMC_BTR1_BUSTURN_0;
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/* Bank1 NOR/SRAM control register configuration
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* This is actually not needed as already set by default after reset */
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FSMC_Bank1->BTCR[FSMC_BANK] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
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/* Display backlight control */
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/* TIM3 is an alternate function 2 (AF2) */
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pwmStart(&PWMD3, &pwmcfg);
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palSetPadMode(GPIOB, 0, PAL_MODE_ALTERNATE(2));
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pwmEnableChannel(&PWMD3, 2, 100);
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break;
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}
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}
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static GFXINLINE void post_init_board(GDisplay *g) {
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(void) g;
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}
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static GFXINLINE void setpin_reset(GDisplay *g, bool_t state) {
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(void) g;
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(void) state;
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}
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static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
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(void) g;
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pwmEnableChannel(&PWMD3, 2, percent);
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}
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static GFXINLINE void acquire_bus(GDisplay *g) {
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(void) g;
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}
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static GFXINLINE void release_bus(GDisplay *g) {
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(void) g;
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}
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static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
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(void) g;
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GDISP_REG = index;
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}
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static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
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(void) g;
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GDISP_RAM = data;
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}
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static GFXINLINE void setreadmode(GDisplay *g) {
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(void) g;
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FSMC_Bank1->BTCR[FSMC_BANK+1] = FSMC_BTR1_ADDSET_3 | FSMC_BTR1_DATAST_3 | FSMC_BTR1_BUSTURN_0; /* FSMC timing */
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}
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static GFXINLINE void setwritemode(GDisplay *g) {
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(void) g;
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FSMC_Bank1->BTCR[FSMC_BANK+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0; /* FSMC timing */
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}
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static GFXINLINE uint16_t read_data(GDisplay *g) {
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(void) g;
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return GDISP_RAM;
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}
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#if defined(GDISP_USE_DMA) || defined(__DOXYGEN__)
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static GFXINLINE void dma_with_noinc(GDisplay *g, color_t *buffer, int area) {
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(void) g;
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dmaStreamSetPeripheral(GDISP_DMA_STREAM, buffer);
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dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
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for (; area > 0; area -= 65535) {
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dmaStreamSetTransactionSize(GDISP_DMA_STREAM, area > 65535 ? 65535 : area);
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dmaStreamEnable(GDISP_DMA_STREAM);
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dmaWaitCompletion(GDISP_DMA_STREAM);
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}
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}
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static GFXINLINE void dma_with_inc(GDisplay *g, color_t *buffer, int area) {
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(void) g;
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dmaStreamSetPeripheral(GDISP_DMA_STREAM, buffer);
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dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PINC | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
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for (; area > 0; area -= 65535) {
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dmaStreamSetTransactionSize(GDISP_DMA_STREAM, area > 65535 ? 65535 : area);
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dmaStreamEnable(GDISP_DMA_STREAM);
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dmaWaitCompletion(GDISP_DMA_STREAM);
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}
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}
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#endif
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#endif /* _GDISP_LLD_BOARD_H */
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