194 lines
5.1 KiB
C
194 lines
5.1 KiB
C
/*
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* This file is subject to the terms of the GFX License. If a copy of
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* the license was not distributed with this file, you can obtain one at:
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*
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* http://ugfx.org/license.html
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*/
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/**
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* @file drivers/gdisp/SSD2119/gdisp_lld_board_embest_dmstf4bb.h
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* @brief GDISP Graphic Driver subsystem board FSMC interface for the SSD2119 display.
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*
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* @addtogroup GDISP
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* @{
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*/
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#ifndef _GDISP_LLD_BOARD_H
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#define _GDISP_LLD_BOARD_H
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/* This board file uses only FSMC, so don't undefine this. */
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#define GDISP_USE_FSMC
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/* But it is OK to disable DMA use. */
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#define GDISP_USE_DMA
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#define GDISP_DMA_STREAM STM32_DMA2_STREAM6
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/* Using FSMC A19 (PE3) as DC */
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#define GDISP_REG (*((volatile uint16_t *) 0x60000000)) /* DC = 0 */
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#define GDISP_RAM (*((volatile uint16_t *) 0x60100000)) /* DC = 1 */
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#define SET_RST palSetPad(GPIOD, 3);
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#define CLR_RST palClearPad(GPIOD, 3);
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/*
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* PWM configuration structure. We use timer 4 channel 2 (orange LED on board).
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* The reason for so high clock is that with any lower, onboard coil is squeaking.
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* The major disadvantage of this clock is a lack of linearity between PWM duty
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* cycle width and brightness. In fact only with low preset one sees any change
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* (eg. duty cycle between 1-20). Feel free to adjust this, maybe only my board
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* behaves like this. According to the G5126 datesheet (backlight LED driver)
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* the PWM frequency should be somewhere between 200 Hz to 200 kHz.
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*/
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static const PWMConfig pwmcfg = {
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1000000, /* 1 MHz PWM clock frequency. */
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100, /* PWM period is 100 cycles. */
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NULL,
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{
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{PWM_OUTPUT_ACTIVE_HIGH, NULL},
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{PWM_OUTPUT_ACTIVE_HIGH, NULL},
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{PWM_OUTPUT_ACTIVE_HIGH, NULL},
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{PWM_OUTPUT_ACTIVE_HIGH, NULL}
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},
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0
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};
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/**
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* @brief Initialise the board for the display.
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* @notes This board definition uses GPIO and assumes exclusive access to these GPIO pins
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*
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* @notapi
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*/
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static inline void init_board(void) {
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unsigned char FSMC_Bank;
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#ifndef GDISP_USE_FSMC
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#error "This board uses only FSMC, please define GDISP_USE_FSMC"
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#endif
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#if defined(STM32F4XX) || defined(STM32F2XX)
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/* STM32F4 FSMC init */
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rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0);
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#if defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM)
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if (dmaStreamAllocate(GDISP_DMA_STREAM, 0, NULL, NULL))
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gfxExit();
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dmaStreamSetMemory0(GDISP_DMA_STREAM, &GDISP_RAM);
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dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
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#endif
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#else
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#error "FSMC not implemented for this device"
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#endif
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/* Group pins */
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IOBus busD = {GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) | (1 << 7) | (1 << 8) |
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(1 << 9) | (1 << 10) | (1 << 14) | (1 << 15), 0};
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IOBus busE = {GPIOE, (1 << 3) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) |
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(1 << 13) | (1 << 14) | (1 << 15), 0};
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/* FSMC is an alternate function 12 (AF12) */
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palSetBusMode(&busD, PAL_MODE_ALTERNATE(12));
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palSetBusMode(&busE, PAL_MODE_ALTERNATE(12));
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FSMC_Bank = 0;
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/* FSMC timing register configuration */
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FSMC_Bank1->BTCR[FSMC_Bank + 1] = (FSMC_BTR1_ADDSET_2 | FSMC_BTR1_ADDSET_1) \
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| (FSMC_BTR1_DATAST_2 | FSMC_BTR1_DATAST_1) \
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| FSMC_BTR1_BUSTURN_0;
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/* Bank1 NOR/PSRAM control register configuration
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* Write enable, memory databus width set to 16 bit, memory bank enable */
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FSMC_Bank1->BTCR[FSMC_Bank] = FSMC_BCR1_WREN | FSMC_BCR1_MWID_0 | FSMC_BCR1_MBKEN;
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/* Display backlight control */
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/* TIM4 is an alternate function 2 (AF2) */
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pwmStart(&PWMD4, &pwmcfg);
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palSetPadMode(GPIOD, 13, PAL_MODE_ALTERNATE(2));
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pwmEnableChannel(&PWMD4, 1, 100);
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}
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/**
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* @brief Set or clear the lcd reset pin.
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*
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* @param[in] state TRUE = lcd in reset, FALSE = normal operation
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*
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* @notapi
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*/
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static inline void setpin_reset(bool_t state) {
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if (state) {
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CLR_RST;
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} else {
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SET_RST;
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}
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}
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/**
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* @brief Set the lcd back-light level.
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*
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* @param[in] percent 0 to 100%
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*
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* @notapi
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*/
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static inline void set_backlight(uint8_t percent) {
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pwmEnableChannel(&PWMD4, 1, percent);
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}
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/**
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* @brief Take exclusive control of the bus
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* @note Not needed, not implemented
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*
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* @notapi
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*/
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static inline void acquire_bus(void) {
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/* Nothing to do here since LCD is the only device on that bus */
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}
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/**
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* @brief Release exclusive control of the bus
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* @note Not needed, not implemented
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*
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* @notapi
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*/
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static inline void release_bus(void) {
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/* Nothing to do here since LCD is the only device on that bus */
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}
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/**
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* @brief Send data to the index register.
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*
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* @param[in] index The index register to set
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*
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* @notapi
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*/
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static inline void write_index(uint16_t index) {
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GDISP_REG = index;
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}
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/**
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* @brief Send data to the lcd.
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*
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* @param[in] data The data to send
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*
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* @notapi
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*/
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static inline void write_data(uint16_t data) {
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GDISP_RAM = data;
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}
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#if GDISP_HARDWARE_READPIXEL || GDISP_HARDWARE_SCROLL || defined(__DOXYGEN__)
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/**
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* @brief Read data from the lcd.
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*
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* @return The data from the lcd
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* @note The chip select may need to be asserted/de-asserted
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* around the actual spi read
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*
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* @notapi
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*/
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static inline uint16_t read_data(void) {
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return GDISP_RAM;
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}
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#endif
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#endif /* _GDISP_LLD_BOARD_H */
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/** @} */
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