106 lines
3.3 KiB
C
106 lines
3.3 KiB
C
/*
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* This file is subject to the terms of the GFX License. If a copy of
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* the license was not distributed with this file, you can obtain one at:
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*
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* http://chibios-gfx.com/license.html
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*/
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/**
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* @file drivers/gdisp/SSD1963/board_SSD1963_fsmc.h
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* @brief GDISP Graphic Driver subsystem board interface for the SSD1963 display.
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*/
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#ifndef _GDISP_LLD_BOARD_H
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#define _GDISP_LLD_BOARD_H
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static const LCD_Parameters DisplayTimings[] = {
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// You need one of these array elements per display
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{
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480, 272, // Panel width and height
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2, 2, 41, // Horizontal Timings (back porch, front porch, pulse)
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CALC_PERIOD(480,2,2,41), // Total Horizontal Period (calculated from above line)
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2, 2, 10, // Vertical Timings (back porch, front porch, pulse)
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CALC_PERIOD(272,2,2,10), // Total Vertical Period (calculated from above line)
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CALC_FPR(480,272,2,2,41,2,2,10,60ULL) // FPR - the 60ULL is the frames per second. Note the ULL!
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},
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};
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// For a multiple display configuration we would put all this in a structure and then
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// set g->board to that structure.
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/* Using FSMC A16 as RS */
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#define GDISP_REG (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
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#define GDISP_RAM (*((volatile uint16_t *) 0x60020000)) /* RS = 1 */
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static inline void init_board(GDisplay *g) {
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// As we are not using multiple displays we set g->board to NULL as we don't use it.
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g->board = 0;
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switch(g->controllerdisplay) {
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case 0: // Set up for Display 0
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#if defined(STM32F1XX) || defined(STM32F3XX)
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/* FSMC setup for F1/F3 */
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rccEnableAHB(RCC_AHBENR_FSMCEN, 0);
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#elif defined(STM32F4XX) || defined(STM32F2XX)
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/* STM32F2-F4 FSMC init */
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rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0);
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#else
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#error "FSMC not implemented for this device"
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#endif
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/* set pins to FSMC mode */
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IOBus busD = {GPIOD, (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5) | (1 << 7) | (1 << 8) |
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(1 << 9) | (1 << 10) | (1 << 11) | (1 << 14) | (1 << 15), 0};
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IOBus busE = {GPIOE, (1 << 7) | (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) |
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(1 << 13) | (1 << 14) | (1 << 15), 0};
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palSetBusMode(&busD, PAL_MODE_ALTERNATE(12));
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palSetBusMode(&busE, PAL_MODE_ALTERNATE(12));
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/* FSMC timing */
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FSMC_Bank1->BTCR[0+1] = (FSMC_BTR1_ADDSET_1 | FSMC_BTR1_ADDSET_3) \
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| (FSMC_BTR1_DATAST_1 | FSMC_BTR1_DATAST_3) \
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| (FSMC_BTR1_BUSTURN_1 | FSMC_BTR1_BUSTURN_3) ;
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/* Bank1 NOR/SRAM control register configuration
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* This is actually not needed as already set by default after reset */
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FSMC_Bank1->BTCR[0] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
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break;
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}
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}
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static inline void post_init_board(GDisplay *g) {
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(void) g;
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/* FSMC delay reduced as the controller now runs at full speed */
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FSMC_Bank1->BTCR[0+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0 ;
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FSMC_Bank1->BTCR[0] = FSMC_BCR1_MWID_0 | FSMC_BCR1_WREN | FSMC_BCR1_MBKEN;
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}
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static inline void setpin_reset(GDisplay *g, bool_t state) {
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(void) g;
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(void) state;
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}
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static inline void acquire_bus(GDisplay *g) {
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(void) g;
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}
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static inline void release_bus(GDisplay *g) {
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(void) g;
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}
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static inline void write_index(GDisplay *g, uint16_t index) {
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(void) g;
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GDISP_REG = index;
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}
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static inline void write_data(GDisplay *g, uint16_t data) {
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(void) g;
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GDISP_RAM = data;
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}
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#endif /* _GDISP_LLD_BOARD_H */
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