506 lines
20 KiB
C
506 lines
20 KiB
C
/*
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* This file is subject to the terms of the GFX License. If a copy of
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* the license was not distributed with this file, you can obtain one at:
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*
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* http://ugfx.io/license.html
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*/
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#ifndef _GDISP_LLD_BOARD_H
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#define _GDISP_LLD_BOARD_H
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#include "stm32f746g_discovery_sdram.h"
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#ifndef GFX_LTDC_USE_DIRECTIO
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#define GFX_LTDC_USE_DIRECTIO GFXON
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#endif
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#ifndef GFX_LTDC_TIMING_SET
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/* Options are:
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* 0 - don't initialise the display VCO and LTDC clocks - something else will do it
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* 1 - uGFX preferred timings (default)
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* 2 - Alternate timings
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*/
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#define GFX_LTDC_TIMING_SET 1
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#endif
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#if GFX_USE_OS_CHIBIOS && !GFX_USE_DIRECTIO
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#include "hal.h"
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#include "ch.h"
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#else
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#include "stm32f7xx_hal_rcc.h"
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#include "stm32f7xx_hal_gpio.h"
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#endif
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#include <string.h>
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#if !GFX_USE_OS_CHIBIOS
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#define AFRL AFR[0]
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#define AFRH AFR[1]
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#endif
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#define ALLOW_2ND_LAYER GFXON
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static const ltdcConfig driverCfg = {
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480, 272, // Width, Height (pixels)
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41, 10, // Horizontal, Vertical sync (pixels)
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13, 2, // Horizontal, Vertical back porch (pixels)
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32, 2, // Horizontal, Vertical front porch (pixels)
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0, // Sync flags
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0x000000, // Clear color (RGB888)
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{ // Background layer config
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(LLDCOLOR_TYPE *)SDRAM_DEVICE_ADDR, // Frame buffer address
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480, 272, // Width, Height (pixels)
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480 * LTDC_PIXELBYTES, // Line pitch (bytes)
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LTDC_PIXELFORMAT, // Pixel format
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0, 0, // Start pixel position (x, y)
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480, 272, // Size of virtual layer (cx, cy)
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0x00000000, // Default color (ARGB8888)
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0x000000, // Color key (RGB888)
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LTDC_BLEND_FIX1_FIX2, // Blending factors
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0, // Palette (RGB888, can be NULL)
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0, // Palette length
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0xFF, // Constant alpha factor
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LTDC_LEF_ENABLE // Layer configuration flags
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},
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#if ALLOW_2ND_LAYER
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{ // Foreground layer config (if turned on)
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(LLDCOLOR_TYPE *)(SDRAM_DEVICE_ADDR+(480 * 272 * LTDC_PIXELBYTES)), // Frame buffer address
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480, 272, // Width, Height (pixels)
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480 * LTDC_PIXELBYTES, // Line pitch (bytes)
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LTDC_PIXELFORMAT, // Pixel format
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0, 0, // Start pixel position (x, y)
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480, 272, // Size of virtual layer (cx, cy)
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0x00000000, // Default color (ARGB8888)
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0x000000, // Color key (RGB888)
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LTDC_BLEND_MOD1_MOD2, // Blending factors
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0, // Palette (RGB888, can be NULL)
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0, // Palette length
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0xFF, // Constant alpha factor
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LTDC_LEF_ENABLE // Layer configuration flags
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}
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#else
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LTDC_UNUSED_LAYER_CONFIG
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#endif
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};
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static void configureLcdPins(void) {
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#if GFX_USE_OS_CHIBIOS && !GFX_LTDC_USE_DIRECTIO
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palSetPadMode(GPIOI, GPIOI_LCD_R0, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PI15: LCD_R0
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palSetPadMode(GPIOJ, GPIOJ_LCD_R1, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ0 : LCD_R1
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palSetPadMode(GPIOJ, GPIOJ_LCD_R2, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ1 : LCD_R2
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palSetPadMode(GPIOJ, GPIOJ_LCD_R3, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ2 : LCD_R3
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palSetPadMode(GPIOJ, GPIOJ_LCD_R4, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ3 : LCD_R4
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palSetPadMode(GPIOJ, GPIOJ_LCD_R5, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ4 : LCD_R5
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palSetPadMode(GPIOJ, GPIOJ_LCD_R6, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ5 : LCD_R6
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palSetPadMode(GPIOJ, GPIOJ_LCD_R7, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ6 : LCD_R7
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palSetPadMode(GPIOJ, GPIOJ_LCD_G0, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ7 : LCD_G0
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palSetPadMode(GPIOJ, GPIOJ_LCD_G1, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ8 : LCD_G1
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palSetPadMode(GPIOJ, GPIOJ_LCD_G2, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ9 : LCD_G2
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palSetPadMode(GPIOJ, GPIOJ_LCD_G3, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ10: LCD_G3
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palSetPadMode(GPIOJ, GPIOJ_LCD_G4, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ11: LCD_G4
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palSetPadMode(GPIOK, GPIOK_LCD_G5, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PK0 : LCD_G5
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palSetPadMode(GPIOK, GPIOK_LCD_G6, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PK1 : LCD_G6
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palSetPadMode(GPIOK, GPIOK_LCD_G7, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PK2 : LCD_G7
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palSetPadMode(GPIOE, GPIOE_LCD_B0, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PE4 : LCD_B0
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palSetPadMode(GPIOJ, GPIOJ_LCD_B1, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ13: LCD_B1
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palSetPadMode(GPIOJ, GPIOJ_LCD_B2, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ14: LCD_B2
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palSetPadMode(GPIOJ, GPIOJ_LCD_B3, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PJ15: LCD_B3
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palSetPadMode(GPIOG, GPIOG_LCD_B4, PAL_MODE_ALTERNATE(9) | PAL_STM32_OSPEED_HIGHEST); // PG12: LCD_B4
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palSetPadMode(GPIOK, GPIOK_LCD_B5, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PK4 : LCD_B5
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palSetPadMode(GPIOK, GPIOK_LCD_B6, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PK5 : LCD_B6
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palSetPadMode(GPIOK, GPIOK_LCD_B7, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PK6 : LCD_B7
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palSetPadMode(GPIOK, GPIOK_LCD_DE, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PK7 : LCD_DE
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palSetPadMode(GPIOI, GPIOI_LCD_VSYNC, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PI9 : LCD_VSYNC
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palSetPadMode(GPIOI, GPIOI_LCD_HSYNC, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PI10: LCD_HSYNC
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palSetPadMode(GPIOI, GPIOI_LCD_INT, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PI13: LCD_INT
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palSetPadMode(GPIOI, GPIOI_LCD_CLK, PAL_MODE_ALTERNATE(14) | PAL_STM32_OSPEED_HIGHEST); // PI14: LCD_CLK
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palSetPadMode(GPIOI, GPIOI_LCD_DISP, PAL_MODE_OUTPUT_PUSHPULL | PAL_STM32_OSPEED_HIGHEST); // PI12: LCD_DISP_PIN
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palSetPadMode(GPIOK, GPIOK_LCD_BL_CTRL, PAL_MODE_OUTPUT_PUSHPULL | PAL_STM32_OSPEED_HIGHEST); // PK3 : LCD_BL_CTRL
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#else
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//-------------------------------------------
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// Initialise port PE
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN;
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GPIOE->MODER |= (
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GPIO_MODER_MODER4_1 // PE4: LCD_B0 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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);
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GPIOE->MODER &=~ (
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GPIO_MODER_MODER4_0
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);
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GPIOE->OTYPER &=~ (
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GPIO_OTYPER_OT_4
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);
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GPIOE->OSPEEDR |= (
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GPIO_OSPEEDER_OSPEEDR4_0 | GPIO_OSPEEDER_OSPEEDR4_1
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);
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GPIOE->PUPDR &=~ (
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GPIO_PUPDR_PUPDR4_0 | GPIO_PUPDR_PUPDR4_1
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);
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GPIOE->AFRL |= (
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(14U << 4*4)
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);
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//-------------------------------------------
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// Initialise port PG
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOGEN;
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GPIOG->MODER |= (
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GPIO_MODER_MODER12_1 // PG12: LCD_B4 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(9)
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);
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GPIOG->MODER &=~ (
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GPIO_MODER_MODER12_0
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);
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GPIOG->OTYPER &=~ (
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GPIO_OTYPER_OT_12
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);
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GPIOG->OSPEEDR |= (
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GPIO_OSPEEDER_OSPEEDR12_0 | GPIO_OSPEEDER_OSPEEDR12_1
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);
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GPIOG->PUPDR &=~ (
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GPIO_PUPDR_PUPDR12_0 | GPIO_PUPDR_PUPDR12_1
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);
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GPIOG->AFRH |= (
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( 9U << 4*(12-8))
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);
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//-------------------------------------------
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// Initialise port PI
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOIEN;
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GPIOI->MODER |= (
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GPIO_MODER_MODER9_1 // PI9: LCD_VSYNC - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER10_1 // PI10: LCD_HSYNC - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER12_0 // PI12: LCD_DISP_PIN - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_OUTPUT_PUSHPULL
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| GPIO_MODER_MODER13_1 // PI13: LCD_INT - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER14_1 // PI14: LCD_CLK - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER15_1 // PI15: LCD_R0 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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);
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GPIOI->MODER &=~ (
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GPIO_MODER_MODER9_0
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| GPIO_MODER_MODER10_0
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| GPIO_MODER_MODER12_1
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| GPIO_MODER_MODER13_0
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| GPIO_MODER_MODER14_0
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| GPIO_MODER_MODER15_0
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);
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GPIOI->OTYPER &=~ (
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GPIO_OTYPER_OT_9
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| GPIO_OTYPER_OT_10
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| GPIO_OTYPER_OT_12
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| GPIO_OTYPER_OT_13
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| GPIO_OTYPER_OT_14
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| GPIO_OTYPER_OT_15
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);
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GPIOI->OSPEEDR |= (
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GPIO_OSPEEDER_OSPEEDR9_0 | GPIO_OSPEEDER_OSPEEDR9_1
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| GPIO_OSPEEDER_OSPEEDR10_0 | GPIO_OSPEEDER_OSPEEDR10_1
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| GPIO_OSPEEDER_OSPEEDR12_0 | GPIO_OSPEEDER_OSPEEDR12_1
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| GPIO_OSPEEDER_OSPEEDR13_0 | GPIO_OSPEEDER_OSPEEDR13_1
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| GPIO_OSPEEDER_OSPEEDR14_0 | GPIO_OSPEEDER_OSPEEDR14_1
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| GPIO_OSPEEDER_OSPEEDR15_0 | GPIO_OSPEEDER_OSPEEDR15_1
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);
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GPIOI->PUPDR &=~ (
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GPIO_PUPDR_PUPDR9_0 | GPIO_PUPDR_PUPDR9_1
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| GPIO_PUPDR_PUPDR10_0 | GPIO_PUPDR_PUPDR10_1
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| GPIO_PUPDR_PUPDR12_0 | GPIO_PUPDR_PUPDR12_1
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| GPIO_PUPDR_PUPDR13_0 | GPIO_PUPDR_PUPDR13_1
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| GPIO_PUPDR_PUPDR14_0 | GPIO_PUPDR_PUPDR14_1
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| GPIO_PUPDR_PUPDR15_0 | GPIO_PUPDR_PUPDR15_1
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);
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GPIOI->AFRH |= (
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(14U << 4*(9-8))
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| (14U << 4*(10-8))
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| ( 0U << 4*(12-8))
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| (14U << 4*(13-8))
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| (14U << 4*(14-8))
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| (14U << 4*(15-8))
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);
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//-------------------------------------------
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// Initialise port PJ
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOJEN;
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GPIOJ->MODER |= (
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GPIO_MODER_MODER0_1 // PJ0: LCD_R1 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER1_1 // PJ1: LCD_R2 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER2_1 // PJ2: LCD_R3 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER3_1 // PJ3: LCD_R4 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER4_1 // PJ4: LCD_R5 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER5_1 // PJ5: LCD_R6 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER6_1 // PJ6: LCD_R7 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER7_1 // PJ7: LCD_G0 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER8_1 // PJ8: LCD_G1 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER9_1 // PJ9: LCD_G2 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER10_1 // PJ10: LCD_G3 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER11_1 // PJ11: LCD_G4 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER13_1 // PJ13: LCD_B1 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER14_1 // PJ14: LCD_B2 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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| GPIO_MODER_MODER15_1 // PJ15: LCD_B3 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
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);
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GPIOJ->MODER &=~ (
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GPIO_MODER_MODER0_0
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| GPIO_MODER_MODER1_0
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| GPIO_MODER_MODER2_0
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| GPIO_MODER_MODER3_0
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| GPIO_MODER_MODER4_0
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| GPIO_MODER_MODER5_0
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| GPIO_MODER_MODER6_0
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| GPIO_MODER_MODER7_0
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| GPIO_MODER_MODER8_0
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| GPIO_MODER_MODER9_0
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| GPIO_MODER_MODER10_0
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| GPIO_MODER_MODER11_0
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| GPIO_MODER_MODER13_0
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| GPIO_MODER_MODER14_0
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| GPIO_MODER_MODER15_0
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);
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GPIOJ->OTYPER &=~ (
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GPIO_OTYPER_OT_0
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| GPIO_OTYPER_OT_1
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| GPIO_OTYPER_OT_2
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| GPIO_OTYPER_OT_3
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| GPIO_OTYPER_OT_4
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| GPIO_OTYPER_OT_5
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| GPIO_OTYPER_OT_6
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| GPIO_OTYPER_OT_7
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| GPIO_OTYPER_OT_8
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| GPIO_OTYPER_OT_9
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| GPIO_OTYPER_OT_10
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| GPIO_OTYPER_OT_11
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| GPIO_OTYPER_OT_13
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| GPIO_OTYPER_OT_14
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| GPIO_OTYPER_OT_15
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);
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GPIOJ->OSPEEDR |= (
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GPIO_OSPEEDER_OSPEEDR0_0 | GPIO_OSPEEDER_OSPEEDR0_1
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| GPIO_OSPEEDER_OSPEEDR1_0 | GPIO_OSPEEDER_OSPEEDR1_1
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| GPIO_OSPEEDER_OSPEEDR2_0 | GPIO_OSPEEDER_OSPEEDR2_1
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| GPIO_OSPEEDER_OSPEEDR3_0 | GPIO_OSPEEDER_OSPEEDR3_1
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| GPIO_OSPEEDER_OSPEEDR4_0 | GPIO_OSPEEDER_OSPEEDR4_1
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| GPIO_OSPEEDER_OSPEEDR5_0 | GPIO_OSPEEDER_OSPEEDR5_1
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| GPIO_OSPEEDER_OSPEEDR6_0 | GPIO_OSPEEDER_OSPEEDR6_1
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| GPIO_OSPEEDER_OSPEEDR7_0 | GPIO_OSPEEDER_OSPEEDR7_1
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| GPIO_OSPEEDER_OSPEEDR8_0 | GPIO_OSPEEDER_OSPEEDR8_1
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| GPIO_OSPEEDER_OSPEEDR9_0 | GPIO_OSPEEDER_OSPEEDR9_1
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| GPIO_OSPEEDER_OSPEEDR10_0 | GPIO_OSPEEDER_OSPEEDR10_1
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| GPIO_OSPEEDER_OSPEEDR11_0 | GPIO_OSPEEDER_OSPEEDR11_1
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| GPIO_OSPEEDER_OSPEEDR13_0 | GPIO_OSPEEDER_OSPEEDR13_1
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| GPIO_OSPEEDER_OSPEEDR14_0 | GPIO_OSPEEDER_OSPEEDR14_1
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| GPIO_OSPEEDER_OSPEEDR15_0 | GPIO_OSPEEDER_OSPEEDR15_1
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);
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GPIOJ->PUPDR &=~ (
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GPIO_PUPDR_PUPDR0_0 | GPIO_PUPDR_PUPDR0_1
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| GPIO_PUPDR_PUPDR1_0 | GPIO_PUPDR_PUPDR1_1
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| GPIO_PUPDR_PUPDR2_0 | GPIO_PUPDR_PUPDR2_1
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| GPIO_PUPDR_PUPDR3_0 | GPIO_PUPDR_PUPDR3_1
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| GPIO_PUPDR_PUPDR4_0 | GPIO_PUPDR_PUPDR4_1
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| GPIO_PUPDR_PUPDR5_0 | GPIO_PUPDR_PUPDR5_1
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| GPIO_PUPDR_PUPDR6_0 | GPIO_PUPDR_PUPDR6_1
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| GPIO_PUPDR_PUPDR7_0 | GPIO_PUPDR_PUPDR7_1
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| GPIO_PUPDR_PUPDR8_0 | GPIO_PUPDR_PUPDR8_1
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| GPIO_PUPDR_PUPDR9_0 | GPIO_PUPDR_PUPDR9_1
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| GPIO_PUPDR_PUPDR10_0 | GPIO_PUPDR_PUPDR10_1
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| GPIO_PUPDR_PUPDR11_0 | GPIO_PUPDR_PUPDR11_1
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| GPIO_PUPDR_PUPDR13_0 | GPIO_PUPDR_PUPDR13_1
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| GPIO_PUPDR_PUPDR14_0 | GPIO_PUPDR_PUPDR14_1
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| GPIO_PUPDR_PUPDR15_0 | GPIO_PUPDR_PUPDR15_1
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);
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GPIOJ->AFRL |= (
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(14U << 4*0)
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| (14U << 4*1)
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| (14U << 4*2)
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| (14U << 4*3)
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| (14U << 4*4)
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| (14U << 4*5)
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| (14U << 4*6)
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| (14U << 4*7)
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);
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GPIOJ->AFRH |= (
|
|
(14U << 4*(8-8))
|
|
| (14U << 4*(9-8))
|
|
| (14U << 4*(10-8))
|
|
| (14U << 4*(11-8))
|
|
| (14U << 4*(13-8))
|
|
| (14U << 4*(14-8))
|
|
| (14U << 4*(15-8))
|
|
);
|
|
|
|
//-------------------------------------------
|
|
// Initialise port PK
|
|
|
|
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOKEN;
|
|
GPIOK->MODER |= (
|
|
GPIO_MODER_MODER0_1 // PK0: LCD_G5 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
|
|
| GPIO_MODER_MODER1_1 // PK1: LCD_G6 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
|
|
| GPIO_MODER_MODER2_1 // PK2: LCD_G7 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
|
|
| GPIO_MODER_MODER3_0 // PK3: LCD_BL_CTRL - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_OUTPUT_PUSHPULL
|
|
| GPIO_MODER_MODER4_1 // PK4: LCD_B5 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
|
|
| GPIO_MODER_MODER5_1 // PK5: LCD_B6 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
|
|
| GPIO_MODER_MODER6_1 // PK6: LCD_B7 - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
|
|
| GPIO_MODER_MODER7_1 // PK7: LCD_DE - PAL_STM32_OSPEED_HIGHEST, PAL_MODE_ALTERNATE(14)
|
|
);
|
|
GPIOK->MODER &=~ (
|
|
GPIO_MODER_MODER0_0
|
|
| GPIO_MODER_MODER1_0
|
|
| GPIO_MODER_MODER2_0
|
|
| GPIO_MODER_MODER3_1
|
|
| GPIO_MODER_MODER4_0
|
|
| GPIO_MODER_MODER5_0
|
|
| GPIO_MODER_MODER6_0
|
|
| GPIO_MODER_MODER7_0
|
|
);
|
|
GPIOK->OTYPER &=~ (
|
|
GPIO_OTYPER_OT_0
|
|
| GPIO_OTYPER_OT_1
|
|
| GPIO_OTYPER_OT_2
|
|
| GPIO_OTYPER_OT_3
|
|
| GPIO_OTYPER_OT_4
|
|
| GPIO_OTYPER_OT_5
|
|
| GPIO_OTYPER_OT_6
|
|
| GPIO_OTYPER_OT_7
|
|
);
|
|
GPIOK->OSPEEDR |= (
|
|
GPIO_OSPEEDER_OSPEEDR0_0 | GPIO_OSPEEDER_OSPEEDR0_1
|
|
| GPIO_OSPEEDER_OSPEEDR1_0 | GPIO_OSPEEDER_OSPEEDR1_1
|
|
| GPIO_OSPEEDER_OSPEEDR2_0 | GPIO_OSPEEDER_OSPEEDR2_1
|
|
| GPIO_OSPEEDER_OSPEEDR3_0 | GPIO_OSPEEDER_OSPEEDR3_1
|
|
| GPIO_OSPEEDER_OSPEEDR4_0 | GPIO_OSPEEDER_OSPEEDR4_1
|
|
| GPIO_OSPEEDER_OSPEEDR5_0 | GPIO_OSPEEDER_OSPEEDR5_1
|
|
| GPIO_OSPEEDER_OSPEEDR6_0 | GPIO_OSPEEDER_OSPEEDR6_1
|
|
| GPIO_OSPEEDER_OSPEEDR7_0 | GPIO_OSPEEDER_OSPEEDR7_1
|
|
);
|
|
GPIOK->PUPDR &=~ (
|
|
GPIO_PUPDR_PUPDR0_0 | GPIO_PUPDR_PUPDR0_1
|
|
| GPIO_PUPDR_PUPDR1_0 | GPIO_PUPDR_PUPDR1_1
|
|
| GPIO_PUPDR_PUPDR2_0 | GPIO_PUPDR_PUPDR2_1
|
|
| GPIO_PUPDR_PUPDR3_0 | GPIO_PUPDR_PUPDR3_1
|
|
| GPIO_PUPDR_PUPDR4_0 | GPIO_PUPDR_PUPDR4_1
|
|
| GPIO_PUPDR_PUPDR5_0 | GPIO_PUPDR_PUPDR5_1
|
|
| GPIO_PUPDR_PUPDR6_0 | GPIO_PUPDR_PUPDR6_1
|
|
| GPIO_PUPDR_PUPDR7_0 | GPIO_PUPDR_PUPDR7_1
|
|
);
|
|
GPIOK->AFRL |= (
|
|
(14U << 4*0)
|
|
| (14U << 4*1)
|
|
| (14U << 4*2)
|
|
| ( 0U << 4*3)
|
|
| (14U << 4*4)
|
|
| (14U << 4*5)
|
|
| (14U << 4*6)
|
|
| (14U << 4*7)
|
|
);
|
|
#endif
|
|
}
|
|
|
|
static GFXINLINE void init_ltdc_clock()
|
|
{
|
|
// Reset the LTDC peripheral
|
|
RCC->APB2RSTR |= RCC_APB2RSTR_LTDCRST;
|
|
RCC->APB2RSTR = 0;
|
|
|
|
// Enable the LTDC clock
|
|
RCC->DCKCFGR1 = (RCC->DCKCFGR1 & ~RCC_DCKCFGR1_PLLSAIDIVR) | (1 << 16);
|
|
|
|
// Enable the peripheral
|
|
RCC->APB2ENR |= RCC_APB2ENR_LTDCEN;
|
|
}
|
|
|
|
#if LTDC_USE_DMA2D
|
|
static GFXINLINE void init_dma2d_clock()
|
|
{
|
|
// Enable DMA2D clock
|
|
RCC->AHB1ENR |= RCC_AHB1ENR_DMA2DEN;
|
|
}
|
|
#endif
|
|
|
|
static GFXINLINE void init_board(GDisplay *g) {
|
|
(void) g;
|
|
|
|
// Set pin directions
|
|
configureLcdPins();
|
|
|
|
// Enable the display and turn on the backlight
|
|
#if GFX_USE_OS_CHIBIOS && !GFX_LTDC_USE_DIRECTIO
|
|
palSetPad(GPIOI, GPIOI_LCD_DISP);
|
|
palSetPad(GPIOK, GPIOK_LCD_BL_CTRL);
|
|
#else
|
|
GPIOI->ODR |= (1 << 12); // PowerOn
|
|
GPIOK->ODR |= (1 << 3); // Backlight on
|
|
#endif
|
|
|
|
#if GFX_LTDC_TIMING_SET != 0
|
|
#define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */
|
|
#define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */
|
|
#define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */
|
|
#define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */
|
|
#define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */
|
|
#define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */
|
|
|
|
// Some operating systems get these wrong eg ChibiOS - define our own values
|
|
#undef STM32_PLLSAIN_VALUE
|
|
#undef STM32_PLLSAIQ_VALUE
|
|
#undef STM32_PLLSAIP_VALUE
|
|
#undef STM32_PLLSAIR_VALUE
|
|
|
|
/* Display timing */
|
|
// RK043FN48H LCD clock configuration
|
|
// PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 Mhz
|
|
// PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 192 Mhz
|
|
// PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 192/5 = 38.4 Mhz
|
|
// LTDC clock frequency = PLLLCDCLK / STM32_PLLSAIR_POST = 38.4/4 = 9.6Mhz
|
|
#if GFX_LTDC_TIMING_SET == 1
|
|
#define RK043FN48H_FREQUENCY_DIVIDER 5
|
|
#define STM32_PLLSAIN_VALUE 192
|
|
#define STM32_PLLSAIQ_VALUE 4
|
|
#define STM32_PLLSAIP_VALUE 4
|
|
#define STM32_PLLSAIR_VALUE RK043FN48H_FREQUENCY_DIVIDER
|
|
#define STM32_PLLSAIR_POST STM32_SAIR_DIV4
|
|
#elif GFX_LTDC_TIMING_SET == 2
|
|
#define RK043FN48H_FREQUENCY_DIVIDER 4
|
|
#define STM32_PLLSAIN_VALUE 192
|
|
#define STM32_PLLSAIQ_VALUE 4
|
|
#define STM32_PLLSAIP_VALUE 4
|
|
#define STM32_PLLSAIR_VALUE RK043FN48H_FREQUENCY_DIVIDER
|
|
#define STM32_PLLSAIR_POST STM32_SAIR_DIV4
|
|
#else
|
|
#error "LTDC: - Unknown timing set for the STM32F746-Discovery board"
|
|
#endif
|
|
|
|
RCC->CR &= ~RCC_CR_PLLSAION;
|
|
RCC->PLLSAICFGR = ((STM32_PLLSAIP_VALUE/2-1)<<16) | (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24);
|
|
RCC->DCKCFGR1 = (RCC->DCKCFGR1 & ~RCC_DCKCFGR1_PLLSAIDIVR) | STM32_PLLSAIR_POST;
|
|
RCC->CR |= RCC_CR_PLLSAION;
|
|
while(!(RCC->CR & RCC_CR_PLLSAIRDY)); // wait for PLLSAI to lock
|
|
#endif
|
|
|
|
// Initialise the SDRAM
|
|
BSP_SDRAM_Init();
|
|
}
|
|
|
|
static GFXINLINE void post_init_board(GDisplay* g) {
|
|
(void) g;
|
|
}
|
|
|
|
static GFXINLINE void set_backlight(GDisplay* g, gU8 percent) {
|
|
(void) g;
|
|
|
|
// ST was stupid enought not to hook this up to a pin that
|
|
// is able to act as PWM output...
|
|
#if GFX_USE_OS_CHIBIOS && !GFX_LTDC_USE_DIRECTIO
|
|
if (percent <= 0) {
|
|
palClearPad(GPIOK, GPIOK_LCD_BL_CTRL); // Backlight off
|
|
} else {
|
|
palSetPad(GPIOK, GPIOK_LCD_BL_CTRL); // Backlight on
|
|
}
|
|
#else
|
|
if (percent <= 0) {
|
|
GPIOK->ODR &=~ (1 << 3); // Backlight off
|
|
} else {
|
|
GPIOK->ODR |= (1 << 3); // Backlight on
|
|
}
|
|
#endif
|
|
}
|
|
|
|
#endif /* _GDISP_LLD_BOARD_H */
|