08e1b0ebc7
Documenting the drivers interface should be done inside a template driver or the gdisp LLD abstraction.
409 lines
12 KiB
C
409 lines
12 KiB
C
/*
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* This file is subject to the terms of the GFX License. If a copy of
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* the license was not distributed with this file, you can obtain one at:
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*
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* http://ugfx.org/license.html
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*/
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#include "gfx.h"
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#if GFX_USE_GDISP
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#define GDISP_DRIVER_VMT GDISPVMT_SSD2119
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#include "drivers/gdisp/SSD2119/gdisp_lld_config.h"
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#include "src/gdisp/driver.h"
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#include "board_SSD2119.h"
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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#ifndef GDISP_SCREEN_HEIGHT
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#define GDISP_SCREEN_HEIGHT 240
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#endif
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#ifndef GDISP_SCREEN_WIDTH
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#define GDISP_SCREEN_WIDTH 320
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#endif
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#ifndef GDISP_INITIAL_CONTRAST
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#define GDISP_INITIAL_CONTRAST 50
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#endif
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#ifndef GDISP_INITIAL_BACKLIGHT
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#define GDISP_INITIAL_BACKLIGHT 100
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#endif
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#include "drivers/gdisp/SSD2119/ssd2119.h"
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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// Some common routines and macros
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#define dummy_read(g) { volatile uint16_t dummy; dummy = read_data(g); (void) dummy; }
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#define write_reg(g, reg, data) { write_index(g, reg); write_data(g, data); }
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static void set_cursor(GDisplay* g) {
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/* Reg SSD2119_REG_X_RAM_ADDR is 9 bit value
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* Reg SSD2119_REG_Y_RAM_ADDR is an 8 bit
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* Use a bit mask to make sure they are not set too high
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*/
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switch(g->g.Orientation) {
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default:
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case GDISP_ROTATE_0:
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write_reg(g, SSD2119_REG_X_RAM_ADDR, g->p.x & 0x01FF);
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write_reg(g, SSD2119_REG_Y_RAM_ADDR, g->p.y & 0x00FF);
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break;
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case GDISP_ROTATE_90:
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write_reg(g, SSD2119_REG_X_RAM_ADDR, g->p.y & 0x01FF);
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write_reg(g, SSD2119_REG_Y_RAM_ADDR, (GDISP_SCREEN_HEIGHT-1 - g->p.x) & 0x00FF);
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break;
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case GDISP_ROTATE_180:
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write_reg(g, SSD2119_REG_X_RAM_ADDR, (GDISP_SCREEN_WIDTH-1 - g->p.x) & 0x01FF);
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write_reg(g, SSD2119_REG_Y_RAM_ADDR, (GDISP_SCREEN_HEIGHT-1 - g->p.y) & 0x00FF);
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break;
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case GDISP_ROTATE_270:
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write_reg(g, SSD2119_REG_X_RAM_ADDR, (GDISP_SCREEN_WIDTH-1 - g->p.y) & 0x01FF);
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write_reg(g, SSD2119_REG_Y_RAM_ADDR, g->p.x & 0x00FF);
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break;
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}
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write_index(g, SSD2119_REG_RAM_DATA);
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}
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static void set_viewport(GDisplay* g) {
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/* Reg 0x44 - Vertical RAM address position
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* Upper Byte - VEA
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* Lower Byte - VSA
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* 0 <= VSA <= VEA <= 0xEF
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* Reg 0x45,0x46 - Horizontal RAM address position
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* Lower 9 bits gives 0-511 range in each value, HSA and HEA respectively
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* 0 <= HSA <= HEA <= 0x13F
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*/
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switch(g->g.Orientation) {
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default:
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case GDISP_ROTATE_0:
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write_reg(g, SSD2119_REG_V_RAM_POS, (((g->p.y + g->p.cy - 1) << 8) & 0xFF00 ) | (g->p.y & 0x00FF));
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write_reg(g, SSD2119_REG_H_RAM_START, (g->p.x & 0x01FF));
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write_reg(g, SSD2119_REG_H_RAM_END, (g->p.x + g->p.cx - 1) & 0x01FF);
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break;
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case GDISP_ROTATE_90:
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write_reg(g, SSD2119_REG_V_RAM_POS, (((GDISP_SCREEN_HEIGHT-1 - g->p.x) & 0x00FF) << 8) | ((GDISP_SCREEN_HEIGHT - (g->p.x + g->p.cx)) & 0x00FF));
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write_reg(g, SSD2119_REG_H_RAM_START, (g->p.y & 0x01FF));
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write_reg(g, SSD2119_REG_H_RAM_END, (g->p.y + g->p.cy - 1) & 0x01FF);
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break;
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case GDISP_ROTATE_180:
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write_reg(g, SSD2119_REG_V_RAM_POS, (((GDISP_SCREEN_HEIGHT-1 - g->p.y) & 0x00FF) << 8) | ((GDISP_SCREEN_HEIGHT - (g->p.y + g->p.cy)) & 0x00FF));
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write_reg(g, SSD2119_REG_H_RAM_START, (GDISP_SCREEN_WIDTH - (g->p.x + g->p.cx)) & 0x01FF);
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write_reg(g, SSD2119_REG_H_RAM_END, (GDISP_SCREEN_WIDTH-1 - g->p.x) & 0x01FF);
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break;
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case GDISP_ROTATE_270:
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write_reg(g, SSD2119_REG_V_RAM_POS, (((g->p.x + g->p.cx - 1) << 8) & 0xFF00 ) | (g->p.x & 0x00FF));
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write_reg(g, SSD2119_REG_H_RAM_START, (GDISP_SCREEN_WIDTH - (g->p.y + g->p.cy)) & 0x01FF);
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write_reg(g, SSD2119_REG_H_RAM_END, (GDISP_SCREEN_WIDTH-1 - g->p.y) & 0x01FF);
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break;
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}
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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LLDSPEC bool_t gdisp_lld_init(GDisplay* g) {
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// no private area for this controller
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g->priv = 0;
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// initialise the board interface
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init_board(g);
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// Hardware reset
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setpin_reset(g, TRUE);
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gfxSleepMilliseconds(20);
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setpin_reset(g, FALSE);
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gfxSleepMilliseconds(20);
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// Get the bus for the following initialisation commands
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acquire_bus(g);
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// Enter sleep mode (if we are not already there).
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write_reg(g, SSD2119_REG_SLEEP_MODE_1, 0x0001);
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gfxSleepMicroseconds(5);
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// Set initial power parameters.
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write_reg(g, SSD2119_REG_PWR_CTRL_5, 0x00B2);
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gfxSleepMicroseconds(5);
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write_reg(g, SSD2119_REG_VCOM_OTP_1, 0x0006);
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gfxSleepMicroseconds(5);
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// Start the oscillator.
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write_reg(g, SSD2119_REG_OSC_START, 0x0001);
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gfxSleepMicroseconds(5);
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// Set pixel format and basic display orientation (scanning direction).
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write_reg(g, SSD2119_REG_OUTPUT_CTRL, 0x30EF);
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gfxSleepMicroseconds(5);
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write_reg(g, SSD2119_REG_LCD_DRIVE_AC_CTRL, 0x0600);
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gfxSleepMicroseconds(5);
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// Exit sleep mode.
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write_reg(g, SSD2119_REG_SLEEP_MODE_1, 0x0000);
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gfxSleepMicroseconds(5);
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// Configure pixel color format and MCU interface parameters.
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write_reg(g, SSD2119_REG_ENTRY_MODE, 0x6830); // ENTRY_MODE_DEFAULT
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gfxSleepMicroseconds(5);
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// Set analog parameters.
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write_reg(g, SSD2119_REG_SLEEP_MODE_2, 0x0999);
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gfxSleepMicroseconds(5);
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write_reg(g, SSD2119_REG_ANALOG_SET, 0x3800);
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gfxSleepMicroseconds(5);
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// Enable the display.
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write_reg(g, SSD2119_REG_DISPLAY_CTRL, 0x0033);
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gfxSleepMicroseconds(5);
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// Set VCIX2 voltage to 6.1V.
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write_reg(g, SSD2119_REG_PWR_CTRL_2, 0x0005);
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gfxSleepMicroseconds(5);
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// Configure gamma correction.
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write_reg(g, SSD2119_REG_GAMMA_CTRL_1, 0x0000);
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gfxSleepMicroseconds(5);
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write_reg(g, SSD2119_REG_GAMMA_CTRL_2, 0x0303);
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gfxSleepMicroseconds(5);
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write_reg(g, SSD2119_REG_GAMMA_CTRL_3, 0x0407);
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gfxSleepMicroseconds(5);
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write_reg(g, SSD2119_REG_GAMMA_CTRL_4, 0x0301);
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gfxSleepMicroseconds(5);
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write_reg(g, SSD2119_REG_GAMMA_CTRL_5, 0x0301);
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gfxSleepMicroseconds(5);
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write_reg(g, SSD2119_REG_GAMMA_CTRL_6, 0x0403);
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gfxSleepMicroseconds(5);
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write_reg(g, SSD2119_REG_GAMMA_CTRL_7, 0x0707);
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gfxSleepMicroseconds(5);
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write_reg(g, SSD2119_REG_GAMMA_CTRL_8, 0x0400);
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gfxSleepMicroseconds(5);
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write_reg(g, SSD2119_REG_GAMMA_CTRL_9, 0x0a00);
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gfxSleepMicroseconds(5);
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write_reg(g, SSD2119_REG_GAMMA_CTRL_10, 0x1000);
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gfxSleepMicroseconds(5);
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// Configure Vlcd63 and VCOMl.
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write_reg(g, SSD2119_REG_PWR_CTRL_3, 0x000A);
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gfxSleepMicroseconds(5);
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write_reg(g, SSD2119_REG_PWR_CTRL_4, 0x2E00);
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gfxSleepMicroseconds(5);
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// Set the display size and ensure that the GRAM window is set to allow access to the full display buffer.
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write_reg(g, SSD2119_REG_V_RAM_POS, (GDISP_SCREEN_HEIGHT - 1) << 8);
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gfxSleepMicroseconds(5);
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write_reg(g, SSD2119_REG_H_RAM_START, 0x0000);
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gfxSleepMicroseconds(5);
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write_reg(g, SSD2119_REG_H_RAM_END, GDISP_SCREEN_WIDTH - 1);
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gfxSleepMicroseconds(5);
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write_reg(g, SSD2119_REG_X_RAM_ADDR, 0x00);
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gfxSleepMicroseconds(5);
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write_reg(g, SSD2119_REG_Y_RAM_ADDR, 0x00);
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gfxSleepMicroseconds(5);
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// Finish Init
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post_init_board(g);
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// Release the bus
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release_bus(g);
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/* Turn on the back-light */
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set_backlight(g, GDISP_INITIAL_BACKLIGHT);
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/* Initialise the GDISP structure */
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g->g.Width = GDISP_SCREEN_WIDTH;
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g->g.Height = GDISP_SCREEN_HEIGHT;
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g->g.Orientation = GDISP_ROTATE_0;
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g->g.Powermode = powerOn;
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g->g.Backlight = GDISP_INITIAL_BACKLIGHT;
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g->g.Contrast = GDISP_INITIAL_CONTRAST;
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return TRUE;
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}
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#if GDISP_HARDWARE_STREAM_WRITE
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LLDSPEC void gdisp_lld_write_start(GDisplay* g) {
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acquire_bus(g);
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set_viewport(g);
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}
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LLDSPEC void gdisp_lld_write_color(GDisplay* g) {
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write_data(g, gdispColor2Native(g->p.color));
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}
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LLDSPEC void gdisp_lld_write_stop(GDisplay* g) {
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release_bus(g);
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}
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LLDSPEC void gdisp_lld_write_pos(GDisplay* g) {
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set_cursor(g);
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}
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#endif
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#if GDISP_HARDWARE_STREAM_READ
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LLDSPEC void gdisp_lld_read_start(GDisplay* g) {
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acquire_bus(g);
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set_viewport(g);
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set_cursor(g);
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setreadmode(g);
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dummy_read(g);
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}
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LLDSPEC color_t gdisp_lld_read_color(GDisplay* g) {
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uint16_t data;
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data = read_data(g);
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return gdispNative2Color(data);
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}
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LLDSPEC void gdisp_lld_read_stop(GDisplay* g) {
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setwritemode(g);
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release_bus(g);
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}
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#endif
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#if GDISP_HARDWARE_FILLS && defined(GDISP_USE_DMA)
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LLDSPEC void gdisp_lld_fill_area(GDisplay* g) {
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uint16_t c;
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c = gdispColor2Native(g->p.color);
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acquire_bus(g);
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set_viewport(g);
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set_cursor(g);
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dma_with_noinc(g, &c, g->p.cx * g->p.cy);
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release_bus(g);
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}
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#endif
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#if GDISP_HARDWARE_BITFILLS && defined(GDISP_USE_DMA)
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#if GDISP_PIXELFORMAT != GDISP_LLD_PIXELFORMAT
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#error "GDISP: SSD2119: BitBlit is only available in RGB565 pixel format"
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#endif
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LLDSPEC void gdisp_lld_blit_area(GDisplay* g) {
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pixel_t* buffer;
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coord_t ynct;
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buffer = (pixel_t*)g->p.ptr + g->p.x1 + g->p.y1 * g->p.x2;
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acquire_bus(g);
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set_viewport(g);
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set_cursor(g);
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if (g->p.x2 == g->p.cx) {
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dma_with_inc(g, buffer, g->p.cx * g->p.cy);
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} else {
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for (ycnt = g->p.cy; ycnt; ycnt--, buffer += g->p.x2)
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dma_with_inc(g, buffer, g->p.cy);
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}
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release_bus(g);
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}
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#endif
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#if GDISP_NEED_CONTROL && GDISP_HARDWARE_CONTROL
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LLDSPEC void gdisp_lld_control(GDisplay *g) {
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switch(g->p.x) {
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case GDISP_CONTROL_POWER:
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if (g->g.Powermode == (powermode_t)g->p.ptr)
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return;
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switch((powermode_t)g->p.ptr) {
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case powerOff:
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case powerDeepSleep:
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acquire_bus(g);
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write_reg(g, SSD2119_REG_SLEEP_MODE_1, 0x0001); // Enter sleep mode
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write_reg(g, SSD2119_REG_SLEEP_MODE_2, 0x2999); // Enable deep sleep function
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write_reg(g, SSD2119_REG_DISPLAY_CTRL, 0x0000); // Display off
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if ((powermode_t)g->p.ptr == powerOff)
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write_reg(g, SSD2119_REG_OSC_START, 0x0000); // Turn off oscillator
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release_bus(g);
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set_backlight(g, 0);
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break;
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case powerSleep:
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acquire_bus(g);
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write_reg(g, SSD2119_REG_SLEEP_MODE_1, 0x0001); // Enter sleep mode
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write_reg(g, SSD2119_REG_DISPLAY_CTRL, 0x0000); // Display off
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release_bus(g);
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set_backlight(g, 0);
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break;
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case powerOn:
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acquire_bus(g);
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if (g->g.Powermode == powerOff) {
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write_reg(g, SSD2119_REG_OSC_START, 0x0001); // Start the oscillator
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gfxSleepMicroseconds(5);
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write_reg(g, SSD2119_REG_SLEEP_MODE_2, 0x0999); // Disable deep sleep function
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} else if (g->g.Powermode == powerDeepSleep)
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write_reg(g, SSD2119_REG_SLEEP_MODE_2, 0x0999); // Disable deep sleep function
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write_reg(g, SSD2119_REG_SLEEP_MODE_1, 0x0000); // Leave sleep mode
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write_reg(g, SSD2119_REG_DISPLAY_CTRL, 0x0033); // Display on
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release_bus(g);
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gfxSleepMicroseconds(25);
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set_backlight(g, g->g.Backlight);
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break;
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default:
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return;
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}
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g->g.Powermode = (powermode_t)g->p.ptr;
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return;
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case GDISP_CONTROL_ORIENTATION:
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if (g->g.Orientation == (orientation_t)g->p.ptr)
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return;
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switch((orientation_t)g->p.ptr) {
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case GDISP_ROTATE_0:
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acquire_bus(g);
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/* ID = 11 AM = 0 */
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write_reg(g, SSD2119_REG_ENTRY_MODE, 0x6830);
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release_bus(g);
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g->g.Height = GDISP_SCREEN_HEIGHT;
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g->g.Width = GDISP_SCREEN_WIDTH;
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break;
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case GDISP_ROTATE_90:
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acquire_bus(g);
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/* ID = 01 AM = 1 */
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write_reg(g, SSD2119_REG_ENTRY_MODE, 0x6818);
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release_bus(g);
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g->g.Height = GDISP_SCREEN_WIDTH;
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g->g.Width = GDISP_SCREEN_HEIGHT;
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break;
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case GDISP_ROTATE_180:
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acquire_bus(g);
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/* ID = 00 AM = 0 */
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write_reg(g, SSD2119_REG_ENTRY_MODE, 0x6800);
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release_bus(g);
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g->g.Height = GDISP_SCREEN_HEIGHT;
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g->g.Width = GDISP_SCREEN_WIDTH;
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break;
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case GDISP_ROTATE_270:
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acquire_bus(g);
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/* ID = 10 AM = 1 */
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write_reg(g, SSD2119_REG_ENTRY_MODE, 0x6828);
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release_bus(g);
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g->g.Height = GDISP_SCREEN_WIDTH;
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g->g.Width = GDISP_SCREEN_HEIGHT;
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break;
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default:
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return;
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}
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g->g.Orientation = (orientation_t)g->p.ptr;
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return;
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case GDISP_CONTROL_BACKLIGHT:
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if ((unsigned)g->p.ptr > 100)
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g->p.ptr = (void *)100;
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set_backlight(g, (unsigned)g->p.ptr);
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g->g.Backlight = (unsigned)g->p.ptr;
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return;
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//case GDISP_CONTROL_CONTRAST:
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default:
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return;
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}
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}
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#endif
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#endif /* GFX_USE_GDISP */
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