217 lines
6.3 KiB
C
217 lines
6.3 KiB
C
/*
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* This file is subject to the terms of the GFX License. If a copy of
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* the license was not distributed with this file, you can obtain one at:
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*
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* http://ugfx.io/license.html
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*/
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#ifndef _GDISP_LLD_BOARD_H
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#define _GDISP_LLD_BOARD_H
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#include "stm32f4xx_fmc.h"
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#include "stm32f429i_discovery_sdram.h"
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#include <string.h>
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#define SPI_PORT &SPID5
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#define DC_PORT GPIOD
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#define DC_PIN GPIOD_LCD_WRX
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static const SPIConfig spi_cfg = {
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NULL,
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GPIOC,
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GPIOC_SPI5_LCD_CS,
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((1 << 3) & SPI_CR1_BR) | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR
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};
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#define LTDC_USE_DMA2D GFXON
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#define LTDC_USE_2ND_LAYER GFXON
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#define LTDC_DMA_CACHE_FLUSH GFXOFF // This will be turned on automatically on certain systems/platforms
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static const ltdcConfig driverCfg = {
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240, 320,
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10, 2,
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20, 2,
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10, 4,
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0,
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0x000000,
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{
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(LLDCOLOR_TYPE *)SDRAM_BANK_ADDR, // frame
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240, 320, // width, height
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240 * LTDC_PIXELBYTES, // pitch
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LTDC_PIXELFORMAT, // fmt
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0, 0, // x, y
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240, 320, // cx, cy
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0x00000000, // defcolor
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0x000000, // keycolor
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LTDC_BLEND_FIX1_FIX2, // blending
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0, // palette
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0, // palettelen
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0xFF, // alpha
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LTDC_LEF_ENABLE // flags
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},
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#if LTDC_USE_2ND_LAYER
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{ // Foreground layer config (if turned on)
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(LLDCOLOR_TYPE *)(SDRAM_BANK_ADDR+(240 * 320 * LTDC_PIXELBYTES)), // Frame buffer address
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240, 320, // width, height
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240 * LTDC_PIXELBYTES, // pitch
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LTDC_PIXELFORMAT, // fmt
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0, 0, // x, y
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240, 320, // cx, cy
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0x00000000, // Default color (ARGB8888)
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0x000000, // Color key (RGB888)
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LTDC_BLEND_MOD1_MOD2, // Blending factors
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0, // Palette (RGB888, can be NULL)
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0, // Palette length
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0xFF, // Constant alpha factor
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LTDC_LEF_ENABLE // Layer configuration flags
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}
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#else
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LTDC_UNUSED_LAYER_CONFIG
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#endif
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};
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#include "ili9341.h"
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static void acquire_bus(GDisplay *g) {
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(void) g;
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spiSelect(SPI_PORT);
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}
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static void release_bus(GDisplay *g) {
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(void) g;
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spiUnselect(SPI_PORT);
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}
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static void write_index(GDisplay *g, gU8 index) {
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static gU8 sindex;
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(void) g;
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palClearPad(DC_PORT, DC_PIN);
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sindex = index;
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spiSend(SPI_PORT, 1, &sindex);
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}
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static void write_data(GDisplay *g, gU8 data) {
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static gU8 sdata;
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(void) g;
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palSetPad(DC_PORT, DC_PIN);
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sdata = data;
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spiSend(SPI_PORT, 1, &sdata);
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}
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static void Init9341(GDisplay *g) {
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#define REG_TYPEMASK 0xFF00
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#define REG_DATAMASK 0x00FF
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#define REG_DATA 0x0000
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#define REG_COMMAND 0x0100
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#define REG_DELAY 0x0200
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static const gU16 initdata[] = {
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REG_COMMAND | ILI9341_CMD_RESET,
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REG_DELAY | 5,
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REG_COMMAND | ILI9341_CMD_DISPLAY_OFF,
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REG_COMMAND | ILI9341_SET_FRAME_CTL_NORMAL, 0x00, 0x1B,
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REG_COMMAND | ILI9341_SET_FUNCTION_CTL, 0x0A, 0xA2,
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REG_COMMAND | ILI9341_SET_POWER_CTL_1, 0x10,
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REG_COMMAND | ILI9341_SET_POWER_CTL_2, 0x10,
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#if 1
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REG_COMMAND | ILI9341_SET_VCOM_CTL_1, 0x45, 0x15,
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REG_COMMAND | ILI9341_SET_VCOM_CTL_2, 0x90,
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#else
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REG_COMMAND | ILI9341_SET_VCOM_CTL_1, 0x35, 0x3E,
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REG_COMMAND | ILI9341_SET_VCOM_CTL_2, 0xBE,
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#endif
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REG_COMMAND | ILI9341_SET_MEM_ACS_CTL, 0xC8,
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REG_COMMAND | ILI9341_SET_RGB_IF_SIG_CTL, 0xC2,
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REG_COMMAND | ILI9341_SET_FUNCTION_CTL, 0x0A, 0xA7, 0x27, 0x04,
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REG_COMMAND | ILI9341_SET_COL_ADDR, 0x00, 0x00, 0x00, 0xEF,
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REG_COMMAND | ILI9341_SET_PAGE_ADDR, 0x00, 0x00, 0x01, 0x3F,
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REG_COMMAND | ILI9341_SET_IF_CTL, 0x01, 0x00, 0x06,
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REG_COMMAND | ILI9341_SET_GAMMA, 0x01,
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REG_COMMAND | ILI9341_SET_PGAMMA,
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#if 1
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0x0F, 0x29, 0x24, 0x0C, 0x0E, 0x09, 0x4E, 0x78,
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0x3C, 0x09, 0x13, 0x05, 0x17, 0x11, 0x00,
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#else
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0x1F, 0x1a, 0x18, 0x0a, 0x0f, 0x06, 0x45, 0x87,
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0x32, 0x0a, 0x07, 0x02, 0x07, 0x05, 0x00,
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#endif
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REG_COMMAND | ILI9341_SET_NGAMMA,
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#if 1
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0x00, 0x16, 0x1B, 0x04, 0x11, 0x07, 0x31, 0x33,
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0x42, 0x05, 0x0C, 0x0A, 0x28, 0x2F, 0x0F,
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#else
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0x00, 0x25, 0x27, 0x05, 0x10, 0x09, 0x3a, 0x78,
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0x4d, 0x05, 0x18, 0x0d, 0x38, 0x3a, 0x1f,
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#endif
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REG_COMMAND | ILI9341_CMD_SLEEP_OFF,
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REG_DELAY | 10,
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REG_COMMAND | ILI9341_CMD_DISPLAY_ON,
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REG_COMMAND | ILI9341_SET_MEM
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};
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const gU16 *p;
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acquire_bus(g);
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for(p = initdata; p < &initdata[sizeof(initdata)/sizeof(initdata[0])]; p++) {
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switch(*p & REG_TYPEMASK) {
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case REG_DATA: write_data(g, *p); break;
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case REG_COMMAND: write_index(g, *p); break;
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case REG_DELAY: gfxSleepMilliseconds(*p & 0xFF); break;
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}
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}
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release_bus(g);
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}
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static void init_board(GDisplay *g) {
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(void) g;
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palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); // UART_TX
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palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7)); // UART_RX
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palSetPadMode(GPIOF, GPIOF_LCD_DCX, PAL_MODE_ALTERNATE(5));
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palSetPadMode(GPIOF, GPIOF_LCD_DE, PAL_MODE_ALTERNATE(14));
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#define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */
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#define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */
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#define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */
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#define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */
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#define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */
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#define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */
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#define STM32_PLLSAIN_VALUE 192
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#define STM32_PLLSAIQ_VALUE 7
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#define STM32_PLLSAIR_VALUE 4
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#define STM32_PLLSAIR_POST STM32_SAIR_DIV4
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/* PLLSAI activation.*/
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RCC->PLLSAICFGR = (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24);
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RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST;
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RCC->CR |= RCC_CR_PLLSAION;
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while(!(RCC->CR & RCC_CR_PLLSAIRDY)); // wait for PLLSAI to lock
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// Initialise the SDRAM
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SDRAM_Init();
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// Clear the SDRAM
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memset((void *)SDRAM_BANK_ADDR, 0, 0x400000);
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spiStart(SPI_PORT, &spi_cfg);
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Init9341(g);
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}
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static GFXINLINE void post_init_board(GDisplay *g) {
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(void) g;
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}
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static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
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(void) g;
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(void) percent;
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}
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#endif /* _GDISP_LLD_BOARD_H */
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