86 lines
2.8 KiB
C
86 lines
2.8 KiB
C
/*
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* This file is subject to the terms of the GFX License. If a copy of
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* the license was not distributed with this file, you can obtain one at:
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*
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* http://ugfx.org/license.html
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*/
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#ifndef _GDISP_LLD_BOARD_H
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#define _GDISP_LLD_BOARD_H
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#include "stm32f4xx_fmc.h"
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#include "stm32f429i_discovery_sdram.h"
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#include <string.h>
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static const ltdcConfig driverCfg = {
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480, 270, // Width, Height (pixels)
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41, 10, // Horizontal, Vertical sync (pixels)
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13, 2, // Horizontal, Vertical back porch (pixels)
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32, 2, // Horizontal, Vertical front porch (pixels)
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0, // Sync flags
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0x000000, // Clear color (RGB888)
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{ // Background layer config
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(LLDCOLOR_TYPE *)SDRAM_BANK_ADDR, // Frame buffer address
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480, 270, // Width, Height (pixels)
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480 * LTDC_PIXELBYTES, // Line pitch (bytes)
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LTDC_PIXELFORMAT, // Pixel format
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0, 0, // Start pixel position (x, y)
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480, 270, // Size of virtual layer (cx, cy)
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LTDC_COLOR_FUCHSIA, // Default color (ARGB8888)
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0x980088, // Color key (RGB888)
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LTDC_BLEND_FIX1_FIX2, // Blending factors
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0, // Palette (RGB888, can be NULL)
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0, // Palette length
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0xFF, // Constant alpha factor
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LTDC_LEF_ENABLE // Layer configuration flags
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},
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LTDC_UNUSED_LAYER_CONFIG // Foreground layer config
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};
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static inline void init_board(GDisplay *g) {
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// As we are not using multiple displays we set g->board to NULL as we don't use it.
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g->board = 0;
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switch(g->controllerdisplay) {
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case 0:
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#define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */
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#define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */
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#define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */
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#define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */
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#define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */
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#define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */
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#define STM32_PLLSAIN_VALUE 192
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#define STM32_PLLSAIQ_VALUE 7
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#define STM32_PLLSAIR_VALUE 4
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#define STM32_PLLSAIR_POST STM32_SAIR_DIV4
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/* PLLSAI activation.*/
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RCC->PLLSAICFGR = (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24);
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RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST;
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RCC->CR |= RCC_CR_PLLSAION;
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// Initialise the SDRAM
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SDRAM_Init();
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// Clear the SDRAM
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memset((void *)SDRAM_BANK_ADDR, 0, 0x400000);
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break;
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}
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}
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static inline void post_init_board(GDisplay *g) {
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(void) g;
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}
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static inline void set_backlight(GDisplay *g, uint8_t percent) {
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(void) g;
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(void) percent;
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}
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#endif /* _GDISP_LLD_BOARD_H */
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