131 lines
3.3 KiB
C
131 lines
3.3 KiB
C
/*
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* This file is subject to the terms of the GFX License. If a copy of
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* the license was not distributed with this file, you can obtain one at:
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*
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* http://ugfx.org/license.html
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*/
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#ifndef _GDISP_LLD_BOARD_H
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#define _GDISP_LLD_BOARD_H
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#include "stm32f4xx_fmc.h"
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#include "stm32f429i_discovery_sdram.h"
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#include <string.h>
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#define SPI_PORT &SPID5
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#define DC_PORT GPIOD
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#define DC_PIN GPIOD_LCD_WRX
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static const SPIConfig spi_cfg = {
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NULL,
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GPIOC,
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GPIOC_SPI5_LCD_CS,
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((1 << 3) & SPI_CR1_BR) | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR
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};
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static const ltdcConfig driverCfg = {
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240, 320,
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10, 2,
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20, 2,
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10, 4,
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0,
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0x000000,
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{
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(LLDCOLOR_TYPE *)SDRAM_BANK_ADDR, // frame
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240, 320, // width, height
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240 * LTDC_PIXELBYTES, // pitch
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LTDC_PIXELFORMAT, // fmt
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0, 0, // x, y
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240, 320, // cx, cy
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LTDC_COLOR_FUCHSIA, // defcolor
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0x980088, // keycolor
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LTDC_BLEND_FIX1_FIX2, // blending
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0, // palette
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0, // palettelen
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0xFF, // alpha
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LTDC_LEF_ENABLE // flags
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},
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LTDC_UNUSED_LAYER_CONFIG
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};
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static GFXINLINE void init_board(GDisplay *g) {
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// As we are not using multiple displays we set g->board to NULL as we don't use it.
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g->board = 0;
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switch(g->controllerdisplay) {
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case 0: // Set up for Display 0
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palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); // UART_TX
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palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7)); // UART_RX
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palSetPadMode(GPIOF, GPIOF_LCD_DCX, PAL_MODE_ALTERNATE(5));
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palSetPadMode(GPIOF, GPIOF_LCD_DE, PAL_MODE_ALTERNATE(14));
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#define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */
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#define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */
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#define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */
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#define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */
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#define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */
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#define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */
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#define STM32_PLLSAIN_VALUE 192
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#define STM32_PLLSAIQ_VALUE 7
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#define STM32_PLLSAIR_VALUE 4
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#define STM32_PLLSAIR_POST STM32_SAIR_DIV4
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/* PLLSAI activation.*/
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RCC->PLLSAICFGR = (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24);
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RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST;
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RCC->CR |= RCC_CR_PLLSAION;
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// Initialise the SDRAM
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SDRAM_Init();
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// Clear the SDRAM
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memset((void *)SDRAM_BANK_ADDR, 0, 0x400000);
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spiStart(SPI_PORT, &spi_cfg);
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break;
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}
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}
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static GFXINLINE void post_init_board(GDisplay *g) {
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(void) g;
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}
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static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
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(void) g;
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(void) percent;
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}
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static GFXINLINE void acquire_bus(GDisplay *g) {
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(void) g;
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spiSelect(SPI_PORT);
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}
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static GFXINLINE void release_bus(GDisplay *g) {
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(void) g;
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spiUnselect(SPI_PORT);
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}
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static GFXINLINE void write_index(GDisplay *g, uint8_t index) {
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static uint8_t sindex;
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(void) g;
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palClearPad(DC_PORT, DC_PIN);
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sindex = index;
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spiSend(SPI_PORT, 1, &sindex);
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}
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static GFXINLINE void write_data(GDisplay *g, uint8_t data) {
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static uint8_t sdata;
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(void) g;
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palSetPad(DC_PORT, DC_PIN);
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sdata = data;
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spiSend(SPI_PORT, 1, &sdata);
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}
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#endif /* _GDISP_LLD_BOARD_H */
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