137 lines
3.5 KiB
C
137 lines
3.5 KiB
C
/*
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* This file is subject to the terms of the GFX License. If a copy of
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* the license was not distributed with this file, you can obtain one at:
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*
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* http://ugfx.org/license.html
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*/
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/**
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* @file boards/addons/gdisp/board_SSD1306_spi.h
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* @brief GDISP Graphic Driver subsystem board interface for the SSD1306 display.
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*
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* @note This file contains a mix of hardware specific and operating system specific
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* code. You will need to change it for your CPU and/or operating system.
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*/
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#ifndef _GDISP_LLD_BOARD_H
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#define _GDISP_LLD_BOARD_H
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// The command byte to put on the front of each page line
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#define SSD1306_PAGE_PREFIX 0x40 // Co = 0, D/C = 1
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// For a multiple display configuration we would put all this in a structure and then
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// set g->board to that structure.
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#define SSD1306_RESET_PORT GPIOB
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#define SSD1306_RESET_PIN 5
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#define SSD1306_MISO_PORT GPIOB
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#define SSD1306_MISO_PIN 8
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#define SSD1306_MOSI_PORT GPIOB
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#define SSD1306_MOSI_PIN 7
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#define SSD1306_SCK_PORT GPIOB
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#define SSD1306_SCK_PIN 6
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#define SSD1306_CS_PORT GPIOB
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#define SSD1306_CS_PIN 5
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#define SET_RST palSetPad(SSD1306_RESET_PORT, SSD1306_RESET_PIN);
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#define CLR_RST palClearPad(SSD1306_RESET_PORT, SSD1306_RESET_PIN);
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/*
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* SPI1 configuration structure.
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* Speed 42MHz, CPHA=0, CPOL=0, 8bits frames, MSb transmitted first.
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* The slave select line is the pin 4 on the port GPIOA.
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*/
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static const SPIConfig spi1config = {
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0,
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/* HW dependent part.*/
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SSD1306_MISO_PORT,
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SSD1306_MISO_PIN,
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0
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//SPI_CR1_BR_0
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};
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#if GFX_USE_OS_CHIBIOS
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static int32_t thdPriority = 0;
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#endif
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static inline void init_board(GDisplay *g) {
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unsigned i;
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// As we are not using multiple displays we set g->board to NULL as we don't use it.
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g->board = 0;
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switch(g->controllerdisplay) {
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case 0: // Set up for Display 0
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// RESET pin.
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palSetPadMode(SSD1306_RESET_PORT, SSD1306_RESET_PIN, PAL_MODE_OUTPUT_PUSHPULL);
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palSetPadMode(SSD1306_MISO_PORT, SSD1306_MISO_PIN, PAL_MODE_ALTERNATE(1)|
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PAL_STM32_OSPEED_HIGHEST);
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palSetPadMode(SSD1306_MOSI_PORT, SSD1306_MOSI_PIN, PAL_MODE_ALTERNATE(1)|
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PAL_STM32_OSPEED_HIGHEST);
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palSetPadMode(SSD1306_SCK_PORT, SSD1306_SCK_PIN, PAL_MODE_ALTERNATE(1)|
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PAL_STM32_OSPEED_HIGHEST);
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palSetPad(SSD1306_CS_PORT, SSD1306_CS_PIN);
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palSetPadMode(SSD1306_CS_PORT, SSD1306_CS_PIN, PAL_MODE_ALTERNATE(1)|
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PAL_STM32_OSPEED_HIGHEST);
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spiInit();
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break;
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}
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}
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static inline void post_init_board(GDisplay *g) {
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(void) g;
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}
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static inline void setpin_reset(GDisplay *g, bool_t state) {
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(void) g;
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if(state)
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CLR_RST
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else
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SET_RST
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}
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static inline void acquire_bus(GDisplay *g) {
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(void) g;
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#if GFX_USE_OS_CHIBIOS
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thdPriority = (int32_t)chThdGetPriority();
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chThdSetPriority(HIGHPRIO);
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#endif
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spiAcquireBus(&SPID1);
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}
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static inline void release_bus(GDisplay *g) {
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(void) g;
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#if GFX_USE_OS_CHIBIOS
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chThdSetPriority(thdPriority);
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#endif
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spiReleaseBus(&SPID1);
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}
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static inline void write_cmd(GDisplay *g, uint8_t cmd) {
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uint8_t command[2];
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(void) g;
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command[0] = 0x00; // Co = 0, D/C = 0
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command[1] = cmd;
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spiStart(&SPID1, &spi1config);
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spiSelect(&SPID1);
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spiStartSend(&SPID1, 2, command);
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spiUnselect(&SPID1);
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spiStop(&SPID1);
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}
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static inline void write_data(GDisplay *g, uint8_t* data, uint16_t length) {
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(void) g;
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spiStart(&SPID1, &spi1config);
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spiSelect(&SPID1);
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spiStartSend(&SPID1, length, data);
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spiUnselect(&SPID1);
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spiStop(&SPID1);
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}
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#endif /* _GDISP_LLD_BOARD_H */
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