Merge branch 'master' into Alternate_Raw32_Scheduler
Conflicts: src/gos/gos_raw32.c
This commit is contained in:
commit
0367815bab
30
boards/base/STM32F746-Discovery/board.mk
Normal file
30
boards/base/STM32F746-Discovery/board.mk
Normal file
@ -0,0 +1,30 @@
|
||||
GFXINC += $(GFXLIB)/boards/base/STM32F746-Discovery
|
||||
GFXSRC += $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c \
|
||||
$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f7xx_ll_fmc.c
|
||||
GFXDEFS += STM32F746xx
|
||||
|
||||
ifeq ($(OPT_OS),raw32)
|
||||
GFXSRC += $(HAL)/Src/stm32f7xx_hal.c \
|
||||
$(HAL)/Src/stm32f7xx_hal_cortex.c \
|
||||
$(HAL)/Src/stm32f7xx_hal_flash.c \
|
||||
$(HAL)/Src/stm32f7xx_hal_flash_ex.c \
|
||||
$(HAL)/Src/stm32f7xx_hal_rcc.c \
|
||||
$(HAL)/Src/stm32f7xx_hal_rcc_ex.h \
|
||||
$(HAL)/Src/stm32f7xx_hal_gpio.c \
|
||||
$(HAL)/Src/stm32f7xx_hal_pwr.c \
|
||||
$(HAL)/Src/stm32f7xx_hal_pwr_ex.c \
|
||||
$(HAL)/Src/stm32f7xx_hal_sdram.c \
|
||||
$(HAL)/Src/stm32f7xx_hal_dma.c
|
||||
GFXSRC += $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_startup.s \
|
||||
$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c \
|
||||
$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c \
|
||||
$(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746g_raw32_interrupts.c
|
||||
GFXDEFS += GFX_OS_EXTRA_INIT_FUNCTION=Raw32OSInit
|
||||
SRCFLAGS+= -std=c99
|
||||
GFXINC += $(CMSIS)/Device/ST/STM32F7xx/Include \
|
||||
$(CMSIS)/Include \
|
||||
$(HAL)/Inc
|
||||
LDSCRIPT = $(GFXLIB)/boards/base/STM32F746-Discovery/stm32f746nghx_flash.ld
|
||||
endif
|
||||
|
||||
include $(GFXLIB)/drivers/gdisp/STM32LTDC/driver.mk
|
170
boards/base/STM32F746-Discovery/board_STM32LTDC.h
Normal file
170
boards/base/STM32F746-Discovery/board_STM32LTDC.h
Normal file
@ -0,0 +1,170 @@
|
||||
/*
|
||||
* This file is subject to the terms of the GFX License. If a copy of
|
||||
* the license was not distributed with this file, you can obtain one at:
|
||||
*
|
||||
* http://ugfx.org/license.html
|
||||
*/
|
||||
|
||||
#ifndef _GDISP_LLD_BOARD_H
|
||||
#define _GDISP_LLD_BOARD_H
|
||||
|
||||
#include "stm32f7xx_ll_fmc.h"
|
||||
#include "stm32f746g_discovery_sdram.h"
|
||||
#include <string.h>
|
||||
|
||||
static const ltdcConfig driverCfg = {
|
||||
480, 272, // Width, Height (pixels)
|
||||
41, 10, // Horizontal, Vertical sync (pixels)
|
||||
13, 2, // Horizontal, Vertical back porch (pixels)
|
||||
32, 2, // Horizontal, Vertical front porch (pixels)
|
||||
0, // Sync flags
|
||||
0x000000, // Clear color (RGB888)
|
||||
|
||||
{ // Background layer config
|
||||
(LLDCOLOR_TYPE *)SDRAM_DEVICE_ADDR, // Frame buffer address
|
||||
480, 272, // Width, Height (pixels)
|
||||
480 * LTDC_PIXELBYTES, // Line pitch (bytes)
|
||||
LTDC_PIXELFORMAT, // Pixel format
|
||||
0, 0, // Start pixel position (x, y)
|
||||
480, 272, // Size of virtual layer (cx, cy)
|
||||
LTDC_COLOR_FUCHSIA, // Default color (ARGB8888)
|
||||
0x980088, // Color key (RGB888)
|
||||
LTDC_BLEND_FIX1_FIX2, // Blending factors
|
||||
0, // Palette (RGB888, can be NULL)
|
||||
0, // Palette length
|
||||
0xFF, // Constant alpha factor
|
||||
LTDC_LEF_ENABLE // Layer configuration flags
|
||||
},
|
||||
|
||||
LTDC_UNUSED_LAYER_CONFIG // Foreground layer config
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief LCD special pins
|
||||
*/
|
||||
/* Display enable pin */
|
||||
#define LCD_DISP_PIN GPIO_PIN_12
|
||||
#define LCD_DISP_GPIO_PORT GPIOI
|
||||
|
||||
/* Backlight control pin */
|
||||
#define LCD_BL_CTRL_PIN GPIO_PIN_3
|
||||
#define LCD_BL_CTRL_GPIO_PORT GPIOK
|
||||
|
||||
/* Display timing */
|
||||
#define RK043FN48H_FREQUENCY_DIVIDER 5
|
||||
|
||||
static void SetBoardPinDirectionsForLCD(void)
|
||||
{
|
||||
GPIO_InitTypeDef gpio_init_structure;
|
||||
|
||||
// Enable GPIOs clock */
|
||||
__HAL_RCC_GPIOE_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOG_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOI_CLK_ENABLE(); // Display pin
|
||||
__HAL_RCC_GPIOJ_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOK_CLK_ENABLE(); // BL pin
|
||||
|
||||
//*** LTDC Pins configuration
|
||||
// GPIOE configuration
|
||||
gpio_init_structure.Pin = GPIO_PIN_4;
|
||||
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
|
||||
gpio_init_structure.Pull = GPIO_NOPULL;
|
||||
gpio_init_structure.Speed = GPIO_SPEED_FAST;
|
||||
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
|
||||
HAL_GPIO_Init(GPIOE, &gpio_init_structure);
|
||||
|
||||
// GPIOG configuration
|
||||
gpio_init_structure.Pin = GPIO_PIN_12;
|
||||
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
|
||||
gpio_init_structure.Alternate = GPIO_AF9_LTDC;
|
||||
HAL_GPIO_Init(GPIOG, &gpio_init_structure);
|
||||
|
||||
// GPIOI LTDC alternate configuration
|
||||
gpio_init_structure.Pin = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | \
|
||||
GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
|
||||
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
|
||||
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
|
||||
HAL_GPIO_Init(GPIOI, &gpio_init_structure);
|
||||
|
||||
// GPIOJ configuration
|
||||
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | \
|
||||
GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | \
|
||||
GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | \
|
||||
GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
|
||||
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
|
||||
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
|
||||
HAL_GPIO_Init(GPIOJ, &gpio_init_structure);
|
||||
|
||||
// GPIOK configuration
|
||||
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | \
|
||||
GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7;
|
||||
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
|
||||
gpio_init_structure.Alternate = GPIO_AF14_LTDC;
|
||||
HAL_GPIO_Init(GPIOK, &gpio_init_structure);
|
||||
|
||||
// LCD_DISP GPIO configuration
|
||||
gpio_init_structure.Pin = LCD_DISP_PIN; /* LCD_DISP pin has to be manually controlled */
|
||||
gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
HAL_GPIO_Init(LCD_DISP_GPIO_PORT, &gpio_init_structure);
|
||||
|
||||
// LCD_BL_CTRL GPIO configuration
|
||||
gpio_init_structure.Pin = LCD_BL_CTRL_PIN; /* LCD_BL_CTRL pin has to be manually controlled */
|
||||
gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
HAL_GPIO_Init(LCD_BL_CTRL_GPIO_PORT, &gpio_init_structure);
|
||||
}
|
||||
|
||||
static inline void init_board(GDisplay *g) {
|
||||
|
||||
// As we are not using multiple displays we set g->board to NULL as we don't use it.
|
||||
g->board = 0;
|
||||
|
||||
switch(g->controllerdisplay) {
|
||||
case 0:
|
||||
|
||||
// Set pin directions
|
||||
SetBoardPinDirectionsForLCD();
|
||||
|
||||
// Enable the display and turn on the backlight
|
||||
HAL_GPIO_WritePin(LCD_DISP_GPIO_PORT, LCD_DISP_PIN, GPIO_PIN_SET);
|
||||
HAL_GPIO_WritePin(LCD_BL_CTRL_GPIO_PORT, LCD_BL_CTRL_PIN, GPIO_PIN_SET);
|
||||
|
||||
#define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */
|
||||
#define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */
|
||||
#define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */
|
||||
#define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */
|
||||
#define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */
|
||||
#define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */
|
||||
|
||||
// RK043FN48H LCD clock configuration
|
||||
// PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 Mhz
|
||||
// PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 192 Mhz
|
||||
// PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 192/5 = 38.4 Mhz
|
||||
// LTDC clock frequency = PLLLCDCLK / LTDC_PLLSAI_DIVR_4 = 38.4/4 = 9.6Mhz
|
||||
#define STM32_PLLSAIN_VALUE 192
|
||||
#define STM32_PLLSAIQ_VALUE 7
|
||||
#define STM32_PLLSAIR_VALUE RK043FN48H_FREQUENCY_DIVIDER
|
||||
#define STM32_PLLSAIR_POST STM32_SAIR_DIV4
|
||||
RCC->PLLSAICFGR = (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24);
|
||||
RCC->DCKCFGR1 = (RCC->DCKCFGR1 & ~RCC_DCKCFGR1_PLLSAIDIVR) | STM32_PLLSAIR_POST;
|
||||
RCC->CR |= RCC_CR_PLLSAION;
|
||||
|
||||
// Initialise the SDRAM
|
||||
BSP_SDRAM_Init();
|
||||
|
||||
// Clear the SDRAM
|
||||
//memset((void *)SDRAM_BANK_ADDR, 0, 0x400000);
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void post_init_board(GDisplay *g) {
|
||||
(void) g;
|
||||
}
|
||||
|
||||
static inline void set_backlight(GDisplay *g, uint8_t percent) {
|
||||
(void) g;
|
||||
(void) percent;
|
||||
}
|
||||
|
||||
#endif /* _GDISP_LLD_BOARD_H */
|
72
boards/base/STM32F746-Discovery/example_raw32/Makefile
Normal file
72
boards/base/STM32F746-Discovery/example_raw32/Makefile
Normal file
@ -0,0 +1,72 @@
|
||||
# Possible Targets: all clean Debug cleanDebug Release cleanRelease
|
||||
|
||||
##############################################################################################
|
||||
# Settings
|
||||
#
|
||||
|
||||
# General settings
|
||||
# See $(GFXLIB)/tools/gmake_scripts/readme.txt for the list of variables
|
||||
OPT_OS = raw32
|
||||
OPT_THUMB = yes
|
||||
OPT_LINK_OPTIMIZE = no
|
||||
OPT_CPU = stm32m7
|
||||
|
||||
# uGFX settings
|
||||
# See $(GFXLIB)/tools/gmake_scripts/library_ugfx.mk for the list of variables
|
||||
GFXLIB = ../ugfx
|
||||
GFXBOARD = STM32F746-Discovery
|
||||
GFXDEMO = modules/gdisp/basics
|
||||
#GFXDRIVERS =
|
||||
|
||||
# ChibiOS settings
|
||||
# Note: not supported by ChibiOS yet!
|
||||
ifeq ($(OPT_OS),chibios)
|
||||
# See $(GFXLIB)/tools/gmake_scripts/os_chibios.mk for the list of variables
|
||||
CHIBIOS = ../ChibiOS
|
||||
CHIBIOS_BOARD = ST_STM32F746_DISCOVERY
|
||||
CHIBIOS_PLATFORM = STM32F7xx
|
||||
CHIBIOS_PORT = GCC/ARMCMx/STM32F7xx
|
||||
CHIBIOS_LDSCRIPT = STM32F746.ld
|
||||
|
||||
#CHIBIOS = ../ChibiOS3
|
||||
#CHIBIOS_VERSION = 3
|
||||
#CHIBIOS_BOARD = ST_STM32F746_DISCOVERY
|
||||
#CHIBIOS_CPUCLASS = ARMCMx
|
||||
#CHIBIOS_PLATFORM = STM32/STM32F7xx
|
||||
#CHIBIOS_PORT = stm32f7xx
|
||||
#CHIBIOS_LDSCRIPT = STM32F746.ld
|
||||
endif
|
||||
|
||||
# Raw32 settings
|
||||
CMSIS = ../STM32/CMSIS
|
||||
HAL = ../STM32/STM32F7xx_HAL_Driver
|
||||
|
||||
##############################################################################################
|
||||
# Set these for your project
|
||||
#
|
||||
|
||||
ARCH = arm-none-eabi-
|
||||
SRCFLAGS = -ggdb -O0
|
||||
CFLAGS =
|
||||
CXXFLAGS = -fno-rtti
|
||||
ASFLAGS =
|
||||
LDFLAGS =
|
||||
|
||||
SRC =
|
||||
|
||||
OBJS =
|
||||
DEFS = GOS_RAW_HEAP_SIZE=40960
|
||||
LIBS =
|
||||
INCPATH =
|
||||
|
||||
LIBPATH =
|
||||
LDSCRIPT =
|
||||
|
||||
##############################################################################################
|
||||
# These should be at the end
|
||||
#
|
||||
|
||||
include $(GFXLIB)/tools/gmake_scripts/library_ugfx.mk
|
||||
include $(GFXLIB)/tools/gmake_scripts/os_$(OPT_OS).mk
|
||||
include $(GFXLIB)/tools/gmake_scripts/compiler_gcc.mk
|
||||
# *** EOF ***
|
94
boards/base/STM32F746-Discovery/example_raw32/openocd.cfg
Normal file
94
boards/base/STM32F746-Discovery/example_raw32/openocd.cfg
Normal file
@ -0,0 +1,94 @@
|
||||
# This is a script file for OpenOCD ?.?.?
|
||||
#
|
||||
# It is set up for the STM32F749-Discovery board using the ST-Link JTAG adaptor.
|
||||
#
|
||||
# Assuming the current directory is your project directory containing this openocd.cfg file...
|
||||
#
|
||||
# To program your device:
|
||||
#
|
||||
# openocd -f openocd.cfg -c "Burn yourfile.bin" -c shutdown
|
||||
#
|
||||
# To debug your device:
|
||||
#
|
||||
# openocd
|
||||
# (This will run openocd in gdb server debug mode. Leave it running in the background)
|
||||
#
|
||||
# gdb yourfile.elf
|
||||
# (To start gdb. Then run the following commands in gdb...)
|
||||
#
|
||||
# target remote 127.0.0.1:3333
|
||||
# monitor Debug
|
||||
# stepi
|
||||
# (This last stepi resynchronizes gdb).
|
||||
#
|
||||
# If you want to reprogram from within gdb:
|
||||
#
|
||||
# monitor Burn yourfile.bin
|
||||
#
|
||||
|
||||
echo ""
|
||||
echo "##### Loading debugger..."
|
||||
source [find interface/stlink-v2-1.cfg]
|
||||
|
||||
echo ""
|
||||
echo "##### Loading CPU..."
|
||||
source [find target/stm32f7x.cfg]
|
||||
|
||||
echo ""
|
||||
echo "##### Configuring..."
|
||||
#reset_config srst_only srst_nogate
|
||||
#cortex_m maskisr (auto|on|off)
|
||||
#cortex_m vector_catch [all|none|list]
|
||||
#cortex_m reset_config (srst|sysresetreq|vectreset)
|
||||
#gdb_breakpoint_override hard
|
||||
|
||||
proc Debug { } {
|
||||
echo ""
|
||||
echo "##### Debug Session Connected..."
|
||||
reset init
|
||||
echo "Ready..."
|
||||
}
|
||||
|
||||
proc Burn {file} {
|
||||
echo ""
|
||||
echo "##### Burning $file to device..."
|
||||
halt
|
||||
# Due to an issue with the combination of the ST-Link adapters and OpenOCD
|
||||
# applying the stm32f2x unlock 0 command actaully applies read protection - VERY BAD!
|
||||
# If this happens to you - use the ST-Link utility to set the option byte back to normal.
|
||||
# If you are using a different debugger eg a FT2232 based adapter you can uncomment the line below.
|
||||
#stm32f2x unlock 0
|
||||
#flash protect 0 0 last off
|
||||
reset halt
|
||||
flash write_image erase $file 0 elf
|
||||
verify_image $file 0x0 elf
|
||||
#flash protect 0 0 last on
|
||||
reset
|
||||
echo "Burning Complete!"
|
||||
}
|
||||
|
||||
echo ""
|
||||
echo "##### Leaving Configuration Mode..."
|
||||
init
|
||||
reset init
|
||||
flash probe 0
|
||||
flash banks
|
||||
#flash info 0
|
||||
|
||||
echo ""
|
||||
echo "##### Waiting for debug connections..."
|
||||
|
||||
##### OLD ######
|
||||
#source [find interface/stlink-v2-1.cfg]
|
||||
#source [find target/stm32f7x.cfg]
|
||||
#
|
||||
#proc flash_chip {} {
|
||||
# halt
|
||||
# reset halt
|
||||
# flash write_image erase main.elf 0 elf
|
||||
# verify_image main.elf 0 elf
|
||||
# reset
|
||||
# shutdown
|
||||
#}
|
||||
#
|
||||
#init
|
@ -0,0 +1,418 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_conf.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 25-June-2015
|
||||
* @brief HAL configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_CONF_H
|
||||
#define __STM32F7xx_HAL_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* ########################## Module Selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
#define HAL_MODULE_ENABLED
|
||||
/* #define HAL_ADC_MODULE_ENABLED */
|
||||
/* #define HAL_CAN_MODULE_ENABLED */
|
||||
/* #define HAL_CEC_MODULE_ENABLED */
|
||||
/* #define HAL_CRC_MODULE_ENABLED */
|
||||
/* #define HAL_CRYP_MODULE_ENABLED */
|
||||
/* #define HAL_DAC_MODULE_ENABLED */
|
||||
/* #define HAL_DCMI_MODULE_ENABLED */
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
/* #define HAL_DMA2D_MODULE_ENABLED */
|
||||
/* #define HAL_ETH_MODULE_ENABLED */
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
/* #define HAL_NAND_MODULE_ENABLED */
|
||||
/* #define HAL_NOR_MODULE_ENABLED */
|
||||
/* #define HAL_SRAM_MODULE_ENABLED */
|
||||
#define HAL_SDRAM_MODULE_ENABLED
|
||||
/* #define HAL_HASH_MODULE_ENABLED */
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
/* #define HAL_I2C_MODULE_ENABLED */
|
||||
/* #define HAL_I2S_MODULE_ENABLED */
|
||||
/* #define HAL_IWDG_MODULE_ENABLED */
|
||||
/* #define HAL_LPTIM_MODULE_ENABLED */
|
||||
/* #define HAL_LTDC_MODULE_ENABLED */
|
||||
#define HAL_PWR_MODULE_ENABLED
|
||||
/* #define HAL_QSPI_MODULE_ENABLED */
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
/* #define HAL_RNG_MODULE_ENABLED */
|
||||
/* #define HAL_RTC_MODULE_ENABLED */
|
||||
/* #define HAL_SAI_MODULE_ENABLED */
|
||||
/* #define HAL_SD_MODULE_ENABLED */
|
||||
/* #define HAL_SPDIFRX_MODULE_ENABLED */
|
||||
/* #define HAL_SPI_MODULE_ENABLED */
|
||||
/* #define HAL_TIM_MODULE_ENABLED */
|
||||
/* #define HAL_UART_MODULE_ENABLED */
|
||||
/* #define HAL_USART_MODULE_ENABLED */
|
||||
/* #define HAL_IRDA_MODULE_ENABLED */
|
||||
/* #define HAL_SMARTCARD_MODULE_ENABLED */
|
||||
/* #define HAL_WWDG_MODULE_ENABLED */
|
||||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
/* #define HAL_PCD_MODULE_ENABLED */
|
||||
/* #define HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
|
||||
/* ########################## HSE/HSI Values adaptation ##################### */
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI) value.
|
||||
*/
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE ((uint32_t)40000)
|
||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature. */
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
/**
|
||||
* @brief External clock source for I2S peripheral
|
||||
* This value is used by the I2S HAL module to compute the I2S clock source
|
||||
* frequency, this source is inserted directly through I2S_CKIN pad.
|
||||
*/
|
||||
#if !defined (EXTERNAL_CLOCK_VALUE)
|
||||
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* EXTERNAL_CLOCK_VALUE */
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
|
||||
/* ########################### System Configuration ######################### */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
|
||||
#define USE_RTOS 0
|
||||
#define ART_ACCLERATOR_ENABLE 1 /* To enable instruction cache and prefetch */
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/* #define USE_FULL_ASSERT 1 */
|
||||
|
||||
/* ################## Ethernet peripheral configuration ##################### */
|
||||
|
||||
/* Section 1 : Ethernet peripheral configuration */
|
||||
|
||||
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
|
||||
#define MAC_ADDR0 2
|
||||
#define MAC_ADDR1 0
|
||||
#define MAC_ADDR2 0
|
||||
#define MAC_ADDR3 0
|
||||
#define MAC_ADDR4 0
|
||||
#define MAC_ADDR5 0
|
||||
|
||||
/* Definition of the Ethernet driver buffers size and count */
|
||||
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
|
||||
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
|
||||
#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
|
||||
#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
|
||||
|
||||
/* Section 2: PHY configuration section */
|
||||
|
||||
/* DP83848 PHY Address*/
|
||||
#define DP83848_PHY_ADDRESS 0x01
|
||||
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
|
||||
#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
|
||||
/* PHY Configuration delay */
|
||||
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
|
||||
|
||||
#define PHY_READ_TO ((uint32_t)0x0000FFFF)
|
||||
#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
|
||||
|
||||
/* Section 3: Common PHY Registers */
|
||||
|
||||
#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
|
||||
#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
|
||||
|
||||
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
|
||||
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
|
||||
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
|
||||
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
|
||||
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
|
||||
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
|
||||
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
|
||||
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
|
||||
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
|
||||
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
|
||||
|
||||
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
|
||||
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
|
||||
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
|
||||
|
||||
/* Section 4: Extended PHY Registers */
|
||||
|
||||
#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
|
||||
#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
|
||||
#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
|
||||
|
||||
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
|
||||
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
|
||||
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
|
||||
|
||||
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
|
||||
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
|
||||
|
||||
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
|
||||
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_rcc.h"
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_adc.h"
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CAN_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_can.h"
|
||||
#endif /* HAL_CAN_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CEC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_cec.h"
|
||||
#endif /* HAL_CEC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_crc.h"
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRYP_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_cryp.h"
|
||||
#endif /* HAL_CRYP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA2D_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_dma2d.h"
|
||||
#endif /* HAL_DMA2D_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_dac.h"
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DCMI_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_dcmi.h"
|
||||
#endif /* HAL_DCMI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ETH_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_eth.h"
|
||||
#endif /* HAL_ETH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_flash.h"
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_sram.h"
|
||||
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NOR_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_nor.h"
|
||||
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NAND_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_nand.h"
|
||||
#endif /* HAL_NAND_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SDRAM_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_sdram.h"
|
||||
#endif /* HAL_SDRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HASH_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_hash.h"
|
||||
#endif /* HAL_HASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_i2s.h"
|
||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LPTIM_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_lptim.h"
|
||||
#endif /* HAL_LPTIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LTDC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_ltdc.h"
|
||||
#endif /* HAL_LTDC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_QSPI_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_qspi.h"
|
||||
#endif /* HAL_QSPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RNG_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_rng.h"
|
||||
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SAI_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_sai.h"
|
||||
#endif /* HAL_SAI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SD_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_sd.h"
|
||||
#endif /* HAL_SD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPDIFRX_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_spdifrx.h"
|
||||
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HCD_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_hcd.h"
|
||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_CONF_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
502
boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c
Normal file
502
boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c
Normal file
@ -0,0 +1,502 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32746g_discovery_sdram.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 25-June-2015
|
||||
* @brief This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory
|
||||
* device mounted on STM32746G-Discovery board.
|
||||
@verbatim
|
||||
1. How To use this driver:
|
||||
--------------------------
|
||||
- This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted
|
||||
on STM32746G-Discovery board.
|
||||
- This driver does not need a specific component driver for the SDRAM device
|
||||
to be included with.
|
||||
|
||||
2. Driver description:
|
||||
---------------------
|
||||
+ Initialization steps:
|
||||
o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This
|
||||
function includes the MSP layer hardware resources initialization and the
|
||||
FMC controller configuration to interface with the external SDRAM memory.
|
||||
o It contains the SDRAM initialization sequence to program the SDRAM external
|
||||
device using the function BSP_SDRAM_Initialization_sequence(). Note that this
|
||||
sequence is standard for all SDRAM devices, but can include some differences
|
||||
from a device to another. If it is the case, the right sequence should be
|
||||
implemented separately.
|
||||
|
||||
+ SDRAM read/write operations
|
||||
o SDRAM external memory can be accessed with read/write operations once it is
|
||||
initialized.
|
||||
Read/write operation can be performed with AHB access using the functions
|
||||
BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions
|
||||
BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA().
|
||||
o The AHB access is performed with 32-bit width transaction, the DMA transfer
|
||||
configuration is fixed at single (no burst) word transfer (see the
|
||||
SDRAM_MspInit() static function).
|
||||
o User can implement his own functions for read/write access with his desired
|
||||
configurations.
|
||||
o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler()
|
||||
is called in IRQ handler file, to serve the generated interrupt once the DMA
|
||||
transfer is complete.
|
||||
o You can send a command to the SDRAM device in runtime using the function
|
||||
BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between
|
||||
the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "gfx.h"
|
||||
#include "stm32f746g_discovery_sdram.h"
|
||||
#include "stm32f7xx_hal_rcc.h"
|
||||
#include "stm32f7xx_hal_rcc_ex.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32746G_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32746G_DISCOVERY_SDRAM STM32746G_DISCOVERY_SDRAM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Types_Definitions STM32746G_DISCOVERY_SDRAM Private Types Definitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Defines STM32746G_DISCOVERY_SDRAM Private Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Macros STM32746G_DISCOVERY_SDRAM Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Variables STM32746G_DISCOVERY_SDRAM Private Variables
|
||||
* @{
|
||||
*/
|
||||
static SDRAM_HandleTypeDef sdramHandle;
|
||||
static FMC_SDRAM_TimingTypeDef Timing;
|
||||
static FMC_SDRAM_CommandTypeDef Command;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Function_Prototypes STM32746G_DISCOVERY_SDRAM Private Function Prototypes
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Functions STM32746G_DISCOVERY_SDRAM Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the SDRAM device.
|
||||
* @retval SDRAM status
|
||||
*/
|
||||
uint8_t BSP_SDRAM_Init(void)
|
||||
{
|
||||
static uint8_t sdramstatus = SDRAM_ERROR;
|
||||
/* SDRAM device configuration */
|
||||
sdramHandle.Instance = FMC_SDRAM_DEVICE;
|
||||
|
||||
/* Timing configuration for 100Mhz as SD clock frequency (System clock is up to 200Mhz) */
|
||||
Timing.LoadToActiveDelay = 2;
|
||||
Timing.ExitSelfRefreshDelay = 7;
|
||||
Timing.SelfRefreshTime = 4;
|
||||
Timing.RowCycleDelay = 7;
|
||||
Timing.WriteRecoveryTime = 2;
|
||||
Timing.RPDelay = 2;
|
||||
Timing.RCDDelay = 2;
|
||||
|
||||
sdramHandle.Init.SDBank = FMC_SDRAM_BANK1;
|
||||
sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
|
||||
sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
|
||||
sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
|
||||
sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
|
||||
sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
|
||||
sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
|
||||
sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD;
|
||||
sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
|
||||
sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
|
||||
|
||||
/* SDRAM controller initialization */
|
||||
|
||||
BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */
|
||||
|
||||
if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)
|
||||
{
|
||||
sdramstatus = SDRAM_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
sdramstatus = SDRAM_OK;
|
||||
}
|
||||
|
||||
/* SDRAM initialization sequence */
|
||||
BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
|
||||
|
||||
return sdramstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the SDRAM device.
|
||||
* @retval SDRAM status
|
||||
*/
|
||||
uint8_t BSP_SDRAM_DeInit(void)
|
||||
{
|
||||
static uint8_t sdramstatus = SDRAM_ERROR;
|
||||
/* SDRAM device de-initialization */
|
||||
sdramHandle.Instance = FMC_SDRAM_DEVICE;
|
||||
|
||||
if(HAL_SDRAM_DeInit(&sdramHandle) != HAL_OK)
|
||||
{
|
||||
sdramstatus = SDRAM_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
sdramstatus = SDRAM_OK;
|
||||
}
|
||||
|
||||
/* SDRAM controller de-initialization */
|
||||
BSP_SDRAM_MspDeInit(&sdramHandle, NULL);
|
||||
|
||||
return sdramstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Programs the SDRAM device.
|
||||
* @param RefreshCount: SDRAM refresh counter value
|
||||
* @retval None
|
||||
*/
|
||||
void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
|
||||
{
|
||||
__IO uint32_t tmpmrd = 0;
|
||||
|
||||
/* Step 1: Configure a clock configuration enable command */
|
||||
Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
|
||||
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
|
||||
Command.AutoRefreshNumber = 1;
|
||||
Command.ModeRegisterDefinition = 0;
|
||||
|
||||
/* Send the command */
|
||||
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
|
||||
|
||||
/* Step 2: Insert 100 us minimum delay */
|
||||
/* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
|
||||
HAL_Delay(1);
|
||||
|
||||
/* Step 3: Configure a PALL (precharge all) command */
|
||||
Command.CommandMode = FMC_SDRAM_CMD_PALL;
|
||||
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
|
||||
Command.AutoRefreshNumber = 1;
|
||||
Command.ModeRegisterDefinition = 0;
|
||||
|
||||
/* Send the command */
|
||||
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
|
||||
|
||||
/* Step 4: Configure an Auto Refresh command */
|
||||
Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
|
||||
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
|
||||
Command.AutoRefreshNumber = 8;
|
||||
Command.ModeRegisterDefinition = 0;
|
||||
|
||||
/* Send the command */
|
||||
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
|
||||
|
||||
/* Step 5: Program the external memory mode register */
|
||||
tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\
|
||||
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
|
||||
SDRAM_MODEREG_CAS_LATENCY_2 |\
|
||||
SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
|
||||
SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
|
||||
|
||||
Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
|
||||
Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
|
||||
Command.AutoRefreshNumber = 1;
|
||||
Command.ModeRegisterDefinition = tmpmrd;
|
||||
|
||||
/* Send the command */
|
||||
HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
|
||||
|
||||
/* Step 6: Set the refresh rate counter */
|
||||
/* Set the device refresh rate */
|
||||
HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads an amount of data from the SDRAM memory in polling mode.
|
||||
* @param uwStartAddress: Read start address
|
||||
* @param pData: Pointer to data to be read
|
||||
* @param uwDataSize: Size of read data from the memory
|
||||
* @retval SDRAM status
|
||||
*/
|
||||
uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
|
||||
{
|
||||
if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
|
||||
{
|
||||
return SDRAM_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
return SDRAM_OK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads an amount of data from the SDRAM memory in DMA mode.
|
||||
* @param uwStartAddress: Read start address
|
||||
* @param pData: Pointer to data to be read
|
||||
* @param uwDataSize: Size of read data from the memory
|
||||
* @retval SDRAM status
|
||||
*/
|
||||
uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
|
||||
{
|
||||
if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
|
||||
{
|
||||
return SDRAM_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
return SDRAM_OK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes an amount of data to the SDRAM memory in polling mode.
|
||||
* @param uwStartAddress: Write start address
|
||||
* @param pData: Pointer to data to be written
|
||||
* @param uwDataSize: Size of written data from the memory
|
||||
* @retval SDRAM status
|
||||
*/
|
||||
uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
|
||||
{
|
||||
if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
|
||||
{
|
||||
return SDRAM_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
return SDRAM_OK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes an amount of data to the SDRAM memory in DMA mode.
|
||||
* @param uwStartAddress: Write start address
|
||||
* @param pData: Pointer to data to be written
|
||||
* @param uwDataSize: Size of written data from the memory
|
||||
* @retval SDRAM status
|
||||
*/
|
||||
uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
|
||||
{
|
||||
if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
|
||||
{
|
||||
return SDRAM_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
return SDRAM_OK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sends command to the SDRAM bank.
|
||||
* @param SdramCmd: Pointer to SDRAM command structure
|
||||
* @retval SDRAM status
|
||||
*/
|
||||
uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
|
||||
{
|
||||
if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK)
|
||||
{
|
||||
return SDRAM_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
return SDRAM_OK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handles SDRAM DMA transfer interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void BSP_SDRAM_DMA_IRQHandler(void)
|
||||
{
|
||||
HAL_DMA_IRQHandler(sdramHandle.hdma);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes SDRAM MSP.
|
||||
* @param hsdram: SDRAM handle
|
||||
* @param Params
|
||||
* @retval None
|
||||
*/
|
||||
__weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params)
|
||||
{
|
||||
static DMA_HandleTypeDef dma_handle;
|
||||
GPIO_InitTypeDef gpio_init_structure;
|
||||
|
||||
/* Enable FMC clock */
|
||||
__HAL_RCC_FMC_CLK_ENABLE();
|
||||
|
||||
/* Enable chosen DMAx clock */
|
||||
__DMAx_CLK_ENABLE();
|
||||
|
||||
/* Enable GPIOs clock */
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOD_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOE_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOF_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOG_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOH_CLK_ENABLE();
|
||||
|
||||
/* Common GPIO configuration */
|
||||
gpio_init_structure.Mode = GPIO_MODE_AF_PP;
|
||||
gpio_init_structure.Pull = GPIO_PULLUP;
|
||||
gpio_init_structure.Speed = GPIO_SPEED_FAST;
|
||||
gpio_init_structure.Alternate = GPIO_AF12_FMC;
|
||||
|
||||
/* GPIOC configuration */
|
||||
gpio_init_structure.Pin = GPIO_PIN_3;
|
||||
HAL_GPIO_Init(GPIOC, &gpio_init_structure);
|
||||
|
||||
/* GPIOD configuration */
|
||||
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_8 | GPIO_PIN_9 |
|
||||
GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15;
|
||||
HAL_GPIO_Init(GPIOD, &gpio_init_structure);
|
||||
|
||||
/* GPIOE configuration */
|
||||
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
|
||||
GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
|
||||
GPIO_PIN_15;
|
||||
HAL_GPIO_Init(GPIOE, &gpio_init_structure);
|
||||
|
||||
/* GPIOF configuration */
|
||||
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
|
||||
GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
|
||||
GPIO_PIN_15;
|
||||
HAL_GPIO_Init(GPIOF, &gpio_init_structure);
|
||||
|
||||
/* GPIOG configuration */
|
||||
gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\
|
||||
GPIO_PIN_15;
|
||||
HAL_GPIO_Init(GPIOG, &gpio_init_structure);
|
||||
|
||||
/* GPIOH configuration */
|
||||
gpio_init_structure.Pin = GPIO_PIN_3 | GPIO_PIN_5;
|
||||
HAL_GPIO_Init(GPIOH, &gpio_init_structure);
|
||||
|
||||
/* Configure common DMA parameters */
|
||||
dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL;
|
||||
dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY;
|
||||
dma_handle.Init.PeriphInc = DMA_PINC_ENABLE;
|
||||
dma_handle.Init.MemInc = DMA_MINC_ENABLE;
|
||||
dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
|
||||
dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
|
||||
dma_handle.Init.Mode = DMA_NORMAL;
|
||||
dma_handle.Init.Priority = DMA_PRIORITY_HIGH;
|
||||
dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
||||
dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
|
||||
dma_handle.Init.MemBurst = DMA_MBURST_SINGLE;
|
||||
dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE;
|
||||
|
||||
dma_handle.Instance = SDRAM_DMAx_STREAM;
|
||||
|
||||
/* Associate the DMA handle */
|
||||
__HAL_LINKDMA(hsdram, hdma, dma_handle);
|
||||
|
||||
/* Deinitialize the stream for new transfer */
|
||||
HAL_DMA_DeInit(&dma_handle);
|
||||
|
||||
/* Configure the DMA stream */
|
||||
HAL_DMA_Init(&dma_handle);
|
||||
|
||||
/* NVIC configuration for DMA transfer complete interrupt */
|
||||
HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0);
|
||||
HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes SDRAM MSP.
|
||||
* @param hsdram: SDRAM handle
|
||||
* @param Params
|
||||
* @retval None
|
||||
*/
|
||||
__weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params)
|
||||
{
|
||||
static DMA_HandleTypeDef dma_handle;
|
||||
|
||||
/* Disable NVIC configuration for DMA interrupt */
|
||||
HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn);
|
||||
|
||||
/* Deinitialize the stream for new transfer */
|
||||
dma_handle.Instance = SDRAM_DMAx_STREAM;
|
||||
HAL_DMA_DeInit(&dma_handle);
|
||||
|
||||
/* GPIO pins clock, FMC clock and DMA clock can be shut down in the applications
|
||||
by surcharging this __weak function */
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
170
boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h
Normal file
170
boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h
Normal file
@ -0,0 +1,170 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32746g_discovery_sdram.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 25-June-2015
|
||||
* @brief This file contains the common defines and functions prototypes for
|
||||
* the stm32746g_discovery_sdram.c driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F746G_DISCOVERY_SDRAM_H
|
||||
#define __STM32F746G_DISCOVERY_SDRAM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_rcc.h"
|
||||
#include "stm32f7xx_hal_rcc_ex.h"
|
||||
#include "stm32f7xx_hal_dma.h"
|
||||
#include "stm32f7xx_hal_gpio.h"
|
||||
#include "stm32f7xx_hal_sdram.h"
|
||||
#include "stm32f7xx_ll_fmc.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32746G_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32746G_DISCOVERY_SDRAM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Types STM32746G_DISCOVERY_SDRAM Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SDRAM status structure definition
|
||||
*/
|
||||
#define SDRAM_OK ((uint8_t)0x00)
|
||||
#define SDRAM_ERROR ((uint8_t)0x01)
|
||||
|
||||
/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Constants STM32746G_DISCOVERY_SDRAM Exported Constants
|
||||
* @{
|
||||
*/
|
||||
#define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000)
|
||||
#define SDRAM_DEVICE_SIZE ((uint32_t)0x800000) /* SDRAM device size in MBytes */
|
||||
|
||||
/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */
|
||||
#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16
|
||||
|
||||
#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2
|
||||
/* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */
|
||||
|
||||
#define REFRESH_COUNT ((uint32_t)0x0603) /* SDRAM refresh counter (100Mhz SD clock) */
|
||||
|
||||
#define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
|
||||
|
||||
/* DMA definitions for SDRAM DMA transfer */
|
||||
#define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
|
||||
#define __DMAx_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
|
||||
#define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0
|
||||
#define SDRAM_DMAx_STREAM DMA2_Stream0
|
||||
#define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn
|
||||
#define SDRAM_DMAx_IRQHandler DMA2_Stream0_IRQHandler
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FMC SDRAM Mode definition register defines
|
||||
*/
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
|
||||
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
|
||||
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
|
||||
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
|
||||
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Macro STM32746G_DISCOVERY_SDRAM Exported Macro
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32746G_DISCOVERY_SDRAM_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
uint8_t BSP_SDRAM_Init(void);
|
||||
uint8_t BSP_SDRAM_DeInit(void);
|
||||
void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount);
|
||||
uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
|
||||
uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
|
||||
uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
|
||||
uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize);
|
||||
uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
|
||||
void BSP_SDRAM_DMA_IRQHandler(void);
|
||||
|
||||
/* These functions can be modified in case the current settings (e.g. DMA stream)
|
||||
need to be changed for specific application needs */
|
||||
void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params);
|
||||
void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32746G_DISCOVERY_SDRAM_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
185
boards/base/STM32F746-Discovery/stm32f746g_raw32_interrupts.c
Normal file
185
boards/base/STM32F746-Discovery/stm32f746g_raw32_interrupts.c
Normal file
@ -0,0 +1,185 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file LTDC/LTDC_Display_1Layer/Src/stm32f7xx_it.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 25-June-2015
|
||||
* @brief Main Interrupt Service Routines.
|
||||
* This file provides template for all exceptions handler and
|
||||
* peripherals interrupt service routine.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Examples
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup LTDC_Display_1Layer
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/******************************************************************************/
|
||||
/* Cortex-M4 Processor Exceptions Handlers */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief This function handles NMI exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||