62 changed files with 11890 additions and 11890 deletions
@ -1,3 +1,3 @@ |
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BOARDINC = $(GFXLIB)/boards/base/FireBull-STM32F103-FB/chibios_board |
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BOARDSRC = $(BOARDINC)/board.c \
|
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|
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BOARDINC = $(GFXLIB)/boards/base/FireBull-STM32F103-FB/chibios_board |
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BOARDSRC = $(BOARDINC)/board.c \
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|
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@ -1,88 +1,88 @@ |
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/*
|
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, |
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2011,2012,2013 Giovanni Di Sirio. |
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|
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This file is part of ChibiOS/RT. |
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|
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ChibiOS/RT is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 3 of the License, or |
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(at your option) any later version. |
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|
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ChibiOS/RT is distributed in the hope that it will be useful, |
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but WITHOUT ANY WARRANTY; without even the implied warranty of |
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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GNU General Public License for more details. |
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|
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You should have received a copy of the GNU General Public License |
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along with this program. If not, see <http://www.gnu.org/licenses/>.
|
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*/ |
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|
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#include "ch.h" |
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#include "hal.h" |
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|
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#if HAL_USE_PAL || defined(__DOXYGEN__) |
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/**
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* @brief PAL setup. |
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* @details Digital I/O ports static configuration as defined in @p board.h. |
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* This variable is used by the HAL when initializing the PAL driver. |
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*/ |
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const PALConfig pal_default_config = |
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{ |
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{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, |
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VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, |
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{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, |
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VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, |
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{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, |
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VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, |
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{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, |
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VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, |
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{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, |
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VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, |
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{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, |
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VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, |
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{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, |
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VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, |
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{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, |
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VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, |
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{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, |
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VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} |
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}; |
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#endif |
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|
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/**
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* @brief Early initialization code. |
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* @details This initialization must be performed just after stack setup |
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* and before any other initialization. |
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*/ |
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void __early_init(void) { |
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|
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stm32_clock_init(); |
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} |
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|
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#if HAL_USE_SDC |
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/*
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* Card detection through the card internal pull-up on D3. |
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*/ |
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bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { |
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|
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(void)sdcp; |
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return (bool_t)!palReadPad(GPIOD, GPIOD_SDIO_CD_N); |
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} |
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|
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/*
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* Card write protection detection is not possible, the card is always |
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* reported as not protected. |
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*/ |
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bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { |
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|
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(void)sdcp; |
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return 0; |
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} |
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#endif /* HAL_USE_SDC */ |
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|
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/**
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* @brief Board-specific initialization code. |
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*/ |
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void boardInit(void) { |
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} |
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/*
|
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, |
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2011,2012,2013 Giovanni Di Sirio. |
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|
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This file is part of ChibiOS/RT. |
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|
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ChibiOS/RT is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 3 of the License, or |
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(at your option) any later version. |
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|
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ChibiOS/RT is distributed in the hope that it will be useful, |
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but WITHOUT ANY WARRANTY; without even the implied warranty of |
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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GNU General Public License for more details. |
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|
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You should have received a copy of the GNU General Public License |
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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|
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#include "ch.h" |
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#include "hal.h" |
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#if HAL_USE_PAL || defined(__DOXYGEN__) |
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/**
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* @brief PAL setup. |
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* @details Digital I/O ports static configuration as defined in @p board.h. |
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* This variable is used by the HAL when initializing the PAL driver. |
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*/ |
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const PALConfig pal_default_config = |
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{ |
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{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, |
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VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, |
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{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, |
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VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, |
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{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, |
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VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, |
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{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, |
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VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, |
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{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, |
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VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, |
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{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, |
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VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, |
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{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, |
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VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, |
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{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, |
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VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, |
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{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, |
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VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} |
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}; |
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#endif |
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|
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/**
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* @brief Early initialization code. |
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* @details This initialization must be performed just after stack setup |
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* and before any other initialization. |
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*/ |
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void __early_init(void) { |
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stm32_clock_init(); |
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} |
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|
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#if HAL_USE_SDC |
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/*
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* Card detection through the card internal pull-up on D3. |
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*/ |
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bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { |
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(void)sdcp; |
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return (bool_t)!palReadPad(GPIOD, GPIOD_SDIO_CD_N); |
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} |
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|
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/*
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* Card write protection detection is not possible, the card is always |
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* reported as not protected. |
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*/ |
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bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { |
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|
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(void)sdcp; |
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return 0; |
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} |
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#endif /* HAL_USE_SDC */ |
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|
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/**
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* @brief Board-specific initialization code. |
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*/ |
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void boardInit(void) { |
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} |
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File diff suppressed because it is too large
@ -1,3 +1,3 @@ |
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BOARDINC = $(GFXLIB)/boards/base/Marlin/chibios_board |
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BOARDSRC = $(BOARDINC)/board.c \
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BOARDINC = $(GFXLIB)/boards/base/Marlin/chibios_board |
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BOARDSRC = $(BOARDINC)/board.c \
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@ -1,106 +1,106 @@ |
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio |
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|
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Licensed under the Apache License, Version 2.0 (the "License"); |
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you may not use this file except in compliance with the License. |
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You may obtain a copy of the License at |
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|
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http://www.apache.org/licenses/LICENSE-2.0
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|
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Unless required by applicable law or agreed to in writing, software |
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distributed under the License is distributed on an "AS IS" BASIS, |
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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See the License for the specific language governing permissions and |
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limitations under the License. |
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*/ |
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|
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#include "hal.h" |
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|
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#if HAL_USE_PAL || defined(__DOXYGEN__) |
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/**
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* @brief PAL setup. |
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* @details Digital I/O ports static configuration as defined in @p board.h. |
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* This variable is used by the HAL when initializing the PAL driver. |
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*/ |
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const PALConfig pal_default_config = |
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{ |
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{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, |
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VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, |
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{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, |
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VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, |
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{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, |
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VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, |
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{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, |
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VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, |
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{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, |
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VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, |
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{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, |
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VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, |
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{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, |
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VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, |
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{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, |
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VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, |
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{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, |
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VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} |
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}; |
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#endif |
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|
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/**
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* @brief Early initialization code. |
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* @details This initialization must be performed just after stack setup |
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* and before any other initialization. |
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*/ |
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void __early_init(void) { |
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|
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stm32_clock_init(); |
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} |
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|
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#if HAL_USE_SDC || defined(__DOXYGEN__) |
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/**
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* @brief SDC card detection. |
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*/ |
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bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { |
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(void)sdcp; |
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/* TODO: Fill the implementation.*/ |
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return TRUE; |
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} |
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|
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/**
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* @brief SDC card write protection detection. |
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*/ |
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bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { |
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(void)sdcp; |
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/* TODO: Fill the implementation.*/ |
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return FALSE; |
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} |
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#endif /* HAL_USE_SDC */ |
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|
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#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) |
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/**
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* @brief MMC_SPI card detection. |
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*/ |
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bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { |
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(void)mmcp; |
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return !palReadPad(GPIOD, GPIOD_SD_CD); |
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} |
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/**
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* @brief MMC_SPI card write protection detection. |
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*/ |
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bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { |
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(void)mmcp; |
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/* Board has no write protection detection */ |
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return FALSE; |
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} |
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#endif |
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/**
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* @brief Board-specific initialization code. |
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* @todo Add your board-specific code, if any. |
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*/ |
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void boardInit(void) { |
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} |
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio |
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|
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Licensed under the Apache License, Version 2.0 (the "License"); |
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you may not use this file except in compliance with the License. |
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You may obtain a copy of the License at |
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|
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http://www.apache.org/licenses/LICENSE-2.0
|
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|
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Unless required by applicable law or agreed to in writing, software |
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distributed under the License is distributed on an "AS IS" BASIS, |
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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See the License for the specific language governing permissions and |
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limitations under the License. |
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*/ |
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|
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#include "hal.h" |
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|
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#if HAL_USE_PAL || defined(__DOXYGEN__) |
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/**
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* @brief PAL setup. |
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* @details Digital I/O ports static configuration as defined in @p board.h. |
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* This variable is used by the HAL when initializing the PAL driver. |
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*/ |
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const PALConfig pal_default_config = |
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{ |
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{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, |
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VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, |
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{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, |
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VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, |
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{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, |
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VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, |
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{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, |
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VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, |
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{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, |
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VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, |
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{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, |
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VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, |
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{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, |
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VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, |
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{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, |
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VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, |
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{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, |
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VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} |
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}; |
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#endif |
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|
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/**
|
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* @brief Early initialization code. |
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* @details This initialization must be performed just after stack setup |
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* and before any other initialization. |
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*/ |
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void __early_init(void) { |
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|
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stm32_clock_init(); |
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} |
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|
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#if HAL_USE_SDC || defined(__DOXYGEN__) |
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/**
|
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* @brief SDC card detection. |
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*/ |
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bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { |
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|
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(void)sdcp; |
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/* TODO: Fill the implementation.*/ |
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return TRUE; |
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} |
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|
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/**
|
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* @brief SDC card write protection detection. |
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*/ |
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bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { |
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|
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(void)sdcp; |
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/* TODO: Fill the implementation.*/ |
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return FALSE; |
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} |
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#endif /* HAL_USE_SDC */ |
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|
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#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) |
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/**
|
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* @brief MMC_SPI card detection. |
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*/ |
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bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { |
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|
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(void)mmcp; |
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return !palReadPad(GPIOD, GPIOD_SD_CD); |
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} |
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|
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/**
|
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* @brief MMC_SPI card write protection detection. |
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*/ |
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bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { |
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|
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(void)mmcp; |
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/* Board has no write protection detection */ |
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return FALSE; |
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} |
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#endif |
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|
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/**
|
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* @brief Board-specific initialization code. |
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* @todo Add your board-specific code, if any. |
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*/ |
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void boardInit(void) { |
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} |
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|
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File diff suppressed because it is too large
@ -1,6 +1,6 @@ |
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# Required include directories
|
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BOARDINC = $(GFXLIB)/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board |
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|
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# List of all the board related files.
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BOARDSRC = $(BOARDINC)/board.c \
|
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# Required include directories
|
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BOARDINC = $(GFXLIB)/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board |
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|
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# List of all the board related files.
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BOARDSRC = $(BOARDINC)/board.c \
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$(BOARDINC)/flash_memory.c |
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@ -1,88 +1,88 @@ |
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/*
|
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio |
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|
|||
Licensed under the Apache License, Version 2.0 (the "License"); |
|||
you may not use this file except in compliance with the License. |
|||
You may obtain a copy of the License at |
|||
|
|||
http://www.apache.org/licenses/LICENSE-2.0
|
|||
|
|||
Unless required by applicable law or agreed to in writing, software |
|||
distributed under the License is distributed on an "AS IS" BASIS, |
|||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
|||
See the License for the specific language governing permissions and |
|||
limitations under the License. |
|||
*/ |
|||
|
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#include "ch.h" |
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#include "hal.h" |
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|
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/**
|
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* @brief PAL setup. |
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* @details Digital I/O ports static configuration as defined in @p board.h. |
|||
* This variable is used by the HAL when initializing the PAL driver. |
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*/ |
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#if HAL_USE_PAL || defined(__DOXYGEN__) |
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const PALConfig pal_default_config = |
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{ |
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{VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, |
|||
{VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, |
|||
{VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, |
|||
{VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, |
|||
{VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, |
|||
{VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH}, |
|||
{VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH}, |
|||
}; |
|||
#endif |
|||
|
|||
/*
|
|||
* Early initialization code. |
|||
* This initialization must be performed just after stack setup and before |
|||
* any other initialization. |
|||
*/ |
|||
void __early_init(void) { |
|||
stm32_clock_init(); |
|||
} |
|||
|
|||
#if HAL_USE_SDC || defined(__DOXYGEN__) |
|||
/**
|
|||
* @brief SDC card detection. |
|||
*/ |
|||
bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { |
|||
(void)sdcp; |
|||
|
|||
return TRUE; |
|||
} |
|||
|
|||
/**
|
|||
* @brief SDC card write protection detection. |
|||
*/ |
|||
bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { |
|||
(void)sdcp; |
|||
|
|||
return FALSE; |
|||
} |
|||
#endif /* HAL_USE_SDC */ |
|||
|
|||
#if HAL_USE_MMC_SPI |
|||
/* Board-related functions related to the MMC_SPI driver.*/ |
|||
bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { |
|||
(void)mmcp; |
|||
|
|||
return TRUE; |
|||
} |
|||
|
|||
bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { |
|||
(void)mmcp; |
|||
|
|||
return FALSE; |
|||
} |
|||
#endif |
|||
|
|||
/*
|
|||
* Board-specific initialization code. |
|||
*/ |
|||
void boardInit(void) { |
|||
|
|||
} |
|||
|
|||
/*
|
|||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio |
|||
|
|||
Licensed under the Apache License, Version 2.0 (the "License"); |
|||
you may not use this file except in compliance with the License. |
|||
You may obtain a copy of the License at |
|||
|
|||
http://www.apache.org/licenses/LICENSE-2.0
|
|||
|
|||
Unless required by applicable law or agreed to in writing, software |
|||
distributed under the License is distributed on an "AS IS" BASIS, |
|||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
|||
See the License for the specific language governing permissions and |
|||
limitations under the License. |
|||
*/ |
|||
|
|||
#include "ch.h" |
|||
#include "hal.h" |
|||
|
|||
/**
|
|||
* @brief PAL setup. |
|||
* @details Digital I/O ports static configuration as defined in @p board.h. |
|||
* This variable is used by the HAL when initializing the PAL driver. |
|||
*/ |
|||
#if HAL_USE_PAL || defined(__DOXYGEN__) |
|||
const PALConfig pal_default_config = |
|||
{ |
|||
{VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, |
|||
{VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, |
|||
{VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, |
|||
{VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, |
|||
{VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, |
|||
{VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH}, |
|||
{VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH}, |
|||
}; |
|||
#endif |
|||
|
|||
/*
|
|||
* Early initialization code. |
|||
* This initialization must be performed just after stack setup and before |
|||
* any other initialization. |
|||
*/ |
|||
void __early_init(void) { |
|||
stm32_clock_init(); |
|||
} |
|||
|
|||
#if HAL_USE_SDC || defined(__DOXYGEN__) |
|||
/**
|
|||
* @brief SDC card detection. |
|||
*/ |
|||
bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { |
|||
(void)sdcp; |
|||
|
|||
return TRUE; |
|||
} |
|||
|
|||
/**
|
|||
* @brief SDC card write protection detection. |
|||
*/ |
|||
bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { |
|||
(void)sdcp; |
|||
|
|||
return FALSE; |
|||
} |
|||
#endif /* HAL_USE_SDC */ |
|||
|
|||
#if HAL_USE_MMC_SPI |
|||
/* Board-related functions related to the MMC_SPI driver.*/ |
|||
bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { |
|||
(void)mmcp; |
|||
|
|||
return TRUE; |
|||
} |
|||
|
|||
bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { |
|||
(void)mmcp; |
|||
|
|||
return FALSE; |
|||
} |
|||
#endif |
|||
|
|||
/*
|
|||
* Board-specific initialization code. |
|||
*/ |
|||
void boardInit(void) { |
|||
|
|||
} |
|||
|
|||
|
|||
@ -1,196 +1,196 @@ |
|||
/*
|
|||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio |
|||
|
|||
Licensed under the Apache License, Version 2.0 (the "License"); |
|||
you may not use this file except in compliance with the License. |
|||
You may obtain a copy of the License at |
|||
|
|||
http://www.apache.org/licenses/LICENSE-2.0
|
|||
|
|||
Unless required by applicable law or agreed to in writing, software |
|||
distributed under the License is distributed on an "AS IS" BASIS, |
|||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
|||
See the License for the specific language governing permissions and |
|||
limitations under the License. |
|||
*/ |
|||
|
|||
#ifndef _BOARD_H_ |
|||
#define _BOARD_H_ |
|||
|
|||
/*
|
|||
* Setup for the Olimex STM32-LCD proto board. |
|||
*/ |
|||
|
|||
/*
|
|||
* Board identifier. |
|||
*/ |
|||
#define BOARD_OLIMEX_STM32_LCD |
|||
#define BOARD_NAME "Olimex STM32-LCD" |
|||
|
|||
/*
|
|||
* Board frequencies. |
|||
*/ |
|||
#define STM32_LSECLK 32768 |
|||
#define STM32_HSECLK 8000000 |
|||
|
|||
/*
|
|||
* MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. |
|||
*/ |
|||
#define STM32F10X_HD |
|||
|
|||
/*
|
|||
* IO pins assignments. |
|||
*/ |
|||
#define GPIOA_SPI1NSS 4 |
|||
|
|||
#define GPIOB_SPI2NSS 12 |
|||
|
|||
#define GPIOA_USB_P 0 |
|||
#define GPIOD_USB_DISC 2 |
|||
|
|||
#define GPIOE_TFT_RST 2 |
|||
#define GPIOD_TFT_LIGHT 13 |
|||
#define GPIOC_TFT_YD 0 |
|||
#define GPIOC_TFT_YU 1 |
|||
#define GPIOC_TFT_XL 2 |
|||
#define GPIOC_TFT_XR 3 |
|||
|
|||
/*
|
|||
* I/O ports initial setup, this configuration is established soon after reset |
|||
* in the initialization code. |
|||
* |
|||
* The digits have the following meaning: |
|||
* 0 - Analog input. |
|||
* 1 - Push Pull output 10MHz. |
|||
* 2 - Push Pull output 2MHz. |
|||
* 3 - Push Pull output 50MHz. |
|||
* 4 - Digital input. |
|||
* 5 - Open Drain output 10MHz. |
|||
* 6 - Open Drain output 2MHz. |
|||
* 7 - Open Drain output 50MHz. |
|||
* 8 - Digital input with PullUp or PullDown resistor depending on ODR. |
|||
* 9 - Alternate Push Pull output 10MHz. |
|||
* A - Alternate Push Pull output 2MHz. |
|||
* B - Alternate Push Pull output 50MHz. |
|||
* C - Reserved. |
|||
* D - Alternate Open Drain output 10MHz. |
|||
* E - Alternate Open Drain output 2MHz. |
|||
* F - Alternate Open Drain output 50MHz. |
|||
* Please refer to the STM32 Reference Manual for details. |
|||
*/ |
|||
|
|||
/*
|
|||
* Port A setup. |
|||
* Everything input with pull-up except: |
|||
* PA0 - Normal input (USB P). |
|||
* PA2 - Alternate output (USART2 TX). |
|||
* PA3 - Normal input (USART2 RX). |
|||
* PA11 - Normal input (USB DM). |
|||
* PA12 - Normal input (USB DP). |
|||
*/ |
|||
#define VAL_GPIOACRL 0x88884B84 /* PA7...PA0 */ |
|||
#define VAL_GPIOACRH 0x88844888 /* PA15...PA8 */ |
|||
#define VAL_GPIOAODR 0xFFFFFFFF |
|||
|
|||
/*
|
|||
* Port B setup. |
|||
* Everything input with pull-up except: |
|||
*/ |
|||
#define VAL_GPIOBCRL 0x88888888 /* PB7...PB0 */ |
|||
#define VAL_GPIOBCRH 0x88888888 /* PB15...PB8 */ |
|||
#define VAL_GPIOBODR 0xFFFFFFFF |
|||
|
|||
/*
|
|||
* Port C setup. |
|||
* Everything input with pull-up except: |
|||
* PC0 - Analog Input (TP_YD). |
|||
* PC1 - Analog Input (TP_YU). |
|||
* PC2 - Analog Input (TP_XL). |
|||
* PC3 - Analog Input (TP_XR). |
|||
* PC8 - Alternate PP 50M (SD_D0). |
|||
* PC9 - Alternate PP 50M (SD_D1). |
|||
* PC10 - Alternate PP 50M (SD_D2). |
|||
* PC11 - Alternate PP 50M (SD_D3). |
|||
* PC12 - Alternate PP 50M (SD_CLK). |
|||
* PC14 - Normal input (XTAL). |
|||
* PC15 - Normal input (XTAL). |
|||
*/ |
|||
#define VAL_GPIOCCRL 0x88880000 /* PC7...PC0 */ |
|||
#define VAL_GPIOCCRH 0x448BBBBB /* PC15...PC8 */ |
|||
#define VAL_GPIOCODR 0xFFFFFFFF |
|||
|
|||
/*
|
|||
* Port D setup. |
|||
* Everything input with pull-up except: |
|||
* PD2 - Alternate PP 50M (SD_CMD) |
|||
* PD0 - Alternate PP 50M (FSMC_D2) |
|||
* PD1 - Alternate PP 50M (FSMC_D3) |
|||
* PD4 - Alternate PP 50M (TFT_RD) |
|||
* PD5 - Alternate PP 50M (TFT_WR) |
|||
* PD7 - Alternate PP 50M (TFT_CS) |
|||
* PD8 - Alternate PP 50M (FSMC_D13) |
|||
* PD9 - Alternate PP 50M (FSMC_D14) |
|||
* PD10 - Alternate PP 50M (FSMC_D15) |
|||
* PD14 - Alternate PP 50M (FSMC_D0) |
|||
* PD15 - Alternate PP 50M (FSMC_D1) |
|||
*/ |
|||
#define VAL_GPIODCRL 0xBBBB8BBB /* PD7...PD0 */ |
|||
#define VAL_GPIODCRH 0xBB388BBB /* PD15...PD8 */ |
|||
#define VAL_GPIODODR 0xFFFFFFFF |
|||
|
|||
/*
|
|||
* Port E setup. |
|||
* Everything input with pull-up except: |
|||
* PE2 - Digital Output (TFT_RST) |
|||
* PE3 - Alternate PP 50M (TFT_RS) |
|||
* PE7 - Alternate PP 50M (FSMC_D4) |
|||
* PE8 - Alternate PP 50M (FSMC_D5) |
|||
* PE9 - Alternate PP 50M (FSMC_D6) |
|||
* PE10 - Alternate PP 50M (FSMC_D7) |
|||
* PE11 - Alternate PP 50M (FSMC_D8) |
|||
* PE12 - Alternate PP 50M (FSMC_D9) |
|||
* PE13 - Alternate PP 50M (FSMC_D10) |
|||
* PE14 - Alternate PP 50M (FSMC_D11) |
|||
* PE15 - Alternate PP 50M (FSMC_D12) |
|||
*/ |
|||
#define VAL_GPIOECRL 0xB888B388 /* PE7...PE0 */ |
|||
#define VAL_GPIOECRH 0xBBBBBBBB /* PE15...PE8 */ |
|||
#define VAL_GPIOEODR 0xFFFFFFFF |
|||
|
|||
/*
|
|||
* Port F setup. |
|||
* Everything input with pull-up expect: |
|||
*/ |
|||
#define VAL_GPIOFCRL 0x88888888 /* PF7...PF0 */ |
|||
#define VAL_GPIOFCRH 0x88888888 /* PF15...PF8 */ |
|||
#define VAL_GPIOFODR 0xFFFFFFFF |
|||
|
|||
/*
|
|||
* Port G setup. |
|||
* Everything input with pull-up expect: |
|||
*/ |
|||
#define VAL_GPIOGCRL 0x88888888 /* PG7...PG0 */ |
|||
#define VAL_GPIOGCRH 0x88888888 /* PG15...PG8 */ |
|||
#define VAL_GPIOGODR 0xFFFFFFFF |
|||
|
|||
/*
|
|||
* USB bus activation macro, required by the USB driver. |
|||
*/ |
|||
#define usb_lld_connect_bus(usbp) palClearPad(GPIOD, GPIOD_USB_DISC) |
|||
|
|||
/*
|
|||
* USB bus de-activation macro, required by the USB driver. |
|||
*/ |
|||
#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOD, GPIOD_USB_DISC) |
|||
|
|||
#if !defined(_FROM_ASM_) |
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
void boardInit(void); |
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
#endif /* _FROM_ASM_ */ |
|||
|
|||
#endif /* _BOARD_H_ */ |
|||
/*
|
|||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio |
|||
|
|||
Licensed under the Apache License, Version 2.0 (the "License"); |
|||
you may not use this file except in compliance with the License. |
|||
You may obtain a copy of the License at |
|||
|
|||
http://www.apache.org/licenses/LICENSE-2.0
|
|||
|
|||
Unless required by applicable law or agreed to in writing, software |
|||
distributed under the License is distributed on an "AS IS" BASIS, |
|||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
|||
See the License for the specific language governing permissions and |
|||
limitations under the License. |
|||
*/ |
|||
|
|||
#ifndef _BOARD_H_ |
|||
#define _BOARD_H_ |
|||
|
|||
/*
|
|||
* Setup for the Olimex STM32-LCD proto board. |
|||
*/ |
|||
|
|||
/*
|
|||
* Board identifier. |
|||
*/ |
|||
#define BOARD_OLIMEX_STM32_LCD |
|||
#define BOARD_NAME "Olimex STM32-LCD" |
|||
|
|||
/*
|
|||
* Board frequencies. |
|||
*/ |
|||
#define STM32_LSECLK 32768 |
|||
#define STM32_HSECLK 8000000 |
|||
|
|||
/*
|
|||
* MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. |
|||
*/ |
|||
#define STM32F10X_HD |
|||
|
|||
/*
|
|||
* IO pins assignments. |
|||
*/ |
|||
#define GPIOA_SPI1NSS 4 |
|||
|
|||
#define GPIOB_SPI2NSS 12 |
|||
|
|||
#define GPIOA_USB_P 0 |
|||
#define GPIOD_USB_DISC 2 |
|||
|
|||
#define GPIOE_TFT_RST 2 |
|||
#define GPIOD_TFT_LIGHT 13 |
|||
#define GPIOC_TFT_YD 0 |
|||
#define GPIOC_TFT_YU 1 |
|||
#define GPIOC_TFT_XL 2 |
|||
#define GPIOC_TFT_XR 3 |
|||
|
|||
/*
|
|||
* I/O ports initial setup, this configuration is established soon after reset |
|||
* in the initialization code. |
|||
* |
|||
* The digits have the following meaning: |
|||
* 0 - Analog input. |
|||
* 1 - Push Pull output 10MHz. |
|||
* 2 - Push Pull output 2MHz. |
|||
* 3 - Push Pull output 50MHz. |
|||
* 4 - Digital input. |
|||
* 5 - Open Drain output 10MHz. |
|||
* 6 - Open Drain output 2MHz. |
|||
* 7 - Open Drain output 50MHz. |
|||
* 8 - Digital input with PullUp or PullDown resistor depending on ODR. |
|||
* 9 - Alternate Push Pull output 10MHz. |
|||
* A - Alternate Push Pull output 2MHz. |
|||
* B - Alternate Push Pull output 50MHz. |
|||
* C - Reserved. |
|||
* D - Alternate Open Drain output 10MHz. |
|||
* E - Alternate Open Drain output 2MHz. |
|||
* F - Alternate Open Drain output 50MHz. |
|||
* Please refer to the STM32 Reference Manual for details. |
|||
*/ |
|||
|
|||
/*
|
|||
* Port A setup. |
|||
* Everything input with pull-up except: |
|||
* PA0 - Normal input (USB P). |
|||
* PA2 - Alternate output (USART2 TX). |
|||
* PA3 - Normal input (USART2 RX). |
|||
* PA11 - Normal input (USB DM). |
|||
* PA12 - Normal input (USB DP). |
|||
*/ |
|||
#define VAL_GPIOACRL 0x88884B84 /* PA7...PA0 */ |
|||
#define VAL_GPIOACRH 0x88844888 /* PA15...PA8 */ |
|||
#define VAL_GPIOAODR 0xFFFFFFFF |
|||
|
|||
/*
|
|||
* Port B setup. |
|||
* Everything input with pull-up except: |
|||
*/ |
|||
#define VAL_GPIOBCRL 0x88888888 /* PB7...PB0 */ |
|||
#define VAL_GPIOBCRH 0x88888888 /* PB15...PB8 */ |
|||
#define VAL_GPIOBODR 0xFFFFFFFF |
|||
|
|||
/*
|
|||
* Port C setup. |
|||
* Everything input with pull-up except: |
|||
* PC0 - Analog Input (TP_YD). |
|||
* PC1 - Analog Input (TP_YU). |
|||
* PC2 - Analog Input (TP_XL). |
|||
* PC3 - Analog Input (TP_XR). |
|||
* PC8 - Alternate PP 50M (SD_D0). |
|||
* PC9 - Alternate PP 50M (SD_D1). |
|||
* PC10 - Alternate PP 50M (SD_D2). |
|||
* PC11 - Alternate PP 50M (SD_D3). |
|||
* PC12 - Alternate PP 50M (SD_CLK). |
|||
* PC14 - Normal input (XTAL). |
|||
* PC15 - Normal input (XTAL). |
|||
*/ |
|||
#define VAL_GPIOCCRL 0x88880000 /* PC7...PC0 */ |
|||
#define VAL_GPIOCCRH 0x448BBBBB /* PC15...PC8 */ |
|||
#define VAL_GPIOCODR 0xFFFFFFFF |
|||
|
|||
/*
|
|||
* Port D setup. |
|||
* Everything input with pull-up except: |
|||
* PD2 - Alternate PP 50M (SD_CMD) |
|||
* PD0 - Alternate PP 50M (FSMC_D2) |
|||
* PD1 - Alternate PP 50M (FSMC_D3) |
|||
* PD4 - Alternate PP 50M (TFT_RD) |
|||
* PD5 - Alternate PP 50M (TFT_WR) |
|||
* PD7 - Alternate PP 50M (TFT_CS) |
|||
* PD8 - Alternate PP 50M (FSMC_D13) |
|||
* PD9 - Alternate PP 50M (FSMC_D14) |
|||
* PD10 - Alternate PP 50M (FSMC_D15) |
|||
* PD14 - Alternate PP 50M (FSMC_D0) |
|||
* PD15 - Alternate PP 50M (FSMC_D1) |
|||
*/ |
|||
#define VAL_GPIODCRL 0xBBBB8BBB /* PD7...PD0 */ |
|||
#define VAL_GPIODCRH 0xBB388BBB /* PD15...PD8 */ |
|||
#define VAL_GPIODODR 0xFFFFFFFF |
|||
|
|||
/*
|
|||
* Port E setup. |
|||
* Everything input with pull-up except: |
|||
* PE2 - Digital Output (TFT_RST) |
|||
* PE3 - Alternate PP 50M (TFT_RS) |
|||
* PE7 - Alternate PP 50M (FSMC_D4) |
|||
* PE8 - Alternate PP 50M (FSMC_D5) |
|||
* PE9 - Alternate PP 50M (FSMC_D6) |
|||
* PE10 - Alternate PP 50M (FSMC_D7) |
|||
* PE11 - Alternate PP 50M (FSMC_D8) |
|||
* PE12 - Alternate PP 50M (FSMC_D9) |
|||
* PE13 - Alternate PP 50M (FSMC_D10) |
|||
* PE14 - Alternate PP 50M (FSMC_D11) |
|||
* PE15 - Alternate PP 50M (FSMC_D12) |
|||
*/ |
|||
#define VAL_GPIOECRL 0xB888B388 /* PE7...PE0 */ |
|||
#define VAL_GPIOECRH 0xBBBBBBBB /* PE15...PE8 */ |
|||
#define VAL_GPIOEODR 0xFFFFFFFF |
|||
|
|||
/*
|
|||
* Port F setup. |
|||
* Everything input with pull-up expect: |
|||
*/ |
|||
#define VAL_GPIOFCRL 0x88888888 /* PF7...PF0 */ |
|||
#define VAL_GPIOFCRH 0x88888888 /* PF15...PF8 */ |
|||
#define VAL_GPIOFODR 0xFFFFFFFF |
|||
|
|||
/*
|
|||
* Port G setup. |
|||
* Everything input with pull-up expect: |
|||
*/ |
|||
#define VAL_GPIOGCRL 0x88888888 /* PG7...PG0 */ |
|||
#define VAL_GPIOGCRH 0x88888888 /* PG15...PG8 */ |
|||
#define VAL_GPIOGODR 0xFFFFFFFF |
|||
|
|||
/*
|
|||
* USB bus activation macro, required by the USB driver. |
|||
*/ |
|||
#define usb_lld_connect_bus(usbp) palClearPad(GPIOD, GPIOD_USB_DISC) |
|||
|
|||
/*
|
|||
* USB bus de-activation macro, required by the USB driver. |
|||
*/ |
|||
#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOD, GPIOD_USB_DISC) |
|||
|
|||
#if !defined(_FROM_ASM_) |
|||
#ifdef __cplusplus |
|||
extern "C" { |
|||
#endif |
|||
void boardInit(void); |
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
#endif /* _FROM_ASM_ */ |
|||
|
|||
#endif /* _BOARD_H_ */ |
|||
|
|||
@ -1,3 +1,3 @@ |
|||
BOARDINC = $(GFXLIB)/boards/base/Olimex-STM32-LCD/chibios_board |
|||
BOARDSRC = $(BOARDINC)/board.c \
|
|||
|
|||
BOARDINC = $(GFXLIB)/boards/base/Olimex-STM32-LCD/chibios_board |
|||
BOARDSRC = $(BOARDINC)/board.c \
|
|||
|
|||
|
|||
@ -1,7 +1,7 @@ |
|||
GFXINC += $(GFXLIB)/boards/base/STM32F429i-Discovery/chibios |
|||
GFXSRC += $(GFXLIB)/boards/base/STM32F429i-Discovery/chibios/stm32f429i_discovery_sdram.c \
|
|||
$(GFXLIB)/boards/base/STM32F429i-Discovery/chibios/stm32f4xx_fmc.c |
|||
|
|||
GFXDEFS += -DGFX_USE_OS_CHIBIOS=GFXON |
|||
include $(GFXLIB)/drivers/gdisp/STM32LTDC/driver.mk |
|||
include $(GFXLIB)/drivers/ginput/touch/STMPE811/driver.mk |
|||
GFXINC += $(GFXLIB)/boards/base/STM32F429i-Discovery/chibios |
|||
GFXSRC += $(GFXLIB)/boards/base/STM32F429i-Discovery/chibios/stm32f429i_discovery_sdram.c \
|
|||
$(GFXLIB)/boards/base/STM32F429i-Discovery/chibios/stm32f4xx_fmc.c |
|||
|
|||
GFXDEFS += -DGFX_USE_OS_CHIBIOS=GFXON |
|||
include $(GFXLIB)/drivers/gdisp/STM32LTDC/driver.mk |
|||
include $(GFXLIB)/drivers/ginput/touch/STMPE811/driver.mk |
|||
|
|||
@ -1,212 +1,212 @@ |
|||
/*
|
|||
* This file is subject to the terms of the GFX License. If a copy of |
|||
* the license was not distributed with this file, you can obtain one at: |
|||
* |
|||
* http://ugfx.io/license.html
|
|||
*/ |
|||
|
|||
#ifndef _GDISP_LLD_BOARD_H |
|||
#define _GDISP_LLD_BOARD_H |
|||
|
|||
#include "stm32f4xx_fmc.h" |
|||
#include "stm32f429i_discovery_sdram.h" |
|||
#include <string.h> |
|||
|
|||
#define SPI_PORT &SPID5 |
|||
#define DC_PORT GPIOD |
|||
#define DC_PIN GPIOD_LCD_WRX |
|||
|
|||
static const SPIConfig spi_cfg = { |
|||
NULL, |
|||
GPIOC, |
|||
GPIOC_SPI5_LCD_CS, |
|||
((1 << 3) & SPI_CR1_BR) | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR |
|||
}; |
|||
|
|||
static const ltdcConfig driverCfg = { |
|||
240, 320, |
|||
10, 2, |
|||
20, 2, |
|||
10, 4, |
|||
0, |
|||
0x000000, |
|||
{ |
|||
(LLDCOLOR_TYPE *)SDRAM_BANK_ADDR, // frame
|
|||
240, 320, // width, height
|
|||
240 * LTDC_PIXELBYTES, // pitch
|
|||
LTDC_PIXELFORMAT, // fmt
|
|||
0, 0, // x, y
|
|||
240, 320, // cx, cy
|
|||
0x00000000, // defcolor
|
|||
0x000000, // keycolor
|
|||
LTDC_BLEND_FIX1_FIX2, // blending
|
|||
0, // palette
|
|||
0, // palettelen
|
|||
0xFF, // alpha
|
|||
LTDC_LEF_ENABLE // flags
|
|||
}, |
|||
#if STM32LTDC_USE_LAYER2 || STM32LTDC_USE_DOUBLEBUFFERING |
|||
{ // Foreground layer config (if turned on)
|
|||
(LLDCOLOR_TYPE *)(SDRAM_BANK_ADDR+(240 * 320 * LTDC_PIXELBYTES)), // Frame buffer address
|
|||
240, 320, // width, height
|
|||
240 * LTDC_PIXELBYTES, // pitch
|
|||
LTDC_PIXELFORMAT, // fmt
|
|||
0, 0, // x, y
|
|||
240, 320, // cx, cy
|
|||
0x00000000, // Default color (ARGB8888)
|
|||
0x000000, // Color key (RGB888)
|
|||
LTDC_BLEND_MOD1_MOD2, // Blending factors
|
|||
0, // Palette (RGB888, can be NULL)
|
|||
0, // Palette length
|
|||
0xFF, // Constant alpha factor
|
|||
LTDC_LEF_ENABLE // Layer configuration flags
|
|||
} |
|||
#else |
|||
LTDC_UNUSED_LAYER_CONFIG |
|||
#endif |
|||
}; |
|||
|
|||
#include "ili9341.h" |
|||
|
|||
static void acquire_bus(GDisplay *g) { |
|||
(void) g; |
|||
|
|||
spiSelect(SPI_PORT); |
|||
} |
|||
|
|||
static void release_bus(GDisplay *g) { |
|||
(void) g; |
|||
|
|||
spiUnselect(SPI_PORT); |
|||
} |
|||
|
|||
static void write_index(GDisplay *g, gU8 index) { |
|||
static gU8 sindex; |
|||
(void) g; |
|||
|
|||
palClearPad(DC_PORT, DC_PIN); |
|||
sindex = index; |
|||
spiSend(SPI_PORT, 1, &sindex); |
|||
} |
|||
|
|||
static void write_data(GDisplay *g, gU8 data) { |
|||
static gU8 sdata; |
|||
(void) g; |
|||
|
|||
palSetPad(DC_PORT, DC_PIN); |
|||
sdata = data; |
|||
spiSend(SPI_PORT, 1, &sdata); |
|||
} |
|||
|
|||
static void Init9341(GDisplay *g) { |
|||
#define REG_TYPEMASK 0xFF00 |
|||
#define REG_DATAMASK 0x00FF |
|||
|
|||
#define REG_DATA 0x0000 |
|||
#define REG_COMMAND 0x0100 |
|||
#define REG_DELAY 0x0200 |
|||
|
|||
static const gU16 initdata[] = { |
|||
REG_COMMAND | ILI9341_CMD_RESET, |
|||
REG_DELAY | 5, |
|||
REG_COMMAND | ILI9341_CMD_DISPLAY_OFF, |
|||
REG_COMMAND | ILI9341_SET_FRAME_CTL_NORMAL, 0x00, 0x1B, |
|||
REG_COMMAND | ILI9341_SET_FUNCTION_CTL, 0x0A, 0xA2, |
|||
REG_COMMAND | ILI9341_SET_POWER_CTL_1, 0x10, |
|||
REG_COMMAND | ILI9341_SET_POWER_CTL_2, 0x10, |
|||
#if 1 |
|||
REG_COMMAND | ILI9341_SET_VCOM_CTL_1, 0x45, 0x15, |
|||
REG_COMMAND | ILI9341_SET_VCOM_CTL_2, 0x90, |
|||
#else |
|||
REG_COMMAND | ILI9341_SET_VCOM_CTL_1, 0x35, 0x3E, |
|||
REG_COMMAND | ILI9341_SET_VCOM_CTL_2, 0xBE, |
|||
#endif |
|||
REG_COMMAND | ILI9341_SET_MEM_ACS_CTL, 0xC8, |
|||
REG_COMMAND | ILI9341_SET_RGB_IF_SIG_CTL, 0xC2, |
|||
REG_COMMAND | ILI9341_SET_FUNCTION_CTL, 0x0A, 0xA7, 0x27, 0x04, |
|||
REG_COMMAND | ILI9341_SET_COL_ADDR, 0x00, 0x00, 0x00, 0xEF, |
|||
REG_COMMAND | ILI9341_SET_PAGE_ADDR, 0x00, 0x00, 0x01, 0x3F, |
|||
REG_COMMAND | ILI9341_SET_IF_CTL, 0x01, 0x00, 0x06, |
|||
REG_COMMAND | ILI9341_SET_GAMMA, 0x01, |
|||
REG_COMMAND | ILI9341_SET_PGAMMA, |
|||
#if 1 |
|||
0x0F, 0x29, 0x24, 0x0C, 0x0E, 0x09, 0x4E, 0x78, |
|||
0x3C, 0x09, 0x13, 0x05, 0x17, 0x11, 0x00, |
|||
#else |
|||
0x1F, 0x1a, 0x18, 0x0a, 0x0f, 0x06, 0x45, 0x87, |
|||
0x32, 0x0a, 0x07, 0x02, 0x07, 0x05, 0x00, |
|||
#endif |
|||
REG_COMMAND | ILI9341_SET_NGAMMA, |
|||
#if 1 |
|||
0x00, 0x16, 0x1B, 0x04, 0x11, 0x07, 0x31, 0x33, |
|||
0x42, 0x05, 0x0C, 0x0A, 0x28, 0x2F, 0x0F, |
|||
#else |
|||
0x00, 0x25, 0x27, 0x05, 0x10, 0x09, 0x3a, 0x78, |
|||
0x4d, 0x05, 0x18, 0x0d, 0x38, 0x3a, 0x1f, |
|||
#endif |
|||
REG_COMMAND | ILI9341_CMD_SLEEP_OFF, |
|||
REG_DELAY | 10, |
|||
REG_COMMAND | ILI9341_CMD_DISPLAY_ON, |
|||
REG_COMMAND | ILI9341_SET_MEM |
|||
}; |
|||
|
|||
const gU16 *p; |
|||
|
|||
acquire_bus(g); |
|||
for(p = initdata; p < &initdata[sizeof(initdata)/sizeof(initdata[0])]; p++) { |
|||
switch(*p & REG_TYPEMASK) { |
|||
case REG_DATA: write_data(g, *p); break; |
|||
case REG_COMMAND: write_index(g, *p); break; |
|||
case REG_DELAY: gfxSleepMilliseconds(*p & 0xFF); break; |
|||
} |
|||
} |
|||
release_bus(g); |
|||
} |
|||
|
|||
static void init_board(GDisplay *g) { |
|||
(void) g; |
|||
|
|||
palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); // UART_TX
|
|||
palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7)); // UART_RX
|
|||
palSetPadMode(GPIOF, GPIOF_LCD_DCX, PAL_MODE_ALTERNATE(5)); |
|||
palSetPadMode(GPIOF, GPIOF_LCD_DE, PAL_MODE_ALTERNATE(14)); |
|||
|
|||
#define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */ |
|||
#define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */ |
|||
#define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */ |
|||
#define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */ |
|||
#define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */ |
|||
#define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */ |
|||
|
|||
#define STM32_PLLSAIN_VALUE 192 |
|||
#define STM32_PLLSAIQ_VALUE 7 |
|||
#define STM32_PLLSAIR_VALUE 4 |
|||
#define STM32_PLLSAIR_POST STM32_SAIR_DIV4 |
|||
|
|||
/* PLLSAI activation.*/ |
|||
RCC->PLLSAICFGR = (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24); |
|||
RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST; |
|||
RCC->CR |= RCC_CR_PLLSAION; |
|||
while(!(RCC->CR & RCC_CR_PLLSAIRDY)); // wait for PLLSAI to lock
|
|||
|
|||
// Initialise the SDRAM
|
|||
SDRAM_Init(); |
|||
|
|||
// Clear the SDRAM
|
|||
memset((void *)SDRAM_BANK_ADDR, 0, 0x400000); |
|||
|
|||
spiStart(SPI_PORT, &spi_cfg); |
|||
|
|||
Init9341(g); |
|||
} |
|||
|
|||
static GFXINLINE void post_init_board(GDisplay *g) { |
|||
(void) g; |
|||
} |
|||
|
|||
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) { |
|||
(void) g; |
|||
(void) percent; |
|||
} |
|||
|
|||
#endif /* _GDISP_LLD_BOARD_H */ |
|||
/*
|
|||
* This file is subject to the terms of the GFX License. If a copy of |
|||
* the license was not distributed with this file, you can obtain one at: |
|||
* |
|||
* http://ugfx.io/license.html
|
|||
*/ |
|||
|
|||
#ifndef _GDISP_LLD_BOARD_H |
|||
#define _GDISP_LLD_BOARD_H |
|||
|
|||
#include "stm32f4xx_fmc.h" |
|||
#include "stm32f429i_discovery_sdram.h" |
|||
#include <string.h> |
|||
|
|||
#define SPI_PORT &SPID5 |
|||
#define DC_PORT GPIOD |
|||
#define DC_PIN GPIOD_LCD_WRX |
|||
|
|||
static const SPIConfig spi_cfg = { |
|||
NULL, |
|||
GPIOC, |
|||
GPIOC_SPI5_LCD_CS, |
|||
((1 << 3) & SPI_CR1_BR) | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR |
|||
}; |
|||
|
|||
static const ltdcConfig driverCfg = { |
|||
240, 320, |
|||
10, 2, |
|||
20, 2, |
|||
10, 4, |
|||
0, |
|||
0x000000, |
|||
{ |
|||
(LLDCOLOR_TYPE *)SDRAM_BANK_ADDR, // frame
|
|||
240, 320, // width, height
|
|||
240 * LTDC_PIXELBYTES, // pitch
|
|||
LTDC_PIXELFORMAT, // fmt
|
|||
0, 0, // x, y
|
|||
240, 320, // cx, cy
|
|||
0x00000000, // defcolor
|
|||
0x000000, // keycolor
|
|||
LTDC_BLEND_FIX1_FIX2, // blending
|
|||
0, // palette
|
|||
0, // palettelen
|
|||
0xFF, // alpha
|
|||
LTDC_LEF_ENABLE // flags
|
|||
}, |
|||
#if STM32LTDC_USE_LAYER2 || STM32LTDC_USE_DOUBLEBUFFERING |
|||
{ // Foreground layer config (if turned on)
|
|||
(LLDCOLOR_TYPE *)(SDRAM_BANK_ADDR+(240 * 320 * LTDC_PIXELBYTES)), // Frame buffer address
|
|||
240, 320, // width, height
|
|||
240 * LTDC_PIXELBYTES, // pitch
|
|||
LTDC_PIXELFORMAT, // fmt
|
|||
0, 0, // x, y
|
|||
240, 320, // cx, cy
|
|||
0x00000000, // Default color (ARGB8888)
|
|||
0x000000, // Color key (RGB888)
|
|||
LTDC_BLEND_MOD1_MOD2, // Blending factors
|
|||
0, // Palette (RGB888, can be NULL)
|
|||
0, // Palette length
|
|||
0xFF, // Constant alpha factor
|
|||
LTDC_LEF_ENABLE // Layer configuration flags
|
|||
} |
|||
#else |
|||
LTDC_UNUSED_LAYER_CONFIG |
|||
#endif |
|||
}; |
|||
|
|||
#include "ili9341.h" |
|||
|
|||
static void acquire_bus(GDisplay *g) { |
|||
(void) g; |
|||
|
|||
spiSelect(SPI_PORT); |
|||
} |
|||
|
|||
static void release_bus(GDisplay *g) { |
|||
(void) g; |
|||
|
|||
spiUnselect(SPI_PORT); |
|||
} |
|||
|
|||
static void write_index(GDisplay *g, gU8 index) { |
|||
static gU8 sindex; |
|||
(void) g; |
|||
|
|||
palClearPad(DC_PORT, DC_PIN); |
|||
sindex = index; |
|||
spiSend(SPI_PORT, 1, &sindex); |
|||
} |
|||
|
|||
static void write_data(GDisplay *g, gU8 data) { |
|||
static gU8 sdata; |
|||
(void) g; |
|||
|
|||
palSetPad(DC_PORT, DC_PIN); |
|||
sdata = data; |
|||
spiSend(SPI_PORT, 1, &sdata); |
|||
} |
|||
|
|||
static void Init9341(GDisplay *g) { |
|||
#define REG_TYPEMASK 0xFF00 |
|||
#define REG_DATAMASK 0x00FF |
|||
|
|||
#define REG_DATA 0x0000 |
|||
#define REG_COMMAND 0x0100 |
|||
#define REG_DELAY 0x0200 |
|||
|
|||
static const gU16 initdata[] = { |
|||
REG_COMMAND | ILI9341_CMD_RESET, |
|||
REG_DELAY | 5, |
|||
REG_COMMAND | ILI9341_CMD_DISPLAY_OFF, |
|||
REG_COMMAND | ILI9341_SET_FRAME_CTL_NORMAL, 0x00, 0x1B, |
|||
REG_COMMAND | ILI9341_SET_FUNCTION_CTL, 0x0A, 0xA2, |
|||
REG_COMMAND | ILI9341_SET_POWER_CTL_1, 0x10, |
|||
REG_COMMAND | ILI9341_SET_POWER_CTL_2, 0x10, |
|||
#if 1 |
|||
REG_COMMAND | ILI9341_SET_VCOM_CTL_1, 0x45, 0x15, |
|||
REG_COMMAND | ILI9341_SET_VCOM_CTL_2, 0x90, |
|||
#else |
|||
REG_COMMAND | ILI9341_SET_VCOM_CTL_1, 0x35, 0x3E, |
|||
REG_COMMAND | ILI9341_SET_VCOM_CTL_2, 0xBE, |
|||
#endif |
|||
REG_COMMAND | ILI9341_SET_MEM_ACS_CTL, 0xC8, |
|||
REG_COMMAND | ILI9341_SET_RGB_IF_SIG_CTL, 0xC2, |
|||
REG_COMMAND | ILI9341_SET_FUNCTION_CTL, 0x0A, 0xA7, 0x27, 0x04, |
|||
REG_COMMAND | ILI9341_SET_COL_ADDR, 0x00, 0x00, 0x00, 0xEF, |
|||
REG_COMMAND | ILI9341_SET_PAGE_ADDR, 0x00, 0x00, 0x01, 0x3F, |
|||
REG_COMMAND | ILI9341_SET_IF_CTL, 0x01, 0x00, 0x06, |
|||
REG_COMMAND | ILI9341_SET_GAMMA, 0x01, |
|||
REG_COMMAND | ILI9341_SET_PGAMMA, |
|||
#if 1 |
|||
0x0F, 0x29, 0x24, 0x0C, 0x0E, 0x09, 0x4E, 0x78, |
|||
0x3C, 0x09, 0x13, 0x05, 0x17, 0x11, 0x00, |
|||
#else |
|||
0x1F, 0x1a, 0x18, 0x0a, 0x0f, 0x06, 0x45, 0x87, |
|||
0x32, 0x0a, 0x07, 0x02, 0x07, 0x05, 0x00, |
|||
#endif |
|||
REG_COMMAND | ILI9341_SET_NGAMMA, |
|||
#if 1 |
|||
0x00, 0x16, 0x1B, 0x04, 0x11, 0x07, 0x31, 0x33, |
|||
0x42, 0x05, 0x0C, 0x0A, 0x28, 0x2F, 0x0F, |
|||
#else |
|||
0x00, 0x25, 0x27, 0x05, 0x10, 0x09, 0x3a, 0x78, |
|||
0x4d, 0x05, 0x18, 0x0d, 0x38, 0x3a, 0x1f, |
|||
#endif |
|||
REG_COMMAND | ILI9341_CMD_SLEEP_OFF, |
|||
REG_DELAY | 10, |
|||
REG_COMMAND | ILI9341_CMD_DISPLAY_ON, |
|||
REG_COMMAND | ILI9341_SET_MEM |
|||
}; |
|||
|
|||
const gU16 *p; |
|||
|
|||
acquire_bus(g); |
|||
for(p = initdata; p < &initdata[sizeof(initdata)/sizeof(initdata[0])]; p++) { |
|||
switch(*p & REG_TYPEMASK) { |
|||
case REG_DATA: write_data(g, *p); break; |
|||
case REG_COMMAND: write_index(g, *p); break; |
|||
case REG_DELAY: gfxSleepMilliseconds(*p & 0xFF); break; |
|||
} |
|||
} |
|||
release_bus(g); |
|||
} |
|||
|
|||
static void init_board(GDisplay *g) { |
|||
(void) g; |
|||
|
|||
palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); // UART_TX
|
|||
palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7)); // UART_RX
|
|||
palSetPadMode(GPIOF, GPIOF_LCD_DCX, PAL_MODE_ALTERNATE(5)); |
|||
palSetPadMode(GPIOF, GPIOF_LCD_DE, PAL_MODE_ALTERNATE(14)); |
|||
|
|||
#define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */ |
|||
#define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */ |
|||
#define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */ |
|||
#define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */ |
|||
#define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */ |
|||
#define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */ |
|||
|
|||
#define STM32_PLLSAIN_VALUE 192 |
|||
#define STM32_PLLSAIQ_VALUE 7 |
|||
#define STM32_PLLSAIR_VALUE 4 |
|||
#define STM32_PLLSAIR_POST STM32_SAIR_DIV4 |
|||
|
|||
/* PLLSAI activation.*/ |
|||
RCC->PLLSAICFGR = (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24); |
|||
RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST; |
|||
RCC->CR |= RCC_CR_PLLSAION; |
|||
while(!(RCC->CR & RCC_CR_PLLSAIRDY)); // wait for PLLSAI to lock
|
|||
|
|||
// Initialise the SDRAM
|
|||
SDRAM_Init(); |
|||
|
|||
// Clear the SDRAM
|
|||
memset((void *)SDRAM_BANK_ADDR, 0, 0x400000); |
|||
|
|||
spiStart(SPI_PORT, &spi_cfg); |
|||
|
|||
Init9341(g); |
|||
} |
|||
|
|||
static GFXINLINE void post_init_board(GDisplay *g) { |
|||
(void) g; |
|||
} |
|||
|
|||
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) { |
|||
(void) g; |
|||
(void) percent; |
|||
} |
|||
|
|||
#endif /* _GDISP_LLD_BOARD_H */ |
|||
|
|||
@ -1,126 +1,126 @@ |
|||
/*
|
|||
* This file is subject to the terms of the GFX License. If a copy of |
|||
* the license was not distributed with this file, you can obtain one at: |
|||
* |
|||
* http://ugfx.io/license.html
|
|||
*/ |
|||
|
|||
#ifndef _GINPUT_LLD_MOUSE_BOARD_H |
|||
#define _GINPUT_LLD_MOUSE_BOARD_H |
|||
|
|||
// Resolution and Accuracy Settings
|
|||
#define GMOUSE_STMPE811_PEN_CALIBRATE_ERROR 8 |
|||
#define GMOUSE_STMPE811_PEN_CLICK_ERROR 6 |
|||
#define GMOUSE_STMPE811_PEN_MOVE_ERROR 4 |
|||
#define GMOUSE_STMPE811_FINGER_CALIBRATE_ERROR 14 |
|||
#define GMOUSE_STMPE811_FINGER_CLICK_ERROR 18 |
|||
#define GMOUSE_STMPE811_FINGER_MOVE_ERROR 14 |
|||
|
|||
// How much extra data to allocate at the end of the GMouse structure for the board's use
|
|||
#define GMOUSE_STMPE811_BOARD_DATA_SIZE 0 |
|||
|
|||
// Options - Leave these commented to make it user configurable in the gfxconf.h
|
|||
//#define GMOUSE_STMPE811_READ_PRESSURE GFXOFF
|
|||
//#define GMOUSE_STMPE811_SELF_CALIBRATE GFXOFF
|
|||
//#define GMOUSE_STMPE811_TEST_MODE GFXOFF
|
|||
|
|||
// Set to GFXOFF because it does not work properly on this board even though the pin exists.
|
|||
#define GMOUSE_STMPE811_GPIO_IRQPIN GFXOFF |
|||
|
|||
// If GFXON this is a really slow CPU and we should always clear the FIFO between reads.
|
|||
#define GMOUSE_STMPE811_SLOW_CPU GFXOFF |
|||
|
|||
// Slave address
|
|||
#define STMPE811_ADDR 0x41 |
|||
|
|||
// Maximum timeout
|
|||
#define STMPE811_TIMEOUT 0x3000 |
|||
|
|||
static const I2CConfig i2ccfg = { |
|||
OPMODE_I2C, |
|||
400000, |
|||
FAST_DUTY_CYCLE_2, |
|||
}; |
|||
|
|||
static gBool init_board(GMouse* m, unsigned driverinstance) { |
|||
(void) m; |
|||
|
|||
// This board only supports one touch panel
|
|||
if (driverinstance) |
|||
return gFalse; |
|||
|
|||
// Set pin modes
|
|||
#if CH_KERNEL_MAJOR == 2 |
|||
palSetPadMode(GPIOA, 15, PAL_MODE_INPUT | PAL_STM32_PUDR_FLOATING); /* TP IRQ */ |
|||
palSetPadMode(GPIOA, 8, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN); /* SCL */ |
|||
palSetPadMode(GPIOC, 9, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN); /* SDA */ |
|||
#else |
|||
palSetPadMode(GPIOA, 15, PAL_MODE_INPUT | PAL_STM32_PUPDR_FLOATING); /* TP IRQ */ |
|||
palSetPadMode(GPIOA, 8, PAL_MODE_ALTERNATE(4) | PAL_STM32_PUPDR_FLOATING); /* SCL */ |
|||
palSetPadMode(GPIOC, 9, PAL_MODE_ALTERNATE(4) | PAL_STM32_PUPDR_FLOATING); /* SDA */ |
|||
#endif |
|||
|
|||
// Start the I2C
|
|||
i2cStart(&I2CD3, &i2ccfg); |
|||
|
|||
return gTrue; |
|||
} |
|||
|
|||
#if GMOUSE_STMPE811_GPIO_IRQPIN |
|||
static gBool getpin_irq(GMouse* m) { |
|||
(void) m; |
|||
|
|||
return !palReadPad(GPIOA, 15); |
|||
} |
|||
#endif |
|||
|
|||
static GFXINLINE void aquire_bus(GMouse* m) { |
|||
(void) m; |
|||
|
|||
} |
|||
|
|||
static GFXINLINE void release_bus(GMouse* m) { |
|||
(void) m; |
|||
|
|||
} |
|||
|
|||
static void write_reg(GMouse* m, gU8 reg, gU8 val) { |
|||
gU8 txbuf[2]; |
|||
(void) m; |
|||
|
|||
txbuf[0] = reg; |
|||
txbuf[1] = val; |
|||
|
|||
i2cAcquireBus(&I2CD3); |
|||
i2cMasterTransmitTimeout(&I2CD3, STMPE811_ADDR, txbuf, 2, 0, 0, MS2ST(STMPE811_TIMEOUT)); |
|||
i2cReleaseBus(&I2CD3); |
|||
} |
|||
|
|||
static gU8 read_byte(GMouse* m, gU8 reg) { |
|||
gU8 rxbuf[1]; |
|||
(void) m; |
|||
|
|||
rxbuf[0] = 0; |
|||
|
|||
i2cAcquireBus(&I2CD3); |
|||
i2cMasterTransmitTimeout(&I2CD3, STMPE811_ADDR, ®, 1, rxbuf, 1, MS2ST(STMPE811_TIMEOUT)); |
|||
i2cReleaseBus(&I2CD3); |
|||
|
|||
return rxbuf[0]; |
|||
} |
|||
|
|||
static gU16 read_word(GMouse* m, gU8 reg) { |
|||
gU8 rxbuf[2]; |
|||
(void) m; |
|||
|
|||
rxbuf[ | |||