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Fixing line endings

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inmarket 2021-10-20 22:17:27 +10:00
parent ae6a3bc18b
commit 2c1c87ee1b
62 changed files with 11890 additions and 11890 deletions
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6
boards/base/FireBull-STM32F103-FB/chibios_board/board.mk
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@ -1,3 +1,3 @@
BOARDINC = $(GFXLIB)/boards/base/FireBull-STM32F103-FB/chibios_board
BOARDSRC = $(BOARDINC)/board.c \
BOARDINC = $(GFXLIB)/boards/base/FireBull-STM32F103-FB/chibios_board
BOARDSRC = $(BOARDINC)/board.c \

176
boards/base/Marlin/chibios_board/board.c
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@ -1,88 +1,88 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "ch.h"
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
const PALConfig pal_default_config =
{
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
};
#endif
/**
* @brief Early initialization code.
* @details This initialization must be performed just after stack setup
* and before any other initialization.
*/
void __early_init(void) {
stm32_clock_init();
}
#if HAL_USE_SDC
/*
* Card detection through the card internal pull-up on D3.
*/
bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
(void)sdcp;
return (bool_t)!palReadPad(GPIOD, GPIOD_SDIO_CD_N);
}
/*
* Card write protection detection is not possible, the card is always
* reported as not protected.
*/
bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
return 0;
}
#endif /* HAL_USE_SDC */
/**
* @brief Board-specific initialization code.
*/
void boardInit(void) {
}
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "ch.h"
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
const PALConfig pal_default_config =
{
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
};
#endif
/**
* @brief Early initialization code.
* @details This initialization must be performed just after stack setup
* and before any other initialization.
*/
void __early_init(void) {
stm32_clock_init();
}
#if HAL_USE_SDC
/*
* Card detection through the card internal pull-up on D3.
*/
bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
(void)sdcp;
return (bool_t)!palReadPad(GPIOD, GPIOD_SDIO_CD_N);
}
/*
* Card write protection detection is not possible, the card is always
* reported as not protected.
*/
bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
return 0;
}
#endif /* HAL_USE_SDC */
/**
* @brief Board-specific initialization code.
*/
void boardInit(void) {
}

2604
boards/base/Marlin/chibios_board/board.h
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6
boards/base/Marlin/chibios_board/board.mk
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@ -1,3 +1,3 @@
BOARDINC = $(GFXLIB)/boards/base/Marlin/chibios_board
BOARDSRC = $(BOARDINC)/board.c \
BOARDINC = $(GFXLIB)/boards/base/Marlin/chibios_board
BOARDSRC = $(BOARDINC)/board.c \

212
boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.c
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@ -1,106 +1,106 @@
/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
const PALConfig pal_default_config =
{
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
};
#endif
/**
* @brief Early initialization code.
* @details This initialization must be performed just after stack setup
* and before any other initialization.
*/
void __early_init(void) {
stm32_clock_init();
}
#if HAL_USE_SDC || defined(__DOXYGEN__)
/**
* @brief SDC card detection.
*/
bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
return TRUE;
}
/**
* @brief SDC card write protection detection.
*/
bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
return FALSE;
}
#endif /* HAL_USE_SDC */
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
/**
* @brief MMC_SPI card detection.
*/
bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
return !palReadPad(GPIOD, GPIOD_SD_CD);
}
/**
* @brief MMC_SPI card write protection detection.
*/
bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
/* Board has no write protection detection */
return FALSE;
}
#endif
/**
* @brief Board-specific initialization code.
* @todo Add your board-specific code, if any.
*/
void boardInit(void) {
}
/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
const PALConfig pal_default_config =
{
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
};
#endif
/**
* @brief Early initialization code.
* @details This initialization must be performed just after stack setup
* and before any other initialization.
*/
void __early_init(void) {
stm32_clock_init();
}
#if HAL_USE_SDC || defined(__DOXYGEN__)
/**
* @brief SDC card detection.
*/
bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
return TRUE;
}
/**
* @brief SDC card write protection detection.
*/
bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
return FALSE;
}
#endif /* HAL_USE_SDC */
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
/**
* @brief MMC_SPI card detection.
*/
bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
return !palReadPad(GPIOD, GPIOD_SD_CD);
}
/**
* @brief MMC_SPI card write protection detection.
*/
bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
/* Board has no write protection detection */
return FALSE;
}
#endif
/**
* @brief Board-specific initialization code.
* @todo Add your board-specific code, if any.
*/
void boardInit(void) {
}

2592
boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.h
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10
boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/board.mk
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@ -1,6 +1,6 @@
# Required include directories
BOARDINC = $(GFXLIB)/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board
# List of all the board related files.
BOARDSRC = $(BOARDINC)/board.c \
# Required include directories
BOARDINC = $(GFXLIB)/boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board
# List of all the board related files.
BOARDSRC = $(BOARDINC)/board.c \
$(BOARDINC)/flash_memory.c

176
boards/base/Olimex-STM32-LCD/chibios_board/board.c
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@ -1,88 +1,88 @@
/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "ch.h"
#include "hal.h"
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
#if HAL_USE_PAL || defined(__DOXYGEN__)
const PALConfig pal_default_config =
{
{VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
{VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
{VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
{VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
{VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
{VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH},
{VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH},
};
#endif
/*
* Early initialization code.
* This initialization must be performed just after stack setup and before
* any other initialization.
*/
void __early_init(void) {
stm32_clock_init();
}
#if HAL_USE_SDC || defined(__DOXYGEN__)
/**
* @brief SDC card detection.
*/
bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
(void)sdcp;
return TRUE;
}
/**
* @brief SDC card write protection detection.
*/
bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
return FALSE;
}
#endif /* HAL_USE_SDC */
#if HAL_USE_MMC_SPI
/* Board-related functions related to the MMC_SPI driver.*/
bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
return TRUE;
}
bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
return FALSE;
}
#endif
/*
* Board-specific initialization code.
*/
void boardInit(void) {
}
/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "ch.h"
#include "hal.h"
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
#if HAL_USE_PAL || defined(__DOXYGEN__)
const PALConfig pal_default_config =
{
{VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
{VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
{VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
{VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
{VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
{VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH},
{VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH},
};
#endif
/*
* Early initialization code.
* This initialization must be performed just after stack setup and before
* any other initialization.
*/
void __early_init(void) {
stm32_clock_init();
}
#if HAL_USE_SDC || defined(__DOXYGEN__)
/**
* @brief SDC card detection.
*/
bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
(void)sdcp;
return TRUE;
}
/**
* @brief SDC card write protection detection.
*/
bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
return FALSE;
}
#endif /* HAL_USE_SDC */
#if HAL_USE_MMC_SPI
/* Board-related functions related to the MMC_SPI driver.*/
bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
return TRUE;
}
bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
return FALSE;
}
#endif
/*
* Board-specific initialization code.
*/
void boardInit(void) {
}

392
boards/base/Olimex-STM32-LCD/chibios_board/board.h
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@ -1,196 +1,196 @@
/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* Setup for the Olimex STM32-LCD proto board.
*/
/*
* Board identifier.
*/
#define BOARD_OLIMEX_STM32_LCD
#define BOARD_NAME "Olimex STM32-LCD"
/*
* Board frequencies.
*/
#define STM32_LSECLK 32768
#define STM32_HSECLK 8000000
/*
* MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
*/
#define STM32F10X_HD
/*
* IO pins assignments.
*/
#define GPIOA_SPI1NSS 4
#define GPIOB_SPI2NSS 12
#define GPIOA_USB_P 0
#define GPIOD_USB_DISC 2
#define GPIOE_TFT_RST 2
#define GPIOD_TFT_LIGHT 13
#define GPIOC_TFT_YD 0
#define GPIOC_TFT_YU 1
#define GPIOC_TFT_XL 2
#define GPIOC_TFT_XR 3
/*
* I/O ports initial setup, this configuration is established soon after reset
* in the initialization code.
*
* The digits have the following meaning:
* 0 - Analog input.
* 1 - Push Pull output 10MHz.
* 2 - Push Pull output 2MHz.
* 3 - Push Pull output 50MHz.
* 4 - Digital input.
* 5 - Open Drain output 10MHz.
* 6 - Open Drain output 2MHz.
* 7 - Open Drain output 50MHz.
* 8 - Digital input with PullUp or PullDown resistor depending on ODR.
* 9 - Alternate Push Pull output 10MHz.
* A - Alternate Push Pull output 2MHz.
* B - Alternate Push Pull output 50MHz.
* C - Reserved.
* D - Alternate Open Drain output 10MHz.
* E - Alternate Open Drain output 2MHz.
* F - Alternate Open Drain output 50MHz.
* Please refer to the STM32 Reference Manual for details.
*/
/*
* Port A setup.
* Everything input with pull-up except:
* PA0 - Normal input (USB P).
* PA2 - Alternate output (USART2 TX).
* PA3 - Normal input (USART2 RX).
* PA11 - Normal input (USB DM).
* PA12 - Normal input (USB DP).
*/
#define VAL_GPIOACRL 0x88884B84 /* PA7...PA0 */
#define VAL_GPIOACRH 0x88844888 /* PA15...PA8 */
#define VAL_GPIOAODR 0xFFFFFFFF
/*
* Port B setup.
* Everything input with pull-up except:
*/
#define VAL_GPIOBCRL 0x88888888 /* PB7...PB0 */
#define VAL_GPIOBCRH 0x88888888 /* PB15...PB8 */
#define VAL_GPIOBODR 0xFFFFFFFF
/*
* Port C setup.
* Everything input with pull-up except:
* PC0 - Analog Input (TP_YD).
* PC1 - Analog Input (TP_YU).
* PC2 - Analog Input (TP_XL).
* PC3 - Analog Input (TP_XR).
* PC8 - Alternate PP 50M (SD_D0).
* PC9 - Alternate PP 50M (SD_D1).
* PC10 - Alternate PP 50M (SD_D2).
* PC11 - Alternate PP 50M (SD_D3).
* PC12 - Alternate PP 50M (SD_CLK).
* PC14 - Normal input (XTAL).
* PC15 - Normal input (XTAL).
*/
#define VAL_GPIOCCRL 0x88880000 /* PC7...PC0 */
#define VAL_GPIOCCRH 0x448BBBBB /* PC15...PC8 */
#define VAL_GPIOCODR 0xFFFFFFFF
/*
* Port D setup.
* Everything input with pull-up except:
* PD2 - Alternate PP 50M (SD_CMD)
* PD0 - Alternate PP 50M (FSMC_D2)
* PD1 - Alternate PP 50M (FSMC_D3)
* PD4 - Alternate PP 50M (TFT_RD)
* PD5 - Alternate PP 50M (TFT_WR)
* PD7 - Alternate PP 50M (TFT_CS)
* PD8 - Alternate PP 50M (FSMC_D13)
* PD9 - Alternate PP 50M (FSMC_D14)
* PD10 - Alternate PP 50M (FSMC_D15)
* PD14 - Alternate PP 50M (FSMC_D0)
* PD15 - Alternate PP 50M (FSMC_D1)
*/
#define VAL_GPIODCRL 0xBBBB8BBB /* PD7...PD0 */
#define VAL_GPIODCRH 0xBB388BBB /* PD15...PD8 */
#define VAL_GPIODODR 0xFFFFFFFF
/*
* Port E setup.
* Everything input with pull-up except:
* PE2 - Digital Output (TFT_RST)
* PE3 - Alternate PP 50M (TFT_RS)
* PE7 - Alternate PP 50M (FSMC_D4)
* PE8 - Alternate PP 50M (FSMC_D5)
* PE9 - Alternate PP 50M (FSMC_D6)
* PE10 - Alternate PP 50M (FSMC_D7)
* PE11 - Alternate PP 50M (FSMC_D8)
* PE12 - Alternate PP 50M (FSMC_D9)
* PE13 - Alternate PP 50M (FSMC_D10)
* PE14 - Alternate PP 50M (FSMC_D11)
* PE15 - Alternate PP 50M (FSMC_D12)
*/
#define VAL_GPIOECRL 0xB888B388 /* PE7...PE0 */
#define VAL_GPIOECRH 0xBBBBBBBB /* PE15...PE8 */
#define VAL_GPIOEODR 0xFFFFFFFF
/*
* Port F setup.
* Everything input with pull-up expect:
*/
#define VAL_GPIOFCRL 0x88888888 /* PF7...PF0 */
#define VAL_GPIOFCRH 0x88888888 /* PF15...PF8 */
#define VAL_GPIOFODR 0xFFFFFFFF
/*
* Port G setup.
* Everything input with pull-up expect:
*/
#define VAL_GPIOGCRL 0x88888888 /* PG7...PG0 */
#define VAL_GPIOGCRH 0x88888888 /* PG15...PG8 */
#define VAL_GPIOGODR 0xFFFFFFFF
/*
* USB bus activation macro, required by the USB driver.
*/
#define usb_lld_connect_bus(usbp) palClearPad(GPIOD, GPIOD_USB_DISC)
/*
* USB bus de-activation macro, required by the USB driver.
*/
#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOD, GPIOD_USB_DISC)
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
#endif
void boardInit(void);
#ifdef __cplusplus
}
#endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */
/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* Setup for the Olimex STM32-LCD proto board.
*/
/*
* Board identifier.
*/
#define BOARD_OLIMEX_STM32_LCD
#define BOARD_NAME "Olimex STM32-LCD"
/*
* Board frequencies.
*/
#define STM32_LSECLK 32768
#define STM32_HSECLK 8000000
/*
* MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
*/
#define STM32F10X_HD
/*
* IO pins assignments.
*/
#define GPIOA_SPI1NSS 4
#define GPIOB_SPI2NSS 12
#define GPIOA_USB_P 0
#define GPIOD_USB_DISC 2
#define GPIOE_TFT_RST 2
#define GPIOD_TFT_LIGHT 13
#define GPIOC_TFT_YD 0
#define GPIOC_TFT_YU 1
#define GPIOC_TFT_XL 2
#define GPIOC_TFT_XR 3
/*
* I/O ports initial setup, this configuration is established soon after reset
* in the initialization code.
*
* The digits have the following meaning:
* 0 - Analog input.
* 1 - Push Pull output 10MHz.
* 2 - Push Pull output 2MHz.
* 3 - Push Pull output 50MHz.
* 4 - Digital input.
* 5 - Open Drain output 10MHz.
* 6 - Open Drain output 2MHz.
* 7 - Open Drain output 50MHz.
* 8 - Digital input with PullUp or PullDown resistor depending on ODR.
* 9 - Alternate Push Pull output 10MHz.
* A - Alternate Push Pull output 2MHz.
* B - Alternate Push Pull output 50MHz.
* C - Reserved.
* D - Alternate Open Drain output 10MHz.
* E - Alternate Open Drain output 2MHz.
* F - Alternate Open Drain output 50MHz.
* Please refer to the STM32 Reference Manual for details.
*/
/*
* Port A setup.
* Everything input with pull-up except:
* PA0 - Normal input (USB P).
* PA2 - Alternate output (USART2 TX).
* PA3 - Normal input (USART2 RX).
* PA11 - Normal input (USB DM).
* PA12 - Normal input (USB DP).
*/
#define VAL_GPIOACRL 0x88884B84 /* PA7...PA0 */
#define VAL_GPIOACRH 0x88844888 /* PA15...PA8 */
#define VAL_GPIOAODR 0xFFFFFFFF
/*
* Port B setup.
* Everything input with pull-up except:
*/
#define VAL_GPIOBCRL 0x88888888 /* PB7...PB0 */
#define VAL_GPIOBCRH 0x88888888 /* PB15...PB8 */
#define VAL_GPIOBODR 0xFFFFFFFF
/*
* Port C setup.
* Everything input with pull-up except:
* PC0 - Analog Input (TP_YD).
* PC1 - Analog Input (TP_YU).
* PC2 - Analog Input (TP_XL).
* PC3 - Analog Input (TP_XR).
* PC8 - Alternate PP 50M (SD_D0).
* PC9 - Alternate PP 50M (SD_D1).
* PC10 - Alternate PP 50M (SD_D2).
* PC11 - Alternate PP 50M (SD_D3).
* PC12 - Alternate PP 50M (SD_CLK).
* PC14 - Normal input (XTAL).
* PC15 - Normal input (XTAL).
*/
#define VAL_GPIOCCRL 0x88880000 /* PC7...PC0 */
#define VAL_GPIOCCRH 0x448BBBBB /* PC15...PC8 */
#define VAL_GPIOCODR 0xFFFFFFFF
/*
* Port D setup.
* Everything input with pull-up except:
* PD2 - Alternate PP 50M (SD_CMD)
* PD0 - Alternate PP 50M (FSMC_D2)
* PD1 - Alternate PP 50M (FSMC_D3)
* PD4 - Alternate PP 50M (TFT_RD)
* PD5 - Alternate PP 50M (TFT_WR)
* PD7 - Alternate PP 50M (TFT_CS)
* PD8 - Alternate PP 50M (FSMC_D13)
* PD9 - Alternate PP 50M (FSMC_D14)
* PD10 - Alternate PP 50M (FSMC_D15)
* PD14 - Alternate PP 50M (FSMC_D0)
* PD15 - Alternate PP 50M (FSMC_D1)
*/
#define VAL_GPIODCRL 0xBBBB8BBB /* PD7...PD0 */
#define VAL_GPIODCRH 0xBB388BBB /* PD15...PD8 */
#define VAL_GPIODODR 0xFFFFFFFF
/*
* Port E setup.
* Everything input with pull-up except:
* PE2 - Digital Output (TFT_RST)
* PE3 - Alternate PP 50M (TFT_RS)
* PE7 - Alternate PP 50M (FSMC_D4)
* PE8 - Alternate PP 50M (FSMC_D5)
* PE9 - Alternate PP 50M (FSMC_D6)
* PE10 - Alternate PP 50M (FSMC_D7)
* PE11 - Alternate PP 50M (FSMC_D8)
* PE12 - Alternate PP 50M (FSMC_D9)
* PE13 - Alternate PP 50M (FSMC_D10)
* PE14 - Alternate PP 50M (FSMC_D11)
* PE15 - Alternate PP 50M (FSMC_D12)
*/
#define VAL_GPIOECRL 0xB888B388 /* PE7...PE0 */
#define VAL_GPIOECRH 0xBBBBBBBB /* PE15...PE8 */
#define VAL_GPIOEODR 0xFFFFFFFF
/*
* Port F setup.
* Everything input with pull-up expect:
*/
#define VAL_GPIOFCRL 0x88888888 /* PF7...PF0 */
#define VAL_GPIOFCRH 0x88888888 /* PF15...PF8 */
#define VAL_GPIOFODR 0xFFFFFFFF
/*
* Port G setup.
* Everything input with pull-up expect:
*/
#define VAL_GPIOGCRL 0x88888888 /* PG7...PG0 */
#define VAL_GPIOGCRH 0x88888888 /* PG15...PG8 */
#define VAL_GPIOGODR 0xFFFFFFFF
/*
* USB bus activation macro, required by the USB driver.
*/
#define usb_lld_connect_bus(usbp) palClearPad(GPIOD, GPIOD_USB_DISC)
/*
* USB bus de-activation macro, required by the USB driver.
*/
#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOD, GPIOD_USB_DISC)
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
#endif
void boardInit(void);
#ifdef __cplusplus
}
#endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */

6
boards/base/Olimex-STM32-LCD/chibios_board/board.mk
View file

@ -1,3 +1,3 @@
BOARDINC = $(GFXLIB)/boards/base/Olimex-STM32-LCD/chibios_board
BOARDSRC = $(BOARDINC)/board.c \
BOARDINC = $(GFXLIB)/boards/base/Olimex-STM32-LCD/chibios_board
BOARDSRC = $(BOARDINC)/board.c \

14
boards/base/STM32F429i-Discovery/chibios/board.mk
View file

@ -1,7 +1,7 @@
GFXINC += $(GFXLIB)/boards/base/STM32F429i-Discovery/chibios
GFXSRC += $(GFXLIB)/boards/base/STM32F429i-Discovery/chibios/stm32f429i_discovery_sdram.c \
$(GFXLIB)/boards/base/STM32F429i-Discovery/chibios/stm32f4xx_fmc.c
GFXDEFS += -DGFX_USE_OS_CHIBIOS=GFXON
include $(GFXLIB)/drivers/gdisp/STM32LTDC/driver.mk
include $(GFXLIB)/drivers/ginput/touch/STMPE811/driver.mk
GFXINC += $(GFXLIB)/boards/base/STM32F429i-Discovery/chibios
GFXSRC += $(GFXLIB)/boards/base/STM32F429i-Discovery/chibios/stm32f429i_discovery_sdram.c \
$(GFXLIB)/boards/base/STM32F429i-Discovery/chibios/stm32f4xx_fmc.c
GFXDEFS += -DGFX_USE_OS_CHIBIOS=GFXON
include $(GFXLIB)/drivers/gdisp/STM32LTDC/driver.mk
include $(GFXLIB)/drivers/ginput/touch/STMPE811/driver.mk

424
boards/base/STM32F429i-Discovery/chibios/board_STM32LTDC.h
View file

@ -1,212 +1,212 @@
/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.io/license.html
*/
#ifndef _GDISP_LLD_BOARD_H
#define _GDISP_LLD_BOARD_H
#include "stm32f4xx_fmc.h"
#include "stm32f429i_discovery_sdram.h"
#include <string.h>
#define SPI_PORT &SPID5
#define DC_PORT GPIOD
#define DC_PIN GPIOD_LCD_WRX
static const SPIConfig spi_cfg = {
NULL,
GPIOC,
GPIOC_SPI5_LCD_CS,
((1 << 3) & SPI_CR1_BR) | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR
};
static const ltdcConfig driverCfg = {
240, 320,
10, 2,
20, 2,
10, 4,
0,
0x000000,
{
(LLDCOLOR_TYPE *)SDRAM_BANK_ADDR, // frame
240, 320, // width, height
240 * LTDC_PIXELBYTES, // pitch
LTDC_PIXELFORMAT, // fmt
0, 0, // x, y
240, 320, // cx, cy
0x00000000, // defcolor
0x000000, // keycolor
LTDC_BLEND_FIX1_FIX2, // blending
0, // palette
0, // palettelen
0xFF, // alpha
LTDC_LEF_ENABLE // flags
},
#if STM32LTDC_USE_LAYER2 || STM32LTDC_USE_DOUBLEBUFFERING
{ // Foreground layer config (if turned on)
(LLDCOLOR_TYPE *)(SDRAM_BANK_ADDR+(240 * 320 * LTDC_PIXELBYTES)), // Frame buffer address
240, 320, // width, height
240 * LTDC_PIXELBYTES, // pitch
LTDC_PIXELFORMAT, // fmt
0, 0, // x, y
240, 320, // cx, cy
0x00000000, // Default color (ARGB8888)
0x000000, // Color key (RGB888)
LTDC_BLEND_MOD1_MOD2, // Blending factors
0, // Palette (RGB888, can be NULL)
0, // Palette length
0xFF, // Constant alpha factor
LTDC_LEF_ENABLE // Layer configuration flags
}
#else
LTDC_UNUSED_LAYER_CONFIG
#endif
};
#include "ili9341.h"
static void acquire_bus(GDisplay *g) {
(void) g;
spiSelect(SPI_PORT);
}
static void release_bus(GDisplay *g) {
(void) g;
spiUnselect(SPI_PORT);
}
static void write_index(GDisplay *g, gU8 index) {
static gU8 sindex;
(void) g;
palClearPad(DC_PORT, DC_PIN);
sindex = index;
spiSend(SPI_PORT, 1, &sindex);
}
static void write_data(GDisplay *g, gU8 data) {
static gU8 sdata;
(void) g;
palSetPad(DC_PORT, DC_PIN);
sdata = data;
spiSend(SPI_PORT, 1, &sdata);
}
static void Init9341(GDisplay *g) {
#define REG_TYPEMASK 0xFF00
#define REG_DATAMASK 0x00FF
#define REG_DATA 0x0000
#define REG_COMMAND 0x0100
#define REG_DELAY 0x0200
static const gU16 initdata[] = {
REG_COMMAND | ILI9341_CMD_RESET,
REG_DELAY | 5,
REG_COMMAND | ILI9341_CMD_DISPLAY_OFF,
REG_COMMAND | ILI9341_SET_FRAME_CTL_NORMAL, 0x00, 0x1B,
REG_COMMAND | ILI9341_SET_FUNCTION_CTL, 0x0A, 0xA2,
REG_COMMAND | ILI9341_SET_POWER_CTL_1, 0x10,
REG_COMMAND | ILI9341_SET_POWER_CTL_2, 0x10,
#if 1
REG_COMMAND | ILI9341_SET_VCOM_CTL_1, 0x45, 0x15,
REG_COMMAND | ILI9341_SET_VCOM_CTL_2, 0x90,
#else
REG_COMMAND | ILI9341_SET_VCOM_CTL_1, 0x35, 0x3E,
REG_COMMAND | ILI9341_SET_VCOM_CTL_2, 0xBE,
#endif
REG_COMMAND | ILI9341_SET_MEM_ACS_CTL, 0xC8,
REG_COMMAND | ILI9341_SET_RGB_IF_SIG_CTL, 0xC2,
REG_COMMAND | ILI9341_SET_FUNCTION_CTL, 0x0A, 0xA7, 0x27, 0x04,
REG_COMMAND | ILI9341_SET_COL_ADDR, 0x00, 0x00, 0x00, 0xEF,
REG_COMMAND | ILI9341_SET_PAGE_ADDR, 0x00, 0x00, 0x01, 0x3F,
REG_COMMAND | ILI9341_SET_IF_CTL, 0x01, 0x00, 0x06,
REG_COMMAND | ILI9341_SET_GAMMA, 0x01,
REG_COMMAND | ILI9341_SET_PGAMMA,
#if 1
0x0F, 0x29, 0x24, 0x0C, 0x0E, 0x09, 0x4E, 0x78,
0x3C, 0x09, 0x13, 0x05, 0x17, 0x11, 0x00,
#else
0x1F, 0x1a, 0x18, 0x0a, 0x0f, 0x06, 0x45, 0x87,
0x32, 0x0a, 0x07, 0x02, 0x07, 0x05, 0x00,
#endif
REG_COMMAND | ILI9341_SET_NGAMMA,
#if 1
0x00, 0x16, 0x1B, 0x04, 0x11, 0x07, 0x31, 0x33,
0x42, 0x05, 0x0C, 0x0A, 0x28, 0x2F, 0x0F,
#else
0x00, 0x25, 0x27, 0x05, 0x10, 0x09, 0x3a, 0x78,
0x4d, 0x05, 0x18, 0x0d, 0x38, 0x3a, 0x1f,
#endif
REG_COMMAND | ILI9341_CMD_SLEEP_OFF,
REG_DELAY | 10,
REG_COMMAND | ILI9341_CMD_DISPLAY_ON,
REG_COMMAND | ILI9341_SET_MEM
};
const gU16 *p;
acquire_bus(g);
for(p = initdata; p < &initdata[sizeof(initdata)/sizeof(initdata[0])]; p++) {
switch(*p & REG_TYPEMASK) {
case REG_DATA: write_data(g, *p); break;
case REG_COMMAND: write_index(g, *p); break;
case REG_DELAY: gfxSleepMilliseconds(*p & 0xFF); break;
}
}
release_bus(g);
}
static void init_board(GDisplay *g) {
(void) g;
palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); // UART_TX
palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7)); // UART_RX
palSetPadMode(GPIOF, GPIOF_LCD_DCX, PAL_MODE_ALTERNATE(5));
palSetPadMode(GPIOF, GPIOF_LCD_DE, PAL_MODE_ALTERNATE(14));
#define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */
#define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */
#define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */
#define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */
#define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */
#define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */
#define STM32_PLLSAIN_VALUE 192
#define STM32_PLLSAIQ_VALUE 7
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIR_POST STM32_SAIR_DIV4
/* PLLSAI activation.*/
RCC->PLLSAICFGR = (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24);
RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST;
RCC->CR |= RCC_CR_PLLSAION;
while(!(RCC->CR & RCC_CR_PLLSAIRDY)); // wait for PLLSAI to lock
// Initialise the SDRAM
SDRAM_Init();
// Clear the SDRAM
memset((void *)SDRAM_BANK_ADDR, 0, 0x400000);
spiStart(SPI_PORT, &spi_cfg);
Init9341(g);
}
static GFXINLINE void post_init_board(GDisplay *g) {
(void) g;
}
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
(void) percent;
}
#endif /* _GDISP_LLD_BOARD_H */
/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.io/license.html
*/
#ifndef _GDISP_LLD_BOARD_H
#define _GDISP_LLD_BOARD_H
#include "stm32f4xx_fmc.h"
#include "stm32f429i_discovery_sdram.h"
#include <string.h>
#define SPI_PORT &SPID5
#define DC_PORT GPIOD
#define DC_PIN GPIOD_LCD_WRX
static const SPIConfig spi_cfg = {
NULL,
GPIOC,
GPIOC_SPI5_LCD_CS,
((1 << 3) & SPI_CR1_BR) | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_MSTR
};
static const ltdcConfig driverCfg = {
240, 320,
10, 2,
20, 2,
10, 4,
0,
0x000000,
{
(LLDCOLOR_TYPE *)SDRAM_BANK_ADDR, // frame
240, 320, // width, height
240 * LTDC_PIXELBYTES, // pitch
LTDC_PIXELFORMAT, // fmt
0, 0, // x, y
240, 320, // cx, cy
0x00000000, // defcolor
0x000000, // keycolor
LTDC_BLEND_FIX1_FIX2, // blending
0, // palette
0, // palettelen
0xFF, // alpha
LTDC_LEF_ENABLE // flags
},
#if STM32LTDC_USE_LAYER2 || STM32LTDC_USE_DOUBLEBUFFERING
{ // Foreground layer config (if turned on)
(LLDCOLOR_TYPE *)(SDRAM_BANK_ADDR+(240 * 320 * LTDC_PIXELBYTES)), // Frame buffer address
240, 320, // width, height
240 * LTDC_PIXELBYTES, // pitch
LTDC_PIXELFORMAT, // fmt
0, 0, // x, y
240, 320, // cx, cy
0x00000000, // Default color (ARGB8888)
0x000000, // Color key (RGB888)
LTDC_BLEND_MOD1_MOD2, // Blending factors
0, // Palette (RGB888, can be NULL)
0, // Palette length
0xFF, // Constant alpha factor
LTDC_LEF_ENABLE // Layer configuration flags
}
#else
LTDC_UNUSED_LAYER_CONFIG
#endif
};
#include "ili9341.h"
static void acquire_bus(GDisplay *g) {
(void) g;
spiSelect(SPI_PORT);
}
static void release_bus(GDisplay *g) {
(void) g;
spiUnselect(SPI_PORT);
}
static void write_index(GDisplay *g, gU8 index) {
static gU8 sindex;
(void) g;
palClearPad(DC_PORT, DC_PIN);
sindex = index;
spiSend(SPI_PORT, 1, &sindex);
}
static void write_data(GDisplay *g, gU8 data) {
static gU8 sdata;
(void) g;
palSetPad(DC_PORT, DC_PIN);
sdata = data;
spiSend(SPI_PORT, 1, &sdata);
}
static void Init9341(GDisplay *g) {
#define REG_TYPEMASK 0xFF00
#define REG_DATAMASK 0x00FF
#define REG_DATA 0x0000
#define REG_COMMAND 0x0100
#define REG_DELAY 0x0200
static const gU16 initdata[] = {
REG_COMMAND | ILI9341_CMD_RESET,
REG_DELAY | 5,
REG_COMMAND | ILI9341_CMD_DISPLAY_OFF,
REG_COMMAND | ILI9341_SET_FRAME_CTL_NORMAL, 0x00, 0x1B,
REG_COMMAND | ILI9341_SET_FUNCTION_CTL, 0x0A, 0xA2,
REG_COMMAND | ILI9341_SET_POWER_CTL_1, 0x10,
REG_COMMAND | ILI9341_SET_POWER_CTL_2, 0x10,
#if 1
REG_COMMAND | ILI9341_SET_VCOM_CTL_1, 0x45, 0x15,
REG_COMMAND | ILI9341_SET_VCOM_CTL_2, 0x90,
#else
REG_COMMAND | ILI9341_SET_VCOM_CTL_1, 0x35, 0x3E,
REG_COMMAND | ILI9341_SET_VCOM_CTL_2, 0xBE,
#endif
REG_COMMAND | ILI9341_SET_MEM_ACS_CTL, 0xC8,
REG_COMMAND | ILI9341_SET_RGB_IF_SIG_CTL, 0xC2,
REG_COMMAND | ILI9341_SET_FUNCTION_CTL, 0x0A, 0xA7, 0x27, 0x04,
REG_COMMAND | ILI9341_SET_COL_ADDR, 0x00, 0x00, 0x00, 0xEF,
REG_COMMAND | ILI9341_SET_PAGE_ADDR, 0x00, 0x00, 0x01, 0x3F,
REG_COMMAND | ILI9341_SET_IF_CTL, 0x01, 0x00, 0x06,
REG_COMMAND | ILI9341_SET_GAMMA, 0x01,
REG_COMMAND | ILI9341_SET_PGAMMA,
#if 1
0x0F, 0x29, 0x24, 0x0C, 0x0E, 0x09, 0x4E, 0x78,
0x3C, 0x09, 0x13, 0x05, 0x17, 0x11, 0x00,
#else
0x1F, 0x1a, 0x18, 0x0a, 0x0f, 0x06, 0x45, 0x87,
0x32, 0x0a, 0x07, 0x02, 0x07, 0x05, 0x00,
#endif
REG_COMMAND | ILI9341_SET_NGAMMA,
#if 1
0x00, 0x16, 0x1B, 0x04, 0x11, 0x07, 0x31, 0x33,
0x42, 0x05, 0x0C, 0x0A, 0x28, 0x2F, 0x0F,
#else
0x00, 0x25, 0x27, 0x05, 0x10, 0x09, 0x3a, 0x78,
0x4d, 0x05, 0x18, 0x0d, 0x38, 0x3a, 0x1f,
#endif
REG_COMMAND | ILI9341_CMD_SLEEP_OFF,
REG_DELAY | 10,
REG_COMMAND | ILI9341_CMD_DISPLAY_ON,
REG_COMMAND | ILI9341_SET_MEM
};
const gU16 *p;
acquire_bus(g);
for(p = initdata; p < &initdata[sizeof(initdata)/sizeof(initdata[0])]; p++) {
switch(*p & REG_TYPEMASK) {
case REG_DATA: write_data(g, *p); break;
case REG_COMMAND: write_index(g, *p); break;
case REG_DELAY: gfxSleepMilliseconds(*p & 0xFF); break;
}
}
release_bus(g);
}
static void init_board(GDisplay *g) {
(void) g;
palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(7)); // UART_TX
palSetPadMode(GPIOA, 10, PAL_MODE_ALTERNATE(7)); // UART_RX
palSetPadMode(GPIOF, GPIOF_LCD_DCX, PAL_MODE_ALTERNATE(5));
palSetPadMode(GPIOF, GPIOF_LCD_DE, PAL_MODE_ALTERNATE(14));
#define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */
#define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */
#define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */
#define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */
#define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */
#define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */
#define STM32_PLLSAIN_VALUE 192
#define STM32_PLLSAIQ_VALUE 7
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIR_POST STM32_SAIR_DIV4
/* PLLSAI activation.*/
RCC->PLLSAICFGR = (STM32_PLLSAIN_VALUE << 6) | (STM32_PLLSAIR_VALUE << 28) | (STM32_PLLSAIQ_VALUE << 24);
RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST;
RCC->CR |= RCC_CR_PLLSAION;
while(!(RCC->CR & RCC_CR_PLLSAIRDY)); // wait for PLLSAI to lock
// Initialise the SDRAM
SDRAM_Init();
// Clear the SDRAM
memset((void *)SDRAM_BANK_ADDR, 0, 0x400000);
spiStart(SPI_PORT, &spi_cfg);
Init9341(g);
}
static GFXINLINE void post_init_board(GDisplay *g) {
(void) g;
}
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
(void) percent;
}
#endif /* _GDISP_LLD_BOARD_H */

252
boards/base/STM32F429i-Discovery/chibios/gmouse_lld_STMPE811_board.h
View file

@ -1,126 +1,126 @@
/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.io/license.html
*/
#ifndef _GINPUT_LLD_MOUSE_BOARD_H
#define _GINPUT_LLD_MOUSE_BOARD_H
// Resolution and Accuracy Settings
#define GMOUSE_STMPE811_PEN_CALIBRATE_ERROR 8
#define GMOUSE_STMPE811_PEN_CLICK_ERROR 6
#define GMOUSE_STMPE811_PEN_MOVE_ERROR 4
#define GMOUSE_STMPE811_FINGER_CALIBRATE_ERROR 14
#define GMOUSE_STMPE811_FINGER_CLICK_ERROR 18
#define GMOUSE_STMPE811_FINGER_MOVE_ERROR 14
// How much extra data to allocate at the end of the GMouse structure for the board's use
#define GMOUSE_STMPE811_BOARD_DATA_SIZE 0
// Options - Leave these commented to make it user configurable in the gfxconf.h
//#define GMOUSE_STMPE811_READ_PRESSURE GFXOFF
//#define GMOUSE_STMPE811_SELF_CALIBRATE GFXOFF
//#define GMOUSE_STMPE811_TEST_MODE GFXOFF
// Set to GFXOFF because it does not work properly on this board even though the pin exists.
#define GMOUSE_STMPE811_GPIO_IRQPIN GFXOFF
// If GFXON this is a really slow CPU and we should always clear the FIFO between reads.
#define GMOUSE_STMPE811_SLOW_CPU GFXOFF
// Slave address
#define STMPE811_ADDR 0x41
// Maximum timeout
#define STMPE811_TIMEOUT 0x3000
static const I2CConfig i2ccfg = {
OPMODE_I2C,
400000,
FAST_DUTY_CYCLE_2,
};
static gBool init_board(GMouse* m, unsigned driverinstance) {
(void) m;
// This board only supports one touch panel
if (driverinstance)
return gFalse;
// Set pin modes
#if CH_KERNEL_MAJOR == 2
palSetPadMode(GPIOA, 15, PAL_MODE_INPUT | PAL_STM32_PUDR_FLOATING); /* TP IRQ */
palSetPadMode(GPIOA, 8, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN); /* SCL */
palSetPadMode(GPIOC, 9, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN); /* SDA */
#else
palSetPadMode(GPIOA, 15, PAL_MODE_INPUT | PAL_STM32_PUPDR_FLOATING); /* TP IRQ */
palSetPadMode(GPIOA, 8, PAL_MODE_ALTERNATE(4) | PAL_STM32_PUPDR_FLOATING); /* SCL */
palSetPadMode(GPIOC, 9, PAL_MODE_ALTERNATE(4) | PAL_STM32_PUPDR_FLOATING); /* SDA */
#endif
// Start the I2C
i2cStart(&I2CD3, &i2ccfg);
return gTrue;
}
#if GMOUSE_STMPE811_GPIO_IRQPIN
static gBool getpin_irq(GMouse* m) {
(void) m;
return !palReadPad(GPIOA, 15);
}
#endif
static GFXINLINE void aquire_bus(GMouse* m) {
(void) m;
}
static GFXINLINE void release_bus(GMouse* m) {
(void) m;
}
static void write_reg(GMouse* m, gU8 reg, gU8 val) {
gU8 txbuf[2];
(void) m;
txbuf[0] = reg;
txbuf[1] = val;
i2cAcquireBus(&I2CD3);
i2cMasterTransmitTimeout(&I2CD3, STMPE811_ADDR, txbuf, 2, 0, 0, MS2ST(STMPE811_TIMEOUT));
i2cReleaseBus(&I2CD3);
}
static gU8 read_byte(GMouse* m, gU8 reg) {
gU8 rxbuf[1];
(void) m;
rxbuf[0] = 0;
i2cAcquireBus(&I2CD3);
i2cMasterTransmitTimeout(&I2CD3, STMPE811_ADDR, &reg, 1, rxbuf, 1, MS2ST(STMPE811_TIMEOUT));
i2cReleaseBus(&I2CD3);
return rxbuf[0];
}
static gU16 read_word(GMouse* m, gU8 reg) {
gU8 rxbuf[2];
(void) m;
rxbuf[0] = 0;
rxbuf[1] = 0;
i2cAcquireBus(&I2CD3);
i2cMasterTransmitTimeout(&I2CD3, STMPE811_ADDR, &reg, 1, rxbuf, 2, MS2ST(STMPE811_TIMEOUT));
i2cReleaseBus(&I2CD3);
return (((gU16)rxbuf[0]) << 8) | rxbuf[1];
}
#endif /* _GINPUT_LLD_MOUSE_BOARD_H */
/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.io/license.html
*/
#ifndef _GINPUT_LLD_MOUSE_BOARD_H
#define _GINPUT_LLD_MOUSE_BOARD_H
// Resolution and Accuracy Settings
#define GMOUSE_STMPE811_PEN_CALIBRATE_ERROR 8
#define GMOUSE_STMPE811_PEN_CLICK_ERROR 6
#define GMOUSE_STMPE811_PEN_MOVE_ERROR 4
#define GMOUSE_STMPE811_FINGER_CALIBRATE_ERROR 14
#define GMOUSE_STMPE811_FINGER_CLICK_ERROR 18
#define GMOUSE_STMPE811_FINGER_MOVE_ERROR 14
// How much extra data to allocate at the end of the GMouse structure for the board's use
#define GMOUSE_STMPE811_BOARD_DATA_SIZE 0
// Options - Leave these commented to make it user configurable in the gfxconf.h
//#define GMOUSE_STMPE811_READ_PRESSURE GFXOFF
//#define GMOUSE_STMPE811_SELF_CALIBRATE GFXOFF
//#define GMOUSE_STMPE811_TEST_MODE GFXOFF
// Set to GFXOFF because it does not work properly on this board even though the pin exists.
#define GMOUSE_STMPE811_GPIO_IRQPIN GFXOFF
// If GFXON this is a really slow CPU and we should always clear the FIFO between reads.
#define GMOUSE_STMPE811_SLOW_CPU GFXOFF
// Slave address
#define STMPE811_ADDR 0x41
// Maximum timeout
#define STMPE811_TIMEOUT 0x3000
static const I2CConfig i2ccfg = {
OPMODE_I2C,
400000,
FAST_DUTY_CYCLE_2,
};
static gBool init_board(GMouse* m, unsigned driverinstance) {
(void) m;
// This board only supports one touch panel
if (driverinstance)
return gFalse;
// Set pin modes
#if CH_KERNEL_MAJOR == 2
palSetPadMode(GPIOA, 15, PAL_MODE_INPUT | PAL_STM32_PUDR_FLOATING); /* TP IRQ */
palSetPadMode(GPIOA, 8, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN); /* SCL */
palSetPadMode(GPIOC, 9, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN); /* SDA */
#else
palSetPadMode(GPIOA, 15, PAL_MODE_INPUT | PAL_STM32_PUPDR_FLOATING); /* TP IRQ */
palSetPadMode(GPIOA, 8, PAL_MODE_ALTERNATE(4) | PAL_STM32_PUPDR_FLOATING); /* SCL */
palSetPadMode(GPIOC, 9, PAL_MODE_ALTERNATE(4) | PAL_STM32_PUPDR_FLOATING); /* SDA */
#endif
// Start the I2C
i2cStart(&I2CD3, &i2ccfg);
return gTrue;
}
#if GMOUSE_STMPE811_GPIO_IRQPIN
static gBool getpin_irq(GMouse* m) {
(void) m;
return !palReadPad(GPIOA, 15);
}
#endif
static GFXINLINE void aquire_bus(GMouse* m) {
(void) m;
}
static GFXINLINE void release_bus(GMouse* m) {
(void) m;
}
static void write_reg(GMouse* m, gU8 reg, gU8 val) {
gU8 txbuf[2];
(void) m;
txbuf[0] = reg;
txbuf[1] = val;
i2cAcquireBus(&I2CD3);
i2cMasterTransmitTimeout(&I2CD3, STMPE811_ADDR, txbuf, 2, 0, 0, MS2ST(STMPE811_TIMEOUT));
i2cReleaseBus(&I2CD3);
}
static gU8 read_byte(GMouse* m, gU8 reg) {
gU8 rxbuf[1];
(void) m;
rxbuf[0] = 0;
i2cAcquireBus(&I2CD3);
i2cMasterTransmitTimeout(&I2CD3, STMPE811_ADDR, &reg, 1, rxbuf, 1, MS2ST(STMPE811_TIMEOUT));
i2cReleaseBus(&I2CD3);
return rxbuf[0];
}
static gU16 read_word(GMouse* m, gU8 reg) {
gU8 rxbuf[2];
(void) m;
rxbuf[0] = 0;
rxbuf[1] = 0;
i2cAcquireBus(&I2CD3);
i2cMasterTransmitTimeout(&I2CD3, STMPE811_ADDR, &reg, 1, rxbuf, 2, MS2ST(STMPE811_TIMEOUT));
i2cReleaseBus(&I2CD3);
return (((gU16)rxbuf[0]) << 8) | rxbuf[1];
}
#endif /* _GINPUT_LLD_MOUSE_BOARD_H */

2760
boards/base/STM32F429i-Discovery/chibios/stm32f4xx_fmc.c
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File diff suppressed because it is too large Load diff

220
boards/base/STM32F469i-Discovery/CubeHAL/gmouse_lld_FT6x06_board.h
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@ -1,110 +1,110 @@
/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.io/license.html
*/
#ifndef _GINPUT_LLD_MOUSE_BOARD_H
#define _GINPUT_LLD_MOUSE_BOARD_H
#include "ft6x06.h"
#include "stm32f4xx.h"
#include "stm32f4xx_hal.h"
// Resolution and Accuracy Settings
#define GMOUSE_FT6x06_PEN_CALIBRATE_ERROR 40
#define GMOUSE_FT6x06_PEN_CLICK_ERROR 16
#define GMOUSE_FT6x06_PEN_MOVE_ERROR 14
#define GMOUSE_FT6x06_FINGER_CALIBRATE_ERROR 50
#define GMOUSE_FT6x06_FINGER_CLICK_ERROR 28
#define GMOUSE_FT6x06_FINGER_MOVE_ERROR 24
// How much extra data to allocate at the end of the GMouse structure for the board's use
#define GMOUSE_FT6x06_BOARD_DATA_SIZE 0
/* The FT6x06 I2C slave address */
#define FT6x06_SLAVE_ADDR 0x54
I2C_HandleTypeDef i2cHandle;
/* Maximum speed (400kHz) */
#define CLOCKSPEED 400000;
static gBool init_board(GMouse* m, unsigned instance) {
(void)m;
(void)instance;
GPIO_InitTypeDef gpioInit;
/* I2C1_SCL PB8 */
__HAL_RCC_GPIOB_CLK_ENABLE(); // Enable GPIOB clock
gpioInit.Pin = GPIO_PIN_8;
gpioInit.Mode = GPIO_MODE_AF_OD; // I2C -> Open-drain
gpioInit.Pull = GPIO_NOPULL; // Open-drain -> no pull
gpioInit.Speed = GPIO_SPEED_FREQ_HIGH; // High speed
gpioInit.Alternate = GPIO_AF4_I2C1; // Alternate function 4
HAL_GPIO_Init(GPIOB, &gpioInit);
/* I2C1_SDA PB9 */
gpioInit.Pin = GPIO_PIN_9;
HAL_GPIO_Init(GPIOB, &gpioInit);
/* LCD_INT PJ5 */
__HAL_RCC_GPIOJ_CLK_ENABLE();
gpioInit.Pin = GPIO_PIN_5;
gpioInit.Mode = GPIO_MODE_INPUT; // Input mode
gpioInit.Pull = GPIO_PULLUP; // Pull-up
HAL_GPIO_Init(GPIOJ, &gpioInit);
/* I2C1 intialization */
i2cHandle.Instance = I2C1;
i2cHandle.Init.ClockSpeed = CLOCKSPEED;
i2cHandle.Init.DutyCycle = I2C_DUTYCYCLE_2; // Normal duty cycle
i2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; // No dual adressing needed
i2cHandle.Init.OwnAddress1 = 0x00;
i2cHandle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
i2cHandle.Init.OwnAddress2 = 0x00;
i2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; // All not needed so disabled
i2cHandle.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
__HAL_RCC_I2C1_CLK_ENABLE();
if(HAL_I2C_Init(&i2cHandle) == HAL_OK)
return gTrue;
return gFalse;
}
static GFXINLINE void aquire_bus(GMouse* m) {
(void)m;
}
static GFXINLINE void release_bus(GMouse* m) {
(void)m;
}
static void write_reg(GMouse* m, gU8 reg, gU8 val) {
(void)m;
HAL_I2C_Mem_Write(&i2cHandle, FT6x06_SLAVE_ADDR, (gU16)reg, I2C_MEMADD_SIZE_8BIT, &val, 1, 1000);
}
static gU8 read_byte(GMouse* m, gU8 reg) {
(void)m;
gU8 result;
HAL_I2C_Mem_Read(&i2cHandle, FT6x06_SLAVE_ADDR, (gU16)reg, I2C_MEMADD_SIZE_8BIT, &result, 1, 1000);
return result;
}
static gU16 read_word(GMouse* m, gU8 reg) {
(void)m;
gU8 result[2];
HAL_I2C_Mem_Read(&i2cHandle, FT6x06_SLAVE_ADDR, (gU16)reg, I2C_MEMADD_SIZE_8BIT, result, 2, 1000);
return (result[0]<<8 | result[1]);
}
#endif /* _GINPUT_LLD_MOUSE_BOARD_H */
/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.io/license.html
*/
#ifndef _GINPUT_LLD_MOUSE_BOARD_H
#define _GINPUT_LLD_MOUSE_BOARD_H
#include "ft6x06.h"
#include "stm32f4xx.h"
#include "stm32f4xx_hal.h"
// Resolution and Accuracy Settings
#define GMOUSE_FT6x06_PEN_CALIBRATE_ERROR 40
#define GMOUSE_FT6x06_PEN_CLICK_ERROR 16
#define GMOUSE_FT6x06_PEN_MOVE_ERROR 14
#define GMOUSE_FT6x06_FINGER_CALIBRATE_ERROR 50
#define GMOUSE_FT6x06_FINGER_CLICK_ERROR 28
#define GMOUSE_FT6x06_FINGER_MOVE_ERROR 24
// How much extra data to allocate at the end of the GMouse structure for the board's use
#define GMOUSE_FT6x06_BOARD_DATA_SIZE 0
/* The FT6x06 I2C slave address */
#define FT6x06_SLAVE_ADDR 0x54
I2C_HandleTypeDef i2cHandle;
/* Maximum speed (400kHz) */
#define CLOCKSPEED 400000;
static gBool init_board(GMouse* m, unsigned instance) {
(void)m;
(void)instance;
GPIO_InitTypeDef gpioInit;
/* I2C1_SCL PB8 */
__HAL_RCC_GPIOB_CLK_ENABLE(); // Enable GPIOB clock
gpioInit.Pin = GPIO_PIN_8;
gpioInit.Mode = GPIO_MODE_AF_OD; // I2C -> Open-drain
gpioInit.Pull = GPIO_NOPULL; // Open-drain -> no pull
gpioInit.Speed = GPIO_SPEED_FREQ_HIGH; // High speed
gpioInit.Alternate = GPIO_AF4_I2C1; // Alternate function 4
HAL_GPIO_Init(GPIOB, &gpioInit);
/* I2C1_SDA PB9 */
gpioInit.Pin = GPIO_PIN_9;
HAL_GPIO_Init(GPIOB, &gpioInit);
/* LCD_INT PJ5 */
__HAL_RCC_GPIOJ_CLK_ENABLE();
gpioInit.Pin = GPIO_PIN_5;
gpioInit.Mode = GPIO_MODE_INPUT; // Input mode
gpioInit.Pull = GPIO_PULLUP; // Pull-up
HAL_GPIO_Init(GPIOJ, &gpioInit);
/* I2C1 intialization */
i2cHandle.Instance = I2C1;
i2cHandle.Init.ClockSpeed = CLOCKSPEED;
i2cHandle.Init.DutyCycle = I2C_DUTYCYCLE_2; // Normal duty cycle
i2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; // No dual adressing needed
i2cHandle.Init.OwnAddress1 = 0x00;
i2cHandle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
i2cHandle.Init.OwnAddress2 = 0x00;
i2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; // All not needed so disabled
i2cHandle.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
__HAL_RCC_I2C1_CLK_ENABLE();
if(HAL_I2C_Init(&i2cHandle) == HAL_OK)
return gTrue;
return gFalse;
}
static GFXINLINE void aquire_bus(GMouse* m) {
(void)m;
}
static GFXINLINE void release_bus(GMouse* m) {
(void)m;
}
static void write_reg(GMouse* m, gU8 reg, gU8 val) {
(void)m;
HAL_I2C_Mem_Write(&i2cHandle, FT6x06_SLAVE_ADDR, (gU16)reg, I2C_MEMADD_SIZE_8BIT, &val, 1, 1000);
}
static gU8 read_byte(GMouse* m, gU8 reg) {
(void)m;
gU8 result;
HAL_I2C_Mem_Read(&i2cHandle, FT6x06_SLAVE_ADDR, (gU16)reg, I2C_MEMADD_SIZE_8BIT, &result, 1, 1000);
return result;
}
static gU16 read_word(GMouse* m, gU8 reg) {
(void)m;
gU8 result[2];
HAL_I2C_Mem_Read(&i2cHandle, FT6x06_SLAVE_ADDR, (gU16)reg, I2C_MEMADD_SIZE_8BIT, result, 2, 1000);
return (result[0]<<8 | result[1]);
}
#endif /* _GINPUT_LLD_MOUSE_BOARD_H */

908
boards/base/STM32F469i-Discovery/otm8009a.c
View file

@ -1,454 +1,454 @@
/**
******************************************************************************
* @file otm8009a.c
* @author MCD Application Team
* @version V1.0.2
* @date 27-January-2017
* @brief This file provides the LCD Driver for KoD KM-040TMP-02-0621 (WVGA)
* DSI LCD Display OTM8009A.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "otm8009a.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @defgroup OTM8009A OTM8009A
* @brief This file provides a set of functions needed to drive the
* otm8009a IC display driver.
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup OTM8009A_Private_Constants OTM8009A Private Constants
* @{
*/
/*
* @brief Constant tables of register settings used to transmit DSI
* command packets as power up initialization sequence of the KoD LCD (OTM8009A LCD Driver)
*/
const gU8 lcdRegData1[] = {0x80,0x09,0x01,0xFF};
const gU8 lcdRegData2[] = {0x80,0x09,0xFF};
const gU8 lcdRegData3[] = {0x00,0x09,0x0F,0x0E,0x07,0x10,0x0B,0x0A,0x04,0x07,0x0B,0x08,0x0F,0x10,0x0A,0x01,0xE1};
const gU8 lcdRegData4[] = {0x00,0x09,0x0F,0x0E,0x07,0x10,0x0B,0x0A,0x04,0x07,0x0B,0x08,0x0F,0x10,0x0A,0x01,0xE2};
const gU8 lcdRegData5[] = {0x79,0x79,0xD8};
const gU8 lcdRegData6[] = {0x00,0x01,0xB3};
const gU8 lcdRegData7[] = {0x85,0x01,0x00,0x84,0x01,0x00,0xCE};
const gU8 lcdRegData8[] = {0x18,0x04,0x03,0x39,0x00,0x00,0x00,0x18,0x03,0x03,0x3A,0x00,0x00,0x00,0xCE};
const gU8 lcdRegData9[] = {0x18,0x02,0x03,0x3B,0x00,0x00,0x00,0x18,0x01,0x03,0x3C,0x00,0x00,0x00,0xCE};
const gU8 lcdRegData10[] = {0x01,0x01,0x20,0x20,0x00,0x00,0x01,0x02,0x00,0x00,0xCF};
const gU8 lcdRegData11[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const gU8 lcdRegData12[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const gU8 lcdRegData13[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const gU8 lcdRegData14[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const gU8 lcdRegData15[] = {0x00,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const gU8 lcdRegData16[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00,0xCB};
const gU8 lcdRegData17[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const gU8 lcdRegData18[] = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xCB};
const gU8 lcdRegData19[] = {0x00,0x26,0x09,0x0B,0x01,0x25,0x00,0x00,0x00,0x00,0xCC};
const gU8 lcdRegData20[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x26,0x0A,0x0C,0x02,0xCC};
const gU8 lcdRegData21[] = {0x25,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCC};
const gU8 lcdRegData22[] = {0x00,0x25,0x0C,0x0A,0x02,0x26,0x00,0x00,0x00,0x00,0xCC};
const gU8 lcdRegData23[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x25,0x0B,0x09,0x01,0xCC};
const gU8 lcdRegData24[] = {0x26,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCC};
const gU8 lcdRegData25[] = {0xFF,0xFF,0xFF,0xFF};
/*
* CASET value (Column Address Set) : X direction LCD GRAM boundaries
* depending on LCD orientation mode and PASET value (Page Address Set) : Y direction
* LCD GRAM boundaries depending on LCD orientation mode
* XS[15:0] = 0x000 = 0, XE[15:0] = 0x31F = 799 for landscape mode : apply to CASET
* YS[15:0] = 0x000 = 0, YE[15:0] = 0x31F = 799 for portrait mode : : apply to PASET
*/
const gU8 lcdRegData27[] = {0x00, 0x00, 0x03, 0x1F, OTM8009A_CMD_CASET};
/*
* XS[15:0] = 0x000 = 0, XE[15:0] = 0x1DF = 479 for portrait mode : apply to CASET
* YS[15:0] = 0x000 = 0, YE[15:0] = 0x1DF = 479 for landscape mode : apply to PASET
*/
const gU8 lcdRegData28[] = {0x00, 0x00, 0x01, 0xDF, OTM8009A_CMD_PASET};
const gU8 ShortRegData1[] = {OTM8009A_CMD_NOP, 0x00};
const gU8 ShortRegData2[] = {OTM8009A_CMD_NOP, 0x80};
const gU8 ShortRegData3[] = {0xC4, 0x30};
const gU8 ShortRegData4[] = {OTM8009A_CMD_NOP, 0x8A};
const gU8 ShortRegData5[] = {0xC4, 0x40};
const gU8 ShortRegData6[] = {OTM8009A_CMD_NOP, 0xB1};
const gU8 ShortRegData7[] = {0xC5, 0xA9};
const gU8 ShortRegData8[] = {OTM8009A_CMD_NOP, 0x91};
const gU8 ShortRegData9[] = {0xC5, 0x34};
const gU8 ShortRegData10[] = {OTM8009A_CMD_NOP, 0xB4};
const gU8 ShortRegData11[] = {0xC0, 0x50};
const gU8 ShortRegData12[] = {0xD9, 0x4E};
const gU8 ShortRegData13[] = {OTM8009A_CMD_NOP, 0x81};
const gU8 ShortRegData14[] = {0xC1, 0x66};
const gU8 ShortRegData15[] = {OTM8009A_CMD_NOP, 0xA1};
const gU8 ShortRegData16[] = {0xC1, 0x08};
const gU8 ShortRegData17[] = {OTM8009A_CMD_NOP, 0x92};
const gU8 ShortRegData18[] = {0xC5, 0x01};
const gU8 ShortRegData19[] = {OTM8009A_CMD_NOP, 0x95};
const gU8 ShortRegData20[] = {OTM8009A_CMD_NOP, 0x94};
const gU8 ShortRegData21[] = {0xC5, 0x33};
const gU8 ShortRegData22[] = {OTM8009A_CMD_NOP, 0xA3};
const gU8 ShortRegData23[] = {0xC0, 0x1B};
const gU8 ShortRegData24[] = {OTM8009A_CMD_NOP, 0x82};
const gU8 ShortRegData25[] = {0xC5, 0x83};
const gU8 ShortRegData26[] = {0xC4, 0x83};
const gU8 ShortRegData27[] = {0xC1, 0x0E};
const gU8 ShortRegData28[] = {OTM8009A_CMD_NOP, 0xA6};
const gU8 ShortRegData29[] = {OTM8009A_CMD_NOP, 0xA0};
const gU8 ShortRegData30[] = {OTM8009A_CMD_NOP, 0xB0};
const gU8 ShortRegData31[] = {OTM8009A_CMD_NOP, 0xC0};
const gU8 ShortRegData32[] = {OTM8009A_CMD_NOP, 0xD0};
const gU8 ShortRegData33[] = {OTM8009A_CMD_NOP, 0x90};
const gU8 ShortRegData34[] = {OTM8009A_CMD_NOP, 0xE0};
const gU8 ShortRegData35[] = {OTM8009A_CMD_NOP, 0xF0};
const gU8 ShortRegData36[] = {OTM8009A_CMD_SLPOUT, 0x00};
const gU8 ShortRegData37[] = {OTM8009A_CMD_COLMOD, OTM8009A_COLMOD_RGB565};
const gU8 ShortRegData38[] = {OTM8009A_CMD_COLMOD, OTM8009A_COLMOD_RGB888};
const gU8 ShortRegData39[] = {OTM8009A_CMD_MADCTR, OTM8009A_MADCTR_MODE_LANDSCAPE};
const gU8 ShortRegData40[] = {OTM8009A_CMD_WRDISBV, 0x7F};
const gU8 ShortRegData41[] = {OTM8009A_CMD_WRCTRLD, 0x2C};
const gU8 ShortRegData42[] = {OTM8009A_CMD_WRCABC, 0x02};
const gU8 ShortRegData43[] = {OTM8009A_CMD_WRCABCMB, 0xFF};
const gU8 ShortRegData44[] = {OTM8009A_CMD_DISPON, 0x00};
const gU8 ShortRegData45[] = {OTM8009A_CMD_RAMWR, 0x00};
const gU8 ShortRegData46[] = {0xCF, 0x00};
const gU8 ShortRegData47[] = {0xC5, 0x66};
const gU8 ShortRegData48[] = {OTM8009A_CMD_NOP, 0xB6};
const gU8 ShortRegData49[] = {0xF5, 0x06};
const gU8 ShortRegData50[] = {OTM8009A_CMD_NOP, 0xB1};
const gU8 ShortRegData51[] = {0xC6, 0x06};
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup OTM8009A_Exported_Variables
* @{
*/
/**
* @}
*/
/* Exported functions ---------------------------------------------------------*/
/** @defgroup OTM8009A_Exported_Functions OTM8009A Exported Functions
* @{
*/
/**
* @brief DSI IO write short/long command.
* @note : Can be surcharged by application code implementation of the function.
*/
__weak void DSI_IO_WriteCmd(gU32 NbrParams, gU8 *pParams)
{
/* NOTE : This function Should not be modified, when it is needed,
the DSI_IO_WriteCmd could be implemented in the user file
*/
}
/**
* @brief Initializes the LCD KoD display part by communication in DSI mode in Video Mode
* with IC Display Driver OTM8009A (see IC Driver specification for more information).
* @param hdsi_eval : pointer on DSI configuration structure
* @param hdsivideo_handle : pointer on DSI video mode configuration structure
* @retval Status
*/
gU8 OTM8009A_Init(gU32 ColorCoding, gU32 orientation)
{
/* Enable CMD2 to access vendor specific commands */
/* Enter in command 2 mode and set EXTC to enable address shift function (0x00) */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
DSI_IO_WriteCmd( 3, (gU8 *)lcdRegData1);
/* Enter ORISE Command 2 */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2); /* Shift address to 0x80 */
DSI_IO_WriteCmd( 2, (gU8 *)lcdRegData2);
/////////////////////////////////////////////////////////////////////
/* SD_PCH_CTRL - 0xC480h - 129th parameter - Default 0x00 */
/* Set SD_PT */
/* -> Source output level during porch and non-display area to GND */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData3);
OTM8009A_IO_Delay(10);
/* Not documented */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData4);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData5);
OTM8009A_IO_Delay(10);
/////////////////////////////////////////////////////////////////////
/* PWR_CTRL4 - 0xC4B0h - 178th parameter - Default 0xA8 */
/* Set gvdd_en_test */
/* -> enable GVDD test mode !!! */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData6);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData7);
/* PWR_CTRL2 - 0xC590h - 146th parameter - Default 0x79 */
/* Set pump 4 vgh voltage */
/* -> from 15.0v down to 13.0v */
/* Set pump 5 vgh voltage */
/* -> from -12.0v downto -9.0v */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData8);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData9);
/* P_DRV_M - 0xC0B4h - 181th parameter - Default 0x00 */
/* -> Column inversion */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData10);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData11);
/* VCOMDC - 0xD900h - 1st parameter - Default 0x39h */
/* VCOM Voltage settings */
/* -> from -1.0000v downto -1.2625v */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData12);
/* Oscillator adjustment for Idle/Normal mode (LPDT only) set to 65Hz (default is 60Hz) */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData13);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData14);
/* Video mode internal */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData15);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData16);
/* PWR_CTRL2 - 0xC590h - 147h parameter - Default 0x00 */
/* Set pump 4&5 x6 */
/* -> ONLY VALID when PUMP4_EN_ASDM_HV = "0" */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData17);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData18);
/* PWR_CTRL2 - 0xC590h - 150th parameter - Default 0x33h */
/* Change pump4 clock ratio */
/* -> from 1 line to 1/2 line */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData19);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData9);
/* GVDD/NGVDD settings */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
DSI_IO_WriteCmd( 2, (gU8 *)lcdRegData5);
/* PWR_CTRL2 - 0xC590h - 149th parameter - Default 0x33h */
/* Rewrite the default value ! */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData20);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData21);
/* Panel display timing Setting 3 */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData22);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData23);
/* Power control 1 */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData24);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData25);
/* Source driver precharge */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData13);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData26);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData15);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData27);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData28);
DSI_IO_WriteCmd( 2, (gU8 *)lcdRegData6);
/* GOAVST */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
DSI_IO_WriteCmd( 6, (gU8 *)lcdRegData7);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData29);
DSI_IO_WriteCmd( 14, (gU8 *)lcdRegData8);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData30);
DSI_IO_WriteCmd( 14, (gU8 *)lcdRegData9);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData31);
DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData10);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData32);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData46);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData11);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData33);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData12);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData29);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData13);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData30);
DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData14);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData31);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData15);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData32);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData16);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData34);
DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData17);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData35);
DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData18);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData19);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData33);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData20);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData29);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData21);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData30);
DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData22);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData31);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData23);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData32);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData24);
/////////////////////////////////////////////////////////////////////////////
/* PWR_CTRL1 - 0xc580h - 130th parameter - default 0x00 */
/* Pump 1 min and max DM */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData13);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData47);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData48);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData49);
/////////////////////////////////////////////////////////////////////////////
/* CABC LEDPWM frequency adjusted to 19,5kHz */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData50);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData51);
/* Exit CMD2 mode */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
DSI_IO_WriteCmd( 3, (gU8 *)lcdRegData25);
/*************************************************************************** */
/* Standard DCS Initialization TO KEEP CAN BE DONE IN HSDT */
/*************************************************************************** */
/* NOP - goes back to DCS std command ? */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
/* Gamma correction 2.2+ table (HSDT possible) */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
DSI_IO_WriteCmd( 16, (gU8 *)lcdRegData3);
/* Gamma correction 2.2- table (HSDT possible) */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
DSI_IO_WriteCmd( 16, (gU8 *)lcdRegData4);
/* Send Sleep Out command to display : no parameter */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData36);
/* Wait for sleep out exit */
OTM8009A_IO_Delay(120);
switch(ColorCoding)
{
case OTM8009A_FORMAT_RBG565 :
/* Set Pixel color format to RGB565 */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData37);
break;
case OTM8009A_FORMAT_RGB888 :
/* Set Pixel color format to RGB888 */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData38);
break;
default :
break;
}
/* Send command to configure display in landscape orientation mode. By default
the orientation mode is portrait */
if(orientation == OTM8009A_ORIENTATION_LANDSCAPE)
{
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData39);
DSI_IO_WriteCmd( 4, (gU8 *)lcdRegData27);
DSI_IO_WriteCmd( 4, (gU8 *)lcdRegData28);
}
/** CABC : Content Adaptive Backlight Control section start >> */
/* Note : defaut is 0 (lowest Brightness), 0xFF is highest Brightness, try 0x7F : intermediate value */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData40);
/* defaut is 0, try 0x2C - Brightness Control Block, Display Dimming & BackLight on */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData41);
/* defaut is 0, try 0x02 - image Content based Adaptive Brightness [Still Picture] */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData42);
/* defaut is 0 (lowest Brightness), 0xFF is highest Brightness */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData43);
/** CABC : Content Adaptive Backlight Control section end << */
/* Send Command Display On */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData44);
/* NOP command */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
/* Send Command GRAM memory write (no parameters) : this initiates frame write via other DSI commands sent by */
/* DSI host from LTDC incoming pixels in video mode */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData45);
return 0;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file otm8009a.c
* @author MCD Application Team
* @version V1.0.2
* @date 27-January-2017
* @brief This file provides the LCD Driver for KoD KM-040TMP-02-0621 (WVGA)
* DSI LCD Display OTM8009A.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "otm8009a.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @defgroup OTM8009A OTM8009A
* @brief This file provides a set of functions needed to drive the
* otm8009a IC display driver.
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup OTM8009A_Private_Constants OTM8009A Private Constants
* @{
*/
/*
* @brief Constant tables of register settings used to transmit DSI
* command packets as power up initialization sequence of the KoD LCD (OTM8009A LCD Driver)
*/
const gU8 lcdRegData1[] = {0x80,0x09,0x01,0xFF};
const gU8 lcdRegData2[] = {0x80,0x09,0xFF};
const gU8 lcdRegData3[] = {0x00,0x09,0x0F,0x0E,0x07,0x10,0x0B,0x0A,0x04,0x07,0x0B,0x08,0x0F,0x10,0x0A,0x01,0xE1};
const gU8 lcdRegData4[] = {0x00,0x09,0x0F,0x0E,0x07,0x10,0x0B,0x0A,0x04,0x07,0x0B,0x08,0x0F,0x10,0x0A,0x01,0xE2};
const gU8 lcdRegData5[] = {0x79,0x79,0xD8};
const gU8 lcdRegData6[] = {0x00,0x01,0xB3};
const gU8 lcdRegData7[] = {0x85,0x01,0x00,0x84,0x01,0x00,0xCE};
const gU8 lcdRegData8[] = {0x18,0x04,0x03,0x39,0x00,0x00,0x00,0x18,0x03,0x03,0x3A,0x00,0x00,0x00,0xCE};
const gU8 lcdRegData9[] = {0x18,0x02,0x03,0x3B,0x00,0x00,0x00,0x18,0x01,0x03,0x3C,0x00,0x00,0x00,0xCE};
const gU8 lcdRegData10[] = {0x01,0x01,0x20,0x20,0x00,0x00,0x01,0x02,0x00,0x00,0xCF};
const gU8 lcdRegData11[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const gU8 lcdRegData12[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const gU8 lcdRegData13[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const gU8 lcdRegData14[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const gU8 lcdRegData15[] = {0x00,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const gU8 lcdRegData16[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x00,0x00,0xCB};
const gU8 lcdRegData17[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCB};
const gU8 lcdRegData18[] = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xCB};
const gU8 lcdRegData19[] = {0x00,0x26,0x09,0x0B,0x01,0x25,0x00,0x00,0x00,0x00,0xCC};
const gU8 lcdRegData20[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x26,0x0A,0x0C,0x02,0xCC};
const gU8 lcdRegData21[] = {0x25,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCC};
const gU8 lcdRegData22[] = {0x00,0x25,0x0C,0x0A,0x02,0x26,0x00,0x00,0x00,0x00,0xCC};
const gU8 lcdRegData23[] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x25,0x0B,0x09,0x01,0xCC};
const gU8 lcdRegData24[] = {0x26,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xCC};
const gU8 lcdRegData25[] = {0xFF,0xFF,0xFF,0xFF};
/*
* CASET value (Column Address Set) : X direction LCD GRAM boundaries
* depending on LCD orientation mode and PASET value (Page Address Set) : Y direction
* LCD GRAM boundaries depending on LCD orientation mode
* XS[15:0] = 0x000 = 0, XE[15:0] = 0x31F = 799 for landscape mode : apply to CASET
* YS[15:0] = 0x000 = 0, YE[15:0] = 0x31F = 799 for portrait mode : : apply to PASET
*/
const gU8 lcdRegData27[] = {0x00, 0x00, 0x03, 0x1F, OTM8009A_CMD_CASET};
/*
* XS[15:0] = 0x000 = 0, XE[15:0] = 0x1DF = 479 for portrait mode : apply to CASET
* YS[15:0] = 0x000 = 0, YE[15:0] = 0x1DF = 479 for landscape mode : apply to PASET
*/
const gU8 lcdRegData28[] = {0x00, 0x00, 0x01, 0xDF, OTM8009A_CMD_PASET};
const gU8 ShortRegData1[] = {OTM8009A_CMD_NOP, 0x00};
const gU8 ShortRegData2[] = {OTM8009A_CMD_NOP, 0x80};
const gU8 ShortRegData3[] = {0xC4, 0x30};
const gU8 ShortRegData4[] = {OTM8009A_CMD_NOP, 0x8A};
const gU8 ShortRegData5[] = {0xC4, 0x40};
const gU8 ShortRegData6[] = {OTM8009A_CMD_NOP, 0xB1};
const gU8 ShortRegData7[] = {0xC5, 0xA9};
const gU8 ShortRegData8[] = {OTM8009A_CMD_NOP, 0x91};
const gU8 ShortRegData9[] = {0xC5, 0x34};
const gU8 ShortRegData10[] = {OTM8009A_CMD_NOP, 0xB4};
const gU8 ShortRegData11[] = {0xC0, 0x50};
const gU8 ShortRegData12[] = {0xD9, 0x4E};
const gU8 ShortRegData13[] = {OTM8009A_CMD_NOP, 0x81};
const gU8 ShortRegData14[] = {0xC1, 0x66};
const gU8 ShortRegData15[] = {OTM8009A_CMD_NOP, 0xA1};
const gU8 ShortRegData16[] = {0xC1, 0x08};
const gU8 ShortRegData17[] = {OTM8009A_CMD_NOP, 0x92};
const gU8 ShortRegData18[] = {0xC5, 0x01};
const gU8 ShortRegData19[] = {OTM8009A_CMD_NOP, 0x95};
const gU8 ShortRegData20[] = {OTM8009A_CMD_NOP, 0x94};
const gU8 ShortRegData21[] = {0xC5, 0x33};
const gU8 ShortRegData22[] = {OTM8009A_CMD_NOP, 0xA3};
const gU8 ShortRegData23[] = {0xC0, 0x1B};
const gU8 ShortRegData24[] = {OTM8009A_CMD_NOP, 0x82};
const gU8 ShortRegData25[] = {0xC5, 0x83};
const gU8 ShortRegData26[] = {0xC4, 0x83};
const gU8 ShortRegData27[] = {0xC1, 0x0E};
const gU8 ShortRegData28[] = {OTM8009A_CMD_NOP, 0xA6};
const gU8 ShortRegData29[] = {OTM8009A_CMD_NOP, 0xA0};
const gU8 ShortRegData30[] = {OTM8009A_CMD_NOP, 0xB0};
const gU8 ShortRegData31[] = {OTM8009A_CMD_NOP, 0xC0};
const gU8 ShortRegData32[] = {OTM8009A_CMD_NOP, 0xD0};
const gU8 ShortRegData33[] = {OTM8009A_CMD_NOP, 0x90};
const gU8 ShortRegData34[] = {OTM8009A_CMD_NOP, 0xE0};
const gU8 ShortRegData35[] = {OTM8009A_CMD_NOP, 0xF0};
const gU8 ShortRegData36[] = {OTM8009A_CMD_SLPOUT, 0x00};
const gU8 ShortRegData37[] = {OTM8009A_CMD_COLMOD, OTM8009A_COLMOD_RGB565};
const gU8 ShortRegData38[] = {OTM8009A_CMD_COLMOD, OTM8009A_COLMOD_RGB888};
const gU8 ShortRegData39[] = {OTM8009A_CMD_MADCTR, OTM8009A_MADCTR_MODE_LANDSCAPE};
const gU8 ShortRegData40[] = {OTM8009A_CMD_WRDISBV, 0x7F};
const gU8 ShortRegData41[] = {OTM8009A_CMD_WRCTRLD, 0x2C};
const gU8 ShortRegData42[] = {OTM8009A_CMD_WRCABC, 0x02};
const gU8 ShortRegData43[] = {OTM8009A_CMD_WRCABCMB, 0xFF};
const gU8 ShortRegData44[] = {OTM8009A_CMD_DISPON, 0x00};
const gU8 ShortRegData45[] = {OTM8009A_CMD_RAMWR, 0x00};
const gU8 ShortRegData46[] = {0xCF, 0x00};
const gU8 ShortRegData47[] = {0xC5, 0x66};
const gU8 ShortRegData48[] = {OTM8009A_CMD_NOP, 0xB6};
const gU8 ShortRegData49[] = {0xF5, 0x06};
const gU8 ShortRegData50[] = {OTM8009A_CMD_NOP, 0xB1};
const gU8 ShortRegData51[] = {0xC6, 0x06};
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup OTM8009A_Exported_Variables
* @{
*/
/**
* @}
*/
/* Exported functions ---------------------------------------------------------*/
/** @defgroup OTM8009A_Exported_Functions OTM8009A Exported Functions
* @{
*/
/**
* @brief DSI IO write short/long command.
* @note : Can be surcharged by application code implementation of the function.
*/
__weak void DSI_IO_WriteCmd(gU32 NbrParams, gU8 *pParams)
{
/* NOTE : This function Should not be modified, when it is needed,
the DSI_IO_WriteCmd could be implemented in the user file
*/
}
/**
* @brief Initializes the LCD KoD display part by communication in DSI mode in Video Mode
* with IC Display Driver OTM8009A (see IC Driver specification for more information).
* @param hdsi_eval : pointer on DSI configuration structure
* @param hdsivideo_handle : pointer on DSI video mode configuration structure
* @retval Status
*/
gU8 OTM8009A_Init(gU32 ColorCoding, gU32 orientation)
{
/* Enable CMD2 to access vendor specific commands */
/* Enter in command 2 mode and set EXTC to enable address shift function (0x00) */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
DSI_IO_WriteCmd( 3, (gU8 *)lcdRegData1);
/* Enter ORISE Command 2 */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2); /* Shift address to 0x80 */
DSI_IO_WriteCmd( 2, (gU8 *)lcdRegData2);
/////////////////////////////////////////////////////////////////////
/* SD_PCH_CTRL - 0xC480h - 129th parameter - Default 0x00 */
/* Set SD_PT */
/* -> Source output level during porch and non-display area to GND */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData3);
OTM8009A_IO_Delay(10);
/* Not documented */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData4);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData5);
OTM8009A_IO_Delay(10);
/////////////////////////////////////////////////////////////////////
/* PWR_CTRL4 - 0xC4B0h - 178th parameter - Default 0xA8 */
/* Set gvdd_en_test */
/* -> enable GVDD test mode !!! */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData6);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData7);
/* PWR_CTRL2 - 0xC590h - 146th parameter - Default 0x79 */
/* Set pump 4 vgh voltage */
/* -> from 15.0v down to 13.0v */
/* Set pump 5 vgh voltage */
/* -> from -12.0v downto -9.0v */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData8);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData9);
/* P_DRV_M - 0xC0B4h - 181th parameter - Default 0x00 */
/* -> Column inversion */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData10);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData11);
/* VCOMDC - 0xD900h - 1st parameter - Default 0x39h */
/* VCOM Voltage settings */
/* -> from -1.0000v downto -1.2625v */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData12);
/* Oscillator adjustment for Idle/Normal mode (LPDT only) set to 65Hz (default is 60Hz) */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData13);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData14);
/* Video mode internal */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData15);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData16);
/* PWR_CTRL2 - 0xC590h - 147h parameter - Default 0x00 */
/* Set pump 4&5 x6 */
/* -> ONLY VALID when PUMP4_EN_ASDM_HV = "0" */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData17);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData18);
/* PWR_CTRL2 - 0xC590h - 150th parameter - Default 0x33h */
/* Change pump4 clock ratio */
/* -> from 1 line to 1/2 line */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData19);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData9);
/* GVDD/NGVDD settings */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
DSI_IO_WriteCmd( 2, (gU8 *)lcdRegData5);
/* PWR_CTRL2 - 0xC590h - 149th parameter - Default 0x33h */
/* Rewrite the default value ! */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData20);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData21);
/* Panel display timing Setting 3 */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData22);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData23);
/* Power control 1 */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData24);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData25);
/* Source driver precharge */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData13);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData26);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData15);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData27);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData28);
DSI_IO_WriteCmd( 2, (gU8 *)lcdRegData6);
/* GOAVST */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
DSI_IO_WriteCmd( 6, (gU8 *)lcdRegData7);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData29);
DSI_IO_WriteCmd( 14, (gU8 *)lcdRegData8);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData30);
DSI_IO_WriteCmd( 14, (gU8 *)lcdRegData9);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData31);
DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData10);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData32);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData46);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData11);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData33);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData12);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData29);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData13);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData30);
DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData14);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData31);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData15);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData32);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData16);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData34);
DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData17);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData35);
DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData18);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData2);
DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData19);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData33);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData20);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData29);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData21);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData30);
DSI_IO_WriteCmd( 10, (gU8 *)lcdRegData22);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData31);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData23);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData32);
DSI_IO_WriteCmd( 15, (gU8 *)lcdRegData24);
/////////////////////////////////////////////////////////////////////////////
/* PWR_CTRL1 - 0xc580h - 130th parameter - default 0x00 */
/* Pump 1 min and max DM */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData13);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData47);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData48);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData49);
/////////////////////////////////////////////////////////////////////////////
/* CABC LEDPWM frequency adjusted to 19,5kHz */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData50);
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData51);
/* Exit CMD2 mode */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
DSI_IO_WriteCmd( 3, (gU8 *)lcdRegData25);
/*************************************************************************** */
/* Standard DCS Initialization TO KEEP CAN BE DONE IN HSDT */
/*************************************************************************** */
/* NOP - goes back to DCS std command ? */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
/* Gamma correction 2.2+ table (HSDT possible) */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
DSI_IO_WriteCmd( 16, (gU8 *)lcdRegData3);
/* Gamma correction 2.2- table (HSDT possible) */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
DSI_IO_WriteCmd( 16, (gU8 *)lcdRegData4);
/* Send Sleep Out command to display : no parameter */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData36);
/* Wait for sleep out exit */
OTM8009A_IO_Delay(120);
switch(ColorCoding)
{
case OTM8009A_FORMAT_RBG565 :
/* Set Pixel color format to RGB565 */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData37);
break;
case OTM8009A_FORMAT_RGB888 :
/* Set Pixel color format to RGB888 */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData38);
break;
default :
break;
}
/* Send command to configure display in landscape orientation mode. By default
the orientation mode is portrait */
if(orientation == OTM8009A_ORIENTATION_LANDSCAPE)
{
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData39);
DSI_IO_WriteCmd( 4, (gU8 *)lcdRegData27);
DSI_IO_WriteCmd( 4, (gU8 *)lcdRegData28);
}
/** CABC : Content Adaptive Backlight Control section start >> */
/* Note : defaut is 0 (lowest Brightness), 0xFF is highest Brightness, try 0x7F : intermediate value */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData40);
/* defaut is 0, try 0x2C - Brightness Control Block, Display Dimming & BackLight on */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData41);
/* defaut is 0, try 0x02 - image Content based Adaptive Brightness [Still Picture] */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData42);
/* defaut is 0 (lowest Brightness), 0xFF is highest Brightness */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData43);
/** CABC : Content Adaptive Backlight Control section end << */
/* Send Command Display On */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData44);
/* NOP command */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData1);
/* Send Command GRAM memory write (no parameters) : this initiates frame write via other DSI commands sent by */
/* DSI host from LTDC incoming pixels in video mode */
DSI_IO_WriteCmd(0, (gU8 *)ShortRegData45);
return 0;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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boards/base/STM32F469i-Discovery/otm8009a.h
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@ -1,224 +1,224 @@
/**
******************************************************************************
* @file otm8009a.h
* @author MCD Application Team
* @version V1.0.2
* @date 27-January-2017
* @brief This file contains all the constants parameters for the OTM8009A
* which is the LCD Driver for KoD KM-040TMP-02-0621 (WVGA)
* DSI LCD Display.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __OTM8009A_H
#define __OTM8009A_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup otm8009a
* @{
*/
/** @addtogroup OTM8009A_Exported_Variables
* @{
*/
#if defined ( __GNUC__ )
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#endif /* __GNUC__ */
/**
* @brief LCD_OrientationTypeDef
* Possible values of Display Orientation
*/
#define OTM8009A_ORIENTATION_PORTRAIT ((gU32)0x00) /* Portrait orientation choice of LCD screen */
#define OTM8009A_ORIENTATION_LANDSCAPE ((gU32)0x01) /* Landscape orientation choice of LCD screen */
/**
* @brief Possible values of
* pixel data format (ie color coding) transmitted on DSI Data lane in DSI packets
*/
#define OTM8009A_FORMAT_RGB888 ((gU32)0x00) /* Pixel format chosen is RGB888 : 24 bpp */
#define OTM8009A_FORMAT_RBG565 ((gU32)0x02) /* Pixel format chosen is RGB565 : 16 bpp */
/**
* @brief otm8009a_480x800 Size
*/
/* Width and Height in Portrait mode */
#define OTM8009A_480X800_WIDTH ((gU16)480) /* LCD PIXEL WIDTH */
#define OTM8009A_480X800_HEIGHT ((gU16)800) /* LCD PIXEL HEIGHT */
/* Width and Height in Landscape mode */
#define OTM8009A_800X480_WIDTH ((gU16)800) /* LCD PIXEL WIDTH */
#define OTM8009A_800X480_HEIGHT ((gU16)480) /* LCD PIXEL HEIGHT */
/**
* @brief OTM8009A_480X800 Timing parameters for Portrait orientation mode
*/
#define OTM8009A_480X800_HSYNC ((gU16)2) /* Horizontal synchronization */
#define OTM8009A_480X800_HBP ((gU16)34) /* Horizontal back porch */
#define OTM8009A_480X800_HFP ((gU16)34) /* Horizontal front porch */
#define OTM8009A_480X800_VSYNC ((gU16)1) /* Vertical synchronization */
#define OTM8009A_480X800_VBP ((gU16)15) /* Vertical back porch */
#define OTM8009A_480X800_VFP ((gU16)16) /* Vertical front porch */
/**
* @brief OTM8009A_800X480 Timing parameters for Landscape orientation mode
* Same values as for Portrait mode in fact.
*/
#define OTM8009A_800X480_HSYNC OTM8009A_480X800_VSYNC /* Horizontal synchronization */
#define OTM8009A_800X480_HBP OTM8009A_480X800_VBP /* Horizontal back porch */
#define OTM8009A_800X480_HFP OTM8009A_480X800_VFP /* Horizontal front porch */
#define OTM8009A_800X480_VSYNC OTM8009A_480X800_HSYNC /* Vertical synchronization */
#define OTM8009A_800X480_VBP OTM8009A_480X800_HBP /* Vertical back porch */
#define OTM8009A_800X480_VFP OTM8009A_480X800_HFP /* Vertical front porch */
/* List of OTM8009A used commands */
/* Detailed in OTM8009A Data Sheet 'DATA_SHEET_OTM8009A_V0 92.pdf' */
/* Version of 14 June 2012 */
#define OTM8009A_CMD_NOP 0x00 /* NOP command */
#define OTM8009A_CMD_SWRESET 0x01 /* Sw reset command */
#define OTM8009A_CMD_RDDMADCTL 0x0B /* Read Display MADCTR command : read memory display access ctrl */
#define OTM8009A_CMD_RDDCOLMOD 0x0C /* Read Display pixel format */
#define OTM8009A_CMD_SLPIN 0x10 /* Sleep In command */
#define OTM8009A_CMD_SLPOUT 0x11 /* Sleep Out command */
#define OTM8009A_CMD_PTLON 0x12 /* Partial mode On command */
#define OTM8009A_CMD_DISPOFF 0x28 /* Display Off command */
#define OTM8009A_CMD_DISPON 0x29 /* Display On command */
#define OTM8009A_CMD_CASET 0x2A /* Column address set command */
#define OTM8009A_CMD_PASET 0x2B /* Page address set command */
#define OTM8009A_CMD_RAMWR 0x2C /* Memory (GRAM) write command */
#define OTM8009A_CMD_RAMRD 0x2E /* Memory (GRAM) read command */
#define OTM8009A_CMD_PLTAR 0x30 /* Partial area command (4 parameters) */
#define OTM8009A_CMD_TEOFF 0x34 /* Tearing Effect Line Off command : command with no parameter */
#define OTM8009A_CMD_TEEON 0x35 /* Tearing Effect Line On command : command with 1 parameter 'TELOM' */
/* Parameter TELOM : Tearing Effect Line Output Mode : possible values */
#define OTM8009A_TEEON_TELOM_VBLANKING_INFO_ONLY 0x00
#define OTM8009A_TEEON_TELOM_VBLANKING_AND_HBLANKING_INFO 0x01
#define OTM8009A_CMD_MADCTR 0x36 /* Memory Access write control command */
/* Possible used values of MADCTR */
#define OTM8009A_MADCTR_MODE_PORTRAIT 0x00
#define OTM8009A_MADCTR_MODE_LANDSCAPE 0x60 /* MY = 0, MX = 1, MV = 1, ML = 0, RGB = 0 */
#define OTM8009A_CMD_IDMOFF 0x38 /* Idle mode Off command */
#define OTM8009A_CMD_IDMON 0x39 /* Idle mode On command */
#define OTM8009A_CMD_COLMOD 0x3A /* Interface Pixel format command */
/* Possible values of COLMOD parameter corresponding to used pixel formats */
#define OTM8009A_COLMOD_RGB565 0x55
#define OTM8009A_COLMOD_RGB888 0x77
#define OTM8009A_CMD_RAMWRC 0x3C /* Memory write continue command */
#define OTM8009A_CMD_RAMRDC 0x3E /* Memory read continue command */
#define OTM8009A_CMD_WRTESCN 0x44 /* Write Tearing Effect Scan line command */
#define OTM8009A_CMD_RDSCNL 0x45 /* Read Tearing Effect Scan line command */
/* CABC Management : ie : Content Adaptive Back light Control in IC OTM8009a */
#define OTM8009A_CMD_WRDISBV 0x51 /* Write Display Brightness command */
#define OTM8009A_CMD_WRCTRLD 0x53 /* Write CTRL Display command */
#define OTM8009A_CMD_WRCABC 0x55 /* Write Content Adaptive Brightness command */
#define OTM8009A_CMD_WRCABCMB 0x5E /* Write CABC Minimum Brightness command */
/**
* @brief OTM8009A_480X800 frequency divider
*/
#define OTM8009A_480X800_FREQUENCY_DIVIDER 2 /* LCD Frequency divider */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup OTM8009A_Exported_Macros OTM8009A Exported Macros
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup OTM8009A_Exported_Functions
* @{
*/
void DSI_IO_WriteCmd(gU32 NbrParams, gU8 *pParams);
gU8 OTM8009A_Init(gU32 ColorCoding, gU32 orientation);
void OTM8009A_IO_Delay(gU32 Delay);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __OTM8009A_480X800_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file otm8009a.h
* @author MCD Application Team
* @version V1.0.2
* @date 27-January-2017
* @brief This file contains all the constants parameters for the OTM8009A
* which is the LCD Driver for KoD KM-040TMP-02-0621 (WVGA)
* DSI LCD Display.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __OTM8009A_H
#define __OTM8009A_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include <stdint.h>
/** @addtogroup BSP
* @{
*/
/** @addtogroup Components
* @{
*/
/** @addtogroup otm8009a
* @{
*/
/** @addtogroup OTM8009A_Exported_Variables
* @{
*/
#if defined ( __GNUC__ )
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#endif /* __GNUC__ */
/**
* @brief LCD_OrientationTypeDef
* Possible values of Display Orientation
*/
#define OTM8009A_ORIENTATION_PORTRAIT ((gU32)0x00) /* Portrait orientation choice of LCD screen */
#define OTM8009A_ORIENTATION_LANDSCAPE ((gU32)0x01) /* Landscape orientation choice of LCD screen */
/**
* @brief Possible values of
* pixel data format (ie color coding) transmitted on DSI Data lane in DSI packets
*/
#define OTM8009A_FORMAT_RGB888 ((gU32)0x00) /* Pixel format chosen is RGB888 : 24 bpp */
#define OTM8009A_FORMAT_RBG565 ((gU32)0x02) /* Pixel format chosen is RGB565 : 16 bpp */
/**
* @brief otm8009a_480x800 Size
*/
/* Width and Height in Portrait mode */
#define OTM8009A_480X800_WIDTH ((gU16)480) /* LCD PIXEL WIDTH */
#define OTM8009A_480X800_HEIGHT ((gU16)800) /* LCD PIXEL HEIGHT */
/* Width and Height in Landscape mode */
#define OTM8009A_800X480_WIDTH ((gU16)800) /* LCD PIXEL WIDTH */
#define OTM8009A_800X480_HEIGHT ((gU16)480) /* LCD PIXEL HEIGHT */
/**
* @brief OTM8009A_480X800 Timing parameters for Portrait orientation mode
*/
#define OTM8009A_480X800_HSYNC ((gU16)2) /* Horizontal synchronization */
#define OTM8009A_480X800_HBP ((gU16)34) /* Horizontal back porch */
#define OTM8009A_480X800_HFP ((gU16)34) /* Horizontal front porch */
#define OTM8009A_480X800_VSYNC ((gU16)1) /* Vertical synchronization */
#define OTM8009A_480X800_VBP ((gU16)15) /* Vertical back porch */
#define OTM8009A_480X800_VFP ((gU16)16) /* Vertical front porch */
/**
* @brief OTM8009A_800X480 Timing parameters for Landscape orientation mode
* Same values as for Portrait mode in fact.
*/
#define OTM8009A_800X480_HSYNC OTM8009A_480X800_VSYNC /* Horizontal synchronization */
#define OTM8009A_800X480_HBP OTM8009A_480X800_VBP /* Horizontal back porch */
#define OTM8009A_800X480_HFP OTM8009A_480X800_VFP /* Horizontal front porch */
#define OTM8009A_800X480_VSYNC OTM8009A_480X800_HSYNC /* Vertical synchronization */
#define OTM8009A_800X480_VBP OTM8009A_480X800_HBP /* Vertical back porch */
#define OTM8009A_800X480_VFP OTM8009A_480X800_HFP /* Vertical front porch */
/* List of OTM8009A used commands */
/* Detailed in OTM8009A Data Sheet 'DATA_SHEET_OTM8009A_V0 92.pdf' */
/* Version of 14 June 2012 */
#define OTM8009A_CMD_NOP 0x00 /* NOP command */
#define OTM8009A_CMD_SWRESET 0x01 /* Sw reset command */
#define OTM8009A_CMD_RDDMADCTL 0x0B /* Read Display MADCTR command : read memory display access ctrl */
#define OTM8009A_CMD_RDDCOLMOD 0x0C /* Read Display pixel format */
#define OTM8009A_CMD_SLPIN 0x10 /* Sleep In command */
#define OTM8009A_CMD_SLPOUT 0x11 /* Sleep Out command */
#define OTM8009A_CMD_PTLON 0x12 /* Partial mode On command */
#define OTM8009A_CMD_DISPOFF 0x28 /* Display Off command */
#define OTM8009A_CMD_DISPON 0x29 /* Display On command */
#define OTM8009A_CMD_CASET 0x2A /* Column address set command */
#define OTM8009A_CMD_PASET 0x2B /* Page address set command */
#define OTM8009A_CMD_RAMWR 0x2C /* Memory (GRAM) write command */
#define OTM8009A_CMD_RAMRD 0x2E /* Memory (GRAM) read command */
#define OTM8009A_CMD_PLTAR 0x30 /* Partial area command (4 parameters) */
#define OTM8009A_CMD_TEOFF 0x34 /* Tearing Effect Line Off command : command with no parameter */
#define OTM8009A_CMD_TEEON 0x35 /* Tearing Effect Line On command : command with 1 parameter 'TELOM' */
/* Parameter TELOM : Tearing Effect Line Output Mode : possible values */
#define OTM8009A_TEEON_TELOM_VBLANKING_INFO_ONLY 0x00
#define OTM8009A_TEEON_TELOM_VBLANKING_AND_HBLANKING_INFO 0x01
#define OTM8009A_CMD_MADCTR 0x36 /* Memory Access write control command */
/* Possible used values of MADCTR */
#define OTM8009A_MADCTR_MODE_PORTRAIT 0x00
#define OTM8009A_MADCTR_MODE_LANDSCAPE 0x60 /* MY = 0, MX = 1, MV = 1, ML = 0, RGB = 0 */
#define OTM8009A_CMD_IDMOFF 0x38 /* Idle mode Off command */
#define OTM8009A_CMD_IDMON 0x39 /* Idle mode On command */
#define OTM8009A_CMD_COLMOD 0x3A /* Interface Pixel format command */
/* Possible values of COLMOD parameter corresponding to used pixel formats */
#define OTM8009A_COLMOD_RGB565 0x55
#define OTM8009A_COLMOD_RGB888 0x77
#define OTM8009A_CMD_RAMWRC 0x3C /* Memory write continue command */
#define OTM8009A_CMD_RAMRDC 0x3E /* Memory read continue command */
#define OTM8009A_CMD_WRTESCN 0x44 /* Write Tearing Effect Scan line command */
#define OTM8009A_CMD_RDSCNL 0x45 /* Read Tearing Effect Scan line command */
/* CABC Management : ie : Content Adaptive Back light Control in IC OTM8009a */
#define OTM8009A_CMD_WRDISBV 0x51 /* Write Display Brightness command */
#define OTM8009A_CMD_WRCTRLD 0x53 /* Write CTRL Display command */
#define OTM8009A_CMD_WRCABC 0x55 /* Write Content Adaptive Brightness command */
#define OTM8009A_CMD_WRCABCMB 0x5E /* Write CABC Minimum Brightness command */
/**
* @brief OTM8009A_480X800 frequency divider
*/
#define OTM8009A_480X800_FREQUENCY_DIVIDER 2 /* LCD Frequency divider */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup OTM8009A_Exported_Macros OTM8009A Exported Macros
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup OTM8009A_Exported_Functions
* @{
*/
void DSI_IO_WriteCmd(gU32 NbrParams, gU8 *pParams);
gU8 OTM8009A_Init(gU32 ColorCoding, gU32 orientation);
void OTM8009A_IO_Delay(gU32 Delay);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __OTM8009A_480X800_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@ -1,169 +1,169 @@
/**
******************************************************************************
* @file stm32469i_discovery_sdram.h
* @author MCD Application Team
* @version V2.0.0
* @date 27-January-2017
* @brief This file contains the common defines and functions prototypes for
* the stm32469i_discovery_sdram.c driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32469I_DISCOVERY_SDRAM_H
#define __STM32469I_DISCOVERY_SDRAM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup STM32469I_Discovery
* @{
*/
/** @addtogroup STM32469I-Discovery_SDRAM
* @{
*/
/** @defgroup STM32469I-Discovery_SDRAM_Exported_Types STM32469I Discovery SDRAM Exported Types
* @{
*/
/**
* @brief SDRAM status structure definition
*/
#define SDRAM_OK ((gU8)0x00)
#define SDRAM_ERROR ((gU8)0x01)
/**
* @}
*/
/** @defgroup STM32469I-Discovery_SDRAM_Exported_Constants STM32469I Discovery SDRAM Exported Constants
* @{
*/
#define SDRAM_DEVICE_ADDR ((gU32)0xC0000000)
/* SDRAM device size in Bytes */
#define SDRAM_DEVICE_SIZE ((gU32)0x1000000)
#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_32
#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2
/* SDRAM refresh counter (90 MHz SD clock) */
#define REFRESH_COUNT ((gU32)0x0569)
#define SDRAM_TIMEOUT ((gU32)0xFFFF)
/* DMA definitions for SDRAM DMA transfer */
#define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
#define __DMAx_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
#define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0
#define SDRAM_DMAx_STREAM DMA2_Stream0
#define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn
#define SDRAM_DMAx_IRQHandler DMA2_Stream0_IRQHandler
/**
* @brief FMC SDRAM Mode definition register defines
*/
#define SDRAM_MODEREG_BURST_LENGTH_1 ((gU16)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((gU16)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((gU16)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((gU16)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((gU16)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((gU16)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((gU16)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((gU16)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((gU16)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((gU16)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((gU16)0x0200)
/**
* @}
*/
/** @defgroup STM32469I-Discovery_SDRAM_Exported_Macro STM32469I Discovery SDRAM Exported Macro
* @{
*/
/**
* @}
*/
/** @addtogroup STM32469I_Discovery_SDRAM_Exported_Functions
* @{
*/
gU8 BSP_SDRAM_Init(void);
gU8 BSP_SDRAM_DeInit(void);
void BSP_SDRAM_Initialization_sequence(gU32 RefreshCount);
gU8 BSP_SDRAM_ReadData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
gU8 BSP_SDRAM_ReadData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
gU8 BSP_SDRAM_WriteData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
gU8 BSP_SDRAM_WriteData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
gU8 BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
void BSP_SDRAM_DMA_IRQHandler(void);
/* These function can be modified in case the current settings (e.g. DMA stream)
need to be changed for specific application needs */
void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params);
void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32469I_DISCOVERY_SDRAM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file stm32469i_discovery_sdram.h
* @author MCD Application Team
* @version V2.0.0
* @date 27-January-2017
* @brief This file contains the common defines and functions prototypes for
* the stm32469i_discovery_sdram.c driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32469I_DISCOVERY_SDRAM_H
#define __STM32469I_DISCOVERY_SDRAM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
/** @addtogroup BSP
* @{
*/
/** @addtogroup STM32469I_Discovery
* @{
*/
/** @addtogroup STM32469I-Discovery_SDRAM
* @{
*/
/** @defgroup STM32469I-Discovery_SDRAM_Exported_Types STM32469I Discovery SDRAM Exported Types
* @{
*/
/**
* @brief SDRAM status structure definition
*/
#define SDRAM_OK ((gU8)0x00)
#define SDRAM_ERROR ((gU8)0x01)
/**
* @}
*/
/** @defgroup STM32469I-Discovery_SDRAM_Exported_Constants STM32469I Discovery SDRAM Exported Constants
* @{
*/
#define SDRAM_DEVICE_ADDR ((gU32)0xC0000000)
/* SDRAM device size in Bytes */
#define SDRAM_DEVICE_SIZE ((gU32)0x1000000)
#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_32
#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2
/* SDRAM refresh counter (90 MHz SD clock) */
#define REFRESH_COUNT ((gU32)0x0569)
#define SDRAM_TIMEOUT ((gU32)0xFFFF)
/* DMA definitions for SDRAM DMA transfer */
#define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
#define __DMAx_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
#define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0
#define SDRAM_DMAx_STREAM DMA2_Stream0
#define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn
#define SDRAM_DMAx_IRQHandler DMA2_Stream0_IRQHandler
/**
* @brief FMC SDRAM Mode definition register defines
*/
#define SDRAM_MODEREG_BURST_LENGTH_1 ((gU16)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((gU16)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((gU16)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((gU16)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((gU16)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((gU16)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((gU16)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((gU16)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((gU16)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((gU16)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((gU16)0x0200)
/**
* @}
*/
/** @defgroup STM32469I-Discovery_SDRAM_Exported_Macro STM32469I Discovery SDRAM Exported Macro
* @{
*/
/**
* @}
*/
/** @addtogroup STM32469I_Discovery_SDRAM_Exported_Functions
* @{
*/
gU8 BSP_SDRAM_Init(void);
gU8 BSP_SDRAM_DeInit(void);
void BSP_SDRAM_Initialization_sequence(gU32 RefreshCount);
gU8 BSP_SDRAM_ReadData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
gU8 BSP_SDRAM_ReadData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
gU8 BSP_SDRAM_WriteData(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
gU8 BSP_SDRAM_WriteData_DMA(gU32 uwStartAddress, gU32 *pData, gU32 uwDataSize);
gU8 BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
void BSP_SDRAM_DMA_IRQHandler(void);
/* These function can be modified in case the current settings (e.g. DMA stream)
need to be changed for specific application needs */
void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params);
void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32469I_DISCOVERY_SDRAM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@ -1,176 +1,176 @@
/**
******************************************************************************
* @file Templates_LL/Src/stm32f4xx_it.c
* @author MCD Application Team
* @version V1.0.0
* @date 17-February-2017
* @brief Main Interrupt Service Routines.
* This file provides template for all exceptions handler and
* peripherals interrupt service routine.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f469i_raw32_it.h"
/** @addtogroup STM32F4xx_LL_Examples
* @{
*/
/** @addtogroup Templates_LL
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/******************************************************************************/
/* Cortex-M4 Processor Exceptions Handlers */
/******************************************************************************/
/**
* @brief This function handles NMI exception.
* @param None
* @retval None
*/
void NMI_Handler(void)
{
}
/**
* @brief This function handles Hard Fault exception.
* @param None
* @retval None
*/
void HardFault_Handler(void)
{
/* Go to infinite loop when Hard Fault exception occurs */
while (1)
{
}
}
/**
* @brief This function handles Memory Manage exception.
* @param None
* @retval None
*/
void MemManage_Handler(void)
{
/* Go to infinite loop when Memory Manage exception occurs */
while (1)
{
}
}
/**
* @brief This function handles Bus Fault exception.
* @param None
* @retval None
*/
void BusFault_Handler(void)
{
/* Go to infinite loop when Bus Fault exception occurs */
while (1)
{
}
}
/**
* @brief This function handles Usage Fault exception.
* @param None
* @retval None
*/
void UsageFault_Handler(void)
{
/* Go to infinite loop when Usage Fault exception occurs */
while (1)
{
}
}
/**
* @brief This function handles SVCall exception.
* @param None
* @retval None
*/
void SVC_Handler(void)
{
}
/**
* @brief This function handles Debug Monitor exception.
* @param None
* @retval None
*/
void DebugMon_Handler(void)
{
}
/**
* @brief This function handles PendSVC exception.
* @param None
* @retval None
*/
void PendSV_Handler(void)
{
}
/**
* @brief This function handles SysTick Handler.
* @param None
* @retval None
*/
void SysTick_Handler(void)
{
HAL_IncTick();
}
/******************************************************************************/
/* STM32F4xx Peripherals Interrupt Handlers */
/* Add here the Interrupt Handler for the used peripheral(s) (GPIO), for the */
/* available peripheral interrupt handler's name please refer to the startup */
/* file (startup_stm32f4xx.s). */
/******************************************************************************/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file Templates_LL/Src/stm32f4xx_it.c
* @author MCD Application Team
* @version V1.0.0
* @date 17-February-2017
* @brief Main Interrupt Service Routines.
* This file provides template for all exceptions handler and
* peripherals interrupt service routine.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f469i_raw32_it.h"
/** @addtogroup STM32F4xx_LL_Examples
* @{
*/
/** @addtogroup Templates_LL
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/******************************************************************************/
/* Cortex-M4 Processor Exceptions Handlers */
/******************************************************************************/
/**
* @brief This function handles NMI exception.
* @param None
* @retval None
*/
void NMI_Handler(void)
{
}
/**
* @brief This function handles Hard Fault exception.
* @param None
* @retval None
*/
void HardFault_Handler(void)
{
/* Go to infinite loop when Hard Fault exception occurs */
while (1)
{
}
}
/**
* @brief This function handles Memory Manage exception.
* @param None
* @retval None
*/
void MemManage_Handler(void)
{
/* Go to infinite loop when Memory Manage exception occurs */
while (1)
{
}
}
/**
* @brief This function handles Bus Fault exception.
* @param None
* @retval None
*/
void BusFault_Handler(void)
{
/* Go to infinite loop when Bus Fault exception occurs */
while (1)
{
}
}
/**
* @brief This function handles Usage Fault exception.
* @param None
* @retval None
*/
void UsageFault_Handler(void)
{
/* Go to infinite loop when Usage Fault exception occurs */
while (1)
{
}
}
/**
* @brief This function handles SVCall exception.
* @param None
* @retval None
*/
void SVC_Handler(void)
{
}
/**
* @brief This function handles Debug Monitor exception.
* @param None
* @retval None
*/
void DebugMon_Handler(void)
{
}
/**
* @brief This function handles PendSVC exception.
* @param None
* @retval None
*/
void PendSV_Handler(void)
{
}
/**
* @brief This function handles SysTick Handler.
* @param None
* @retval None
*/
void SysTick_Handler(void)
{
HAL_IncTick();
}
/******************************************************************************/
/* STM32F4xx Peripherals Interrupt Handlers */
/* Add here the Interrupt Handler for the used peripheral(s) (GPIO), for the */
/* available peripheral interrupt handler's name please refer to the startup */
/* file (startup_stm32f4xx.s). */
/******************************************************************************/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

138
boards/base/STM32F469i-Discovery/stm32f469i_raw32_it.h
View file

@ -1,69 +1,69 @@
/**
******************************************************************************
* @file Templates_LL/Inc/stm32f4xx_it.h
* @author MCD Application Team
* @version V1.0.0
* @date 17-February-2017
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_IT_H
#define __STM32F4xx_IT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_IT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file Templates_LL/Inc/stm32f4xx_it.h
* @author MCD Application Team
* @version V1.0.0
* @date 17-February-2017
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_IT_H
#define __STM32F4xx_IT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_IT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

900
boards/base/STM32F469i-Discovery/stm32f469i_raw32_system.c
View file

@ -1,450 +1,450 @@
/**
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V1.0.0
* @date 17-February-2017
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f4xx_system
* @{
*/
/** @addtogroup STM32F4xx_System_Private_Includes
* @{
*/
#include "stm32f4xx.h"
#if !defined (HSE_VALUE)
#if defined(USE_STM32469I_DISCO_REVA)
#define HSE_VALUE ((gU32)25000000) /*!< Default value of the External oscillator in Hz */
#else
#define HSE_VALUE ((gU32)8000000) /*!< Default value of the External oscillator in Hz */
#endif /* USE_STM32469I_DISCO_REVA */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((gU32)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use external SDRAM mounted
on DK as data memory */
/* #define DATA_IN_ExtSDRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
gU32 SystemCoreClock = 16000000;
const gU8 AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const gU8 APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
* @{
*/
#if defined (DATA_IN_ExtSDRAM)
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSDRAM */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the FPU setting, vector table location and External memory
* configuration.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (gU32)0x00000001;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (gU32)0xFEF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */
RCC->CR &= (gU32)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
#if defined (DATA_IN_ExtSDRAM)
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSDRAM */
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
* depends on the application requirements), user has to ensure that HSE_VALUE
* is same as the real frequency of the crystal used. Otherwise, this function
* may have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
gU32 tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0)
{
/* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
else
{
/* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
SystemCoreClock = pllvco/pllp;
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK frequency */
SystemCoreClock >>= tmp;
}
#if defined (DATA_IN_ExtSDRAM)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
* This function configures the external memories (SRAM/SDRAM)
* This SRAM/SDRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
register gU32 tmpreg = 0, timeout = 0xFFFF;
register __IO gU32 index;
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH, and GPIOI interface
clock */
RCC->AHB1ENR |= 0x000001FC;
/* Connect PCx pins to FMC Alternate function */
GPIOC->AFR[0] = 0x0000000C;
GPIOC->AFR[1] = 0x00000000;
/* Configure PCx pins in Alternate function mode */
GPIOC->MODER = 0x00000002;
/* Configure PCx pins speed to 100 MHz */
GPIOC->OSPEEDR = 0x00000003;
/* Configure PCx pins Output type to push-pull */
GPIOC->OTYPER = 0x00000000;
/* No pull-up, pull-down for PCx pins */
GPIOC->PUPDR = 0x00000000;
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x000000CC;
GPIOD->AFR[1] = 0xCC000CCC;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xA02A000A;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xF03F000F;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00000CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA800A;
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xFFFFC00F;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0x00CCCCCC;
GPIOF->AFR[1] = 0xCCCCC000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA800AAA;
/* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xFFC00FFF;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0x00CC00CC;
GPIOG->AFR[1] = 0xC000000C;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x80020A0A;
/* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0xC0030F0F;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/* Connect PHx pins to FMC Alternate function */
GPIOH->AFR[0] = 0x0000CC00;
GPIOH->AFR[1] = 0xCCCCCCCC;
/* Configure PHx pins in Alternate function mode */
GPIOH->MODER = 0xAAAA00A0;
/* Configure PHx pins speed to 100 MHz */
GPIOH->OSPEEDR = 0xFFFF00F0;
/* Configure PHx pins Output type to push-pull */
GPIOH->OTYPER = 0x00000000;
/* No pull-up, pull-down for PHx pins */
GPIOH->PUPDR = 0x00000000;
/* Connect PIx pins to FMC Alternate function */
GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0;
/* Configure PIx pins in Alternate function mode */
GPIOI->MODER = 0x0028AAAA;
/* Configure PIx pins speed to 100 MHz */
GPIOI->OSPEEDR = 0x003CFFFF;
/* Configure PIx pins Output type to push-pull */
GPIOI->OTYPER = 0x00000000;
/* No pull-up, pull-down for PIx pins */
GPIOI->PUPDR = 0x00000000;
/* FMC Configuration */
/* Enable the FMC interface clock */
RCC->AHB3ENR |= 0x00000001;
/* Configure and enable SDRAM bank2 */
FMC_Bank5_6->SDCR[0] = 0x000019E4;
FMC_Bank5_6->SDTR[0] = 0x01115351;
/* SDRAM initialization sequence */
/* Clock enable command */
FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Delay */
for (index = 0; index<1000; index++);
/* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Auto refresh command */
FMC_Bank5_6->SDCMR = 0x000000F3;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* MRD register program */
FMC_Bank5_6->SDCMR = 0x00046014;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Set refresh count */
tmpreg = FMC_Bank5_6->SDRTR;
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000056A<<1));
/* Disable write protection */
tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
}
#endif /* DATA_IN_ExtSDRAM */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
/**
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V1.0.0
* @date 17-February-2017
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f4xx_system
* @{
*/
/** @addtogroup STM32F4xx_System_Private_Includes
* @{
*/
#include "stm32f4xx.h"
#if !defined (HSE_VALUE)
#if defined(USE_STM32469I_DISCO_REVA)
#define HSE_VALUE ((gU32)25000000) /*!< Default value of the External oscillator in Hz */
#else
#define HSE_VALUE ((gU32)8000000) /*!< Default value of the External oscillator in Hz */
#endif /* USE_STM32469I_DISCO_REVA */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((gU32)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use external SDRAM mounted
on DK as data memory */
/* #define DATA_IN_ExtSDRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
gU32 SystemCoreClock = 16000000;
const gU8 AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const gU8 APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
* @{
*/
#if defined (DATA_IN_ExtSDRAM)
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSDRAM */
/**
* @}
*/
/** @addtogroup STM32F4xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the FPU setting, vector table location and External memory
* configuration.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (gU32)0x00000001;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (gU32)0xFEF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */
RCC->CR &= (gU32)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
#if defined (DATA_IN_ExtSDRAM)
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSDRAM */
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
* depends on the application requirements), user has to ensure that HSE_VALUE
* is same as the real frequency of the crystal used. Otherwise, this function
* may have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
gU32 tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0)
{
/* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
else
{
/* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
SystemCoreClock = pllvco/pllp;
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK frequency */
SystemCoreClock >>= tmp;
}
#if defined (DATA_IN_ExtSDRAM)
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f4xx.s before jump to main.
* This function configures the external memories (SRAM/SDRAM)
* This SRAM/SDRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
register gU32 tmpreg = 0, timeout = 0xFFFF;
register __IO gU32 index;
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH, and GPIOI interface
clock */
RCC->AHB1ENR |= 0x000001FC;
/* Connect PCx pins to FMC Alternate function */
GPIOC->AFR[0] = 0x0000000C;
GPIOC->AFR[1] = 0x00000000;
/* Configure PCx pins in Alternate function mode */
GPIOC->MODER = 0x00000002;
/* Configure PCx pins speed to 100 MHz */
GPIOC->OSPEEDR = 0x00000003;
/* Configure PCx pins Output type to push-pull */
GPIOC->OTYPER = 0x00000000;
/* No pull-up, pull-down for PCx pins */
GPIOC->PUPDR = 0x00000000;
/* Connect PDx pins to FMC Alternate function */
GPIOD->AFR[0] = 0x000000CC;
GPIOD->AFR[1] = 0xCC000CCC;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xA02A000A;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xF03F000F;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FMC Alternate function */
GPIOE->AFR[0] = 0xC00000CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xAAAA800A;
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xFFFFC00F;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FMC Alternate function */
GPIOF->AFR[0] = 0x00CCCCCC;
GPIOF->AFR[1] = 0xCCCCC000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xAA800AAA;
/* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xFFC00FFF;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FMC Alternate function */
GPIOG->AFR[0] = 0x00CC00CC;
GPIOG->AFR[1] = 0xC000000C;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x80020A0A;
/* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0xC0030F0F;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/* Connect PHx pins to FMC Alternate function */
GPIOH->AFR[0] = 0x0000CC00;
GPIOH->AFR[1] = 0xCCCCCCCC;
/* Configure PHx pins in Alternate function mode */
GPIOH->MODER = 0xAAAA00A0;
/* Configure PHx pins speed to 100 MHz */
GPIOH->OSPEEDR = 0xFFFF00F0;
/* Configure PHx pins Output type to push-pull */
GPIOH->OTYPER = 0x00000000;
/* No pull-up, pull-down for PHx pins */
GPIOH->PUPDR = 0x00000000;
/* Connect PIx pins to FMC Alternate function */
GPIOI->AFR[0] = 0xCCCCCCCC;
GPIOI->AFR[1] = 0x00000CC0;
/* Configure PIx pins in Alternate function mode */
GPIOI->MODER = 0x0028AAAA;
/* Configure PIx pins speed to 100 MHz */
GPIOI->OSPEEDR = 0x003CFFFF;
/* Configure PIx pins Output type to push-pull */
GPIOI->OTYPER = 0x00000000;
/* No pull-up, pull-down for PIx pins */
GPIOI->PUPDR = 0x00000000;
/* FMC Configuration */
/* Enable the FMC interface clock */
RCC->AHB3ENR |= 0x00000001;
/* Configure and enable SDRAM bank2 */
FMC_Bank5_6->SDCR[0] = 0x000019E4;
FMC_Bank5_6->SDTR[0] = 0x01115351;
/* SDRAM initialization sequence */
/* Clock enable command */
FMC_Bank5_6->SDCMR = 0x00000011;
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Delay */
for (index = 0; index<1000; index++);
/* PALL command */
FMC_Bank5_6->SDCMR = 0x00000012;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Auto refresh command */
FMC_Bank5_6->SDCMR = 0x000000F3;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* MRD register program */
FMC_Bank5_6->SDCMR = 0x00046014;
timeout = 0xFFFF;
while((tmpreg != 0) && (timeout-- > 0))
{
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
}
/* Set refresh count */
tmpreg = FMC_Bank5_6->SDRTR;
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000056A<<1));
/* Disable write protection */
tmpreg = FMC_Bank5_6->SDCR[0];
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
}
#endif /* DATA_IN_ExtSDRAM */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

138
boards/base/STM32F746-Discovery/stm32f746g_raw32_ugfx.c
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@ -1,69 +1,69 @@
#include "../../../gfx.h"
#if GFX_COMPAT_V2 && GFX_COMPAT_OLDCOLORS
#undef Red
#undef Green
#undef Blue
#endif
#include "stm32f7xx_hal.h"
#if GFX_USE_OS_CHIBIOS
#define HAL_GPIO_Init(port, ptr) palSetGroupMode(port, (ptr)->Pin, 0, (ptr)->Mode|((ptr)->Speed<<3)|((ptr)->Pull<<5)|((ptr)->Alternate<<7))
#else
gTicks gfxSystemTicks(void)
{
return HAL_GetTick();
}
gTicks gfxMillisecondsToTicks(gDelay ms)
{
return ms;
}
#endif
void SystemClock_Config(void)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
/* Enable HSE Oscillator and activate PLL with HSE as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 25;
RCC_OscInitStruct.PLL.PLLN = 432;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 9;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
/* Activate the OverDrive to reach the 216 MHz Frequency */
HAL_PWREx_EnableOverDrive();
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
}
void Raw32OSInit(void)
{
/* Enable the CPU Cache's */
SCB_EnableICache(); // Enable I-Cache
SCB_EnableDCache(); // Enable D-Cache
/* STM32F7xx HAL library initialization:
- Configure the Flash ART accelerator on ITCM interface
- Configure the Systick to generate an interrupt each 1 msec
- Set NVIC Group Priority to 4
- Global MSP (MCU Support Package) initialization
*/
HAL_Init();
/* Configure the system clock to 216 MHz */
SystemClock_Config();
}
#include "../../../gfx.h"
#if GFX_COMPAT_V2 && GFX_COMPAT_OLDCOLORS
#undef Red
#undef Green
#undef Blue
#endif
#include "stm32f7xx_hal.h"
#if GFX_USE_OS_CHIBIOS
#define HAL_GPIO_Init(port, ptr) palSetGroupMode(port, (ptr)->Pin, 0, (ptr)->Mode|((ptr)->Speed<<3)|((ptr)->Pull<<5)|((ptr)->Alternate<<7))
#else
gTicks gfxSystemTicks(void)
{
return HAL_GetTick();
}
gTicks gfxMillisecondsToTicks(gDelay ms)
{
return ms;
}
#endif
void SystemClock_Config(void)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
/* Enable HSE Oscillator and activate PLL with HSE as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 25;
RCC_OscInitStruct.PLL.PLLN = 432;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 9;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
/* Activate the OverDrive to reach the 216 MHz Frequency */
HAL_PWREx_EnableOverDrive();
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
}
void Raw32OSInit(void)
{
/* Enable the CPU Cache's */
SCB_EnableICache(); // Enable I-Cache
SCB_EnableDCache(); // Enable D-Cache
/* STM32F7xx HAL library initialization:
- Configure the Flash ART accelerator on ITCM interface
- Configure the Systick to generate an interrupt each 1 msec
- Set NVIC Group Priority to 4
- Global MSP (MCU Support Package) initialization
*/
HAL_Init();
/* Configure the system clock to 216 MHz */
SystemClock_Config();
}

1032
changelog.txt
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90
demos/applications/mandelbrot/gfxconf.h
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@ -1,45 +1,45 @@
/*
* Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org>
* Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _GFXCONF_H
#define _GFXCONF_H
/* The operating system to use. One of these must be defined - preferably in your Makefile */
//#define GFX_USE_OS_CHIBIOS GFXOFF
//#define GFX_USE_OS_WIN32 GFXOFF
//#define GFX_USE_OS_LINUX GFXOFF
//#define GFX_USE_OS_OSX GFXOFF
/* GFX sub-systems to turn on */
#define GFX_USE_GDISP GFXON
/* Features for the GDISP sub-system. */
#define GDISP_NEED_VALIDATION GFXON
#endif /* _GFXCONF_H */
/*
* Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org>
* Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _GFXCONF_H
#define _GFXCONF_H
/* The operating system to use. One of these must be defined - preferably in your Makefile */
//#define GFX_USE_OS_CHIBIOS GFXOFF
//#define GFX_USE_OS_WIN32 GFXOFF
//#define GFX_USE_OS_LINUX GFXOFF
//#define GFX_USE_OS_OSX GFXOFF
/* GFX sub-systems to turn on */
#define GFX_USE_GDISP GFXON
/* Features for the GDISP sub-system. */
#define GDISP_NEED_VALIDATION GFXON
#endif /* _GFXCONF_H */

166
demos/applications/mandelbrot/main.c
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@ -1,83 +1,83 @@
/*
* Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org>
* Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "gfx.h"
void mandelbrot(float x1, float y1, float x2, float y2) {
unsigned int i,j, width, height;
gU16 iter;
gColor color;
float fwidth, fheight;
float sy = y2 - y1;
float sx = x2 - x1;
const int MAX = 512;
width = (unsigned int)gdispGetWidth();
height = (unsigned int)gdispGetHeight();
fwidth = width;
fheight = height;
for(i = 0; i < width; i++) {
for(j = 0; j < height; j++) {
float cy = j * sy / fheight + y1;
float cx = i * sx / fwidth + x1;
float x=0.0f, y=0.0f, xx=0.0f, yy=0.0f;
for(iter=0; iter <= MAX && xx+yy<4.0f; iter++) {
xx = x*x;
yy = y*y;
y = 2.0f*x*y + cy;
x = xx - yy + cx;
}
//color = ((iter << 8) | (iter&0xFF));
color = RGB2COLOR(iter<<7, iter<<4, iter);
gdispDrawPixel(i, j, color);
}
}
}
int main(void) {
float cx, cy;
float zoom = 1.0f;
gfxInit();
/* where to zoom in */
cx = -0.086f;
cy = 0.85f;
while(1) {
mandelbrot(-2.0f*zoom+cx, -1.5f*zoom+cy, 2.0f*zoom+cx, 1.5f*zoom+cy);
zoom *= 0.7f;
if(zoom <= 0.00001f)
zoom = 1.0f;
}
}
/*
* Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org>
* Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "gfx.h"
void mandelbrot(float x1, float y1, float x2, float y2) {
unsigned int i,j, width, height;
gU16 iter;
gColor color;
float fwidth, fheight;
float sy = y2 - y1;
float sx = x2 - x1;
const int MAX = 512;
width = (unsigned int)gdispGetWidth();
height = (unsigned int)gdispGetHeight();
fwidth = width;
fheight = height;
for(i = 0; i < width; i++) {
for(j = 0; j < height; j++) {
float cy = j * sy / fheight + y1;
float cx = i * sx / fwidth + x1;
float x=0.0f, y=0.0f, xx=0.0f, yy=0.0f;
for(iter=0; iter <= MAX && xx+yy<4.0f; iter++) {
xx = x*x;
yy = y*y;
y = 2.0f*x*y + cy;
x = xx - yy + cx;
}
//color = ((iter << 8) | (iter&0xFF));
color = RGB2COLOR(iter<<7, iter<<4, iter);
gdispDrawPixel(i, j, color);
}
}
}
int main(void) {
float cx, cy;
float zoom = 1.0f;
gfxInit();
/* where to zoom in */
cx = -0.086f;
cy = 0.85f;
while(1) {
mandelbrot(-2.0f*zoom+cx, -1.5f*zoom+cy, 2.0f*zoom+cx, 1.5f*zoom+cy);
zoom *= 0.7f;
if(zoom <= 0.00001f)
zoom = 1.0f;
}
}

120
demos/applications/notepad/gfxconf.h
View file

@ -1,60 +1,60 @@
/*
* Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org>
* Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _GFXCONF_H
#define _GFXCONF_H
/* The operating system to use. One of these must be defined - preferably in your Makefile */
//#define GFX_USE_OS_CHIBIOS GFXOFF
//#define GFX_USE_OS_WIN32 GFXOFF
//#define GFX_USE_OS_LINUX GFXOFF
//#define GFX_USE_OS_OSX GFXOFF
/* GFX sub-systems to turn on */
#define GFX_USE_GDISP GFXON
#define GFX_USE_GEVENT GFXON
#define GFX_USE_GTIMER GFXON
#define GFX_USE_GINPUT GFXON
/* Features for the GDISP sub-system. */
#define GDISP_NEED_VALIDATION GFXON
#define GDISP_NEED_CLIP GFXON
#define GDISP_NEED_TEXT GFXON
#define GDISP_NEED_CIRCLE GFXON
#define GDISP_NEED_MULTITHREAD GFXON
/* Builtin Fonts */
#define GDISP_INCLUDE_FONT_DEJAVUSANS12_AA GFXON
#define GDISP_INCLUDE_FONT_DEJAVUSANS24_AA GFXON
#define GDISP_NEED_ANTIALIAS GFXON
/* Features for the GINPUT sub-system. */
#define GINPUT_NEED_MOUSE GFXON
#endif /* _GFXCONF_H */
/*
* Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org>
* Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _GFXCONF_H
#define _GFXCONF_H
/* The operating system to use. One of these must be defined - preferably in your Makefile */
//#define GFX_USE_OS_CHIBIOS GFXOFF
//#define GFX_USE_OS_WIN32 GFXOFF
//#define GFX_USE_OS_LINUX GFXOFF
//#define GFX_USE_OS_OSX GFXOFF
/* GFX sub-systems to turn on */
#define GFX_USE_GDISP GFXON
#define GFX_USE_GEVENT GFXON
#define GFX_USE_GTIMER GFXON
#define GFX_USE_GINPUT GFXON
/* Features for the GDISP sub-system. */
#define GDISP_NEED_VALIDATION GFXON
#define GDISP_NEED_CLIP GFXON
#define GDISP_NEED_TEXT GFXON
#define GDISP_NEED_CIRCLE GFXON
#define GDISP_NEED_MULTITHREAD GFXON
/* Builtin Fonts */
#define GDISP_INCLUDE_FONT_DEJAVUSANS12_AA GFXON
#define GDISP_INCLUDE_FONT_DEJAVUSANS24_AA GFXON
#define GDISP_NEED_ANTIALIAS GFXON
/* Features for the GINPUT sub-system. */
#define GINPUT_NEED_MOUSE GFXON
#endif /* _GFXCONF_H */

232
demos/applications/notepad/main.c
View file

@ -1,116 +1,116 @@
/*
* Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org>
* Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "gfx.h"
#define COLOR_SIZE 20
#define PEN_SIZE 20
#define OFFSET 3
#define COLOR_BOX(a) (ev.x >= a && ev.x <= a + COLOR_SIZE)
#define PEN_BOX(a) (ev.y >= a && ev.y <= a + COLOR_SIZE)
#define GET_COLOR(a) (COLOR_BOX(a * COLOR_SIZE + OFFSET))
#define GET_PEN(a) (PEN_BOX(a * 2 * PEN_SIZE + OFFSET))
#define DRAW_COLOR(a) (a * COLOR_SIZE + OFFSET)
#define DRAW_PEN(a) (a * 2 * PEN_SIZE + OFFSET)
#define DRAW_AREA(x, y) (x >= PEN_SIZE + OFFSET + 3 && x <= gdispGetWidth() && \
y >= COLOR_SIZE + OFFSET + 3 && y <= gdispGetHeight())
void drawScreen(void) {
char *msg = "uGFX";
gFont font1, font2;
font1 = gdispOpenFont("DejaVuSans24*");
font2 = gdispOpenFont("DejaVuSans12*");
gdispClear(GFX_WHITE);
gdispDrawString(gdispGetWidth()-gdispGetStringWidth(msg, font1)-3, 3, msg, font1, GFX_BLACK);
/* colors */
gdispFillArea(0 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_BLACK); /* Black */
gdispFillArea(1 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_RED); /* Red */
gdispFillArea(2 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_YELLOW); /* Yellow */
gdispFillArea(3 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_GREEN); /* Green */
gdispFillArea(4 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_BLUE); /* Blue */
gdispDrawBox (5 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_WHITE); /* White */
/* pens */
gdispFillStringBox(OFFSET * 2, DRAW_PEN(1), PEN_SIZE, PEN_SIZE, "1", font2, GFX_WHITE, GFX_BLACK, gJustifyCenter);
gdispFillStringBox(OFFSET * 2, DRAW_PEN(2), PEN_SIZE, PEN_SIZE, "2", font2, GFX_WHITE, GFX_BLACK, gJustifyCenter);
gdispFillStringBox(OFFSET * 2, DRAW_PEN(3), PEN_SIZE, PEN_SIZE, "3", font2, GFX_WHITE, GFX_BLACK, gJustifyCenter);
gdispFillStringBox(OFFSET * 2, DRAW_PEN(4), PEN_SIZE, PEN_SIZE, "4", font2, GFX_WHITE, GFX_BLACK, gJustifyCenter);
gdispFillStringBox(OFFSET * 2, DRAW_PEN(5), PEN_SIZE, PEN_SIZE, "5", font2, GFX_WHITE, GFX_BLACK, gJustifyCenter);
gdispCloseFont(font1);
gdispCloseFont(font2);
}
GEventMouse ev;
int main(void) {
gColor color = GFX_BLACK;
gU16 pen = 0;
gfxInit();
ginputGetMouse(0);
drawScreen();
while (1) {
ginputGetMouseStatus(0, &ev);
if (!(ev.buttons & GINPUT_MOUSE_BTN_LEFT))
continue;
/* inside color box ? */
if(ev.y >= OFFSET && ev.y <= COLOR_SIZE) {
if(GET_COLOR(0)) color = GFX_BLACK;
else if(GET_COLOR(1)) color = GFX_RED;
else if(GET_COLOR(2)) color = GFX_YELLOW;
else if(GET_COLOR(3)) color = GFX_GREEN;
else if(GET_COLOR(4)) color = GFX_BLUE;
else if(GET_COLOR(5)) color = GFX_WHITE;
/* inside pen box ? */
} else if(ev.x >= OFFSET && ev.x <= PEN_SIZE) {
if(GET_PEN(1)) pen = 0;
else if(GET_PEN(2)) pen = 1;
else if(GET_PEN(3)) pen = 2;
else if(GET_PEN(4)) pen = 3;
else if(GET_PEN(5)) pen = 4;
/* inside drawing area ? */
} else if(DRAW_AREA(ev.x, ev.y)) {
if(pen == 0)
gdispDrawPixel(ev.x, ev.y, color);
else
gdispFillCircle(ev.x, ev.y, pen, color);
}
}
}
/*
* Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org>
* Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "gfx.h"
#define COLOR_SIZE 20
#define PEN_SIZE 20
#define OFFSET 3
#define COLOR_BOX(a) (ev.x >= a && ev.x <= a + COLOR_SIZE)
#define PEN_BOX(a) (ev.y >= a && ev.y <= a + COLOR_SIZE)
#define GET_COLOR(a) (COLOR_BOX(a * COLOR_SIZE + OFFSET))
#define GET_PEN(a) (PEN_BOX(a * 2 * PEN_SIZE + OFFSET))
#define DRAW_COLOR(a) (a * COLOR_SIZE + OFFSET)
#define DRAW_PEN(a) (a * 2 * PEN_SIZE + OFFSET)
#define DRAW_AREA(x, y) (x >= PEN_SIZE + OFFSET + 3 && x <= gdispGetWidth() && \
y >= COLOR_SIZE + OFFSET + 3 && y <= gdispGetHeight())
void drawScreen(void) {
char *msg = "uGFX";
gFont font1, font2;
font1 = gdispOpenFont("DejaVuSans24*");
font2 = gdispOpenFont("DejaVuSans12*");
gdispClear(GFX_WHITE);
gdispDrawString(gdispGetWidth()-gdispGetStringWidth(msg, font1)-3, 3, msg, font1, GFX_BLACK);
/* colors */
gdispFillArea(0 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_BLACK); /* Black */
gdispFillArea(1 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_RED); /* Red */
gdispFillArea(2 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_YELLOW); /* Yellow */
gdispFillArea(3 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_GREEN); /* Green */
gdispFillArea(4 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_BLUE); /* Blue */
gdispDrawBox (5 * COLOR_SIZE + 3, 3, COLOR_SIZE, COLOR_SIZE, GFX_WHITE); /* White */
/* pens */
gdispFillStringBox(OFFSET * 2, DRAW_PEN(1), PEN_SIZE, PEN_SIZE, "1", font2, GFX_WHITE, GFX_BLACK, gJustifyCenter);
gdispFillStringBox(OFFSET * 2, DRAW_PEN(2), PEN_SIZE, PEN_SIZE, "2", font2, GFX_WHITE, GFX_BLACK, gJustifyCenter);
gdispFillStringBox(OFFSET * 2, DRAW_PEN(3), PEN_SIZE, PEN_SIZE, "3", font2, GFX_WHITE, GFX_BLACK, gJustifyCenter);
gdispFillStringBox(OFFSET * 2, DRAW_PEN(4), PEN_SIZE, PEN_SIZE, "4", font2, GFX_WHITE, GFX_BLACK, gJustifyCenter);
gdispFillStringBox(OFFSET * 2, DRAW_PEN(5), PEN_SIZE, PEN_SIZE, "5", font2, GFX_WHITE, GFX_BLACK, gJustifyCenter);
gdispCloseFont(font1);
gdispCloseFont(font2);
}
GEventMouse ev;
int main(void) {
gColor color = GFX_BLACK;
gU16 pen = 0;
gfxInit();
ginputGetMouse(0);
drawScreen();
while (1) {
ginputGetMouseStatus(0, &ev);
if (!(ev.buttons & GINPUT_MOUSE_BTN_LEFT))
continue;
/* inside color box ? */
if(ev.y >= OFFSET && ev.y <= COLOR_SIZE) {
if(GET_COLOR(0)) color = GFX_BLACK;
else if(GET_COLOR(1)) color = GFX_RED;
else if(GET_COLOR(2)) color = GFX_YELLOW;
else if(GET_COLOR(3)) color = GFX_GREEN;
else if(GET_COLOR(4)) color = GFX_BLUE;
else if(GET_COLOR(5)) color = GFX_WHITE;
/* inside pen box ? */
} else if(ev.x >= OFFSET && ev.x <= PEN_SIZE) {
if(GET_PEN(1)) pen = 0;
else if(GET_PEN(2)) pen = 1;
else if(GET_PEN(3)) pen = 2;
else if(GET_PEN(4)) pen = 3;
else if(GET_PEN(5)) pen = 4;
/* inside drawing area ? */
} else if(DRAW_AREA(ev.x, ev.y)) {
if(pen == 0)
gdispDrawPixel(ev.x, ev.y, color);
else
gdispFillCircle(ev.x, ev.y, pen, color);
}
}
}

94
demos/modules/gdisp/basics/gfxconf.h
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@ -1,47 +1,47 @@
/*
* Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org>
* Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _GFXCONF_H
#define _GFXCONF_H
/* The operating system to use. One of these must be defined - preferably in your Makefile */
//#define GFX_USE_OS_CHIBIOS GFXOFF
//#define GFX_USE_OS_WIN32 GFXOFF
//#define GFX_USE_OS_LINUX GFXOFF
//#define GFX_USE_OS_OSX GFXOFF
/* GFX sub-systems to turn on */
#define GFX_USE_GDISP GFXON
/* Features for the GDISP sub-system. */
#define GDISP_NEED_VALIDATION GFXON
#define GDISP_NEED_CLIP GFXON
#endif /* _GFXCONF_H */
/*
* Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org>
* Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _GFXCONF_H
#define _GFXCONF_H
/* The operating system to use. One of these must be defined - preferably in your Makefile */
//#define GFX_USE_OS_CHIBIOS GFXOFF
//#define GFX_USE_OS_WIN32 GFXOFF
//#define GFX_USE_OS_LINUX GFXOFF
//#define GFX_USE_OS_OSX GFXOFF
/* GFX sub-systems to turn on */
#define GFX_USE_GDISP GFXON
/* Features for the GDISP sub-system. */
#define GDISP_NEED_VALIDATION GFXON
#define GDISP_NEED_CLIP GFXON
#endif /* _GFXCONF_H */

110
demos/modules/gdisp/basics/main.c
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@ -1,55 +1,55 @@
/*
* Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org>
* Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "gfx.h"
int main(void) {
gCoord width, height;
gCoord i, j;
// Initialize and clear the display
gfxInit();
// Get the screen size
width = gdispGetWidth();
height = gdispGetHeight();
// Code Here
gdispDrawBox(10, 10, width/2, height/2, GFX_YELLOW);
gdispFillArea(width/2, height/2, width/2-10, height/2-10, GFX_BLUE);
gdispDrawLine(5, 30, width-50, height-40, GFX_RED);
for(i = 5, j = 0; i < width && j < height; i += 7, j += i/20)
gdispDrawPixel(i, j, GFX_WHITE);
while(1) {
gfxSleepMilliseconds(500);
}
}
/*
* Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org>
* Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "gfx.h"
int main(void) {
gCoord width, height;
gCoord i, j;
// Initialize and clear the display
gfxInit();
// Get the screen size
width = gdispGetWidth();
height = gdispGetHeight();
// Code Here
gdispDrawBox(10, 10, width/2, height/2, GFX_YELLOW);
gdispFillArea(width/2, height/2, width/2-10, height/2-10, GFX_BLUE);
gdispDrawLine(5, 30, width-50, height-40, GFX_RED);
for(i = 5, j = 0; i < width && j < height; i += 7, j += i/20)
gdispDrawPixel(i, j, GFX_WHITE);
while(1) {
gfxSleepMilliseconds(500);
}
}

110
demos/modules/gdisp/circles/gfxconf.h
View file

@ -1,55 +1,55 @@
/*
* Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org>
* Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _GFXCONF_H
#define _GFXCONF_H
/* The operating system to use. One of these must be defined - preferably in your Makefile */
//#define GFX_USE_OS_CHIBIOS GFXOFF
//#define GFX_USE_OS_WIN32 GFXOFF
//#define GFX_USE_OS_LINUX GFXOFF
//#define GFX_USE_OS_OSX GFXOFF
/* GFX sub-systems to turn on */
#define GFX_USE_GDISP GFXON
#define GFX_USE_GMISC GFXON
/* Features for the GDISP subsystem. */
#define GDISP_NEED_VALIDATION GFXON
#define GDISP_NEED_CLIP GFXON
#define GDISP_NEED_CIRCLE GFXON
#define GDISP_NEED_ELLIPSE GFXON
#define GDISP_NEED_ARC GFXON
/* Features for the GMISC subsystem */
#define GMISC_NEED_FIXEDTRIG GFXON
#define GMISC_NEED_FASTTRIG GFXON
#endif /* _GFXCONF_H */
/*
* Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org>
* Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _GFXCONF_H
#define _GFXCONF_H
/* The operating system to use. One of these must be defined - preferably in your Makefile */
//#define GFX_USE_OS_CHIBIOS GFXOFF
//#define GFX_USE_OS_WIN32 GFXOFF
//#define GFX_USE_OS_LINUX GFXOFF
//#define GFX_USE_OS_OSX GFXOFF
/* GFX sub-systems to turn on */
#define GFX_USE_GDISP GFXON
#define GFX_USE_GMISC GFXON
/* Features for the GDISP subsystem. */
#define GDISP_NEED_VALIDATION GFXON
#define GDISP_NEED_CLIP GFXON
#define GDISP_NEED_CIRCLE GFXON
#define GDISP_NEED_ELLIPSE GFXON
#define GDISP_NEED_ARC GFXON
/* Features for the GMISC subsystem */
#define GMISC_NEED_FIXEDTRIG GFXON
#define GMISC_NEED_FASTTRIG GFXON
#endif /* _GFXCONF_H */

108
demos/modules/gdisp/circles/main.c
View file

@ -1,54 +1,54 @@
/*
* Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org>
* Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "gfx.h"
int main(void) {
gCoord width, height;
// Initialize and clear the display
gfxInit();
// Get the screen size
width = gdispGetWidth();
height = gdispGetHeight();
// Code Here
gdispFillArc(width/2, height/2, width/4, -10, -45, GFX_WHITE);
gdispDrawCircle(width/2+width/8, height/2-height/8, 13, GFX_GREEN);
gdispFillCircle (width/2+width/8, height/2-height/8, 10, GFX_RED);
gdispDrawArc(width/2+width/8, height/2-height/8, 20, 25, 115, GFX_GRAY);
gdispFillEllipse (width-width/6, height-height/6, width/8, height/16, GFX_BLUE);
gdispDrawEllipse (width-width/6, height-height/6, width/16, height/8, GFX_YELLOW);
while(1) {
gfxSleepMilliseconds(500);
}
}
/*
* Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org>
* Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "gfx.h"
int main(void) {
gCoord width, height;
// Initialize and clear the display
gfxInit();
// Get the screen size
width = gdispGetWidth();
height = gdispGetHeight();
// Code Here
gdispFillArc(width/2, height/2, width/4, -10, -45, GFX_WHITE);
gdispDrawCircle(width/2+width/8, height/2-height/8, 13, GFX_GREEN);
gdispFillCircle (width/2+width/8, height/2-height/8, 10, GFX_RED);
gdispDrawArc(width/2+width/8, height/2-height/8, 20, 25, 115, GFX_GRAY);
gdispFillEllipse (width-width/6, height-height/6, width/8, height/16, GFX_BLUE);
gdispDrawEllipse (width-width/6, height-height/6, width/16, height/8, GFX_YELLOW);
while(1) {
gfxSleepMilliseconds(500);
}
}

98
demos/modules/gdisp/fonts_cyrillic/main.c
View file

@ -1,49 +1,49 @@
/*
* Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org>
* Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "gfx.h"
int main(void) {
gFont font1;
// Initialize uGFX and the underlying system
gfxInit();
// Get the fonts we want to use
font1 = gdispOpenFont("Archangelsk Regular 12");
// Demonstrate our other fonts
gdispDrawString(10, 10, "привет мир", font1, GFX_YELLOW);
// Wait forever
while(1) {
gfxSleepMilliseconds(500);
}
}
/*
* Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org>
* Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "gfx.h"
int main(void) {
gFont font1;
// Initialize uGFX and the underlying system
gfxInit();
// Get the fonts we want to use
font1 = gdispOpenFont("Archangelsk Regular 12");
// Demonstrate our other fonts
gdispDrawString(10, 10, "привет мир", font1, GFX_YELLOW);
// Wait forever
while(1) {
gfxSleepMilliseconds(500);
}
}

84
demos/modules/gtimer/gfxconf.h
View file

@ -1,42 +1,42 @@
/*
* Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org>
* Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _GFXCONF_H
#define _GFXCONF_H
/* The operating system to use. One of these must be defined - preferably in your Makefile */
//#define GFX_USE_OS_CHIBIOS GFXOFF
//#define GFX_USE_OS_WIN32 GFXOFF
//#define GFX_USE_OS_LINUX GFXOFF
//#define GFX_USE_OS_OSX GFXOFF
/* GFX sub-systems to turn on */
#define GFX_USE_GTIMER GFXON
#endif /* _GFXCONF_H */
/*
* Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org>
* Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _GFXCONF_H
#define _GFXCONF_H
/* The operating system to use. One of these must be defined - preferably in your Makefile */
//#define GFX_USE_OS_CHIBIOS GFXOFF
//#define GFX_USE_OS_WIN32 GFXOFF
//#define GFX_USE_OS_LINUX GFXOFF
//#define GFX_USE_OS_OSX GFXOFF
/* GFX sub-systems to turn on */
#define GFX_USE_GTIMER GFXON
#endif /* _GFXCONF_H */

130
demos/modules/gtimer/main.c
View file

@ -1,65 +1,65 @@
/*
* Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org>
* Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "gfx.h"
GTimer GT1, GT2;
void callback1(void* arg) {
(void)arg;
palTogglePad(GPIOD, GPIOD_LED3);
}
void callback2(void* arg) {
(void)arg;
palSetPad(GPIOD, GPIOD_LED4);
}
int main(void) {
gfxInit();
/* initialize the timers */
gtimerInit(&GT1);
gtimerInit(&GT2);
/* continious mode - callback1() called without any argument every 250ms */
gtimerStart(&GT1, callback1, 0, gTrue, 250);
/* single shot mode - callback2() called without any argument once after 1s */
gtimerStart(&GT2, callback2, 0, gFalse, 1000);
while(1) {
gfxSleepMilliseconds(500);
}
return 0;
}
/*
* Copyright (c) 2012, 2013, Joel Bodenmann aka Tectu <joel@unormal.org>
* Copyright (c) 2012, 2013, Andrew Hannam aka inmarket
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the <organization> nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "gfx.h"
GTimer GT1, GT2;
void callback1(void* arg) {
(void)arg;
palTogglePad(GPIOD, GPIOD_LED3);
}
void callback2(void* arg) {
(void)arg;
palSetPad(GPIOD, GPIOD_LED4);
}
int main(void) {
gfxInit();
/* initialize the timers */
gtimerInit(&GT1);
gtimerInit(&GT2);
/* continious mode - callback1() called without any argument every 250ms */
gtimerStart(&GT1, callback1, 0, gTrue, 250);
/* single shot mode - callback2() called without any argument once after 1s */
gtimerStart(&GT2, callback2, 0, gFalse, 1000);
while(1) {
gfxSleepMilliseconds(500);
}
return 0;
}

4
docs/readme.txt
View file

@ -1,2 +1,2 @@
If there is no html directory containing the HTML version of the API documentation, you
can find an online version of the documentation at http://api.ugfx.io
If there is no html directory containing the HTML version of the API documentation, you
can find an online version of the documentation at http://api.ugfx.io

268
drivers/gdisp/HX8347D/HX8347D.h
View file

@ -1,134 +1,134 @@
/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.io/license.html
*/
#ifndef _HX8347D_H
#define _HX8347D_H
/* HX8347D registers */
/* page 0 registers */
#define HX8347D_REG_HID 0x00 /* Himax ID */
#define HX8347D_REG_DMODE 0x01 /* Display mode control */
#define HX8347D_REG_SCH 0x02 /* Column address start high */
#define HX8347D_REG_SCL 0x03 /* Column address start low */
#define HX8347D_REG_ECH 0x04 /* Column address end high */
#define HX8347D_REG_ECL 0x05 /* Column address end low */
#define HX8347D_REG_SPH 0x06 /* Row address start high */
#define HX8347D_REG_SPL 0x07 /* Row address start low */
#define HX8347D_REG_EPH 0x08 /* Row address end high */
#define HX8347D_REG_EPL 0x09 /* Row address end low */
#define HX8347D_REG_PSLH 0x0a /* Partial area start row high */
#define HX8347D_REG_PSLL 0x0b /* Partial area start row low */
#define HX8347D_REG_PELH 0x0c /* Partial area end row high */
#define HX8347D_REG_PELL 0x0d /* Partial area end row low */
#define HX8347D_REG_TFAH 0x0e /* Vertical scroll top fixed area high */
#define HX8347D_REG_TFAL 0x0f /* Vertical scroll top fixed area low */
#define HX8347D_REG_VSAH 0x10 /* Vertical scroll height area high */
#define HX8347D_REG_VSAL 0x11 /* Vertical scroll height area low */
#define HX8347D_REG_BFAH 0x12 /* Vertical scroll button area high */
#define HX8347D_REG_BFAL 0x13 /* Vertical scroll button area low */
#define HX8347D_REG_VSPH 0x14 /* Vertical scroll start address high */
#define HX8347D_REG_VSPL 0x15 /* Vertical scroll start address low */
#define HX8347D_REG_MAC 0x16 /* Memory access control */
#define HX8347D_REG_COLMOD 0x17 /* COLMOD */
#define HX8347D_REG_OSCCH 0x18 /* OSC control 2 */
#define HX8347D_REG_OSCCL 0x19 /* OSC control 1 */
#define HX8347D_REG_PWC1 0x1a /* Power control 1 */
#define HX8347D_REG_PWC2 0x1b /* Power control 2 */
#define HX8347D_REG_PWC3 0x1c /* Power control 3 */
#define HX8347D_REG_PWC4 0x1d /* Power control 4 */
#define HX8347D_REG_PWC5 0x1e /* Power control 5 */
#define HX8347D_REG_PWC6 0x1f /* Power control 6 */
#define HX8347D_REG_SRAMWC 0x22 /* SRAM write control */
#define HX8347D_REG_VMF 0x23 /* VCOM control 1 */
#define HX8347D_REG_VMH 0x24 /* VCOM control 2 */
#define HX8347D_REG_VML 0x25 /* VCOM control 3 */
#define HX8347D_REG_DC1 0x26 /* Display control 1 */
#define HX8347D_REG_DC2 0x27 /* Display control 2 */
#define HX8347D_REG_DC3 0x28 /* Display control 3 */
#define HX8347D_REG_FRC1 0x29 /* Frame rate control 1 */
#define HX8347D_REG_FRC2 0x2a /* Frame rate control 2 */
#define HX8347D_REG_FRC3 0x2b /* Frame rate control 3 */
#define HX8347D_REG_FRC4 0x2c /* Frame rate control 4 */
#define HX8347D_REG_GDON 0x2d /* Cycle control 1 */
#define HX8347D_REG_GDOF 0x2e /* Cycle control 2 */
#define HX8347D_REG_DINV 0x2f /* Display inversion */
#define HX8347D_REG_RGB1 0x31 /* RGB interface control 1 */
#define HX8347D_REG_RGB2 0x32 /* RGB interface control 2 */
#define HX8347D_REG_RGB3 0x33 /* RGB interface control 3 */
#define HX8347D_REG_RGB4 0x34 /* RGB interface control 4 */
#define HX8347D_REG_PCH 0x36 /* Panel characteristic */
#define HX8347D_REG_OTP1 0x38 /* OTP control 1 */
#define HX8347D_REG_OTP2 0x39 /* OTP control 2 */
#define HX8347D_REG_OTP3 0x3a /* OTP control 3 */
#define HX8347D_REG_CABC1 0x3c /* CABC control 1 */
#define HX8347D_REG_CABC2 0x3d /* CABC control 2 */
#define HX8347D_REG_CABC3 0x3e /* CABC control 3 */
#define HX8347D_REG_CABC4 0x3f /* CABC control 4 */
#define HX8347D_REG_VRP0 0x40 /* Gamma control 1 */
#define HX8347D_REG_VRP1 0x41 /* Gamma control 2 */
#define HX8347D_REG_VRP2 0x42 /* Gamma control 3 */
#define HX8347D_REG_VRP3 0x43 /* Gamma control 4 */
#define HX8347D_REG_VRP4 0x44 /* Gamma control 5 */
#define HX8347D_REG_VRP5 0x45 /* Gamma control 6 */
#define HX8347D_REG_PRP0 0x46 /* Gamma control 7 */
#define HX8347D_REG_PRP1 0x47 /* Gamma control 8 */
#define HX8347D_REG_PKP0 0x48 /* Gamma control 9 */
#define HX8347D_REG_PKP1 0x49 /* Gamma control 10 */
#define HX8347D_REG_PKP2 0x4a /* Gamma control 11 */
#define HX8347D_REG_PKP3 0x4b /* Gamma control 12 */
#define HX8347D_REG_PKP4 0x4c /* Gamma control 13 */
#define HX8347D_REG_VRN0 0x50 /* Gamma control 14 */
#define HX8347D_REG_VRN1 0x51 /* Gamma control 15 */
#define HX8347D_REG_VRN2 0x52 /* Gamma control 16 */
#define HX8347D_REG_VRN3 0x53 /* Gamma control 17 */
#define HX8347D_REG_VRN4 0x54 /* Gamma control 18 */
#define HX8347D_REG_VRN5 0x55 /* Gamma control 19 */
#define HX8347D_REG_PRN0 0x56 /* Gamma control 20 */
#define HX8347D_REG_PRN1 0x57 /* Gamma control 21 */
#define HX8347D_REG_PKN0 0x58 /* Gamma control 22 */
#define HX8347D_REG_PKN1 0x59 /* Gamma control 23 */
#define HX8347D_REG_PKN2 0x5a /* Gamma control 24 */
#define HX8347D_REG_PKN3 0x5b /* Gamma control 25 */
#define HX8347D_REG_PKN4 0x5c /* Gamma control 26 */
#define HX8347D_REG_CGM 0x5d /* Gamma control 27 */
#define HX8347D_REG_TEC 0x60 /* TE control */
#define HX8347D_REG_PS1 0xe4 /* Power saving 1 */
#define HX8347D_REG_PS2 0xe5 /* Power saving 2 */
#define HX8347D_REG_PS3 0xe6 /* Power saving 3 */
#define HX8347D_REG_PS4 0xe7 /* Power saving 4 */
#define HX8347D_REG_OPONN 0xe8 /* Source OP control normal */
#define HX8347D_REG_OPONI 0xe9 /* Source OP control idle */
#define HX8347D_REG_STBAH 0xea /* Power control internal use 1 */
#define HX8347D_REG_STBAL 0xeb /* Power control internal use 2 */
#define HX8347D_REG_PTBAH 0xec /* Source control internal use 1 */
#define HX8347D_REG_PTBAL 0xed /* Source control internal use 2 */
/* page 1 registers */
#define HX8347D_REG_CABC5 0xc3 /* CABC control 5 */
#define HX8347D_REG_CABC6 0xc5 /* CABC control 6 */
#define HX8347D_REG_CABC7 0xc7 /* CABC control 7 */
#define HX8347D_REG_DBG0 0xcb /* Gain select register 0 */
#define HX8347D_REG_DBG1 0xcc /* Gain select register 1 */
#define HX8347D_REG_DBG2 0xcd /* Gain select register 2 */
#define HX8347D_REG_DBG3 0xce /* Gain select register 3 */
#define HX8347D_REG_DBG4 0xcf /* Gain select register 4 */
#define HX8347D_REG_DBG5 0xd0 /* Gain select register 5 */
#define HX8347D_REG_DBG6 0xd1 /* Gain select register 6 */
#define HX8347D_REG_DBG7 0xd2 /* Gain select register 7 */
#define HX8347D_REG_DBG8 0xd3 /* Gain select register 8 */
#define HX8347D_REG_PGSEL 0xff /* Page select */
#endif /* _HX8347D_H */
/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.io/license.html
*/
#ifndef _HX8347D_H
#define _HX8347D_H
/* HX8347D registers */
/* page 0 registers */
#define HX8347D_REG_HID 0x00 /* Himax ID */
#define HX8347D_REG_DMODE 0x01 /* Display mode control */
#define HX8347D_REG_SCH 0x02 /* Column address start high */
#define HX8347D_REG_SCL 0x03 /* Column address start low */
#define HX8347D_REG_ECH 0x04 /* Column address end high */
#define HX8347D_REG_ECL 0x05 /* Column address end low */
#define HX8347D_REG_SPH 0x06 /* Row address start high */
#define HX8347D_REG_SPL 0x07 /* Row address start low */
#define HX8347D_REG_EPH 0x08 /* Row address end high */
#define HX8347D_REG_EPL 0x09 /* Row address end low */
#define HX8347D_REG_PSLH 0x0a /* Partial area start row high */
#define HX8347D_REG_PSLL 0x0b /* Partial area start row low */
#define HX8347D_REG_PELH 0x0c /* Partial area end row high */
#define HX8347D_REG_PELL 0x0d /* Partial area end row low */
#define HX8347D_REG_TFAH 0x0e /* Vertical scroll top fixed area high */
#define HX8347D_REG_TFAL 0x0f /* Vertical scroll top fixed area low */
#define HX8347D_REG_VSAH 0x10 /* Vertical scroll height area high */
#define HX8347D_REG_VSAL 0x11 /* Vertical scroll height area low */
#define HX8347D_REG_BFAH 0x12 /* Vertical scroll button area high */
#define HX8347D_REG_BFAL 0x13 /* Vertical scroll button area low */
#define HX8347D_REG_VSPH 0x14 /* Vertical scroll start address high */
#define HX8347D_REG_VSPL 0x15 /* Vertical scroll start address low */
#define HX8347D_REG_MAC 0x16 /* Memory access control */
#define HX8347D_REG_COLMOD 0x17 /* COLMOD */
#define HX8347D_REG_OSCCH 0x18 /* OSC control 2 */
#define HX8347D_REG_OSCCL 0x19 /* OSC control 1 */
#define HX8347D_REG_PWC1 0x1a /* Power control 1 */
#define HX8347D_REG_PWC2 0x1b /* Power control 2 */
#define HX8347D_REG_PWC3 0x1c /* Power control 3 */
#define HX8347D_REG_PWC4 0x1d /* Power control 4 */
#define HX8347D_REG_PWC5 0x1e /* Power control 5 */
#define HX8347D_REG_PWC6 0x1f /* Power control 6 */
#define HX8347D_REG_SRAMWC 0x22 /* SRAM write control */
#define HX8347D_REG_VMF 0x23 /* VCOM control 1 */
#define HX8347D_REG_VMH 0x24 /* VCOM control 2 */
#define HX8347D_REG_VML 0x25 /* VCOM control 3 */
#define HX8347D_REG_DC1 0x26 /* Display control 1 */
#define HX8347D_REG_DC2 0x27 /* Display control 2 */
#define HX8347D_REG_DC3 0x28 /* Display control 3 */
#define HX8347D_REG_FRC1 0x29 /* Frame rate control 1 */
#define HX8347D_REG_FRC2 0x2a /* Frame rate control 2 */
#define HX8347D_REG_FRC3 0x2b /* Frame rate control 3 */
#define HX8347D_REG_FRC4 0x2c /* Frame rate control 4 */
#define HX8347D_REG_GDON 0x2d /* Cycle control 1 */
#define HX8347D_REG_GDOF 0x2e /* Cycle control 2 */
#define HX8347D_REG_DINV 0x2f /* Display inversion */
#define HX8347D_REG_RGB1 0x31 /* RGB interface control 1 */
#define HX8347D_REG_RGB2 0x32 /* RGB interface control 2 */
#define HX8347D_REG_RGB3 0x33 /* RGB interface control 3 */
#define HX8347D_REG_RGB4 0x34 /* RGB interface control 4 */
#define HX8347D_REG_PCH 0x36 /* Panel characteristic */
#define HX8347D_REG_OTP1 0x38 /* OTP control 1 */
#define HX8347D_REG_OTP2 0x39 /* OTP control 2 */
#define HX8347D_REG_OTP3 0x3a /* OTP control 3 */
#define HX8347D_REG_CABC1 0x3c /* CABC control 1 */
#define HX8347D_REG_CABC2 0x3d /* CABC control 2 */
#define HX8347D_REG_CABC3 0x3e /* CABC control 3 */
#define HX8347D_REG_CABC4 0x3f /* CABC control 4 */
#define HX8347D_REG_VRP0 0x40 /* Gamma control 1 */
#define HX8347D_REG_VRP1 0x41 /* Gamma control 2 */
#define HX8347D_REG_VRP2 0x42 /* Gamma control 3 */
#define HX8347D_REG_VRP3 0x43 /* Gamma control 4 */
#define HX8347D_REG_VRP4 0x44 /* Gamma control 5 */
#define HX8347D_REG_VRP5 0x45 /* Gamma control 6 */
#define HX8347D_REG_PRP0 0x46 /* Gamma control 7 */
#define HX8347D_REG_PRP1 0x47 /* Gamma control 8 */
#define HX8347D_REG_PKP0 0x48 /* Gamma control 9 */
#define HX8347D_REG_PKP1 0x49 /* Gamma control 10 */
#define HX8347D_REG_PKP2 0x4a /* Gamma control 11 */
#define HX8347D_REG_PKP3 0x4b /* Gamma control 12 */
#define HX8347D_REG_PKP4 0x4c /* Gamma control 13 */
#define HX8347D_REG_VRN0 0x50 /* Gamma control 14 */
#define HX8347D_REG_VRN1 0x51 /* Gamma control 15 */
#define HX8347D_REG_VRN2 0x52 /* Gamma control 16 */
#define HX8347D_REG_VRN3 0x53 /* Gamma control 17 */
#define HX8347D_REG_VRN4 0x54 /* Gamma control 18 */
#define HX8347D_REG_VRN5 0x55 /* Gamma control 19 */
#define HX8347D_REG_PRN0 0x56 /* Gamma control 20 */
#define HX8347D_REG_PRN1 0x57 /* Gamma control 21 */
#define HX8347D_REG_PKN0 0x58 /* Gamma control 22 */
#define HX8347D_REG_PKN1 0x59 /* Gamma control 23 */
#define HX8347D_REG_PKN2 0x5a /* Gamma control 24 */
#define HX8347D_REG_PKN3 0x5b /* Gamma control 25 */
#define HX8347D_REG_PKN4 0x5c /* Gamma control 26 */
#define HX8347D_REG_CGM 0x5d /* Gamma control 27 */
#define HX8347D_REG_TEC 0x60 /* TE control */
#define HX8347D_REG_PS1 0xe4 /* Power saving 1 */
#define HX8347D_REG_PS2 0xe5 /* Power saving 2 */
#define HX8347D_REG_PS3 0xe6 /* Power saving 3 */
#define HX8347D_REG_PS4 0xe7 /* Power saving 4 */
#define HX8347D_REG_OPONN 0xe8 /* Source OP control normal */
#define HX8347D_REG_OPONI 0xe9 /* Source OP control idle */
#define HX8347D_REG_STBAH 0xea /* Power control internal use 1 */
#define HX8347D_REG_STBAL 0xeb /* Power control internal use 2 */
#define HX8347D_REG_PTBAH 0xec /* Source control internal use 1 */
#define HX8347D_REG_PTBAL 0xed /* Source control internal use 2 */
/* page 1 registers */
#define HX8347D_REG_CABC5 0xc3 /* CABC control 5 */
#define HX8347D_REG_CABC6 0xc5 /* CABC control 6 */
#define HX8347D_REG_CABC7 0xc7 /* CABC control 7 */
#define HX8347D_REG_DBG0 0xcb /* Gain select register 0 */
#define HX8347D_REG_DBG1 0xcc /* Gain select register 1 */
#define HX8347D_REG_DBG2 0xcd /* Gain select register 2 */
#define HX8347D_REG_DBG3 0xce /* Gain select register 3 */
#define HX8347D_REG_DBG4 0xcf /* Gain select register 4 */
#define HX8347D_REG_DBG5 0xd0 /* Gain select register 5 */
#define HX8347D_REG_DBG6 0xd1 /* Gain select register 6 */
#define HX8347D_REG_DBG7 0xd2 /* Gain select register 7 */
#define HX8347D_REG_DBG8 0xd3 /* Gain select register 8 */
#define HX8347D_REG_PGSEL 0xff /* Page select */
#endif /* _HX8347D_H */

48
drivers/gdisp/HX8347D/gdisp_lld_config.h
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@ -1,24 +1,24 @@
/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.io/license.html
*/
#ifndef _GDISP_LLD_CONFIG_H
#define _GDISP_LLD_CONFIG_H
#if GFX_USE_GDISP
/*===========================================================================*/
/* Driver hardware support. */
/*===========================================================================*/
#define GDISP_HARDWARE_STREAM_WRITE GFXON
#define GDISP_HARDWARE_CONTROL GFXON
#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_RGB565
#endif /* GFX_USE_GDISP */
#endif /* _GDISP_LLD_CONFIG_H */
/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.io/license.html
*/
#ifndef _GDISP_LLD_CONFIG_H
#define _GDISP_LLD_CONFIG_H
#if GFX_USE_GDISP
/*===========================================================================*/
/* Driver hardware support. */
/*===========================================================================*/
#define GDISP_HARDWARE_STREAM_WRITE GFXON
#define GDISP_HARDWARE_CONTROL GFXON
#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_RGB565
#endif /* GFX_USE_GDISP */
#endif /* _GDISP_LLD_CONFIG_H */

32
drivers/gdisp/ILI9325/gdisp_lld_config.h
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@ -4,23 +4,23 @@
*
* http://ugfx.io/license.html
*/
#ifndef GDISP_LLD_CONFIG_H
#define GDISP_LLD_CONFIG_H
#if GFX_USE_GDISP
/*===========================================================================*/
/* Driver hardware support. */
/*===========================================================================*/
#ifndef GDISP_LLD_CONFIG_H
#define GDISP_LLD_CONFIG_H
#if GFX_USE_GDISP
/*===========================================================================*/
/* Driver hardware support. */
/*===========================================================================*/
#define GDISP_HARDWARE_STREAM_WRITE GFXON
#define GDISP_HARDWARE_STREAM_READ GFXON
#define GDISP_HARDWARE_STREAM_POS GFXON
#define GDISP_HARDWARE_CONTROL GFXON
#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_RGB565
#endif /* GFX_USE_GDISP */
#endif /* _GDISP_LLD_CONFIG_H */
#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_RGB565
#endif /* GFX_USE_GDISP */
#endif /* _GDISP_LLD_CONFIG_H */

124
drivers/gdisp/Nokia6610GE12/GE12.h
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@ -4,65 +4,65 @@
*
* http://ugfx.io/license.html
*/
#ifndef GE12_H
#define GE12_H
// *************************************************************************************
// LCD Include File for Philips PCF8833 STN RGB- 132x132x3 Driver (GE12)
//
// Taken from Philips data sheet Feb 14, 2003
// *************************************************************************************
// Philips PCF8833 LCD controller command codes
#define NOP 0x00 // nop
#define SWRESET 0x01 // software reset
#define BSTROFF 0x02 // booster voltage OFF
#define BSTRON 0x03 // booster voltage ON
#define RDDIDIF 0x04 // read display identification
#define RDDST 0x09 // read display status
#define SLEEPIN 0x10 // sleep in
#define SLEEPOUT 0x11 // sleep out
#define PTLON 0x12 // partial display mode
#define NORON 0x13 // display normal mode
#define INVOFF 0x20 // inversion OFF
#define INVON 0x21 // inversion ON
#define DALO 0x22 // all pixel OFF
#define DAL 0x23 // all pixel ON
#define SETCON 0x25 // write contrast
#define DISPOFF 0x28 // display OFF
#define DISPON 0x29 // display ON
#define CASET 0x2A // column address set
#define PASET 0x2B // page address set
#define RAMWR 0x2C // memory write
#define RGBSET 0x2D // colour set
#define PTLAR 0x30 // partial area
#define VSCRDEF 0x33 // vertical scrolling definition
#define TEOFF 0x34 // test mode
#define TEON 0x35 // test mode
#define MADCTL 0x36 // memory access control
#define SEP 0x37 // vertical scrolling start address
#define IDMOFF 0x38 // idle mode OFF
#define IDMON 0x39 // idle mode ON
#define COLMOD 0x3A // interface pixel format
#define SETVOP 0xB0 // set Vop
#define BRS 0xB4 // bottom row swap
#define TRS 0xB6 // top row swap
#define DISCTR 0xB9 // display control
#define DOR 0xBA // data order
#define TCDFE 0xBD // enable/disable DF temperature compensation
#define TCVOPE 0xBF // enable/disable Vop temp comp
#define EC 0xC0 // internal or external oscillator
#define SETMUL 0xC2 // set multiplication factor
#define TCVOPAB 0xC3 // set TCVOP slopes A and B
#define TCVOPCD 0xC4 // set TCVOP slopes c and d
#define TCDF 0xC5 // set divider frequency
#define DF8COLOR 0xC6 // set divider frequency 8-color mode
#define SETBS 0xC7 // set bias system
#define RDTEMP 0xC8 // temperature read back
#define NLI 0xC9 // n-line inversion
#define RDID1 0xDA // read ID1
#define RDID2 0xDB // read ID2
#define RDID3 0xDC // read ID3
#endif /* GE12_H */
#ifndef GE12_H
#define GE12_H
// *************************************************************************************
// LCD Include File for Philips PCF8833 STN RGB- 132x132x3 Driver (GE12)
//
// Taken from Philips data sheet Feb 14, 2003
// *************************************************************************************
// Philips PCF8833 LCD controller command codes
#define NOP 0x00 // nop
#define SWRESET 0x01 // software reset
#define BSTROFF 0x02 // booster voltage OFF
#define BSTRON 0x03 // booster voltage ON
#define RDDIDIF 0x04 // read display identification
#define RDDST 0x09 // read display status
#define SLEEPIN 0x10 // sleep in
#define SLEEPOUT 0x11 // sleep out
#define PTLON 0x12 // partial display mode
#define NORON 0x13 // display normal mode
#define INVOFF 0x20 // inversion OFF
#define INVON 0x21 // inversion ON
#define DALO 0x22 // all pixel OFF
#define DAL 0x23 // all pixel ON
#define SETCON 0x25 // write contrast
#define DISPOFF 0x28 // display OFF
#define DISPON 0x29 // display ON
#define CASET 0x2A // column address set
#define PASET 0x2B // page address set
#define RAMWR 0x2C // memory write
#define RGBSET 0x2D // colour set
#define PTLAR 0x30 // partial area
#define VSCRDEF 0x33 // vertical scrolling definition
#define TEOFF 0x34 // test mode
#define TEON 0x35 // test mode
#define MADCTL 0x36 // memory access control
#define SEP 0x37 // vertical scrolling start address
#define IDMOFF 0x38 // idle mode OFF
#define IDMON 0x39 // idle mode ON
#define COLMOD 0x3A // interface pixel format
#define SETVOP 0xB0 // set Vop
#define BRS 0xB4 // bottom row swap
#define TRS 0xB6 // top row swap
#define DISCTR 0xB9 // display control
#define DOR 0xBA // data order
#define TCDFE 0xBD // enable/disable DF temperature compensation
#define TCVOPE 0xBF // enable/disable Vop temp comp
#define EC 0xC0 // internal or external oscillator
#define SETMUL 0xC2 // set multiplication factor
#define TCVOPAB 0xC3 // set TCVOP slopes A and B
#define TCVOPCD 0xC4 // set TCVOP slopes c and d
#define TCDF 0xC5 // set divider frequency
#define DF8COLOR 0xC6 // set divider frequency 8-color mode
#define SETBS 0xC7 // set bias system
#define RDTEMP 0xC8 // temperature read back
#define NLI 0xC9 // n-line inversion
#define RDID1 0xDA // read ID1
#define RDID2 0xDB // read ID2
#define RDID3 0xDC // read ID3
#endif /* GE12_H */

32
drivers/gdisp/Nokia6610GE12/gdisp_lld_config.h
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@ -4,21 +4,21 @@
*
* http://ugfx.io/license.html
*/
#ifndef _GDISP_LLD_CONFIG_H
#define _GDISP_LLD_CONFIG_H
#if GFX_USE_GDISP
/*===========================================================================*/
/* Driver hardware support. */
/*===========================================================================*/
#ifndef _GDISP_LLD_CONFIG_H
#define _GDISP_LLD_CONFIG_H
#if GFX_USE_GDISP
/*===========================================================================*/
/* Driver hardware support. */
/*===========================================================================*/
#define GDISP_HARDWARE_CONTROL GFXON
#define GDISP_HARDWARE_STREAM_WRITE GFXON
#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_RGB444
#endif /* GFX_USE_GDISP */
#endif /* _GDISP_LLD_CONFIG_H */
#define GDISP_LLD_PIXELFORMAT GDISP_PIXELFORMAT_RGB444
#endif /* GFX_USE_GDISP */
#endif /* _GDISP_LLD_CONFIG_H */

640
drivers/gdisp/RA6963/board_RA6963.h
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@ -1,320 +1,320 @@
/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.io/license.html
*/
/* RA6963 Driver
* Pinout:
* Version 1:
* 1 - Vee Negative Voltage Output
* 2 - GND GND
* 3 - +5V
* 4 - Vo LCD Driver Supply (10-20k Pot between +5V and Vee)
* 5 - /WR Write (Low active)
* 6 - /RD Read (Low active)
* 7 - /CE Chip Enable (Low active)
* 8 - C/D Command or Data
* 9 - /RST Reset (Low active)
* 10..17 - D0..7
* 18 - FS Font Select
* 19 - A Backlight Anode (~4.3V)
* 20 - K Backlight Cathode (GND)
*/
#ifndef _GDISP_LLD_BOARD_H
#define _GDISP_LLD_BOARD_H
// My Settings
#define RA6963_NEED_READ GFXOFF //works, but is very slow!
#define RA6963_HAS_RESET GFXOFF
#define RA6963_NEED_FONT_SELECT GFXOFF
#define RA6963_NEED_BACKLIGHT GFXOFF
#define RA6963_NEED_PWMBACKLIGHT GFXOFF
#define GDISP_SCREEN_HEIGHT 64
#define GDISP_SCREEN_WIDTH 128
#define GDISP_INITIAL_CONTRAST 50
#define GDISP_INITIAL_BACKLIGHT 100
#define RA6963_delay(n) {asm("nop");asm("nop");asm("nop");asm("nop");}
#define LINE_WR PAL_LINE(GPIOB, 8U)
#if RA6963_NEED_READ
#define LINE_RD PAL_LINE(GPIOB, 9U)
#endif
#define LINE_CE PAL_LINE(GPIOB, 10U)
#define LINE_CD PAL_LINE(GPIOB, 11U)
#if RA6963_HAS_RESET
#define LINE_RST PAL_LINE(GPIOB, 12U)
#endif
#define LINE_D0 PAL_LINE(GPIOB, 0U)
#define LINE_D1 PAL_LINE(GPIOB, 1U)
#define LINE_D2 PAL_LINE(GPIOB, 2U)
#define LINE_D3 PAL_LINE(GPIOB, 3U)
#define LINE_D4 PAL_LINE(GPIOB, 4U)
#define LINE_D5 PAL_LINE(GPIOB, 5U)
#define LINE_D6 PAL_LINE(GPIOB, 6U)
#define LINE_D7 PAL_LINE(GPIOB, 7U)
#if RA6963_NEED_FONT_SELECT
#define LINE_FS PAL_LINE(GPIOA, 13U)
#endif
#if RA6963_NEED_BACKLIGHT
#define LINE_BL PAL_LINE(GPIOA, 14U)
#endif
typedef struct {
ioline_t WR; //Write PIN
#if RA6963_NEED_READ
ioline_t RD; //Read PIN (tie to +5V if not needed)
#endif
ioline_t CE; //Chip Enable PIN
ioline_t CD; //Command/Data Select PIN
#if RA6963_HAS_RESET
ioline_t RST; //Reset PIN (tie to +5V if not needed)
#endif
ioline_t D[8]; //Data PINs
#if RA6963_NEED_BACKLIGHT
ioline_t BL; //Backlight PIN
#endif
#if RA6963_NEED_FONT_SELECT
ioline_t FS; //Font Select PIN (tie to GND if not needed)
#endif
} lcd_pins_t;
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
static const lcd_pins_t lcdpins = {
LINE_WR,
#if RA6963_NEED_READ
LINE_RD,
#endif
LINE_CE,
LINE_CD,
#if RA6963_HAS_RESET
LINE_RST,
#endif
{
LINE_D0,
LINE_D1,
LINE_D2,
LINE_D3,
LINE_D4,
LINE_D5,
LINE_D6,
LINE_D7
},
#if RA6963_NEED_BACKLIGHT
LINE_BL,
#endif
#if RA6963_NEED_FONT_SELECT
LINE_FS,
#endif
};
static GFXINLINE void init_board(GDisplay* g){
(void) g;
g->board = 0;
int ii;
//################################DEBUG#######################################
#define DEB13_ON palClearLine(PAL_LINE(GPIOB, 13U))
#define DEB13_OFF palSetLine(PAL_LINE(GPIOB, 13U))
#define DEB14_ON palClearLine(PAL_LINE(GPIOB, 14U))
#define DEB14_OFF palSetLine(PAL_LINE(GPIOB, 14U))
palSetLineMode(PAL_LINE(GPIOB, 13U), PAL_MODE_OUTPUT_PUSHPULL);
DEB13_OFF;
palSetLineMode(PAL_LINE(GPIOB, 14U), PAL_MODE_OUTPUT_PUSHPULL);
DEB14_OFF;
//################################DEBUG#######################################
palSetLineMode(lcdpins.WR, PAL_MODE_OUTPUT_PUSHPULL);
palSetLine(lcdpins.WR);
#if RA6963_NEED_READ
palSetLineMode(lcdpins.RD, PAL_MODE_OUTPUT_PUSHPULL);
palSetLine(lcdpins.RD);
#endif
palSetLineMode(lcdpins.CE, PAL_MODE_OUTPUT_PUSHPULL);
palSetLine(lcdpins.CE);
palSetLineMode(lcdpins.CD, PAL_MODE_OUTPUT_PUSHPULL);
palSetLine(lcdpins.CD);
#if RA6963_HAS_RESET
palSetLine(lcdpins.RST);
palSetLineMode(lcdpins.RST, PAL_MODE_OUTPUT_PUSHPULL);
#endif
for(ii = 0; ii < 8; ii++) {
palSetLineMode(lcdpins.D[ii], PAL_MODE_OUTPUT_PUSHPULL);
palClearLine(lcdpins.D[ii]);
}
#if RA6963_NEED_BACKLIGHT
#if RA6963_NEED_PWMBACKLIGHT
palSetLineMode(lcdpins.BL, PAL_MODE_ALTERNATE(1));
#else
palSetLineMode(lcdpins.BL, PAL_MODE_OUTPUT_PUSHPULL);
#endif
#endif
#if RA6963_NEED_FONT_SELECT
palSetLineMode(lcdpins.FS, PAL_MODE_OUTPUT_PUSHPULL);
palSetLine(lcdpins.FS);
#endif
}
static GFXINLINE void post_init_board(GDisplay *g) {
(void) g;
}
static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
(void) g;
#if RA6963_HAS_RESET //Make Hardware Reset
if (state)
palClearLine(lcdpins.RST);
else
palSetLine(lcdpins.RST);
#else
(void) state;
#endif
}
static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
(void) g;
(void) percent;
#if RA6963_NEED_BACKLIGHT
#if RA6963_NEED_PWMBACKLIGHT
#else
#endif
#endif
}
static GFXINLINE void acquire_bus(GDisplay *g) {
(void) g;
}
static GFXINLINE void release_bus(GDisplay *g) {
(void) g;
}
#if RA6963_NEED_READ
static GFXINLINE gU8 RA6963_busy_wait(gU8 pattern, gBool lh){
gU8 data;
int ii;
for(ii = 0; ii < 2; ii++) //Only interested in Bit 0 and 1
palSetLineMode(lcdpins.D[ii], PAL_MODE_INPUT); //Set pads to input
palClearLine(lcdpins.CE);
palClearLine(lcdpins.RD);
do{
data = 0;
for(ii = 0; ii < 2; ii++){
if (palReadLine(lcdpins.D[ii]) == PAL_HIGH){ //Read output
data |= (1<<ii);
}
}
} while ((data & pattern) == lh);
palSetLine(lcdpins.CE);
palSetLine(lcdpins.RD);
for(ii = 0; ii < 2; ii++) {
palSetLineMode(lcdpins.D[ii], PAL_MODE_OUTPUT_PUSHPULL); //Set pads to output
}
return data;
}
#endif
static GFXINLINE void RA6963_write(gU8 value){
int ii;
for(ii = 0; ii < 8; ii++){
if(value & (1 << ii))
palSetLine(lcdpins.D[ii]);
else
palClearLine(lcdpins.D[ii]);
}
}
static GFXINLINE void write_data(GDisplay* g, gU8 data){
(void)g;
#if RA6963_NEED_READ
RA6963_busy_wait(RA6963_STATUS_BUSY1 | RA6963_STATUS_BUSY2, ~(RA6963_STATUS_BUSY1 | RA6963_STATUS_BUSY2));
#endif
RA6963_write(data);
palClearLine(lcdpins.CD);
palClearLine(lcdpins.CE);
palClearLine(lcdpins.WR);
RA6963_delay(1);
palSetLine(lcdpins.WR);
palSetLine(lcdpins.CE);
palSetLine(lcdpins.CD);
}
static GFXINLINE void write_cmd(GDisplay* g, gU8 data){
(void)g;
#if RA6963_NEED_READ
RA6963_busy_wait(RA6963_STATUS_BUSY1 | RA6963_STATUS_BUSY2, ~(RA6963_STATUS_BUSY1 | RA6963_STATUS_BUSY2));
#endif
RA6963_write(data);
palClearLine(lcdpins.CE);
palClearLine(lcdpins.WR);
RA6963_delay(1);
palSetLine(lcdpins.WR);
palSetLine(lcdpins.CE);
}
static GFXINLINE void setreadmode(GDisplay *g) {
(void) g;
}
static GFXINLINE void setwritemode(GDisplay *g) {
(void) g;
}
static GFXINLINE gU8 read_data(GDisplay *g) {
(void) g;
#if RA6963_NEED_READ
int ii;
gU8 data;
write_cmd(g, RA6963_DATA_READ_AND_NONVARIABLE);
//RA6963_busy_wait(RA6963_STATUS_BUSY1 | RA6963_STATUS_BUSY2, ~(RA6963_STATUS_BUSY1 | RA6963_STATUS_BUSY2));
for(ii = 0; ii < 8; ii++)
palSetLineMode(lcdpins.D[ii], PAL_MODE_INPUT); //Set pads to input
palClearLine(lcdpins.CE);
palClearLine(lcdpins.RD);
do{
data = 0;
for(ii = 0; ii < 2; ii++){
if (palReadLine(lcdpins.D[ii]) == PAL_HIGH){ //Read output
data |= (1<<ii);
}
}
} while ((data & (RA6963_STATUS_BUSY1 | RA6963_STATUS_BUSY2)) == ~(RA6963_STATUS_BUSY1 | RA6963_STATUS_BUSY2));
palClearLine(lcdpins.CD);
// RA6963_delay(1);
data = 0;
for(ii = 0; ii < 8; ii++){
if (palReadLine(lcdpins.D[ii]) == PAL_HIGH){ //Read output
data |= (1<<ii);
}
}
palSetLine(lcdpins.CE);
palSetLine(lcdpins.RD);
palSetLine(lcdpins.CD);
for(ii = 0; ii < 8; ii++) {
palSetLineMode(lcdpins.D[ii], PAL_MODE_OUTPUT_PUSHPULL); //Set pads to output
}
return data;
#else
return 0;
#endif
}
#endif /* _GDISP_LLD_BOARD_H */
/*
* This file is subject to the terms of the GFX License. If a copy of
* the license was not distributed with this file, you can obtain one at:
*
* http://ugfx.io/license.html
*/
/* RA6963 Driver
* Pinout:
* Version 1:
* 1 - Vee Negative Voltage Output
* 2 - GND GND
* 3 - +5V
* 4 - Vo LCD Driver Supply (10-20k Pot between +5V and Vee)
* 5 - /WR Write (Low active)
* 6 - /RD Read (Low active)
* 7 - /CE Chip Enable (Low active)
* 8 - C/D Command or Data
* 9 - /RST Reset (Low active)
* 10..17 - D0..7
* 18 - FS Font Select
* 19 - A Backlight Anode (~4.3V)
* 20 - K Backlight Cathode (GND)
*/
#ifndef _GDISP_LLD_BOARD_H
#define _GDISP_LLD_BOARD_H
// My Settings
#define RA6963_NEED_READ GFXOFF //works, but is very slow!
#define RA6963_HAS_RESET GFXOFF
#define RA6963_NEED_FONT_SELECT GFXOFF
#define RA6963_NEED_BACKLIGHT GFXOFF
#define RA6963_NEED_PWMBACKLIGHT GFXOFF
#define GDISP_SCREEN_HEIGHT 64
#define GDISP_SCREEN_WIDTH 128
#define GDISP_INITIAL_CONTRAST 50
#define GDISP_INITIAL_BACKLIGHT 100
#define RA6963_delay(n) {asm("nop");asm("nop");asm("nop");asm("nop");}
#define LINE_WR PAL_LINE(GPIOB, 8U)
#if RA6963_NEED_READ
#define LINE_RD PAL_LINE(GPIOB, 9U)
#endif
#define LINE_CE PAL_LINE(GPIOB, 10U)
#define LINE_CD PAL_LINE(GPIOB, 11U)
#if RA6963_HAS_RESET
#define LINE_RST PAL_LINE(GPIOB, 12U)
#endif
#define LINE_D0 PAL_LINE(GPIOB, 0U)
#define LINE_D1 PAL_LINE(GPIOB, 1U)
#define LINE_D2 PAL_LINE(GPIOB, 2U)
#define LINE_D3 PAL_LINE(GPIOB, 3U)
#define LINE_D4 PAL_LINE(GPIOB, 4U)
#define LINE_D5 PAL_LINE(GPIOB, 5U)
#define LINE_D6 PAL_LINE(GPIOB, 6U)
#define LINE_D7 PAL_LINE(GPIOB, 7U)
#if RA6963_NEED_FONT_SELECT
#define LINE_FS PAL_LINE(GPIOA, 13U)
#endif
#if RA6963_NEED_BACKLIGHT
#define LINE_BL PAL_LINE(GPIOA, 14U)
#endif
typedef struct {
ioline_t WR; //Write PIN
#if RA6963_NEED_READ
ioline_t RD; //Read PIN (tie to +5V if not needed)
#endif
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