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SSD2119: GDISP_USE_FSMC "switch" added 

Enable FSMC functions only when GDISP_USE_FSMC is set.
ugfx_release_2.6
Mateusz Tomaszkiewicz 2013-06-13 00:20:00 +02:00
parent 2a65ea5388
commit f820fb90d5
2 changed files with 29 additions and 14 deletions
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36
drivers/gdisp/SSD2119/gdisp_lld.c
View File

@ -318,7 +318,7 @@ void gdisp_lld_draw_pixel(coord_t x, coord_t y, color_t color) {
set_cursor(0, 0); set_cursor(0, 0);
stream_start(); stream_start();
#if defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM) #if defined(GDISP_USE_FSMC) && defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM)
uint8_t i; uint8_t i;
dmaStreamSetPeripheral(GDISP_DMA_STREAM, &color); dmaStreamSetPeripheral(GDISP_DMA_STREAM, &color);
dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M); dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
@ -334,7 +334,7 @@ void gdisp_lld_draw_pixel(coord_t x, coord_t y, color_t color) {
uint32_t index; uint32_t index;
for(index = 0; index < area; index++) for(index = 0; index < area; index++)
write_data(color); write_data(color);
#endif // defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM) #endif // defined(GDISP_USE_FSMC) && defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM)
stream_stop(); stream_stop();
release_bus(); release_bus();
@ -369,7 +369,7 @@ void gdisp_lld_draw_pixel(coord_t x, coord_t y, color_t color) {
set_viewport(x, y, cx, cy); set_viewport(x, y, cx, cy);
stream_start(); stream_start();
#if defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM) #if defined(GDISP_USE_FSMC) && defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM)
uint8_t i; uint8_t i;
dmaStreamSetPeripheral(GDISP_DMA_STREAM, &color); dmaStreamSetPeripheral(GDISP_DMA_STREAM, &color);
dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M); dmaStreamSetMode(GDISP_DMA_STREAM, STM32_DMA_CR_PL(0) | STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_DIR_M2M);
@ -385,7 +385,7 @@ void gdisp_lld_draw_pixel(coord_t x, coord_t y, color_t color) {
uint32_t index; uint32_t index;
for(index = 0; index < area; index++) for(index = 0; index < area; index++)
write_data(color); write_data(color);
#endif // defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM) #endif // defined(GDISP_USE_FSMC) && defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM)
stream_stop(); stream_stop();
release_bus(); release_bus();
@ -422,7 +422,7 @@ void gdisp_lld_draw_pixel(coord_t x, coord_t y, color_t color) {
set_viewport(x, y, cx, cy); set_viewport(x, y, cx, cy);
stream_start(); stream_start();
#if defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM) #if defined(GDISP_USE_FSMC) && defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM)
uint32_t area = cx * cy; uint32_t area = cx * cy;
uint8_t i; uint8_t i;
dmaStreamSetPeripheral(GDISP_DMA_STREAM, buffer); dmaStreamSetPeripheral(GDISP_DMA_STREAM, buffer);
@ -444,7 +444,7 @@ void gdisp_lld_draw_pixel(coord_t x, coord_t y, color_t color) {
for(; y < endy; y++, buffer += lg) for(; y < endy; y++, buffer += lg)
for(x=srcx; x < endx; x++) for(x=srcx; x < endx; x++)
write_data(*buffer++); write_data(*buffer++);
#endif // defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM) #endif // defined(GDISP_USE_FSMC) && defined(GDISP_USE_DMA) && defined(GDISP_DMA_STREAM)
stream_stop(); stream_stop();
release_bus(); release_bus();
@ -472,14 +472,18 @@ void gdisp_lld_draw_pixel(coord_t x, coord_t y, color_t color) {
set_cursor(x, y); set_cursor(x, y);
stream_start(); stream_start();
/* FSMC timing */ #if defined(GDISP_USE_FSMC)
FSMC_Bank1->BTCR[FSMC_Bank + 1] = FSMC_BTR1_ADDSET_3 | FSMC_BTR1_DATAST_3 | FSMC_BTR1_BUSTURN_0; /* FSMC timing */
FSMC_Bank1->BTCR[FSMC_Bank + 1] = FSMC_BTR1_ADDSET_3 | FSMC_BTR1_DATAST_3 | FSMC_BTR1_BUSTURN_0;
#endif // defined(GDISP_USE_FSMC)
color = read_data(); // dummy read color = read_data(); // dummy read
color = read_data(); color = read_data();
/* FSMC timing */ #if defined(GDISP_USE_FSMC)
FSMC_Bank1->BTCR[FSMC_Bank + 1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0; /* FSMC timing */
FSMC_Bank1->BTCR[FSMC_Bank + 1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0;
#endif // defined(GDISP_USE_FSMC)
stream_stop(); stream_stop();
release_bus(); release_bus();
@ -536,15 +540,19 @@ void gdisp_lld_draw_pixel(coord_t x, coord_t y, color_t color) {
set_viewport(x, row0, cx, 1); set_viewport(x, row0, cx, 1);
stream_start(); stream_start();
/* FSMC timing */ #if defined(GDISP_USE_FSMC)
FSMC_Bank1->BTCR[FSMC_Bank + 1] = FSMC_BTR1_ADDSET_3 | FSMC_BTR1_DATAST_3 | FSMC_BTR1_BUSTURN_0; /* FSMC timing */
FSMC_Bank1->BTCR[FSMC_Bank + 1] = FSMC_BTR1_ADDSET_3 | FSMC_BTR1_DATAST_3 | FSMC_BTR1_BUSTURN_0;
#endif // defined(GDISP_USE_FSMC)
j = read_data(); // dummy read j = read_data(); // dummy read
for (j = 0; (coord_t)j < cx; j++) for (j = 0; (coord_t)j < cx; j++)
buf[j] = read_data(); buf[j] = read_data();
/* FSMC timing */ #if defined(GDISP_USE_FSMC)
FSMC_Bank1->BTCR[FSMC_Bank + 1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0; /* FSMC timing */
FSMC_Bank1->BTCR[FSMC_Bank + 1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0;
#endif // defined(GDISP_USE_FSMC)
stream_stop(); stream_stop();

7
drivers/gdisp/SSD2119/gdisp_lld_board_embest_dmstf4bb.h
View File

@ -16,6 +16,9 @@
#ifndef _GDISP_LLD_BOARD_H #ifndef _GDISP_LLD_BOARD_H
#define _GDISP_LLD_BOARD_H #define _GDISP_LLD_BOARD_H
/* This board file uses only FSMC, so don't undefine this. */
#define GDISP_USE_FSMC
/* But it is OK to disable DMA use. */
#define GDISP_USE_DMA #define GDISP_USE_DMA
#define GDISP_DMA_STREAM STM32_DMA2_STREAM6 #define GDISP_DMA_STREAM STM32_DMA2_STREAM6
@ -57,6 +60,10 @@ static const PWMConfig pwmcfg = {
*/ */
static inline void init_board(void) { static inline void init_board(void) {
#ifndef GDISP_USE_FSMC
#error "This board uses only FSMC, please define GDISP_USE_FSMC"
#endif
#if defined(STM32F4XX) || defined(STM32F2XX) #if defined(STM32F4XX) || defined(STM32F2XX)
/* STM32F4 FSMC init */ /* STM32F4 FSMC init */
rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0); rccEnableAHB3(RCC_AHB3ENR_FSMCEN, 0);