Refactor STM32LTDC driver to outsource hardware specifics such as clock setup to the board file

boards/base/STM32F746-Discovery/board_STM32LTDC.h

@@ -393,6 +393,27 @@ static void configureLcdPins(void) {
 	#endif
 }
 
+static GFXINLINE void init_ltdc_clock()
+{
+	// Reset the LTDC peripheral
+	RCC->APB2RSTR |= RCC_APB2RSTR_LTDCRST;
+	RCC->APB2RSTR = 0;
+	
+	// Enable the LTDC clock
+	RCC->DCKCFGR1 = (RCC->DCKCFGR1 & ~RCC_DCKCFGR1_PLLSAIDIVR) | (1 << 16);
+	
+	// Enable the peripheral
+	RCC->APB2ENR |= RCC_APB2ENR_LTDCEN;
+}
+
+#if LTDC_USE_DMA2D
+	static GFXINLINE void init_dma2d_clock()
+	{
+		// Enable DMA2D clock
+		RCC->AHB1ENR |= RCC_AHB1ENR_DMA2DEN;
+	}
+#endif
+
 static GFXINLINE void init_board(GDisplay *g) {
 	(void) g;
 

boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c

@@ -66,11 +66,11 @@
 #include "stm32f7xx.h"
 
 #if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((gU32)25000000) /*!< Default value of the External oscillator in Hz */
+  #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
 #if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((gU32)16000000) /*!< Value of the Internal oscillator in Hz*/
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 
 /**
@@ -125,9 +125,9 @@
                is no need to call the 2 first functions listed above, since SystemCoreClock
                variable is updated automatically.
   */
-  gU32 SystemCoreClock = 16000000;
-  const gU8 AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-  const gU8 APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+  uint32_t SystemCoreClock = 16000000;
+  const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+  const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
 
 /**
   * @}
@@ -163,19 +163,19 @@ void SystemInit(void)
   #endif
   /* Reset the RCC clock configuration to the default reset state ------------*/
   /* Set HSION bit */
-  RCC->CR |= (gU32)0x00000001;
+  RCC->CR |= (uint32_t)0x00000001;
 
   /* Reset CFGR register */
   RCC->CFGR = 0x00000000;
 
   /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (gU32)0xFEF6FFFF;
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
 
   /* Reset PLLCFGR register */
   RCC->PLLCFGR = 0x24003010;
 
   /* Reset HSEBYP bit */
-  RCC->CR &= (gU32)0xFFFBFFFF;
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
 
   /* Disable all interrupts */
   RCC->CIR = 0x00000000;
@@ -230,7 +230,7 @@ void SystemInit(void)
   */
 void SystemCoreClockUpdate(void)
 {
-  gU32 tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
   
   /* Get SYSCLK source -------------------------------------------------------*/
   tmp = RCC->CFGR & RCC_CFGR_SWS;
@@ -287,8 +287,8 @@ void SystemCoreClockUpdate(void)
   */
 void SystemInit_ExtMemCtl(void)
 {
-  register gU32 tmpreg = 0, timeout = 0xFFFF;
-  register __IO gU32 index;
+  register uint32_t tmpreg = 0, timeout = 0xFFFF;
+  register __IO uint32_t index;
 
   /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG and GPIOH interface 
   clock */

changelog.txt

@@ -8,6 +8,7 @@ FIX:		Fixed GWIN console widget scroll
 FIX:		A warning and adjusted is made if GDISP_IMAGE_BMP_BLIT_BUFFER_SIZE is less than 40 bytes.
 FIX:        Prevent compiler warnings on duplicate const specifiers.
 FEATURE:	Added support for ChibiOS 6.x kernel.
+CHANGE:		Refactor STM32LTDC driver to outsource hardware specifics such as clock setup to the board file.
 
 
 *** Release 2.9 ***

drivers/gdisp/STM32LTDC/board_STM32LTDC_template.h

@@ -55,7 +55,20 @@ static const ltdcConfig driverCfg = {
 #endif
 };
 
-static GFXINLINE void init_board(GDisplay* g) {
+static GFXINLINE void init_ltdc_clock()
+{
+	// Setup LTDC clock and enable the peripheral
+}
+
+#if LTDC_USE_DMA2D
+	static GFXINLINE void init_dma2d_clock()
+	{
+		// Setup DMA2D clock and enable the peripheral
+	}
+#endif
+
+static GFXINLINE void init_board(GDisplay* g)
+{
 	// This is function only called once with the display for the background layer.
 	(void)g;
 }

drivers/gdisp/STM32LTDC/gdisp_lld_STM32LTDC.c

@@ -166,25 +166,8 @@ static void _ltdc_init(void) {
 	// Set up the display scanning
 	gU32 hacc, vacc;
 
-	// Reset the LTDC peripheral
-	RCC->APB2RSTR |= RCC_APB2RSTR_LTDCRST;
-	RCC->APB2RSTR = 0;
-
-	// Enable the LTDC clock
-	#if !LTDC_NO_CLOCK_INIT
-		#if defined(STM32F469xx)
-			RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR);
-		#elif defined(STM32F4) || defined(STM32F429_439xx) || defined(STM32F429xx)
-			RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | (1 << 16);
-		#elif defined(STM32F7) || defined(STM32F746xx)
-			RCC->DCKCFGR1 = (RCC->DCKCFGR1 & ~RCC_DCKCFGR1_PLLSAIDIVR) | (1 << 16);
-		#else
-			#error STM32LTDC driver not implemented for your platform
-		#endif
-	#endif
-
-	// Enable the peripheral
-	RCC->APB2ENR |= RCC_APB2ENR_LTDCEN;
+	// Let the board handle LTDC clock setups
+	init_ltdc_clock();
 
 	// Turn off the controller and its interrupts
 	LTDC->GCR = 0;
@@ -425,8 +408,8 @@ LLDSPEC	gColor gdisp_lld_get_pixel_color(GDisplay* g) {
 
 
 	static void dma2d_init(void) {
-		// Enable DMA2D clock
-		RCC->AHB1ENR |= RCC_AHB1ENR_DMA2DEN;
+		// Let the board handle the clock setup
+		init_dma2d_clock();
 
 		// Output color format
 		#if GDISP_LLD_PIXELFORMAT == GDISP_PIXELFORMAT_RGB565