291 lines
8.4 KiB
C
291 lines
8.4 KiB
C
/*
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* This file is subject to the terms of the GPL License.
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*/
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#ifndef _SSD1848_H
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#define _SSD1848_H
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/*
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* Set the start column address by X5X4X3X2X1X0
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* Set the end column address by Y5Y4Y3Y2Y1Y0
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* Column address = 00000000b (POR)
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* Column address is in a range of 0~32 (0x00~0x20).
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*/
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#define SSD1848_HV_COLUMN_ADDRESS 0x15
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/*
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* Set the start page address by X7X6X5X4X3X2X1X0
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* Set the end page address by Y7Y6Y5Y4Y3Y2Y1Y0
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* Page address = 00000000b (POR)
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* Page address is in a range of 0~129 (0x00~0x81).
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*/
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#define SSD1848_HV_PAGE_ADDRESS 0x75
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/*
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* X2 X1 X0 ROW0…ROW64 ROW65…ROW129
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* 0 0 0 COM0 ->COM64 COM65-> COM129(POR)
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* 0 0 1 COM0->COM64 COM129<-COM65
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* 0 1 0 COM64<-COM0 COM65->COM129
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* 0 1 1 COM64<-COM0 COM129<-COM65
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*/
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#define SSD1848_COM_OUTPUT_SCAN_DIR 0xBB
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/*
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* a) Normal or Reverse page/column/RAM access/scan
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* directions
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* P10 = 0: set page address to normal display (POR)
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* P10 = 1: set page address to inverse display
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* P11 = 0: set column address to normal rotation (POR)
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* P11 = 1: set column address to inverse rotation
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* P12 = 0: set scan direction to column scan(POR)
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* P12 = 1: set scan direction to page scan
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* P13 = 0: set normal scan direction (POR)
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* P13 = 1: set inverse scan direction
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*
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* b) Gray-scale setting
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* X = Light gray PWM count (POR 5 counts)
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* Y = Dark gray PWM count (POR 10 counts)
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* P22P21P20 = X -1 (POR 100)
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* P25P24P23 = Y - X - 1 (POR 100)
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* Remark: Y-X≤8
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*
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* # Remarks: The PWM count for White and Black are 0 and 15 respectively.
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*
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* P30 = 0: PWM (POR)
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* P34 = 0:
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* White | Light Gray | Dark Gray | Black
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* 0% | 33% | 66% | 100%
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*
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* P34 = 1:
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* White | Light Gray | Dark Gray | Black
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* 0% | X/15 | Y/15 | 100%
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*
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* P30 = 1: FRC
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* P31 = 0: 3-frame FRC (POR)
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* White | Light Gray | Dark Gray | Black
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* 0% | 33% | 66% | 100%
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*
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* P31 = 1: 4-frame FRC
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* P33 P32 | White | Light Gray | Dark Gray | Black
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* 00(POR) | 0% | 25% | 75% | 100%
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* 01 | 0% | 50% | 75% | 100%
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* 10 | 0% | 25% | 50% | 100%
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* 11 | Reserved
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*/
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#define SSD1848_DATA_OUTPUT_SCAN_DIR 0xBC
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/* @
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* Driver duty selection
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* Select driver duty from 1/16 to 1/128. As Y5Y4Y3Y2Y1Y0 is increased
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* from 000011b to 011111b, the number of display lines, N is increased
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* at the same rating. To specify the Y5Y4Y3Y2Y1Y0 = (N/4)-1 where 1/N
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* is the driver duty.
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*
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* Y5Y4Y3Y2Y1Y0 = 100000b for 1/130 duty.
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*/
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#define SSD1848_SETDISP_CTRL 0xCA
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/* @
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* X0=0: turns off the reference voltage generator (POR)
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* X0=1: turns on the reference voltage generator
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* X1=0: turns off the internal regulator and voltage follower (POR)
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* X1=1: turns on the internal regulator and voltage follower
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*
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* Select booster level
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* X4 X3 X2 Boost level
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* 0 0 0 4X
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* 0 0 1 5X
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* 0 1 0 6X (POR)
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* 0 1 1 7X
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*/
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#define SSD1848_SETPOWER_CTRL 0x20
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/*
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* a) Select contrast level from 64 contrast steps Contrast increases
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* as X5X4X3X2X1X0 is increased from 000000b to 111111b.
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* X5X4X3X2X1X0 = 100000b (POR)
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*
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* b) The internal regulator gain (1+R2/R1) VOUT increases as Y2Y1Y0
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* is increased from 000b to 111b.
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*
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* The factor, 1+R2/R1, is given by:
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* Y2Y1Y0 = 000: 3.38 (POR)
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* Y2Y1Y0 = 001: 4.41
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* Y2Y1Y0 = 010: 5.44
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* Y2Y1Y0 = 011: 6.47
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* Y2Y1Y0 = 100: 7.50
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* Y2Y1Y0 = 101: 8.52
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* Y2Y1Y0 = 110: 9.55
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* Y2Y1Y0 = 111: 10.58
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*/
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#define SSD1848_SETCONTRAST 0x81
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/*
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* X7X6X5X4X3X2X1X0 : End COM Address = 00000000b (POR)
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*/
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#define SSD1848_ENABLE_PARTIAL_DISP 0xA8
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#define SSD1848_EXIT_PARTIAL_DISP 0xA9
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#define SSD1848_DISPLAYOFF 0xAE
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#define SSD1848_DISPLAYON 0xAF
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#define SSD1848_EXITSLEEP 0x94
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#define SSD1848_ENTERSLEEP 0x95
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#define SSD1848_ENABLE_INTERNAL_CLOCK 0xD1
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#define SSD1848_DISABLE_INTERNAL_CLOCK 0xD2
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/*
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* VOUT average temperature gradients
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* X1 X0 Average Temperature
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* Gradient [%/oC]
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* 0 0 -0.01 (POR)
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* 0 1 -0.06
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*/
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#define SSD1848_TEMP_COMPENSATION 0x82
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/*
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* Enter the "write display data mode" by executing
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* the command 01011100b. The following byte is
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* used to specify the data byte to be written to the
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* GDDRAM directly.
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* The D/C bit should be stated at logic "1" during the
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* display data is written to the GDDRAM.
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*/
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#define SSD1848_WRITE_DISP_DATA 0x5C
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/*
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* Allow user to set bias from 1/ 4 to 1/13
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* B3B2B1B0 Bias ratio
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* 1 0 0 1 1/4 bias
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* 1 0 0 0 1/5 bias
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* 0 1 1 1 1/6 bias
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* 0 1 1 0 1/7 bias
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* 0 1 0 1 1/8 bias
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* 0 1 0 0 1/9 bias
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* 0 0 1 1 1/10 bias
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* 0 0 1 0 1/11 bias
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* 0 0 0 1 1/12 bias
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* 0 0 0 0 1/13 bias (POR)
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* L0 Lock and unlock Cmd
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* 0 unlock (POR)
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* 1 lock and no more cmd/data is written to driver
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* The 2nd byte is sent as Cmd if L0 is set to 1
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*/
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#define SSD1848_SET_BIASING_LOCK 0xFB
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/*
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* This command uses to change the frame
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* frequency; set the N-line inversion and N-line
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* inversion mode
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* X0 = 1 (POR) X0 = 0
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* F4F3F2F1F0
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* 00000 : 56.4 Hz (POR) 64Hz
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* 00111 : +10.1% +11.8%
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* 01000 : +10.7% +15.2%
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* 01001 : +12.5% +15.2%
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* 01010 : +14.1% +20.6%
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* 01011 : +16.1% +20.6%
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* 01100 : +17.4% +25.9%
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* 01101 : +19.5% +25.9%
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* 01110 : +21.4% +32.9%
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* 01111 : +23.7% +32.9%
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* 10000 : +24.6% +37.4%
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* 10001 : +27.1% +37.4%
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* 10010 : +29.2% +46.0%
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* 10011 : +31.8% +46.0%
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* 10100 : +33.6% +54.6%
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* 10101 : +36.5% +54.6%
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* 10110 : +39.0% +66.9%
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* 10111 : +42.2% +66.9%
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* 11000 : +43.2% +75.8%
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* 11001 : +46.6% +75.8%
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* 11010 : +49.7% +94.0%
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*
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* Remark: The frame frequency is typical value
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* for 130mux and PWM mode.
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* The second byte data N5N4N3N2N1N0 sets the nline
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* inversion register from 2 to 64 lines to
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* reduce display crosstalk. Register values from
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* 000001b to 111111b are mapped to 2 lines to 64
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* lines respectively. Value 00000b disables the Nline
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* inversion. 010000 is the POR value. To
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* avoid a fix polarity at some lines, it should be
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* noted that the total number of mux should NOT
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* be a multiple of the lines of inversion (n).
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* N6
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* 0 – reset n-line counter per frame (POR)
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* 1 – will not reset n-line counter per frame
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*/
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#define SSD1848_SET_FRAME_FREQ_LINEINVE 0xF2
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#define SSD1848_DUAL_OPT_SET 0xF6
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#define SSD1848_SET_BLACK_WHITE 0xF7
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#define SSD1848_OTP 0xF8
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#define SSD1848_NORMALDISPLAY 0xA6
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#define SSD1848_INVERTDISPLAY 0xA7
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/*
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* This command specifies 1st Com line function. Byte A specifies the first
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* display line which the graphic start to display. At POR, the 1st Com line
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* is set to 00000000b (0 lines).
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*/
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#define SSD1848_SETSTARTLINE 0x44
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/* Scrolling #defines */
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/*
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* a) Top Block Address
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* X7X6X5X4X3X2X1X0 is used to specify the row
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* address at the top of the scrolling area.
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* Top row address = 00000000b (POR)
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*
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* b) Bottom Block Address
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* Y7Y6Y5Y4Y3Y2Y1Y0 is used to specify the row
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* address at the bottom of the scrolling area.
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* Bottom row address = 00000000b (POR)
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*
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* c) Number of specified Blocks
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* The number of specified blocks = Number of (Top
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* fixed area + Scroll area) blocks –1. If bottom scroll
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* or whole screen scroll mode is chosen, the number
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* of specified blocks is set to Z7Z6Z5Z4Z3Z2Z1Z0
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* Number of specified blocks = 00000000b (POR)
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*
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* d) Area Scroll Mode
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* There are four types of area scroll.
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* P41 P40 Types of Area Scroll
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* 0 0 Center Screen Scroll
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* 0 1 Top Screen Scroll
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* 1 0 Bottom Screen Scroll
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* 1 1 Whole Screen Scroll
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* Type of area scroll = Whole Screen Scroll (POR)
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*/
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#define SSD1848_SET_AREA_SCROLL 0xAA
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/*
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* X5X4X3X2X1X0 specify the start row address
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* of area scrolling.
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* Start block address = 00000000b (POR)
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*/
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#define SSD1848_SCROLL_START 0xAB
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/*
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* Enter the "read display data mode" by executing
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* the command 01011101b. The next byte is a
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* dummy data. The GDDRAM data will be read
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* form the second byte. The GDDRAM column
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* address pointer will be increased by one
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* automatically after each 2-bytes data read.
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*/
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#define SSD1848_READ_DISP_DATA 0x5D
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#endif /* _SSD1848_H */
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