97 lines
3.3 KiB
C
97 lines
3.3 KiB
C
/**
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******************************************************************************
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* @file stm32f429i_discovery_sdram.h
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* @author MCD Application Team
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* @version V1.0.0
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* @date 20-September-2013
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* @brief This file contains all the functions prototypes for the
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* stm324x9i_disco_sdram.c driver.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32429I_DISCO_SDRAM_H
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#define __STM32429I_DISCO_SDRAM_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//FIXME this should not be needed
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#define STM32F429_439xx
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx.h"
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/**
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* @brief FMC SDRAM Bank address
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*/
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#define SDRAM_BANK_ADDR ((gU32)0xD0000000)
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/**
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* @brief FMC SDRAM Memory Width
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*/
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/* #define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_8b */
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#define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_16b
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/**
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* @brief FMC SDRAM CAS Latency
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*/
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/* #define SDRAM_CAS_LATENCY FMC_CAS_Latency_2 */
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#define SDRAM_CAS_LATENCY FMC_CAS_Latency_3
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/**
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* @brief FMC SDRAM Memory clock period
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*/
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#define SDCLOCK_PERIOD FMC_SDClock_Period_2 /* Default configuration used with LCD */
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/* #define SDCLOCK_PERIOD FMC_SDClock_Period_3 */
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/**
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* @brief FMC SDRAM Memory Read Burst feature
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*/
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#define SDRAM_READBURST FMC_Read_Burst_Disable /* Default configuration used with LCD */
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/* #define SDRAM_READBURST FMC_Read_Burst_Enable */
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/**
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* @brief FMC SDRAM Mode definition register defines
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*/
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#define SDRAM_MODEREG_BURST_LENGTH_1 ((gU16)0x0000)
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#define SDRAM_MODEREG_BURST_LENGTH_2 ((gU16)0x0001)
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#define SDRAM_MODEREG_BURST_LENGTH_4 ((gU16)0x0002)
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#define SDRAM_MODEREG_BURST_LENGTH_8 ((gU16)0x0004)
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#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((gU16)0x0000)
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#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((gU16)0x0008)
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#define SDRAM_MODEREG_CAS_LATENCY_2 ((gU16)0x0020)
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#define SDRAM_MODEREG_CAS_LATENCY_3 ((gU16)0x0030)
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#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((gU16)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((gU16)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((gU16)0x0200)
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void SDRAM_Init(void);
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void SDRAM_InitSequence(void);
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void SDRAM_WriteBuffer(gU32* pBuffer, gU32 uwWriteAddress, gU32 uwBufferSize);
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void SDRAM_ReadBuffer(gU32* pBuffer, gU32 uwReadAddress, gU32 uwBufferSize);
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#ifdef __cplusplus
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}
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#endif
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#endif
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