2015-10-05 01:23:31 +00:00
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#include "gfx.h"
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2018-03-10 10:36:12 +00:00
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#if GFX_COMPAT_V2 && GFX_COMPAT_OLDCOLORS
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#undef Red
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#undef Green
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#undef Blue
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#endif
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2015-07-22 19:11:28 +00:00
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#include "stm32f7_i2c.h"
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/*
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* The CR2 register needs atomic access. Hence always use this function to setup a transfer configuration.
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*/
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2018-11-03 00:51:23 +00:00
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static void _i2cConfigTransfer(I2C_TypeDef* i2c, gU16 slaveAddr, gU8 numBytes, gU32 mode, gU32 request)
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2015-07-22 19:11:28 +00:00
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{
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2018-11-03 00:51:23 +00:00
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gU32 tmpreg = 0;
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2015-07-22 19:11:28 +00:00
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// Get the current CR2 register value
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tmpreg = i2c->CR2;
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// Clear tmpreg specific bits
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2018-11-03 00:51:23 +00:00
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tmpreg &= (gU32) ~((gU32) (I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
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2015-07-22 19:11:28 +00:00
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// update tmpreg
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2018-11-03 00:51:23 +00:00
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tmpreg |= (gU32) (((gU32) slaveAddr & I2C_CR2_SADD) | (((gU32) numBytes << 16) & I2C_CR2_NBYTES) | (gU32) mode | (gU32) request);
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2015-07-22 19:11:28 +00:00
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// Update the actual CR2 contents
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i2c->CR2 = tmpreg;
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}
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/*
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* According to the STM32Cube HAL the CR2 register needs to be reset after each transaction.
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*/
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static void _i2cResetCr2(I2C_TypeDef* i2c)
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{
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2018-11-03 00:51:23 +00:00
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i2c->CR2 &= (gU32) ~((gU32) (I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN));
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2015-07-22 19:11:28 +00:00
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}
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2018-06-23 03:02:07 +00:00
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gBool i2cInit(I2C_TypeDef* i2c)
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2015-07-22 19:11:28 +00:00
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{
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// Enable I2Cx peripheral clock.
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// Select APB1 as clock source
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if (i2c == I2C1) {
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RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_I2C1SEL;
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RCC->APB1ENR |= RCC_APB1ENR_I2C1EN;
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} else if (i2c == I2C2) {
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RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_I2C2SEL;
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RCC->APB1ENR |= RCC_APB1ENR_I2C2EN;
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} else if (i2c == I2C3) {
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RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_I2C3SEL;
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RCC->APB1ENR |= RCC_APB1ENR_I2C3EN;
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} else if (i2c == I2C4) {
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RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_I2C4SEL;
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RCC->APB1ENR |= RCC_APB1ENR_I2C4EN;
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} else {
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2018-06-23 03:02:07 +00:00
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return gFalse;
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2015-07-22 19:11:28 +00:00
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}
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// Disable the I2Cx peripheral
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i2c->CR1 &= ~I2C_CR1_PE;
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while (i2c->CR1 & I2C_CR1_PE);
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// Set timings. Asuming I2CCLK is 50 MHz (APB1 clock source)
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i2c->TIMINGR = 0x40912732; // Discovery BSP code from ST examples
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// Use 7-bit addresses
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i2c->CR2 &=~ I2C_CR2_ADD10;
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// Enable auto-end mode
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i2c->CR2 |= I2C_CR2_AUTOEND;
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// Disable the analog filter
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i2c->CR1 |= I2C_CR1_ANFOFF;
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// Disable NOSTRETCH
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i2c->CR1 |= I2C_CR1_NOSTRETCH;
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// Enable the I2Cx peripheral
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i2c->CR1 |= I2C_CR1_PE;
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2018-06-23 03:02:07 +00:00
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return gTrue;
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2015-07-22 19:11:28 +00:00
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}
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2018-11-03 00:51:23 +00:00
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void i2cSend(I2C_TypeDef* i2c, gU8 slaveAddr, gU8* data, gU16 length)
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2015-07-22 19:11:28 +00:00
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{
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// We are currently not able to send more than 255 bytes at once
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if (length > 255) {
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return;
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}
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// Setup the configuration
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_i2cConfigTransfer(i2c, slaveAddr, length, (!I2C_CR2_RD_WRN) | I2C_CR2_AUTOEND, I2C_CR2_START);
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// Transmit the whole buffer
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while (length > 0) {
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while (!(i2c->ISR & I2C_ISR_TXIS));
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i2c->TXDR = *data++;
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length--;
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}
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// Wait until the transfer is complete
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while (!(i2c->ISR & I2C_ISR_TXE));
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// Wait until the stop condition was automagically sent
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while (!(i2c->ISR & I2C_ISR_STOPF));
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// Reset the STOP bit
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i2c->ISR &= ~I2C_ISR_STOPF;
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// Reset the CR2 register
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_i2cResetCr2(i2c);
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}
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2018-11-03 00:51:23 +00:00
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void i2cSendByte(I2C_TypeDef* i2c, gU8 slaveAddr, gU8 data)
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2015-07-22 19:11:28 +00:00
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{
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i2cSend(i2c, slaveAddr, &data, 1);
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}
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2018-11-03 00:51:23 +00:00
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void i2cWriteReg(I2C_TypeDef* i2c, gU8 slaveAddr, gU8 regAddr, gU8 value)
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2015-07-22 19:11:28 +00:00
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{
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2018-11-03 00:51:23 +00:00
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gU8 txbuf[2];
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2015-07-22 19:11:28 +00:00
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txbuf[0] = regAddr;
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txbuf[1] = value;
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i2cSend(i2c, slaveAddr, txbuf, 2);
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}
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2018-11-03 00:51:23 +00:00
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void i2cRead(I2C_TypeDef* i2c, gU8 slaveAddr, gU8* data, gU16 length)
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2015-07-22 19:11:28 +00:00
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{
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2015-10-05 01:23:31 +00:00
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int i;
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2015-07-22 19:11:28 +00:00
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// We are currently not able to read more than 255 bytes at once
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if (length > 255) {
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return;
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}
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// Setup the configuration
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_i2cConfigTransfer(i2c, slaveAddr, length, I2C_CR2_RD_WRN | I2C_CR2_AUTOEND, I2C_CR2_START);
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// Transmit the whole buffer
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2015-10-05 01:23:31 +00:00
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for (i = 0; i < length; i++) {
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2015-07-22 19:11:28 +00:00
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while (!(i2c->ISR & I2C_ISR_RXNE));
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data[i] = i2c->RXDR;
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}
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// Wait until the stop condition was automagically sent
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while (!(i2c->ISR & I2C_ISR_STOPF));
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// Reset the STOP bit
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i2c->ISR &= ~I2C_ISR_STOPF;
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// Reset the CR2 register
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_i2cResetCr2(i2c);
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}
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2018-11-03 00:51:23 +00:00
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gU8 i2cReadByte(I2C_TypeDef* i2c, gU8 slaveAddr, gU8 regAddr)
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2015-07-22 19:11:28 +00:00
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{
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2018-11-03 00:51:23 +00:00
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gU8 ret = 0xAA;
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2015-07-22 19:11:28 +00:00
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i2cSend(i2c, slaveAddr, ®Addr, 1);
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i2cRead(i2c, slaveAddr, &ret, 1);
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return ret;
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}
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2018-11-03 00:51:23 +00:00
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gU16 i2cReadWord(I2C_TypeDef* i2c, gU8 slaveAddr, gU8 regAddr)
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2015-07-22 19:11:28 +00:00
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{
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2018-11-03 00:51:23 +00:00
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gU8 ret[2] = { 0xAA, 0xAA };
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2015-07-22 19:11:28 +00:00
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i2cSend(i2c, slaveAddr, ®Addr, 1);
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i2cRead(i2c, slaveAddr, ret, 2);
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2018-11-03 00:51:23 +00:00
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return (gU16)((ret[0] << 8) | (ret[1] & 0x00FF));
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2015-07-22 19:11:28 +00:00
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}
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